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author | Stefan Roese <sr@denx.de> | 2007-06-19 16:42:31 +0200 |
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committer | Stefan Roese <sr@denx.de> | 2007-06-19 16:42:31 +0200 |
commit | df8a24cdd30151505cf57bbee5289e91bf53bd1b (patch) | |
tree | ff5305f90f000aead5a0cbf3a8e3501ea6102021 | |
parent | 86ba99e34194394052d24c04dc40d1263d29a26f (diff) | |
download | bootable_bootloader_goldelico_gta04-df8a24cdd30151505cf57bbee5289e91bf53bd1b.zip bootable_bootloader_goldelico_gta04-df8a24cdd30151505cf57bbee5289e91bf53bd1b.tar.gz bootable_bootloader_goldelico_gta04-df8a24cdd30151505cf57bbee5289e91bf53bd1b.tar.bz2 |
[ppc4xx] Fix problem with NAND booting on AMCC Acadia
The latest changes showed a problem with the location of the NAND-SPL
image in the OCM and the init-data area (incl. cache). This patch
fixes this problem.
Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r-- | board/amcc/acadia/Makefile | 2 | ||||
-rw-r--r-- | board/amcc/acadia/acadia.c | 2 | ||||
-rw-r--r-- | board/amcc/acadia/memory.c | 11 | ||||
-rw-r--r-- | cpu/ppc4xx/start.S | 6 | ||||
-rw-r--r-- | include/configs/acadia.h | 4 | ||||
-rw-r--r-- | nand_spl/board/amcc/acadia/Makefile | 14 | ||||
-rw-r--r-- | nand_spl/board/amcc/acadia/config.mk | 4 | ||||
-rw-r--r-- | nand_spl/board/amcc/acadia/u-boot.lds | 2 |
8 files changed, 34 insertions, 11 deletions
diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile index ddbcb80..c56b273 100644 --- a/board/amcc/acadia/Makefile +++ b/board/amcc/acadia/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cmd_acadia.o cpr.o memory.o +COBJS = $(BOARD).o cmd_acadia.o memory.o pll.o SOBJS = SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 46d63e6..0f54025 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -55,10 +55,12 @@ int board_early_init_f(void) { unsigned int reg; +#if !defined(CONFIG_NAND_U_BOOT) /* don't reinit PLL when booting via I2C bootstrap option */ mfsdr(SDR_PINSTP, reg); if (reg != 0xf0000000) board_pll_init_f(); +#endif acadia_gpio_init(); diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 25904d3..9346d2c 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -31,6 +31,8 @@ #include <asm/io.h> #include <asm/gpio.h> +extern void board_pll_init_f(void); + /* * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! */ @@ -67,6 +69,15 @@ static void cram_bcr_write(u32 wr_val) long int initdram(int board_type) { +#if defined(CONFIG_NAND_SPL) + u32 reg; + + /* don't reinit PLL when booting via I2C bootstrap option */ + mfsdr(SDR_PINSTP, reg); + if (reg != 0xf0000000) + board_pll_init_f(); +#endif + #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) int i; u32 val; diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index e135220..16df1e7 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -564,7 +564,7 @@ ProgramCheck: STD_EXCEPTION(0x800, FPUnavailable, UnknownException) STD_EXCEPTION(0x900, Decrementer, DecrementerPITException) STD_EXCEPTION(0xa00, APU, UnknownException) -#endif +#endif STD_EXCEPTION(0xc00, SystemCall, UnknownException) #ifdef CONFIG_440 @@ -889,7 +889,7 @@ _start: */ lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ ori r3,r3,CFG_OCM_DATA_ADDR@l - ori r3,r3,0x8270 /* 32K Offset, 16K for Bank 1, R/W/Enable */ + ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ mtdcr ocmplb3cr1,r3 /* Set PLB Access */ ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ mtdcr ocmplb3cr2,r3 /* Set PLB Access */ @@ -1623,7 +1623,7 @@ trap_init: li r7, .L_APU - _start + _START_OFFSET bl trap_reloc - + li r7, .L_InstructionTLBError - _start + _START_OFFSET bl trap_reloc diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 0f447b0..517d130 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -75,7 +75,7 @@ #define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */ /* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_ADDR 0xf8000000 #define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ @@ -159,7 +159,7 @@ */ #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (12 << 10)) /* Copy SPL here*/ +#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/ #define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ #define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile index 0d6828a..926476f 100644 --- a/nand_spl/board/amcc/acadia/Makefile +++ b/nand_spl/board/amcc/acadia/Makefile @@ -30,7 +30,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o -COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o +COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -39,7 +39,8 @@ LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) nandobj := $(OBJTREE)/nand_spl/ -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \ + $(nandobj)System.map all: $(obj).depend $(ALL) @@ -54,6 +55,11 @@ $(nandobj)u-boot-spl: $(OBJS) -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl +$(nandobj)System.map: $(nandobj)u-boot-spl + @$(NM) $< | \ + grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > $(nandobj)System.map + # create symbolic links for common files # from cpu directory @@ -78,6 +84,10 @@ $(obj)memory.c: @rm -f $(obj)memory.c ln -s $(SRCTREE)/board/amcc/acadia/memory.c $(obj)memory.c +$(obj)pll.c: + @rm -f $(obj)pll.c + ln -s $(SRCTREE)/board/amcc/acadia/pll.c $(obj)pll.c + # from nand_spl directory $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c diff --git a/nand_spl/board/amcc/acadia/config.mk b/nand_spl/board/amcc/acadia/config.mk index 55069b4..3b140fa 100644 --- a/nand_spl/board/amcc/acadia/config.mk +++ b/nand_spl/board/amcc/acadia/config.mk @@ -32,11 +32,11 @@ # We will copy this SPL into internal SRAM in start.S. So we set # TEXT_BASE to starting address in internal SRAM here. # -TEXT_BASE = 0xF8003000 +TEXT_BASE = 0xf8004000 # PAD_TO used to generate a 16kByte binary needed for the combined image # -> PAD_TO = TEXT_BASE + 0x4000 -PAD_TO = 0xF8007000 +PAD_TO = 0xf8008000 ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG diff --git a/nand_spl/board/amcc/acadia/u-boot.lds b/nand_spl/board/amcc/acadia/u-boot.lds index 018def1..a07a773 100644 --- a/nand_spl/board/amcc/acadia/u-boot.lds +++ b/nand_spl/board/amcc/acadia/u-boot.lds @@ -24,7 +24,7 @@ OUTPUT_ARCH(powerpc:common) SECTIONS { - .resetvec 0xF8003FFC : + .resetvec 0xf8004ffc : { *(.resetvec) } = 0xffff |