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author | H. Nikolaus Schaller <hns@goldelico.com> | 2011-02-24 13:21:40 +0100 |
---|---|---|
committer | H. Nikolaus Schaller <hns@goldelico.com> | 2011-02-24 13:21:40 +0100 |
commit | 67fa659acb97323da480a4a545560d4d27c5796a (patch) | |
tree | 648ab5e4cbcdf17bcfe0e79346e264c4f0187662 /arch/powerpc/cpu | |
parent | 872ca46bf7ec07388fc06e687875204663f6080e (diff) | |
parent | c7977858dcf1f656cbe91ea0dc3cb9139c6a8cc8 (diff) | |
download | bootable_bootloader_goldelico_gta04-67fa659acb97323da480a4a545560d4d27c5796a.zip bootable_bootloader_goldelico_gta04-67fa659acb97323da480a4a545560d4d27c5796a.tar.gz bootable_bootloader_goldelico_gta04-67fa659acb97323da480a4a545560d4d27c5796a.tar.bz2 |
git pull denx master
Diffstat (limited to 'arch/powerpc/cpu')
57 files changed, 2581 insertions, 418 deletions
diff --git a/arch/powerpc/cpu/74xx_7xx/cpu.c b/arch/powerpc/cpu/74xx_7xx/cpu.c index ab6f11d..b6a31b4 100644 --- a/arch/powerpc/cpu/74xx_7xx/cpu.c +++ b/arch/powerpc/cpu/74xx_7xx/cpu.c @@ -234,8 +234,7 @@ soft_restart(unsigned long addr) !defined(CONFIG_ELPPC) && \ !defined(CONFIG_PPMC7XX) /* no generic way to do board reset. simply call soft_reset. */ -void -do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong addr; /* flush and disable I/D cache */ @@ -263,7 +262,12 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); #endif soft_restart(addr); - while(1); /* not reached */ + + /* not reached */ + while(1) + ; + + return 1; } #endif diff --git a/arch/powerpc/cpu/74xx_7xx/u-boot.lds b/arch/powerpc/cpu/74xx_7xx/u-boot.lds index 771a845..8429f33 100644 --- a/arch/powerpc/cpu/74xx_7xx/u-boot.lds +++ b/arch/powerpc/cpu/74xx_7xx/u-boot.lds @@ -43,13 +43,14 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - KEEP(*(.got)) _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_)>>2; .data : diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds index 361e714..ab9303f 100644 --- a/arch/powerpc/cpu/mpc512x/u-boot.lds +++ b/arch/powerpc/cpu/mpc512x/u-boot.lds @@ -37,14 +37,15 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - KEEP(*(.got)) _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) *(.fixup) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds index b7fd4bc..69bd7aa 100644 --- a/arch/powerpc/cpu/mpc5xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xx/u-boot.lds @@ -46,13 +46,14 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - KEEP(*(.got)) _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_)>>2; .data : diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds index eeeff6c..7e3b70a 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds @@ -41,13 +41,14 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - KEEP(*(.got)) _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : diff --git a/arch/powerpc/cpu/mpc8220/u-boot.lds b/arch/powerpc/cpu/mpc8220/u-boot.lds index 63cbbd7..72ff671 100644 --- a/arch/powerpc/cpu/mpc8220/u-boot.lds +++ b/arch/powerpc/cpu/mpc8220/u-boot.lds @@ -40,13 +40,14 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - KEEP(*(.got)) _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : diff --git a/arch/powerpc/cpu/mpc824x/u-boot.lds b/arch/powerpc/cpu/mpc824x/u-boot.lds index e7f2837..3b9299c 100644 --- a/arch/powerpc/cpu/mpc824x/u-boot.lds +++ b/arch/powerpc/cpu/mpc824x/u-boot.lds @@ -41,13 +41,14 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - KEEP(*(.got)) _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds index ad2ce37..c76555e 100644 --- a/arch/powerpc/cpu/mpc8260/u-boot.lds +++ b/arch/powerpc/cpu/mpc8260/u-boot.lds @@ -40,13 +40,14 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - KEEP(*(.got)) _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 46a706d..52d4461 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -48,11 +48,26 @@ static struct { #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES +/* private structure for mpc83xx pcie hose */ +static struct mpc83xx_pcie_priv { + u8 index; +} pcie_priv[PCIE_MAX_BUSES] = { + { + /* pcie controller 1 */ + .index = 0, + }, + { + /* pcie controller 2 */ + .index = 1, + }, +}; + static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) { int bus = PCI_BUS(dev) - hose->first_busno; immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - pex83xx_t *pex = &immr->pciexp[bus]; + struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data; + pex83xx_t *pex = &immr->pciexp[pcie_priv->index]; struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev); u32 dev_base = bus << 24 | devfn << 16; @@ -142,6 +157,8 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; + hose->priv_data = &pcie_priv[bus]; + pci_set_ops(hose, pcie_read_config_byte, pcie_read_config_word, diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 93e9f1c..5e616dd 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -161,7 +161,7 @@ int get_clocks(void) #endif } - spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT); + spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; csb_clk = pci_sync_in * (1 + clkin_div) * spmf; sccr = im->clk.sccr; @@ -392,7 +392,7 @@ int get_clocks(void) #endif lbiu_clk = csb_clk * - (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); + (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT)); lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; switch (lcrr) { case 2: @@ -406,11 +406,12 @@ int get_clocks(void) } mem_clk = csb_clk * - (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT)); - corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT; + (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT)); + corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT; + #if defined(CONFIG_MPC8360) mem_sec_clk = csb_clk * (1 + - ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT)); #endif corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); @@ -442,8 +443,8 @@ int get_clocks(void) } #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) - qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT; - qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT; + qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT; + qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT; qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); brg_clk = qe_clk / 2; #endif diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds index 81a7ace..752a175 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds @@ -39,13 +39,14 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - KEEP(*(.got)) _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 63d7923..cbb0fc6 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -50,9 +50,11 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_MPC8569) += ddr-gen3.o +COBJS-$(CONFIG_P1010) += ddr-gen3.o COBJS-$(CONFIG_P1011) += ddr-gen3.o COBJS-$(CONFIG_P1012) += ddr-gen3.o COBJS-$(CONFIG_P1013) += ddr-gen3.o +COBJS-$(CONFIG_P1014) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P1021) += ddr-gen3.o COBJS-$(CONFIG_P1022) += ddr-gen3.o @@ -66,18 +68,36 @@ COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_CORENET) += liodn.o COBJS-$(CONFIG_MP) += mp.o -COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o -COBJS-$(CONFIG_P1022) += p1022_serdes.o COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_FSL_CORENET) += portals.o # various SoC specific assignments +COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o +COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o + +# SoC specific SERDES support +COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o +COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o +COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o +COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o +COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o +COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o +COBJS-$(CONFIG_P1011) += p1021_serdes.o +COBJS-$(CONFIG_P1012) += p1021_serdes.o +COBJS-$(CONFIG_P1013) += p1022_serdes.o +COBJS-$(CONFIG_P1020) += p1021_serdes.o +COBJS-$(CONFIG_P1021) += p1021_serdes.o +COBJS-$(CONFIG_P1022) += p1022_serdes.o +COBJS-$(CONFIG_P2010) += p2020_serdes.o +COBJS-$(CONFIG_P2020) += p2020_serdes.o +COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o +COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o COBJS = $(COBJS-y) COBJS += cpu.o diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index d73f3d7..e94975a 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -47,6 +47,40 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) puts("Work-around for Erratum CPU22 enabled\n"); #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) + puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111) + puts("Work-around for Erratum ESDHC111 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135) + puts("Work-around for Erratum ESDHC135 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136) + puts("Work-around for Erratum ESDHC136 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) + puts("Work-around for Erratum ESDHC-A001 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 + puts("Work-around for Erratum CPC-A002 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 + puts("Work-around for Erratum CPC-A003 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001 + puts("Work-around for Erratum ELBC-A001 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 + puts("Work-around for Erratum DDR-A003 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 + puts("Work-around for Erratum DDR115 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + puts("Work-around for Erratum DDR111 enabled\n"); + puts("Work-around for Erratum DDR134 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index fc5d951..1aad2ba 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2004,2007-2010 Freescale Semiconductor, Inc. + * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. * (C) Copyright 2002, 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -34,6 +34,7 @@ #include <asm/io.h> #include <asm/mmu.h> #include <asm/fsl_law.h> +#include <asm/fsl_lbc.h> #include <post.h> #include <asm/processor.h> #include <asm/fsl_ddr_sdram.h> @@ -165,12 +166,14 @@ int checkcpu (void) } #endif +#if defined(CONFIG_FSL_LBC) if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } +#endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); @@ -199,7 +202,7 @@ int checkcpu (void) /* ------------------------------------------------------------------------- */ -int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[]) +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { /* Everything after the first generation of PQ3 parts has RSTCR */ #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ @@ -283,8 +286,64 @@ void mpc85xx_reginfo(void) { print_tlbcam(); print_laws(); +#if defined(CONFIG_FSL_LBC) print_lbc_regs(); +#endif + +} + +/* Common ddr init for non-corenet fsl 85xx platforms */ +#ifndef CONFIG_FSL_CORENET +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) + { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned int x = 10; + unsigned int i; + + /* + * Work around to stabilize DDR DLL + */ + out_be32(&gur->ddrdllcr, 0x81000000); + asm("sync;isync;msync"); + udelay(200); + while (in_be32(&gur->ddrdllcr) != 0x81000100) { + setbits_be32(&gur->devdisr, 0x00010000); + for (i = 0; i < x; i++) + ; + clrbits_be32(&gur->devdisr, 0x00010000); + x++; + } + } +#endif + +#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) + dram_size = fsl_ddr_sdram(); +#else + dram_size = fixed_sdram(); +#endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + +#if defined(CONFIG_FSL_LBC) + /* Some boards also have sdram on the lbc */ + lbc_sdram_init(); +#endif + + puts("DDR: "); + return dram_size; } +#endif #if CONFIG_POST & CONFIG_SYS_POST_MEMORY diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4b8faa5..8ece970 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com @@ -40,6 +40,8 @@ DECLARE_GLOBAL_DATA_PTR; +extern void srio_init(void); + #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -140,6 +142,13 @@ static void enable_cpc(void) u32 cpccfg0 = in_be32(&cpc->cpccfg0); size += CPC_CFG0_SZ_K(cpccfg0); +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 + setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 + setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); +#endif + out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); /* Read back to sync write */ in_be32(&cpc->cpccsr0); @@ -232,6 +241,12 @@ void cpu_init_f (void) invalidate_cpc(); } +/* Implement a dummy function for those platforms w/o SERDES */ +static void __fsl_serdes__init(void) +{ + return ; +} +__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); /* * Initialize L2 as cache. @@ -375,15 +390,25 @@ int cpu_init_r(void) qe_reset(); #endif -#if defined(CONFIG_SYS_HAS_SERDES) /* needs to be in ram since code uses global static vars */ fsl_serdes_init(); + +#ifdef CONFIG_SYS_SRIO + srio_init(); #endif #if defined(CONFIG_MP) setup_mp(); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136 + { + void *p; + p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; + setbits_be32(p, 1 << (31 - 14)); + } +#endif + #ifdef CONFIG_SYS_LBC_LCRR /* * Modify the CLKDIV field of LCRR register to improve the writing diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index e46dcb7..73b320b 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -9,6 +9,7 @@ #include <common.h> #include <asm/io.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/processor.h> #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL @@ -20,6 +21,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int i; volatile ccsr_ddr_t *ddr; u32 temp_sdram_cfg; +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; + u32 total_gb_size_per_controller; +#endif switch (ctrl_num) { case 0: @@ -65,6 +70,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); + out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); + out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); + out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); + out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); + out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); out_be32(&ddr->sdram_data_init, regs->ddr_data_init); @@ -79,24 +90,125 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); + out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); + out_be32(&ddr->err_disable, regs->err_disable); + out_be32(&ddr->err_int_en, regs->err_int_en); + for (i = 0; i < 32; i++) + out_be32(&ddr->debug[i], regs->debug[i]); /* Set, but do not enable the memory */ temp_sdram_cfg = regs->ddr_sdram_cfg; temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); out_be32(&ddr->sdram_cfg, temp_sdram_cfg); +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 + if (regs->ddr_sdram_rcw_2 & 0x00f00000) { + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); + out_be32(&ddr->debug[2], 0x00000400); + out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); + out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); + out_be32(&ddr->mtcr, 0); + out_be32(&ddr->debug[12], 0x00000015); + out_be32(&ddr->debug[21], 0x24000000); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); + + asm volatile("sync;isync"); + while (!(in_be32(&ddr->debug[1]) & 0x2)) + ; + + switch (regs->ddr_sdram_rcw_2 & 0x00f00000) { + case 0x00000000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); + break; + case 0x00100000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x0a)); + break; + case 0x00200000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x12)); + break; + case 0x00300000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x1a)); + break; + default: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); + printf("Unsupported RC10\n"); + break; + } + + while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) + ; + udelay(6); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->debug[2], 0x0); + out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->debug[12], 0x0); + out_be32(&ddr->debug[21], 0x0); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); + + } +#endif /* * For 8572 DDR1 erratum - DDR controller may enter illegal state * when operatiing in 32-bit bus mode with 4-beat bursts, * This erratum does not affect DDR3 mode, only for DDR2 mode. */ -#ifdef CONFIG_MPC8572 +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) && in_be32(&ddr->sdram_cfg) & 0x80000) { /* set DEBUG_1[31] */ - u32 temp = in_be32(&ddr->debug_1); - out_be32(&ddr->debug_1, temp | 1); + setbits_be32(&ddr->debug[0], 1); } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + /* + * This is the combined workaround for DDR111 and DDR134 + * following the published errata for MPC8572 + */ + + /* 1. Set EEBACR[3] */ + setbits_be32(&ecm->eebacr, 0x10000000); + debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); + + /* 2. Set DINIT in SDRAM_CFG_2*/ + setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); + debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n", + in_be32(&ddr->sdram_cfg_2)); + + /* 3. Set DEBUG_3[21] */ + setbits_be32(&ddr->debug[2], 0x400); + debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); + +#endif /* part 1 of the workaound */ /* * 500 painful micro-seconds must elapse between @@ -108,11 +220,93 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, asm volatile("sync;isync"); /* Let the controller go */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg); + temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + asm volatile("sync;isync"); /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ - while (in_be32(&ddr->sdram_cfg_2) & 0x10) { + while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) udelay(10000); /* throttle polling rate */ + +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + /* continue this workaround */ + + /* 4. Clear DEBUG3[21] */ + clrbits_be32(&ddr->debug[2], 0x400); + debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); + + /* DDR134 workaround starts */ + /* A: Clear sdram_cfg_2[odt_cfg] */ + clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); + debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n", + in_be32(&ddr->sdram_cfg_2)); + + /* B: Set DEBUG1[15] */ + setbits_be32(&ddr->debug[0], 0x10000); + debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); + + /* C: Set timing_cfg_2[cpo] to 0b11111 */ + setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); + debug("Setting TMING_CFG_2[CPO] to 0x%08x\n", + in_be32(&ddr->timing_cfg_2)); + + /* D: Set D6 to 0x9f9f9f9f */ + out_be32(&ddr->debug[5], 0x9f9f9f9f); + debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); + + /* E: Set D7 to 0x9f9f9f9f */ + out_be32(&ddr->debug[6], 0x9f9f9f9f); + debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); + + /* F: Set D2[20] */ + setbits_be32(&ddr->debug[1], 0x800); + debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); + + /* G: Poll on D2[20] until cleared */ + while (in_be32(&ddr->debug[1]) & 0x800) + udelay(10000); /* throttle polling rate */ + + /* H: Clear D1[15] */ + clrbits_be32(&ddr->debug[0], 0x10000); + debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); + + /* I: Set sdram_cfg_2[odt_cfg] */ + setbits_be32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK); + debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); + + /* Continuing with the DDR111 workaround */ + /* 5. Set D2[21] */ + setbits_be32(&ddr->debug[1], 0x400); + debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); + + /* 6. Poll D2[21] until its cleared */ + while (in_be32(&ddr->debug[1]) & 0x400) + udelay(10000); /* throttle polling rate */ + + /* 7. Wait for 400ms/GB */ + total_gb_size_per_controller = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + total_gb_size_per_controller += + ((regs->cs[i].bnds & 0xFFFF) >> 6) + - (regs->cs[i].bnds >> 22) + 1; } + if (in_be32(&ddr->sdram_cfg) & 0x80000) + total_gb_size_per_controller <<= 1; + debug("Wait for %d ms\n", total_gb_size_per_controller * 400); + udelay(total_gb_size_per_controller * 400000); + + /* 8. Set sdram_cfg_2[dinit] if options requires */ + setbits_be32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT); + debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); + + /* 9. Poll until dinit is cleared */ + while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) + udelay(10000); + + /* 10. Clear EEBACR[3] */ + clrbits_be32(&ecm->eebacr, 10000000); + debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); +#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ } diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 53e0596..00fa752 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; extern void ft_qe_setup(void *blob); extern void ft_fixup_num_cores(void *blob); +extern void ft_srio_setup(void *blob); #ifdef CONFIG_MP #include "mp.h" @@ -478,4 +479,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_qportals(blob); #endif + +#ifdef CONFIG_SYS_SRIO + ft_srio_setup(blob); +#endif } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 5bcf91a..7fc00d8 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -33,6 +33,8 @@ static u32 serdes_prtcl_map; +#define HWCONFIG_BUFFER_SIZE 128 + #ifdef DEBUG static const char *serdes_prtcl_str[] = { [NONE] = "NA", @@ -277,6 +279,15 @@ void fsl_serdes_init(void) const char *srds_lpd_arg; size_t arglen; #endif + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + + /* + * Extract hwconfig from environment since we have not properly setup + * the environment but need it for ddr config params + */ + if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + buf = buffer; /* Is serdes enabled at all? */ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) @@ -295,8 +306,8 @@ void fsl_serdes_init(void) if (!IS_SVR_REV(get_svr(), 1, 0)) for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1); - srds_lpd_arg = hwconfig_subarg("serdes", srds_lpd_opt, - &arglen); + srds_lpd_arg = hwconfig_subarg_f("serdes", srds_lpd_opt, + &arglen, buf); if (srds_lpd_arg) srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg, NULL, 0); diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c new file mode 100644 index 0000000..7c49097 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c @@ -0,0 +1,95 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 8 +#define SRDS2_MAX_LANES 4 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, + [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, +}; + +static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x1] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3}, + [0x3] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3}, + [0x5] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3}, + [0x6] = {PCIE3, NONE, NONE, NONE}, + [0x7] = {PCIE3, NONE, SGMII_TSEC1, SGMII_TSEC3}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } + + if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) + serdes2_prtcl_map &= ~(1 << SGMII_TSEC1); + + if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS) + serdes2_prtcl_map &= ~(1 << SGMII_TSEC3); +} diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c new file mode 100644 index 0000000..76288cd --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c @@ -0,0 +1,65 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 8 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg); + + if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg); + return ; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c new file mode 100644 index 0000000..2582637 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c @@ -0,0 +1,65 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 8 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c new file mode 100644 index 0000000..f480c26 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c @@ -0,0 +1,74 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x0] = {PCIE1, NONE, NONE, NONE}, + [0x1] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2}, + [0x2] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2}, + [0x3] = {SRIO1, SRIO2, NONE, NONE}, + [0x4] = {PCIE1, NONE, SGMII_TSEC1, SGMII_TSEC2}, + [0x5] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x6] = {PCIE1, NONE, SRIO1, SRIO2}, + [0x7] = {PCIE1, PCIE1, SRIO1, SRIO2}, + [0x8] = {PCIE1, PCIE1, SRIO1, SRIO2}, + [0x9] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xa] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xb] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xc] = {PCIE1, SRIO1, SGMII_TSEC1, SGMII_TSEC2}, + [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c new file mode 100644 index 0000000..2ff5d9a --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c @@ -0,0 +1,81 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 8 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3}, + [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0xc] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0xd] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0xe] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + serdes1_prtcl_map |= (1 << SGMII_TSEC1); + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + serdes1_prtcl_map |= (1 << SGMII_TSEC2); + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + serdes1_prtcl_map |= (1 << SGMII_TSEC3); + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) + serdes1_prtcl_map |= (1 << SGMII_TSEC4); +} diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c new file mode 100644 index 0000000..457ab5d --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c @@ -0,0 +1,64 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x0] = {PCIE1, NONE, NONE, NONE}, + [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, + [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c new file mode 100644 index 0000000..389ff6b --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c @@ -0,0 +1,73 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x0] = {PCIE1, NONE, NONE, NONE}, + [0x2] = {PCIE1, PCIE2, PCIE3, PCIE3}, + [0x4] = {PCIE1, PCIE1, PCIE3, PCIE3}, + [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x7] = {SRIO2, SRIO1, NONE, NONE}, + [0x8] = {SRIO2, SRIO2, SRIO2, SRIO2}, + [0x9] = {SRIO2, SRIO2, SRIO2, SRIO2}, + [0xa] = {SRIO2, SRIO2, SRIO2, SRIO2}, + [0xb] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3}, + [0xc] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3}, + [0xd] = {PCIE1, SRIO1, SGMII_TSEC2, SGMII_TSEC3}, + [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, + [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c b/arch/powerpc/cpu/mpc85xx/p2040_serdes.c new file mode 100644 index 0000000..a96eff4 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p2040_serdes.c @@ -0,0 +1,66 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> +#include "fsl_corenet_serdes.h" + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, + [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, + [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1, + SATA2, NONE, NONE, NONE, NONE, }, + [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3, + PCIE3, NONE, NONE, NONE, NONE, }, + [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, + SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, + [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, + NONE, NONE, NONE, }, + [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, + NONE, NONE, NONE, }, + [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, + SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, + NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, + [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA, + SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, }, +}; + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c new file mode 100644 index 0000000..febbee9 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -0,0 +1,105 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO( 1, 2, 1, 0), + SET_QP_INFO( 3, 4, 2, 1), + SET_QP_INFO( 5, 6, 3, 2), + SET_QP_INFO( 7, 8, 4, 3), + SET_QP_INFO( 9, 10, 5, 4), + SET_QP_INFO( 0, 0, 0, 5), + SET_QP_INFO( 0, 0, 0, 6), + SET_QP_INFO( 0, 0, 0, 7), + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ +}; + +struct liodn_id_table liodn_tbl[] = { + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), + + SET_SDHC_LIODN(1, 64), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 125), + SET_USB_LIODN(2, "fsl-usb2-dr", 126), + + SET_SATA_LIODN(1, 127), + SET_SATA_LIODN(2, 128), + + SET_PCI_LIODN(1, 193), + SET_PCI_LIODN(2, 194), + SET_PCI_LIODN(3, 195), + SET_PCI_LIODN(4, 196), + + SET_DMA_LIODN(1, 197), + SET_DMA_LIODN(2, 198), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), +}; + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 10), + SET_FMAN_RX_1G_LIODN(1, 1, 11), + SET_FMAN_RX_1G_LIODN(1, 2, 12), + SET_FMAN_RX_1G_LIODN(1, 3, 13), + SET_FMAN_RX_1G_LIODN(1, 4, 14), + SET_FMAN_RX_10G_LIODN(1, 0, 15), +}; +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 129, 130), + SET_SEC_JR_LIODN_ENTRY(1, 131, 132), + SET_SEC_JR_LIODN_ENTRY(2, 133, 134), + SET_SEC_JR_LIODN_ENTRY(3, 135, 136), + SET_SEC_RTIC_LIODN_ENTRY(a, 154), + SET_SEC_RTIC_LIODN_ENTRY(b, 155), + SET_SEC_RTIC_LIODN_ENTRY(c, 156), + SET_SEC_RTIC_LIODN_ENTRY(d, 157), + SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), + SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), +}; + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), +#endif +}; + +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c new file mode 100644 index 0000000..fba9ff2 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c @@ -0,0 +1,151 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> +#include "fsl_corenet_serdes.h" + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, }, + [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, }, + [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1, + SRIO1, }, + [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, + SATA1, SATA2, }, + [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, }, + [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, }, + [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, + [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, }, + [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, +}; + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(u32 prtcl) { + int i; + + if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c new file mode 100644 index 0000000..febbee9 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -0,0 +1,105 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO( 1, 2, 1, 0), + SET_QP_INFO( 3, 4, 2, 1), + SET_QP_INFO( 5, 6, 3, 2), + SET_QP_INFO( 7, 8, 4, 3), + SET_QP_INFO( 9, 10, 5, 4), + SET_QP_INFO( 0, 0, 0, 5), + SET_QP_INFO( 0, 0, 0, 6), + SET_QP_INFO( 0, 0, 0, 7), + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ + SET_QP_INFO( 0, 0, 0, 0), /* for now sdest to 0 */ +}; + +struct liodn_id_table liodn_tbl[] = { + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), + + SET_SDHC_LIODN(1, 64), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 125), + SET_USB_LIODN(2, "fsl-usb2-dr", 126), + + SET_SATA_LIODN(1, 127), + SET_SATA_LIODN(2, 128), + + SET_PCI_LIODN(1, 193), + SET_PCI_LIODN(2, 194), + SET_PCI_LIODN(3, 195), + SET_PCI_LIODN(4, 196), + + SET_DMA_LIODN(1, 197), + SET_DMA_LIODN(2, 198), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), +}; + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 10), + SET_FMAN_RX_1G_LIODN(1, 1, 11), + SET_FMAN_RX_1G_LIODN(1, 2, 12), + SET_FMAN_RX_1G_LIODN(1, 3, 13), + SET_FMAN_RX_1G_LIODN(1, 4, 14), + SET_FMAN_RX_10G_LIODN(1, 0, 15), +}; +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 129, 130), + SET_SEC_JR_LIODN_ENTRY(1, 131, 132), + SET_SEC_JR_LIODN_ENTRY(2, 133, 134), + SET_SEC_JR_LIODN_ENTRY(3, 135, 136), + SET_SEC_RTIC_LIODN_ENTRY(a, 154), + SET_SEC_RTIC_LIODN_ENTRY(b, 155), + SET_SEC_RTIC_LIODN_ENTRY(c, 156), + SET_SEC_RTIC_LIODN_ENTRY(d, 157), + SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), + SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), +}; + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), +#endif +}; + +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/p5020_serdes.c b/arch/powerpc/cpu/mpc85xx/p5020_serdes.c new file mode 100644 index 0000000..fba9ff2 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p5020_serdes.c @@ -0,0 +1,151 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> +#include "fsl_corenet_serdes.h" + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, }, + [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, }, + [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1, + SRIO1, }, + [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, + SATA1, SATA2, }, + [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, }, + [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, }, + [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, + [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, }, + [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, +}; + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(u32 prtcl) { + int i; + + if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index dd4c6b3..f2aa8d0 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) @@ -131,7 +131,9 @@ void get_sys_info (sys_info_t * sysInfo) #else uint plat_ratio,e500_ratio,half_freqSystemBus; +#if defined(CONFIG_FSL_LBC) uint lcrr_div; +#endif int i; #ifdef CONFIG_QE u32 qe_ratio; @@ -168,6 +170,7 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; #endif +#if defined(CONFIG_FSL_LBC) #if defined(CONFIG_SYS_LBC_LCRR) /* We will program LCRR to this value later */ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; @@ -193,6 +196,7 @@ void get_sys_info (sys_info_t * sysInfo) /* In case anyone cares what the unknown value is */ sysInfo->freqLocalBus = lcrr_div; } +#endif } diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 945c1b8..fa98af6 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -753,7 +753,7 @@ dcache_disable: lis r4,0 ori r4,r4,L1CSR0_DCE andc r3,r3,r4 - mtspr L1CSR0,r0 + mtspr L1CSR0,r3 isync blr diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index e3a71ae..31143ba 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -250,10 +250,14 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { int i; unsigned int tlb_size; + unsigned int wimge = 0; unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; u64 size, memsize = (u64)memsize_in_meg << 20; +#ifdef CONFIG_SYS_PPC_DDR_WIMGE + wimge = CONFIG_SYS_PPC_DDR_WIMGE; +#endif size = min(memsize, CONFIG_MAX_MEM_MAPPED); /* Convert (4^max) kB to (2^max) bytes */ @@ -277,7 +281,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) tlb_size = (camsize - 10) / 2; set_tlb(1, ram_tlb_address, p_addr, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, wimge, 0, ram_tlb_index, tlb_size, 1); size -= 1ULL << camsize; diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 85042c5..506c7f2 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2009, 2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -20,7 +20,11 @@ * MA 02111-1307 USA */ -#ifndef RESET_VECTOR_ADDRESS +#include "config.h" /* CONFIG_BOARDDIR */ + +#ifdef CONFIG_RESET_VECTOR_ADDRESS +#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS +#else #define RESET_VECTOR_ADDRESS 0xfffffffc #endif @@ -54,13 +58,14 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - KEEP(*(.got)) _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile index 5b7d80a..b4ef286 100644 --- a/arch/powerpc/cpu/mpc86xx/Makefile +++ b/arch/powerpc/cpu/mpc86xx/Makefile @@ -42,6 +42,8 @@ COBJS-$(CONFIG_MPC8641) += ddr-8641.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-y += interrupts.o COBJS-$(CONFIG_MP) += mp.o +COBJS-$(CONFIG_MPC8610) += mpc8610_serdes.o +COBJS-$(CONFIG_MPC8641) += mpc8641_serdes.o COBJS-y += speed.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c index 4e90fd2..ffcc8e6 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu.c +++ b/arch/powerpc/cpu/mpc86xx/cpu.c @@ -123,8 +123,7 @@ checkcpu(void) } -void -do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; @@ -137,6 +136,8 @@ do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) while (1) ; + + return 1; } diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c index 82c216b..8022024 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc86xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2004,2009 Freescale Semiconductor, Inc. + * Copyright 2004,2009-2011 Freescale Semiconductor, Inc. * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -31,8 +31,10 @@ #include <mpc86xx.h> #include <asm/mmu.h> #include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> #include <asm/mp.h> +extern void srio_init(void); void setup_bats(void); DECLARE_GLOBAL_DATA_PTR; @@ -76,6 +78,13 @@ void cpu_init_f(void) */ int cpu_init_r(void) { + /* needs to be in ram since code uses global static vars */ + fsl_serdes_init(); + +#ifdef CONFIG_SYS_SRIO + srio_init(); +#endif + #if defined(CONFIG_MP) setup_mp(); #endif diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index ff89ee5..61f5110 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2008,2010 Freescale Semiconductor, Inc. + * Copyright 2008, 2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -14,6 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; extern void ft_fixup_num_cores(void *blob); +extern void ft_srio_setup(void *blob); void ft_cpu_setup(void *blob, bd_t *bd) { @@ -58,4 +59,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) ft_fixup_num_cores(blob); #endif + +#ifdef CONFIG_SYS_SRIO + ft_srio_setup(blob); +#endif } diff --git a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c new file mode 100644 index 0000000..0dc1975 --- /dev/null +++ b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c @@ -0,0 +1,85 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_86xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 4 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x1] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x7] = {NONE, NONE, NONE, NONE}, +}; + +static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x0] = {PCIE2, PCIE2, PCIE2, PCIE2}, + [0x4] = {PCIE2, PCIE2, PCIE2, PCIE2}, + [0x7] = {NONE, NONE, NONE, NONE}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; + ccsr_gur_t *gur = &immap->im_gur; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC8610_PORDEVSR_IO_SEL) >> + MPC8610_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c new file mode 100644 index 0000000..3ae9069 --- /dev/null +++ b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c @@ -0,0 +1,94 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_86xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 4 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x3] = {PCIE2, PCIE2, PCIE2, PCIE2}, + [0x5] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0x6] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0x7] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0x9] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xa] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xb] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xe] = {PCIE2, PCIE2, PCIE2, PCIE2}, + [0xf] = {PCIE2, PCIE2, PCIE2, PCIE2}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; + ccsr_gur_t *gur = &immap->im_gur; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC8641_PORDEVSR_IO_SEL) >> + MPC8641_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds index 49a4c78..c550ef5 100644 --- a/arch/powerpc/cpu/mpc86xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds @@ -45,13 +45,14 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - KEEP(*(.got)) _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index d4abeb1..a2d2bd6 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -888,14 +888,14 @@ static int mii_discover_phy(struct eth_device *dev) udelay(10000); /* wait 10ms */ } for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2)); #ifdef ET_DEBUG printf("PHY type 0x%x pass %d type ", phytype, pass); #endif if (phytype != 0xffff) { phyaddr = phyno; phytype |= mii_send(mk_mii_read(phyno, - PHY_PHYIDR1)) << 16; + MII_PHYSID1)) << 16; #ifdef ET_DEBUG printf("PHY @ 0x%x pass %d type ",phyno,pass); diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index ab80dd7..5dfd65b 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -12,11 +12,11 @@ LIB = $(obj)lib8xxx.o ifneq ($(CPU),mpc83xx) COBJS-y += cpu.o -COBJS-$(CONFIG_PCI) += pci_cfg.o endif COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o +COBJS-$(CONFIG_SYS_SRIO) += srio.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 5b30fbd..4335fb4 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains @@ -64,11 +64,15 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(8569, 8569_E, 1), CPU_TYPE_ENTRY(8572, 8572, 2), CPU_TYPE_ENTRY(8572, 8572_E, 2), + CPU_TYPE_ENTRY(P1010, P1010, 1), + CPU_TYPE_ENTRY(P1010, P1010_E, 1), CPU_TYPE_ENTRY(P1011, P1011, 1), CPU_TYPE_ENTRY(P1011, P1011_E, 1), CPU_TYPE_ENTRY(P1012, P1012, 1), CPU_TYPE_ENTRY(P1012, P1012_E, 1), CPU_TYPE_ENTRY(P1013, P1013, 1), + CPU_TYPE_ENTRY(P1014, P1014_E, 1), + CPU_TYPE_ENTRY(P1014, P1014, 1), CPU_TYPE_ENTRY(P1013, P1013_E, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), CPU_TYPE_ENTRY(P1020, P1020_E, 2), @@ -80,6 +84,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), CPU_TYPE_ENTRY(P2020, P2020_E, 2), + CPU_TYPE_ENTRY(P2040, P2040, 4), + CPU_TYPE_ENTRY(P2040, P2040_E, 4), CPU_TYPE_ENTRY(P3041, P3041, 4), CPU_TYPE_ENTRY(P3041, P3041_E, 4), CPU_TYPE_ENTRY(P4040, P4040, 4), diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 3fec100..936c195 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free @@ -18,7 +18,28 @@ #include "ddr.h" -extern unsigned int picos_to_mclk(unsigned int picos); +#ifdef CONFIG_MPC85xx + #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR +#elif defined(CONFIG_MPC86xx) + #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR +#else + #error "Undefined _DDR_ADDR" +#endif + +u32 fsl_ddr_get_version(void) +{ + ccsr_ddr_t *ddr; + u32 ver_major_minor_errata; + + ddr = (void *)_DDR_ADDR; + ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8; + ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8; + + return ver_major_minor_errata; +} + +unsigned int picos_to_mclk(unsigned int picos); + /* * Determine Rtt value. * @@ -187,7 +208,8 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) * Avoid writing for DDR I. The new PQ38 DDR controller * dreams up non-zero default values to be backwards compatible. */ -static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) +static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) { unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ @@ -204,7 +226,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) /* Mode register set cycle time (tMRD). */ unsigned char tmrd_mclk; -#if defined(CONFIG_FSL_DDR3) +#ifdef CONFIG_FSL_DDR3 /* * (tXARD and tXARDS). Empirical? * The DDR3 spec has not tXARD, @@ -214,13 +236,24 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) * tAXPD=1, need design to confirm. */ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ - act_pd_exit_mclk = picos_to_mclk(tXP); - /* Mode register MR0[A12] is '1' - fast exit */ - pre_pd_exit_mclk = act_pd_exit_mclk; - taxpd_mclk = 1; + unsigned int data_rate = fsl_ddr_get_mem_data_rate(); tmrd_mclk = 4; /* set the turnaround time */ trwt_mclk = 1; + if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) + twrt_mclk = 1; + + if (popts->dynamic_power == 0) { /* powerdown is not used */ + act_pd_exit_mclk = 1; + pre_pd_exit_mclk = 1; + taxpd_mclk = 1; + } else { + /* act_pd_exit_mclk = tXARD, see above */ + act_pd_exit_mclk = picos_to_mclk(tXP); + /* Mode register MR0[A12] is '1' - fast exit */ + pre_pd_exit_mclk = act_pd_exit_mclk; + taxpd_mclk = 1; + } #else /* CONFIG_FSL_DDR2 */ /* * (tXARD and tXARDS). Empirical? @@ -450,28 +483,34 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, /* DDR SDRAM Register Control Word */ static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, const common_timing_params_t *common_dimm) { if (common_dimm->all_DIMMs_registered && !common_dimm->all_DIMMs_unbuffered) { - ddr->ddr_sdram_rcw_1 = - common_dimm->rcw[0] << 28 | \ - common_dimm->rcw[1] << 24 | \ - common_dimm->rcw[2] << 20 | \ - common_dimm->rcw[3] << 16 | \ - common_dimm->rcw[4] << 12 | \ - common_dimm->rcw[5] << 8 | \ - common_dimm->rcw[6] << 4 | \ - common_dimm->rcw[7]; - ddr->ddr_sdram_rcw_2 = - common_dimm->rcw[8] << 28 | \ - common_dimm->rcw[9] << 24 | \ - common_dimm->rcw[10] << 20 | \ - common_dimm->rcw[11] << 16 | \ - common_dimm->rcw[12] << 12 | \ - common_dimm->rcw[13] << 8 | \ - common_dimm->rcw[14] << 4 | \ - common_dimm->rcw[15]; + if (popts->rcw_override) { + ddr->ddr_sdram_rcw_1 = popts->rcw_1; + ddr->ddr_sdram_rcw_2 = popts->rcw_2; + } else { + ddr->ddr_sdram_rcw_1 = + common_dimm->rcw[0] << 28 | \ + common_dimm->rcw[1] << 24 | \ + common_dimm->rcw[2] << 20 | \ + common_dimm->rcw[3] << 16 | \ + common_dimm->rcw[4] << 12 | \ + common_dimm->rcw[5] << 8 | \ + common_dimm->rcw[6] << 4 | \ + common_dimm->rcw[7]; + ddr->ddr_sdram_rcw_2 = + common_dimm->rcw[8] << 28 | \ + common_dimm->rcw[9] << 24 | \ + common_dimm->rcw[10] << 20 | \ + common_dimm->rcw[11] << 16 | \ + common_dimm->rcw[12] << 12 | \ + common_dimm->rcw[13] << 8 | \ + common_dimm->rcw[14] << 4 | \ + common_dimm->rcw[15]; + } debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1); debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2); } @@ -509,8 +548,14 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, ecc_en = 0; } - rd_en = (common_dimm->all_DIMMs_registered - && !common_dimm->all_DIMMs_unbuffered); + if (common_dimm->all_DIMMs_registered + && !common_dimm->all_DIMMs_unbuffered) { + rd_en = 1; + twoT_en = 0; + } else { + rd_en = 0; + twoT_en = popts->twoT_en; + } sdram_type = CONFIG_FSL_SDRAM_TYPE; @@ -530,7 +575,6 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, } threeT_en = popts->threeT_en; - twoT_en = popts->twoT_en; ba_intlv_ctl = popts->ba_intlv_ctl; hse = popts->half_strength_driver_enable; @@ -558,7 +602,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) + const memctl_options_t *popts, + const unsigned int unq_mrs_en) { unsigned int frc_sr = 0; /* Force self refresh */ unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ @@ -598,11 +643,17 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, obc_cfg = 0; #endif - ap_en = 0; /* Make this configurable? */ + if (popts->registered_dimm_en) { + rcw_en = 1; + ap_en = popts->ap_en; + } else { + rcw_en = 0; + ap_en = 0; + } #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* Use the DDR controller to auto initialize memory. */ - d_init = 1; + d_init = popts->ECC_init_using_memctl; ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); #else @@ -613,7 +664,6 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_FSL_DDR3) md_en = popts->mirrored_dimm; #endif - rcw_en = popts->registered_dimm_en; qd_en = popts->quad_rank_present ? 1 : 0; ddr->ddr_sdram_cfg_2 = (0 | ((frc_sr & 0x1) << 31) @@ -623,6 +673,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((odt_cfg & 0x3) << 21) | ((num_pr & 0xf) << 12) | (qd_en << 9) + | (unq_mrs_en << 8) | ((obc_cfg & 0x1) << 6) | ((ap_en & 0x1) << 5) | ((d_init & 0x1) << 4) @@ -634,12 +685,14 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) + const memctl_options_t *popts, + const unsigned int unq_mrs_en) { unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ #if defined(CONFIG_FSL_DDR3) + int i; unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ unsigned int srt = 0; /* self-refresh temerature, normal range */ unsigned int asr = 0; /* auto self-refresh disable */ @@ -648,7 +701,8 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, if (popts->rtt_override) rtt_wr = popts->rtt_wr_override_value; - + else + rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; esdmode2 = (0 | ((rtt_wr & 0x3) << 9) | ((srt & 0x1) << 7) @@ -661,6 +715,46 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, | ((esdmode3 & 0xFFFF) << 0) ); debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); + +#ifdef CONFIG_FSL_DDR3 + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < 4; i++) { + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + else + rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; + + esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ + esdmode2 |= (rtt_wr & 0x3) << 9; + switch (i) { + case 1: + ddr->ddr_sdram_mode_4 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_6 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_8 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", + ddr->ddr_sdram_mode_4); + debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", + ddr->ddr_sdram_mode_6); + debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", + ddr->ddr_sdram_mode_8); + } +#endif } /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ @@ -689,7 +783,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, - unsigned int additive_latency) + unsigned int additive_latency, + const unsigned int unq_mrs_en) { unsigned short esdmode; /* Extended SDRAM mode */ unsigned short sdmode; /* SDRAM mode */ @@ -700,7 +795,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, unsigned int rtt; unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ unsigned int al = 0; /* Posted CAS# additive latency (AL) */ - unsigned int dic = 1; /* Output driver impedance, 34ohm */ + unsigned int dic = 0; /* Output driver impedance, 40ohm */ unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), 1=Disable (Test/Debug) */ @@ -717,16 +812,21 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, unsigned int wr_mclk; const unsigned int mclk_ps = get_memory_clk_period_ps(); + int i; - rtt = fsl_ddr_get_rtt(); if (popts->rtt_override) rtt = popts->rtt_override_value; + else + rtt = popts->cs_local_opts[0].odt_rtt_norm; if (additive_latency == (cas_latency - 1)) al = 1; if (additive_latency == (cas_latency - 2)) al = 2; + if (popts->quad_rank_present) + dic = 1; /* output driver impedance 240/7 ohm */ + /* * The esdmode value will also be used for writing * MR1 during write leveling for DDR3, although the @@ -812,6 +912,48 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, ); debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); + + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < 4; i++) { + if (popts->rtt_override) + rtt = popts->rtt_override_value; + else + rtt = popts->cs_local_opts[i].odt_rtt_norm; + + esdmode &= 0xFDBB; /* clear bit 9,6,2 */ + esdmode |= (0 + | ((rtt & 0x4) << 7) /* rtt field is split */ + | ((rtt & 0x2) << 5) /* rtt field is split */ + | ((rtt & 0x1) << 2) /* rtt field is split */ + ); + switch (i) { + case 1: + ddr->ddr_sdram_mode_3 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_5 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_7 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", + ddr->ddr_sdram_mode_3); + debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", + ddr->ddr_sdram_mode_5); + debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", + ddr->ddr_sdram_mode_5); + } } #else /* !CONFIG_FSL_DDR3 */ @@ -821,7 +963,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, - unsigned int additive_latency) + unsigned int additive_latency, + const unsigned int unq_mrs_en) { unsigned short esdmode; /* Extended SDRAM mode */ unsigned short sdmode; /* SDRAM mode */ @@ -1024,7 +1167,7 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, } /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ -static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr) +static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) { unsigned int rodt_on = 0; /* Read to ODT on */ unsigned int rodt_off = 0; /* Read to ODT off */ @@ -1032,7 +1175,8 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr) unsigned int wodt_off = 0; /* Write to ODT off */ #if defined(CONFIG_FSL_DDR3) - rodt_on = 2; /* 2 clocks */ + /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */ + rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1; rodt_off = 4; /* 4 clocks */ wodt_on = 1; /* 1 clocks */ wodt_off = 4; /* 4 clocks */ @@ -1068,6 +1212,7 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) | ((zqoper & 0xF) << 16) | ((zqcs & 0xF) << 8) ); + debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); } /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ @@ -1113,7 +1258,8 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, /* * Write leveling start time * The value use for the DQS_ADJUST for the first sample - * when write leveling is enabled. + * when write leveling is enabled. It probably needs to be + * overriden per platform. */ wrlvl_start = 0x8; /* @@ -1135,6 +1281,7 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, | ((wrlvl_wlr & 0x7) << 8) | ((wrlvl_start & 0x1F) << 0) ); + debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); } /* DDR Self Refresh Counter (DDR_SR_CNTR) */ @@ -1152,6 +1299,12 @@ static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) } } +static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) +{ + ddr->ddr_cdr1 = popts->ddr_cdr1; + debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); +} + unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) { @@ -1176,7 +1329,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_params, - unsigned int dbw_cap_adj) + unsigned int dbw_cap_adj, + unsigned int size_only) { unsigned int i; unsigned int cas_latency; @@ -1184,6 +1338,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, unsigned int sr_it; unsigned int zq_en; unsigned int wrlvl_en; + unsigned int ip_rev = 0; + unsigned int unq_mrs_en = 0; int cs_en = 1; memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); @@ -1394,10 +1550,17 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, printf("CS%d is disabled.\n", i); } + /* + * In the case we only need to compute the ddr sdram size, we only need + * to set csn registers, so return from here. + */ + if (size_only) + return 0; + set_ddr_eor(ddr, popts); #if !defined(CONFIG_FSL_DDR1) - set_timing_cfg_0(ddr); + set_timing_cfg_0(ddr, popts); #endif set_timing_cfg_3(ddr, common_dimm, cas_latency); @@ -1405,26 +1568,30 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_timing_cfg_2(ddr, popts, common_dimm, cas_latency, additive_latency); + set_ddr_cdr1(ddr, popts); set_ddr_sdram_cfg(ddr, popts, common_dimm); + ip_rev = fsl_ddr_get_version(); + if (ip_rev > 0x40400) + unq_mrs_en = 1; - set_ddr_sdram_cfg_2(ddr, popts); + set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en); set_ddr_sdram_mode(ddr, popts, common_dimm, - cas_latency, additive_latency); - set_ddr_sdram_mode_2(ddr, popts); + cas_latency, additive_latency, unq_mrs_en); + set_ddr_sdram_mode_2(ddr, popts, unq_mrs_en); set_ddr_sdram_interval(ddr, popts, common_dimm); set_ddr_data_init(ddr); set_ddr_sdram_clk_cntl(ddr, popts); set_ddr_init_addr(ddr); set_ddr_init_ext_addr(ddr); set_timing_cfg_4(ddr, popts); - set_timing_cfg_5(ddr); + set_timing_cfg_5(ddr, cas_latency); set_ddr_zq_cntl(ddr, zq_en); set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); set_ddr_sr_cntr(ddr, sr_it); - set_ddr_sdram_rcw(ddr, common_dimm); + set_ddr_sdram_rcw(ddr, popts, common_dimm); return check_fsl_memctl_config_regs(ddr); } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index 98acb8d..c7c12c1 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -55,7 +55,8 @@ typedef struct { #define STEP_ALL 0xFFF extern unsigned long long -fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step); +fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, + unsigned int size_only); extern const char * step_to_string(unsigned int step); @@ -64,7 +65,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_parameters, - unsigned int dbw_capacity_adjust); + unsigned int dbw_capacity_adjust, + unsigned int size_only); extern unsigned int compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, @@ -78,5 +80,5 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo); extern unsigned int mclk_to_picos(unsigned int mclk); extern unsigned int get_memory_clk_period_ps(void); extern unsigned int picos_to_mclk(unsigned int picos); - +extern unsigned int fsl_ddr_get_mem_data_rate(void); #endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index 029e566..a58e5a9 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -98,7 +98,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, unsigned int tDQSQ_max_ps = 0; unsigned int tQHS_ps = 0; - unsigned int temp1, temp2, temp3; + unsigned int temp1, temp2; unsigned int additive_latency = 0; #if !defined(CONFIG_FSL_DDR3) const unsigned int mclk_ps = get_memory_clk_period_ps(); @@ -215,18 +215,14 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, } outpdimm->all_DIMMs_registered = 0; + outpdimm->all_DIMMs_unbuffered = 0; if (temp1 && !temp2) { outpdimm->all_DIMMs_registered = 1; - } - - outpdimm->all_DIMMs_unbuffered = 0; - if (!temp1 && temp2) { + printf("Detected RDIMM(s)\n"); + } else if (!temp1 && temp2) { outpdimm->all_DIMMs_unbuffered = 1; - } - - /* CHECKME: */ - if (!outpdimm->all_DIMMs_registered - && !outpdimm->all_DIMMs_unbuffered) { + printf("Detected UDIMM(s)\n"); + } else { printf("ERROR: Mix of registered buffered and unbuffered " "DIMMs detected!\n"); } @@ -237,7 +233,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, outpdimm->rcw[j] = dimm_params[0].rcw[j]; for (i = 1; i < number_of_dimms; i++) if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) { - temp3 = 1; + temp1 = 1; break; } } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 6d582e9..bb96d66 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -233,7 +233,8 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, } unsigned long long -fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step) +fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, + unsigned int size_only) { unsigned int i, j; unsigned int all_controllers_memctl_interleaving = 0; @@ -338,7 +339,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step) &pinfo->memctl_opts[i], &ddr_reg[i], &timing_params[i], pinfo->dimm_params[i], - dbw_capacity_adjust[i]); + dbw_capacity_adjust[i], + size_only); } default: @@ -405,7 +407,7 @@ phys_size_t fsl_ddr_sdram(void) memset(&info, 0, sizeof(fsl_ddr_info_t)); /* Compute it once normally. */ - total_memory = fsl_ddr_compute(&info, STEP_GET_SPD); + total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); /* Check for memory controller interleaving. */ memctl_interleaved = 0; @@ -430,7 +432,8 @@ phys_size_t fsl_ddr_sdram(void) info.memctl_opts[i].memctl_interleaving = 0; debug("Recomputing with memctl_interleaving off.\n"); total_memory = fsl_ddr_compute(&info, - STEP_ASSIGN_ADDRESSES); + STEP_ASSIGN_ADDRESSES, + 0); } } @@ -469,11 +472,30 @@ phys_size_t fsl_ddr_sdram(void) /* Check for 4G or more. Bad. */ if (total_memory >= (1ull << 32)) { printf("Detected %lld MB of memory\n", total_memory >> 20); - printf("This U-Boot only supports < 4G of DDR\n"); - printf("You could rebuild it with CONFIG_PHYS_64BIT\n"); + printf(" This U-Boot only supports < 4G of DDR\n"); + printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); + printf(" "); /* re-align to match init_func_ram print */ total_memory = CONFIG_MAX_MEM_MAPPED; } #endif return total_memory; } + +/* + * fsl_ddr_sdram_size() - This function only returns the size of the total + * memory without setting ddr control registers. + */ +phys_size_t +fsl_ddr_sdram_size(void) +{ + fsl_ddr_info_t info; + unsigned long long total_memory = 0; + + memset(&info, 0 , sizeof(fsl_ddr_info_t)); + + /* Compute it once normally. */ + total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); + + return total_memory; +} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 774c0e4..6ccc3b0 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -1,5 +1,5 @@ /* - * Copyright 2008, 2010 Freescale Semiconductor, Inc. + * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free @@ -13,28 +13,338 @@ #include "ddr.h" +/* + * Use our own stack based buffer before relocation to allow accessing longer + * hwconfig strings that might be in the environment before we've relocated. + * This is pretty fragile on both the use of stack and if the buffer is big + * enough. However we will get a warning from getenv_f for the later. + */ +#define HWCONFIG_BUFFER_SIZE 128 + /* Board-specific functions defined in each board's ddr.c */ extern void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num); +typedef struct { + unsigned int odt_rd_cfg; + unsigned int odt_wr_cfg; + unsigned int odt_rtt_norm; + unsigned int odt_rtt_wr; +} dynamic_odt_t; + +static const dynamic_odt_t single_Q[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS_AND_OTHER_DIMM, + DDR3_RTT_20_OHM, + DDR3_RTT_120_OHM + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, /* tied high */ + DDR3_RTT_OFF, + DDR3_RTT_120_OHM + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS_AND_OTHER_DIMM, + DDR3_RTT_20_OHM, + DDR3_RTT_120_OHM + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, /* tied high */ + DDR3_RTT_OFF, + DDR3_RTT_120_OHM + } +}; + +static const dynamic_odt_t single_D[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR3_RTT_OFF, + DDR3_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static const dynamic_odt_t single_S[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0}, +}; + +static const dynamic_odt_t dual_DD[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR3_RTT_30_OHM, + DDR3_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR3_RTT_30_OHM, + DDR3_RTT_OFF + } +}; + +static const dynamic_odt_t dual_DS[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR3_RTT_30_OHM, + DDR3_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR3_RTT_20_OHM, + DDR3_RTT_120_OHM + }, + {0, 0, 0, 0} +}; +static const dynamic_odt_t dual_SD[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR3_RTT_20_OHM, + DDR3_RTT_120_OHM + }, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR3_RTT_20_OHM, + DDR3_RTT_OFF + } +}; + +static const dynamic_odt_t dual_SS[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR3_RTT_30_OHM, + DDR3_RTT_120_OHM + }, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR3_RTT_30_OHM, + DDR3_RTT_120_OHM + }, + {0, 0, 0, 0} +}; + +static const dynamic_odt_t dual_D0[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR3_RTT_OFF, + DDR3_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static const dynamic_odt_t dual_0D[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR3_RTT_OFF, + DDR3_RTT_OFF + } +}; + +static const dynamic_odt_t dual_S0[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0} + +}; + +static const dynamic_odt_t dual_0S[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + {0, 0, 0, 0} + +}; + +static const dynamic_odt_t odt_unknown[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + } +}; + unsigned int populate_memctl_options(int all_DIMMs_registered, memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { unsigned int i; + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + const dynamic_odt_t *pdodt = odt_unknown; + + /* + * Extract hwconfig from environment since we have not properly setup + * the environment but need it for ddr config params + */ + if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + buf = buffer; /* Chip select options. */ + if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { + switch (pdimm[0].n_ranks) { + case 1: + pdodt = single_S; + break; + case 2: + pdodt = single_D; + break; + case 4: + pdodt = single_Q; + break; + } + } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { + switch (pdimm[0].n_ranks) { + case 2: + switch (pdimm[1].n_ranks) { + case 2: + pdodt = dual_DD; + break; + case 1: + pdodt = dual_DS; + break; + case 0: + pdodt = dual_D0; + break; + } + break; + case 1: + switch (pdimm[1].n_ranks) { + case 2: + pdodt = dual_SD; + break; + case 1: + pdodt = dual_SS; + break; + case 0: + pdodt = dual_S0; + break; + } + break; + case 0: + switch (pdimm[1].n_ranks) { + case 2: + pdodt = dual_0D; + break; + case 1: + pdodt = dual_0S; + break; + } + break; + } + } /* Pick chip-select local options. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */ - - /* only for single CS? */ - popts->cs_local_opts[i].odt_rd_cfg = 0; - - popts->cs_local_opts[i].odt_wr_cfg = 1; +#if defined(CONFIG_FSL_DDR3) + popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg; + popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg; + popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm; + popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr; +#else + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; +#endif popts->cs_local_opts[i].auto_precharge = 0; } @@ -81,10 +391,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, /* Operational Mode Paramters */ /* Pick ECC modes */ -#ifdef CONFIG_DDR_ECC - popts->ECC_mode = 1; /* 0 = disabled, 1 = enabled */ -#else popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */ +#ifdef CONFIG_DDR_ECC + if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf)) + popts->ECC_mode = 1; + } else + popts->ECC_mode = 1; #endif popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ @@ -159,6 +472,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->twoT_en = 0; popts->threeT_en = 0; + /* for RDIMM, address parity enable */ + popts->ap_en = 1; + /* * BSTTOPRE precharge interval * @@ -221,7 +537,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * should be a subset of the requested configuration. */ #if (CONFIG_NUM_DDR_CONTROLLERS > 1) - if (hwconfig_sub("fsl_ddr", "ctlr_intlv")) { + if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) { if (pdimm[0].n_ranks == 0) { printf("There is no rank on CS0 for controller %d. Because only" " rank on CS0 and ranks chip-select interleaved with CS0" @@ -234,19 +550,25 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * test null first. if CONFIG_HWCONFIG is not defined * hwconfig_arg_cmp returns non-zero */ - if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "null")) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", + "null", buf)) { popts->memctl_interleaving = 0; debug("memory controller interleaving disabled.\n"); - } else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "cacheline")) + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "cacheline", buf)) popts->memctl_interleaving_mode = FSL_DDR_CACHE_LINE_INTERLEAVING; - else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "page")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", + "page", buf)) popts->memctl_interleaving_mode = FSL_DDR_PAGE_INTERLEAVING; - else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "bank")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", + "bank", buf)) popts->memctl_interleaving_mode = FSL_DDR_BANK_INTERLEAVING; - else if (hwconfig_subarg_cmp("fsl_ddr", "ctlr_intlv", "superbank")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", + "superbank", buf)) popts->memctl_interleaving_mode = FSL_DDR_SUPERBANK_INTERLEAVING; else { @@ -256,19 +578,24 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, } } #endif - if ((hwconfig_sub("fsl_ddr", "bank_intlv")) && + if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { /* test null first. if CONFIG_HWCONFIG is not defined, - * hwconfig_arg_cmp returns non-zero */ - if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "null")) + * hwconfig_subarg_cmp_f returns non-zero */ + if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "null", buf)) debug("bank interleaving disabled.\n"); - else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "cs0_cs1", buf)) popts->ba_intlv_ctl = FSL_DDR_CS0_CS1; - else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs2_cs3")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "cs2_cs3", buf)) popts->ba_intlv_ctl = FSL_DDR_CS2_CS3; - else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_and_cs2_cs3")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "cs0_cs1_and_cs2_cs3", buf)) popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3; - else if (hwconfig_subarg_cmp("fsl_ddr", "bank_intlv", "cs0_cs1_cs2_cs3")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "cs0_cs1_cs2_cs3", buf)) popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; else printf("hwconfig has unrecognized parameter for bank_intlv.\n"); @@ -342,10 +669,11 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, } } - if (hwconfig_sub("fsl_ddr", "addr_hash")) { - if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "null")) + if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf)) popts->addr_hash = 0; - else if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "true")) + else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", + "true", buf)) popts->addr_hash = 1; } @@ -387,3 +715,34 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) "Memory controller interleaving disabled.\n"); } } + +int fsl_use_spd(void) +{ + int use_spd = 0; + +#ifdef CONFIG_DDR_SPD + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + + /* + * Extract hwconfig from environment since we have not properly setup + * the environment but need it for ddr config params + */ + if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + buf = buffer; + + /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ + if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf)) + use_spd = 1; + else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", + "fixed", buf)) + use_spd = 0; + else + use_spd = 1; + } else + use_spd = 1; +#endif + + return use_spd; +} diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 54e60bb..0c166fd 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains @@ -28,6 +28,7 @@ #include <fdt_support.h> #include <asm/mp.h> #include <asm/fsl_enet.h> +#include <asm/fsl_serdes.h> #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -239,3 +240,23 @@ int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc) return fdt_setprop_string(blob, offset, "phy-connection-type", fsl_phy_enet_if_str[phyc]); } + +#ifdef CONFIG_SYS_SRIO +void ft_srio_setup(void *blob) +{ +#ifdef CONFIG_SRIO1 + if (!is_serdes_configured(SRIO1)) { + fdt_del_node_and_alias(blob, "rio0"); + } +#else + fdt_del_node_and_alias(blob, "rio0"); +#endif +#ifdef CONFIG_SRIO2 + if (!is_serdes_configured(SRIO2)) { + fdt_del_node_and_alias(blob, "rio1"); + } +#else + fdt_del_node_and_alias(blob, "rio1"); +#endif +} +#endif diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index fcef40c..7598ebf 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -9,6 +9,16 @@ #include <common.h> #include <asm/fsl_lbc.h> +#ifdef CONFIG_MPC85xx +/* Boards should provide their own version of this if they use lbc sdram */ +void __lbc_sdram_init(void) +{ + /* Do nothing */ +} +void lbc_sdram_init(void) __attribute__((weak, alias("__lbc_sdram_init"))); +#endif + + void print_lbc_regs(void) { int i; @@ -24,6 +34,11 @@ void init_early_memctl_regs(void) { uint init_br1 = 1; +#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001 + /* Set the local bus monitor timeout value to the maximum */ + clrsetbits_be32(&(LBC_BASE_ADDR)->lbcr, LBCR_BMT|LBCR_BMTPS, 0xf); +#endif + #ifdef CONFIG_MPC85xx /* if cs1 is already set via debugger, leave cs0/cs1 alone */ if (get_lbc_br(1) & BR_V) diff --git a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c deleted file mode 100644 index 53236a3..0000000 --- a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <pci.h> - -struct pci_info { - u32 cfg; -}; - -/* The cfg field is a bit mask in which each bit represents the value of - * cfg_IO_ports[] signal and the bit is set if the interface would be - * enabled based on the value of cfg_IO_ports[] signal - * - * On MPC86xx/PQ3 based systems: - * we extract cfg_IO_ports from GUTS register PORDEVSR - * - * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems - * without PCIe) - */ - -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, -}; -#elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, -}; -#elif defined(CONFIG_MPC8536) -static struct pci_info pci_config_info[] = -{ -}; -#elif defined(CONFIG_MPC8544) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | - (1 << 6) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 6) | (1 << 7), - }, -}; -#elif defined(CONFIG_MPC8548) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI_1] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCI_2] = { - .cfg = 0, - }, - /* PCI_2 is always host and we dont use iosel to determine enable/disable */ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 3) | (1 << 4) | (1 << 7), - }, -}; -#elif defined(CONFIG_MPC8568) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 3) | (1 << 4) | (1 << 7), - }, -}; -#elif defined(CONFIG_MPC8569) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | - (1 << 8) | (1 << 0xc) | (1 << 0xf), - }, -}; -#elif defined(CONFIG_MPC8572) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 2) | (1 << 3) | (1 << 7) | - (1 << 0xb) | (1 << 0xc) | (1 << 0xf), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 3) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 7), - }, -}; -#elif defined(CONFIG_MPC8610) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI_1] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 1) | (1 << 4), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 0) | (1 << 4), - }, -}; -#elif defined(CONFIG_MPC8641) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | - (1 << 7) | (1 << 0xf), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 3) | (1 << 0xe) | (1 << 0xf), - }, -}; -#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ - defined(CONFIG_P1012) || defined(CONFIG_P1021) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 0xe), - }, -}; -#elif defined(CONFIG_P1013) || defined(CONFIG_P1022) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) | - (1 << 0xb) | (1 << 0xd) | (1 << 0xe) | - (1 << 0xf) | (1 << 0x15) | (1 << 0x16) | - (1 << 0x17) | (1 << 0x18) | (1 << 0x19) | - (1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) | - (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) | - (1 << 0xd) | (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | - (1 << 0x18) | (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) | - (1 << 0xa) | (1 << 0xb) | (1 << 0xd) | (1 << 0x15) | - (1 << 0x16) | (1 << 0x17) | (1 << 0x18) | (1 << 0x1c), - }, -}; -#elif defined(CONFIG_P2010) || defined(CONFIG_P2020) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) | - (1 << 0xd) | (1 << 0xe) | (1 << 0xf), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 2) | (1 << 0xe), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 2) | (1 << 4), - }, -}; -#elif defined(CONFIG_FSL_CORENET) -#else -#error Need to define pci_config_info for processor -#endif - -#ifndef CONFIG_FSL_CORENET -int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel) -{ - return ((1 << io_sel) & pci_config_info[trgt].cfg); -} -#endif diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c new file mode 100644 index 0000000..e46d328 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -0,0 +1,86 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> + +#if defined(CONFIG_FSL_CORENET) + #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 + #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 + #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC85xx) + #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO + #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO + #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC86xx) + #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO + #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO + #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ + (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) +#else +#error "No defines for DEVDISR_SRIO" +#endif + +void srio_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; + int srio1_used = 0, srio2_used = 0; + + if (is_serdes_configured(SRIO1)) { + set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS, + law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), + LAW_TRGT_IF_RIO_1); + srio1_used = 1; + printf("SRIO1: enabled\n"); + } else { + printf("SRIO1: disabled\n"); + } + +#ifdef CONFIG_SRIO2 + if (is_serdes_configured(SRIO2)) { + set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS, + law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), + LAW_TRGT_IF_RIO_2); + srio2_used = 1; + printf("SRIO2: enabled\n"); + } else { + printf("SRIO2: disabled\n"); + } +#endif + +#ifdef CONFIG_FSL_CORENET + /* On FSL_CORENET devices we can disable individual ports */ + if (!srio1_used) + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); + if (!srio2_used) + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); +#endif + + /* neither port is used - disable everything */ + if (!srio1_used && !srio2_used) { + setbits_be32(&gur->devdisr, _DEVDISR_SRIO1); + setbits_be32(&gur->devdisr, _DEVDISR_SRIO2); + setbits_be32(&gur->devdisr, _DEVDISR_RMU); + } +} diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index 9634deb..95df1d9 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -416,7 +416,6 @@ static void test(void); static void DQS_calibration_process(void); #endif #endif -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); static unsigned char spd_read(uchar chip, uint addr) { diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index 3b28122..9f8f8fa 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -89,60 +89,60 @@ int phy_setup_aneg (char *devname, unsigned char addr) u16 exsr = 0x0000; #endif - miiphy_read (devname, addr, PHY_BMSR, &bmsr); + miiphy_read (devname, addr, MII_BMSR, &bmsr); #if defined(CONFIG_PHY_GIGE) - if (bmsr & PHY_BMSR_EXT_STAT) - miiphy_read (devname, addr, PHY_EXSR, &exsr); + if (bmsr & BMSR_ESTATEN) + miiphy_read (devname, addr, MII_ESTATUS, &exsr); - if (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)) { + if (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)) { /* 1000BASE-X */ u16 anar = 0x0000; - if (exsr & PHY_EXSR_1000XF) - anar |= PHY_X_ANLPAR_FD; + if (exsr & ESTATUS_1000XF) + anar |= ADVERTISE_1000XFULL; - if (exsr & PHY_EXSR_1000XH) - anar |= PHY_X_ANLPAR_HD; + if (exsr & ESTATUS_1000XH) + anar |= ADVERTISE_1000XHALF; - miiphy_write (devname, addr, PHY_ANAR, anar); + miiphy_write (devname, addr, MII_ADVERTISE, anar); } else #endif { u16 anar, btcr; - miiphy_read (devname, addr, PHY_ANAR, &anar); - anar &= ~(0x5000 | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD | - PHY_ANLPAR_TX | PHY_ANLPAR_10FD | PHY_ANLPAR_10); + miiphy_read (devname, addr, MII_ADVERTISE, &anar); + anar &= ~(0x5000 | LPA_100BASE4 | LPA_100FULL | + LPA_100HALF | LPA_10FULL | LPA_10HALF); - miiphy_read (devname, addr, PHY_1000BTCR, &btcr); + miiphy_read (devname, addr, MII_CTRL1000, &btcr); btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD); - if (bmsr & PHY_BMSR_100T4) - anar |= PHY_ANLPAR_T4; + if (bmsr & BMSR_100BASE4) + anar |= LPA_100BASE4; - if (bmsr & PHY_BMSR_100TXF) - anar |= PHY_ANLPAR_TXFD; + if (bmsr & BMSR_100FULL) + anar |= LPA_100FULL; - if (bmsr & PHY_BMSR_100TXH) - anar |= PHY_ANLPAR_TX; + if (bmsr & BMSR_100HALF) + anar |= LPA_100HALF; - if (bmsr & PHY_BMSR_10TF) - anar |= PHY_ANLPAR_10FD; + if (bmsr & BMSR_10FULL) + anar |= LPA_10FULL; - if (bmsr & PHY_BMSR_10TH) - anar |= PHY_ANLPAR_10; + if (bmsr & BMSR_10HALF) + anar |= LPA_10HALF; - miiphy_write (devname, addr, PHY_ANAR, anar); + miiphy_write (devname, addr, MII_ADVERTISE, anar); #if defined(CONFIG_PHY_GIGE) - if (exsr & PHY_EXSR_1000TF) + if (exsr & ESTATUS_1000_TFULL) btcr |= PHY_1000BTCR_1000FD; - if (exsr & PHY_EXSR_1000TH) + if (exsr & ESTATUS_1000_THALF) btcr |= PHY_1000BTCR_1000HD; - miiphy_write (devname, addr, PHY_1000BTCR, btcr); + miiphy_write (devname, addr, MII_CTRL1000, btcr); #endif } @@ -152,21 +152,21 @@ int phy_setup_aneg (char *devname, unsigned char addr) */ u16 adv; - miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | - PHY_ANLPAR_10FD | PHY_ANLPAR_10); - miiphy_write (devname, addr, PHY_ANAR, adv); + miiphy_read (devname, addr, MII_ADVERTISE, &adv); + adv |= (LPA_LPACK | LPA_100FULL | LPA_100HALF | + LPA_10FULL | LPA_10HALF); + miiphy_write (devname, addr, MII_ADVERTISE, adv); - miiphy_read (devname, addr, PHY_1000BTCR, &adv); + miiphy_read (devname, addr, MII_CTRL1000, &adv); adv |= (0x0300); - miiphy_write (devname, addr, PHY_1000BTCR, adv); + miiphy_write (devname, addr, MII_CTRL1000, adv); #endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &bmcr); - bmcr |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, bmcr); + miiphy_read (devname, addr, MII_BMCR, &bmcr); + bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); + miiphy_write (devname, addr, MII_BMCR, bmcr); return 0; } diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 0e75794..2218508 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -48,21 +48,23 @@ *------------------------------------------------------------------------------- */ -/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards - * +/* + * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards * - * The processor starts at 0xfffffffc and the code is executed - * from flash/rom. - * in memory, but as long we don't jump around before relocating. - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - * This works because the cpu gives the FLASH (CS0) the whole - * address space at startup, and board_init lies as a echo of - * the flash somewhere up there in the memorymap. + * The following description only applies to the NOR flash style booting. + * NAND booting is different. For more details about NAND booting on 4xx + * take a look at doc/README.nand-boot-ppc440. * - * board_init will change CS0 to be positioned at the correct - * address and (s)dram will be positioned at address 0 + * The CPU starts at address 0xfffffffc (last word in the address space). + * The U-Boot image therefore has to be located in the "upper" area of the + * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for + * the boot chip-select (CS0) is quite big and covers this area. On the + * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will + * reconfigure this CS0 (and other chip-selects as well when configured + * this way) in the boot process to the "correct" values matching the + * board layout. */ + #include <asm-offsets.h> #include <config.h> #include <asm/ppc4xx.h> @@ -265,7 +267,7 @@ /* NOTREACHED - board_init_f() does not return */ #endif -#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD) /* * 4xx RAM-booting U-Boot image is started from offset 0 */ diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds index dac0e5b..656f59a 100644 --- a/arch/powerpc/cpu/ppc4xx/u-boot.lds +++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds @@ -23,8 +23,12 @@ #include "config.h" /* CONFIG_BOARDDIR */ #ifndef RESET_VECTOR_ADDRESS +#ifdef CONFIG_RESET_VECTOR_ADDRESS +#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS +#else #define RESET_VECTOR_ADDRESS 0xfffffffc #endif +#endif OUTPUT_ARCH(powerpc) @@ -55,13 +59,14 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - KEEP(*(.got)) _GOT2_TABLE_ = .; KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : @@ -100,7 +105,11 @@ SECTIONS * start.o, since the first shadow TLB only covers 4k * of address space. */ +#ifdef CONFIG_INIT_TLB + CONFIG_INIT_TLB (.bootpg) +#else CONFIG_BOARDDIR/init.o (.bootpg) +#endif } :text = 0xffff #endif |