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author | Kumar Gala <galak@kernel.crashing.org> | 2010-12-17 10:21:22 -0600 |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2011-01-14 01:32:20 -0600 |
commit | f5fa8f366931089344ddc9c995c54a53bc992d2f (patch) | |
tree | 51732394a706e1f2a981dc60bf238a0126fe733d /board/freescale/mpc8548cds/law.c | |
parent | 64e55d5ed40e4de2dd52910f7634304fbebe1840 (diff) | |
download | bootable_bootloader_goldelico_gta04-f5fa8f366931089344ddc9c995c54a53bc992d2f.zip bootable_bootloader_goldelico_gta04-f5fa8f366931089344ddc9c995c54a53bc992d2f.tar.gz bootable_bootloader_goldelico_gta04-f5fa8f366931089344ddc9c995c54a53bc992d2f.tar.bz2 |
powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe code
Remove duplicated code in MPC8548CDS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/mpc8548cds/law.c')
-rw-r--r-- | board/freescale/mpc8548cds/law.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index 98748aa..e59fee8 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008,2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -51,18 +51,10 @@ */ struct law_entry law_table[] = { -#ifdef CONFIG_SYS_PCI1_MEM_PHYS - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), -#endif #ifdef CONFIG_SYS_PCI2_MEM_PHYS SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), #endif -#ifdef CONFIG_SYS_PCIE1_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), -#endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), #ifdef CONFIG_SYS_RIO_MEM_PHYS |