added boot script files to repository

6 files changed, 0 insertions, 1056 deletions

diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile
deleted file mode 100644
index 280c2f6..0000000
--- a/board/netstal/hcu5/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-# (C) Copyright 2007-2008 Netstal Maschinen AG
-# Niklaus Giger (ng@netstal.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o \
-	sdram.o \
-	../common/nm_bsp.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-all:	$(LIB) $(SOBJS)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $^)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt
deleted file mode 100644
index c5737d0..0000000
--- a/board/netstal/hcu5/README.txt
+++ /dev/null
@@ -1,171 +0,0 @@
-HCU5 configuration details and startup sequence
-
-(C) Copyright 2007 Netstal Maschinen AG
-    Niklaus Giger (Niklaus.Giger@netstal.com)
-
-TODO:
------
-- Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT !
-     - Does not occur if both EMAC are connected
-- Fix RTS/CTS problem (HW?)
-  CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after
-  Switching to interrupt driven serial input mode
-
-Caveats:
---------
-Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c)
-see hcu5.c.
-
-
-Memory Bank 0 -- Flash chip
----------------------------
-
-0xfff00000 - 0xffffffff
-
-The flash chip is really only 512Kbytes, but the high address bit of
-the 1Meg region is ignored, so the flash is replicated through the
-region. Thus, this is consistent with a flash base address 0xfff80000.
-
-The placement at the end is to be consistent with reset behavior,
-where the processor itself initially uses this bus to load the branch
-vector and start running.
-
-On-Chip Memory
---------------
-
-0xe0010000- 0xe0013fff   CONFIG_SYS_OCM_BASE
-The 440EPx includes a 16K on-chip memory that can be placed however
-software chooses.
-
-Internal Peripherals
---------------------
-
-0xef600300 - 0xef6008ff
-
-These are scattered various peripherals internal to the PPC440EPX
-chip.
-
-Chip-Select 2: Flash Memory
----------------------------
-
-Not used
-
-Chip-Select 3: CAN Interface
-----------------------------
-0xc800000: 2 Intel 82527 CAN-Controller
-
-
-Chip-Select 4: IMC-bus standard
--------------------------------
-
-0xcc00000: Netstal specific IO-Bus
-
-
-Chip-Select 5: IMC-bus fast (inactive)
---------------------------------------
-
-0xce00000: Netstal specific IO-Bus (fast, but not yet used)
-
-
-Memory Bank 1 -- DDR2
--------------------------------------
-
-0x00000000 - 0xfffffff   # Default 256 MB
-
-PCI ??
-
-USB ??
-Only USB_STORAGE is enabled to load vxWorks
-from a memory stick.
-
-System-LEDs ??? (Analog zu HCU4 ???)
-
-Startup sequence
-----------------
-
-(arch/powerpc/cpu/ppc4xx/resetvec.S)
-depending on configs option
-call _start_440 _start_pci oder _start
-
-(arch/powerpc/cpu/ppc4xx/start.S)
-
-_start_440:
-	initialize register like
-	CCR0
-	debug
-	setup interrupt vectors
-	configure cache regions
-	clear and setup TLB
-	enable internal RAM
-	jump start_ram
-	which in turn will jump to start
-_start:
-	Clear and set up some registers.
-	Debug setup
-	Setup the internal SRAM
-	Setup the stack in internal SRAM
-    setup stack pointer (r1)
-    setup GOT
-	call cpu_init_f	/* run low-level CPU init code	   (from Flash) */
-
-    call cpu_init_f
-    board_init_f: (arch/powerpc/lib\board.c)
-	init_sequence defines a list of function to be called
-	    board_early_init_f: (board/netstal/hcu5/hcu5.c)
-		We are using Bootstrap-Option A
-		if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot
-		Setup the GPIO pins
-		Setup the interrupt controller polarities, triggers, etc.
-		Ethernet, PCI, USB enable
-		setup BOOT FLASH (Chip timing)
-	    init_baudrate,
-	    serial_init
-	    checkcpu
-	    misc_init_f #ifdef
-	    init_func_i2c #ifdef
-	    post_init_f  #ifdef
-	    init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c
-		(EYE function removed!!)
-	    test_dram call
-
-	 * Reserve memory at end of RAM for (top down in that order):
-	 *  - kernel log buffer
-	 *  - protected RAM
-	 *  - LCD framebuffer
-	 *  - monitor code
-	 *  - board info struct
-	Save local variables to board info struct
-	call relocate_code() does not return
-	relocate_code: (arch/powerpc/cpu/ppc4xx/start.S)
--------------------------------------------------------
-From now on our copy is in RAM and we will run from there,
-	starting with board_init_r
--------------------------------------------------------
-    board_init_r: (arch/powerpc/lib\board.c)
-	setup bd function pointers
-	trap_init
-	flash_init: (board/netstal/hcu5/flash.c)
-		/* setup for u-boot erase, update */
-	setup bd flash info
-	cpu_init_r: (arch/powerpc/cpu/ppc4xx/cpu_init.c)
-	    peripheral chip select in using defines like
-	    CONFIG_SYS_EBC_PB0A, CONFIG_SYS_EBC_PB0C from hcu5.h
-	mem_malloc_init
-	malloc_bin_reloc
-	spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
-	env_relocated
-	misc_init_r(bd): (board/netstal/hcu5.c)
-	    ethaddr mit serial number ergänzen
-    Then we will somehow go into the command loop
-
-Most of the HW specific code for the HCU5 may be found in
-include/configs/hcu5.h
-board/netstal/hcu5/*
-arch/powerpc/cpu/ppc4xx/*
-arch/powerpc/lib/*
-include/ppc440.h
-
-Drivers for serial etc are found under drivers/
-
-Don't ask question if you did not look at the README !!
-Most CONFIG_SYS_* and CONFIG_* switches are mentioned/explained there.
diff --git a/board/netstal/hcu5/config.mk b/board/netstal/hcu5/config.mk
deleted file mode 100644
index f641d54..0000000
--- a/board/netstal/hcu5/config.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# (C) Copyright 2005 Netstal Maschinen AG
-#     Niklaus Giger (ng@netstal.com)
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Netstal Maschinen AG: HCU5 boards
-#
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG -g
-endif
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
deleted file mode 100644
index f94d05b..0000000
--- a/board/netstal/hcu5/hcu5.c
+++ /dev/null
@@ -1,414 +0,0 @@
-/*
- *(C) Copyright 2005-2008 Netstal Maschinen AG
- *    Niklaus Giger (Niklaus.Giger@netstal.com)
- *
- *    This source code is free software; you can redistribute it
- *    and/or modify it in source code form under the terms of the GNU
- *    General Public License as published by the Free Software
- *    Foundation; either version 2 of the License, or (at your option)
- *    any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/ppc440.h>
-#include <asm/io.h>
-#include <asm/4xx_pci.h>
-
-#include  "../common/nm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-#undef BOOTSTRAP_OPTION_A_ACTIVE
-
-#define SDR0_CP440		0x0180
-
-#define SYSTEM_RESET		0x30000000
-#define CHIP_RESET		0x20000000
-
-#define SDR0_ECID0		0x0080
-#define SDR0_ECID1		0x0081
-#define SDR0_ECID2		0x0082
-#define SDR0_ECID3		0x0083
-
-#define SYS_IO_ADDRESS			(CONFIG_SYS_CS_2 + 0x00e00000)
-#define SYS_SLOT_ADDRESS		(CONFIG_SYS_CPLD + 0x00400000)
-#define HCU_DIGITAL_IO_REGISTER	(CONFIG_SYS_CPLD + 0x0500000)
-#define HCU_SW_INSTALL_REQUESTED	0x10
-
-/*
- * This function is run very early, out of flash, and before devices are
- * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
- * of being in the init_sequence array.
- *
- * The SDRAM has been initialized already -- start.S:start called
- * init.S:init_sdram early on -- but it is not yet being used for
- * anything, not even stack. So be careful.
- */
-
-int board_early_init_f(void)
-{
-
-#ifdef BOOTSTRAP_OPTION_A_ACTIVE
-	/* Booting with Bootstrap Option A
-	 * First boot, with CPR0_ICFG_RLI_MASK == 0
-	 * no we setup varios boot strapping register,
-	 * then we do reset the PPC440 using a chip reset
-	 * Unfortunately, we cannot use this option, as Nto1 is not set
-	 * with Bootstrap Option A and cannot be changed later on by SW
-	 * There are no other possible boostrap options with a 8 bit ROM
-	 * See Errata (Version 1.04) CHIP_9
-	 */
-
-	u32 cpr0icfg;
-	u32 dbcr;
-
-	mfcpr(CPR0_ICFG, cpr0icfg);
-	if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
-		mtcpr(CPR0_MALD,   0x02000000);
-		mtcpr(CPR0_OPBD,   0x02000000);
-	        mtcpr(CPR0_PERD,   0x05000000);  /* 1:5 */
-		mtcpr(CPR0_PLLC,   0x40000238);
-		mtcpr(CPR0_PLLD,   0x01010414);
-		mtcpr(CPR0_PRIMAD, 0x01000000);
-		mtcpr(CPR0_PRIMBD, 0x01000000);
-		mtcpr(CPR0_SPCID,  0x03000000);
-		mtsdr(SDR0_PFC0,   0x00003E00);  /* [CTE] = 0 */
-		mtsdr(SDR0_CP440,  0x0EAAEA02);  /* [Nto1] = 1*/
-		mtcpr(CPR0_ICFG,   cpr0icfg | CPR0_ICFG_RLI_MASK);
-
-		/*
-		 * Initiate system reset in debug control register DBCR
-		 */
-		dbcr = mfspr(SPRN_DBCR0);
-		mtspr(SPRN_DBCR0, dbcr | CHIP_RESET);
-	}
-	mtsdr(SDR0_CP440, 0x0EAAEA02);  /* [Nto1] = 1*/
-#endif
-	mtdcr(EBC0_CFGADDR, EBC0_CFG);
-	mtdcr(EBC0_CFGDATA, 0xb8400000);
-
-	/*
-	 * Setup the GPIO pins
-	 */
-	out32(GPIO0_OR, 0x00000000);
-	out32(GPIO0_TCR, 0x7C2FF1CF);
-	out32(GPIO0_OSRL, 0x40055000);
-	out32(GPIO0_OSRH, 0x00000000);
-	out32(GPIO0_TSRL, 0x40055000);
-	out32(GPIO0_TSRH, 0x00000400);
-	out32(GPIO0_ISR1L, 0x40000000);
-	out32(GPIO0_ISR1H, 0x00000000);
-	out32(GPIO0_ISR2L, 0x00000000);
-	out32(GPIO0_ISR2H, 0x00000000);
-	out32(GPIO0_ISR3L, 0x00000000);
-	out32(GPIO0_ISR3H, 0x00000000);
-
-	out32(GPIO1_OR, 0x00000000);
-	out32(GPIO1_TCR, 0xC6007FFF);
-	out32(GPIO1_OSRL, 0x00140000);
-	out32(GPIO1_OSRH, 0x00000000);
-	out32(GPIO1_TSRL, 0x00000000);
-	out32(GPIO1_TSRH, 0x00000000);
-	out32(GPIO1_ISR1L, 0x05415555);
-	out32(GPIO1_ISR1H, 0x40000000);
-	out32(GPIO1_ISR2L, 0x00000000);
-	out32(GPIO1_ISR2H, 0x00000000);
-	out32(GPIO1_ISR3L, 0x00000000);
-	out32(GPIO1_ISR3H, 0x00000000);
-
-	/*
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(UIC0PR, 0xfffff7ff);	/* per ref-board manual */
-	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC2ER, 0x00000000);	/* disable all */
-	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-	mtsdr(SDR0_PFC0, 0x00003E00);	/* Pin function:  */
-	mtsdr(SDR0_PFC1, 0x00848000);	/* Pin function: UART0 has 4 pins */
-
-	/* setup BOOT FLASH */
-	mtsdr(SDR0_CUST0, 0xC0082350);
-
-	return 0;
-}
-
-#ifdef CONFIG_BOARD_PRE_INIT
-int board_pre_init(void)
-{
-	return board_early_init_f();
-}
-
-#endif
-
-int sys_install_requested(void)
-{
-	u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
-	return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
-}
-
-int checkboard(void)
-{
-	u16 *hwVersReg    = (u16 *) HCU_HW_VERSION_REGISTER;
-	u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
-	u16 generation = in_be16(boardVersReg) & 0xf0;
-	u16 index      = in_be16(boardVersReg) & 0x0f;
-	u32 ecid0, ecid1, ecid2, ecid3;
-
-	nm_show_print(generation, index, in_be16(hwVersReg) & 0xff);
-	mfsdr(SDR0_ECID0, ecid0);
-	mfsdr(SDR0_ECID1, ecid1);
-	mfsdr(SDR0_ECID2, ecid2);
-	mfsdr(SDR0_ECID3, ecid3);
-
-	printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
-
-	return 0;
-}
-
-u32 hcu_led_get(void)
-{
-	return in16(SYS_IO_ADDRESS) & 0x3f;
-}
-
-/*
- * hcu_led_set  value to be placed into the LEDs (max 6 bit)
- */
-void hcu_led_set(u32 value)
-{
-	out16(SYS_IO_ADDRESS, value);
-}
-
-/*
- * get_serial_number
- */
-u32 get_serial_number(void)
-{
-	u32 *serial = (u32 *)CONFIG_SYS_FLASH_BASE;
-
-	if (in_be32(serial) == 0xffffffff)
-		return 0;
-
-	return in_be32(serial);
-}
-
-
-/*
- * hcu_get_slot
- */
-u32 hcu_get_slot(void)
-{
-	u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
-	return in_be16(slot) & 0x7f;
-}
-
-
-/*
- * misc_init_r.
- */
-int misc_init_r(void)
-{
-	unsigned long usb2d0cr = 0;
-	unsigned long usb2phy0cr, usb2h0cr = 0;
-	unsigned long sdr0_pfc1;
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CONFIG_SYS_MONITOR_LEN,
-			    0xffffffff,
-			    &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
-	/* Env protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    CONFIG_ENV_ADDR_REDUND,
-			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
-			    &flash_info[0]);
-#endif
-#endif
-
-	/*
-	 * USB stuff...
-	 */
-
-	/* SDR Setting */
-	mfsdr(SDR0_PFC1, sdr0_pfc1);
-	mfsdr(SDR0_USB2D0CR, usb2d0cr);
-	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-	mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
-	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
-	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
-	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
-	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
-	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
-	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
-
-	/* An 8-bit/60MHz interface is the only possible alternative
-	 *  when connecting the Device to the PHY
-	 */
-	usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
-
-	/* To enable the USB 2.0 Device function through the UTMI interface */
-	usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-	usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;		/*1*/
-
-	sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-	sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;		/*0*/
-
-	mtsdr(SDR0_PFC1, sdr0_pfc1);
-	mtsdr(SDR0_USB2D0CR, usb2d0cr);
-	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-	mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
-	/*clear resets*/
-	udelay(1000);
-	mtsdr(SDR0_SRST1, 0x00000000);
-	udelay(1000);
-	mtsdr(SDR0_SRST0, 0x00000000);
-	printf("USB:   Host(int phy) Device(ext phy)\n");
-
-	common_misc_init_r();
-	set_params_for_sw_install( sys_install_requested(), "hcu5" );
-	/* We cannot easily enable trace before, as there are other
-	 * routines messing around with sdr0_pfc1. And I do not need it.
-	 */
-	if (mfspr(SPRN_DBCR0) & 0x80000000) {
-		/* External debugger alive
-		 * enable trace facilty for Lauterbach
-		 * CCR0[DTB]=0		Enable broadcast of trace information
-		 * SDR0_PFC0[TRE]	Trace signals are enabled instead of
-		 *			GPIO49-63
-		 */
-	        mtspr(SPRN_CCR0, mfspr(SPRN_CCR0)  &~ (CCR0_DTB));
-		mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
-	}
-	return 0;
-}
-#ifdef CONFIG_PCI
-int board_with_pci(void)
-{
-	u32 reg;
-
-	mfsdr(SDR0_PCI0, reg);
-	return (reg & SDR0_PCI0_PAE_MASK);
-}
-
-/*
- *  pci_pre_init
- *
- *  This routine is called just prior to registering the hose and gives
- *  the board the opportunity to check things. Returning a value of zero
- *  indicates that things are bad & PCI initialization should be aborted.
- *
- *	Different boards may wish to customize the pci controller structure
- *	(add regions, override default access routines, etc) or perform
- *	certain pre-initialization actions.
- *
- */
-int pci_pre_init(struct pci_controller *hose)
-{
-	unsigned long addr;
-
-	if (!board_with_pci()) { return 0; }
-
-	/*
-	 * Set priority for all PLB3 devices to 0.
-	 * Set PLB3 arbiter to fair mode.
-	 */
-	mfsdr(SDR0_AMP1, addr);
-	mtsdr(SDR0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
-	addr = mfdcr(PLB3A0_ACR);
-	mtdcr(PLB3A0_ACR, addr | 0x80000000); /* Sequoia */
-
-	/*
-	 * Set priority for all PLB4 devices to 0.
-	 */
-	mfsdr(SDR0_AMP0, addr);
-	mtsdr(SDR0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
-	addr = mfdcr(PLB4A0_ACR) | 0xa0000000;	/* Was 0x8---- */
-	mtdcr(PLB4A0_ACR, addr);  /* Sequoia */
-
-	/*
-	 * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
-	 * Workaround: Disable write pipelining to DDR SDRAM by setting
-	 * PLB4A0_ACR[WRP] = 0.
-	 */
-	mtdcr(PLB4A0_ACR, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
-
-	/* Segment1 */
-	mtdcr(PLB4A1_ACR, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
-
-	return board_with_pci();
-}
-
-/*
- * Override weak default pci_master_init()
- */
-void pci_master_init(struct pci_controller *hose)
-{
-	if (!board_with_pci())
-		return;
-
-	__pci_master_init(hose);
-}
-#endif	 /* defined(CONFIG_PCI) */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
- */
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
-{
-	if (banknum == 0) {	/* non-CFI boot flash */
-		info->portwidth = 1;
-		info->chipwidth = 1;
-		info->interface = FLASH_CFI_X8;
-		return 1;
-	} else
-		return 0;
-}
diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S
deleted file mode 100644
index 45e63dd..0000000
--- a/board/netstal/hcu5/init.S
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
-	tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
-	/* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
-	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0,
-		AC_RWX | SA_IG )
-
-	/* TLB#2: TLB-entry for EBC */
-	tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_RWX | SA_IG)
-
-	/*
-	 * TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be
-	 * off to use the speed up boot process. It is patched after relocation
-	 * to enable SA_I
-	 */
-	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1,
-		AC_RWX | SA_G)
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-	/* TLB#4: */
-	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1,
-		AC_RW | SA_IG )
-	/* TLB#5: */
-	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1,
-		AC_RW | SA_IG )
-	/* TLB#6: */
-	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1,
-		AC_RW | SA_IG )
-
-	/* TLB-entry for Internal Registers & OCM */
-	/* TLB#7: */
-	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,
-		AC_RWX | SA_IG )
-
-	/*TLB-entry PCI registers*/
-	/* TLB#8: */
-	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
-
-	/* TLB-entry for peripherals */
-	/* TLB#9: */
-	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
-	/*		CAN */
-	/* TLB#10: */
-	tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_RWX | SA_IG )
-
-	/* TLB#11:  CPLD and IMC-Standard 32 MB */
-	tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_RWX | SA_IG )
-
-	/* TLB#12: */
-	tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1,
-		AC_RWX | SA_IG )
-
-	 /*		IMC-Fast 32 MB */
-	/* TLB#13: */
-	tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_RWX | SA_IG )
-	/* TLB#14: */
-	tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1,
-		AC_RWX | SA_IG )
-
-	tlbtab_end
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
deleted file mode 100644
index e5ac46b..0000000
--- a/board/netstal/hcu5/sdram.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * (C) Copyright 2007
- * Niklaus Giger (Niklaus.Giger@netstal.com)
- * (C) Copyright 2006
- * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* define DEBUG for debug output */
-#undef DEBUG
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/ppc440.h>
-
-void hcu_led_set(u32 value);
-void dcbz_area(u32 start_address, u32 num_bytes);
-
-#define ECC_RAM				0x03267F0B
-#define NO_ECC_RAM			0x00267F0B
-
-#define HCU_HW_SDRAM_CONFIG_MASK	0x7
-
-#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
-	/* disable caching on DDR2 */
-
-void board_add_ram_info(int use_default)
-{
-	PPC4xx_SYS_INFO board_cfg;
-	u32 val;
-
-	mfsdram(DDR0_22, val);
-	val &= DDR0_22_CTRL_RAW_MASK;
-	switch (val) {
-	case DDR0_22_CTRL_RAW_ECC_DISABLE:
-		puts(" (ECC disabled");
-		break;
-	case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
-		puts(" (ECC check only");
-		break;
-	case DDR0_22_CTRL_RAW_NO_ECC_RAM:
-		puts(" (no ECC ram");
-		break;
-	case DDR0_22_CTRL_RAW_ECC_ENABLE:
-		puts(" (ECC enabled");
-		break;
-	}
-
-	get_sys_info(&board_cfg);
-	printf(", %lu MHz", (board_cfg.freqPLB * 2) / 1000000);
-
-	mfsdram(DDR0_03, val);
-	val = DDR0_03_CASLAT_DECODE(val);
-	printf(", CL%d)", val);
-}
-
-/*--------------------------------------------------------------------
- * wait_for_dlllock.
- *--------------------------------------------------------------------*/
-static int wait_for_dlllock(void)
-{
-	unsigned long val;
-	int wait = 0;
-
-	/* -----------------------------------------------------------+
-	 * Wait for the DCC master delay line to finish calibration
-	 * ----------------------------------------------------------*/
-	mtdcr(SDRAM0_CFGADDR, DDR0_17);
-	val = DDR0_17_DLLLOCKREG_UNLOCKED;
-
-	while (wait != 0xffff) {
-		val = mfdcr(SDRAM0_CFGDATA);
-		if ((val & DDR0_17_DLLLOCKREG_MASK) ==
-		    DDR0_17_DLLLOCKREG_LOCKED)
-			/* dlllockreg bit on */
-			return 0;
-		else
-			wait++;
-	}
-	debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
-	debug("Waiting for dlllockreg bit to raise\n");
-
-	return -1;
-}
-
-/***********************************************************************
- *
- * sdram_panic -- Panic if we cannot configure the sdram correctly
- *
- ************************************************************************/
-void sdram_panic(const char *reason)
-{
-	printf("\n%s: reason %s",  __FUNCTION__,  reason);
-	hcu_led_set(0xff);
-	while (1) {
-	}
-	/* Never return */
-}
-
-#ifdef CONFIG_DDR_ECC
-void blank_string(int size)
-{
-	int i;
-
-	for (i=0; i<size; i++)
-		putc('\b');
-	for (i=0; i<size; i++)
-		putc(' ');
-	for (i=0; i<size; i++)
-		putc('\b');
-}
-/*---------------------------------------------------------------------------+
- * program_ecc.
- *---------------------------------------------------------------------------*/
-static void program_ecc(unsigned long start_address, unsigned long num_bytes)
-{
-	u32 val;
-	char str[] = "ECC generation -";
-#if defined(CONFIG_PRAM)
-	u32 *magicPtr;
-	u32 magic;
-
-	if ((mfspr(SPRN_DBCR0) & 0x80000000) == 0) {
-		/* only if no external debugger is alive!
-		 * Check whether vxWorks is using EDR logging, if yes zero
-		 * also PostMortem and user reserved memory
-		 */
-		magicPtr = (u32 *)(start_address + num_bytes -
-				(CONFIG_PRAM*1024) + sizeof(u32));
-		magic = in_be32(magicPtr);
-		debug("%s:  CONFIG_PRAM %d kB magic 0x%x 0x%p\n",
-		      __FUNCTION__, CONFIG_PRAM,
-		      magicPtr, magic);
-		if (magic == 0xbeefbabe) {
-			printf("%s: preserving at %p\n", __FUNCTION__, magicPtr);
-			num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
-		}
-	}
-#endif
-
-	sync();
-
-	puts(str);
-
-	/* ECC bit set method for cached memory */
-	/* Fast method, no noticeable delay */
-	dcbz_area(start_address, num_bytes);
-	/* Write modified dcache lines back to memory */
-	clean_dcache_range(start_address, start_address + num_bytes);
-	blank_string(strlen(str));
-
-	/* Clear error status */
-	mfsdram(DDR0_00, val);
-	mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
-
-	/*
-	 * Clear possible ECC errors
-	 * If not done, then we could get an interrupt later on when
-	 * exceptions are enabled.
-	 */
-	mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
-
-	/* Set 'int_mask' parameter to functionnal value */
-	mfsdram(DDR0_01, val);
-	mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
-			  DDR0_01_INT_MASK_ALL_OFF));
-
-	return;
-}
-#endif
-
-
-/***********************************************************************
- *
- * initdram -- 440EPx's DDR controller is a DENALI Core
- *
- ************************************************************************/
-phys_size_t initdram (int board_type)
-{
-	unsigned int dram_size = 0;
-
-	mtsdram(DDR0_02, 0x00000000);
-
-	/* Values must be kept in sync with Excel-table <<A0001492.>> ! */
-	mtsdram(DDR0_00, 0x0000190A);
-	mtsdram(DDR0_01, 0x01000000);
-	mtsdram(DDR0_03, 0x02030602);
-	mtsdram(DDR0_04, 0x0A020200);
-	mtsdram(DDR0_05, 0x02020307);
-	switch (in_be16((u16 *)HCU_HW_VERSION_REGISTER) & HCU_HW_SDRAM_CONFIG_MASK) {
-	case 1:
-		dram_size = 256 * 1024 * 1024 ;
-		mtsdram(DDR0_06, 0x0102C812);  /* 256MB RAM */
-		mtsdram(DDR0_11, 0x0014C800);  /* 256MB RAM */
-		mtsdram(DDR0_43, 0x030A0200);  /* 256MB RAM */
-		break;
-	case 0:
-	default:
-		dram_size = 128 * 1024 * 1024 ;
-		mtsdram(DDR0_06, 0x0102C80D);  /* 128MB RAM */
-		mtsdram(DDR0_11, 0x000FC800);  /* 128MB RAM */
-		mtsdram(DDR0_43, 0x030A0300);  /* 128MB RAM */
-		break;
-	}
-	mtsdram(DDR0_07, 0x00090100);
-
-	/*
-	 * TCPD=200 cycles of clock input is required to lock the DLL.
-	 * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
-	 */
-	mtsdram(DDR0_08, 0x02C80001);
-	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000100);
-	mtsdram(DDR0_12, 0x00000003);
-	mtsdram(DDR0_14, 0x00000000);
-	mtsdram(DDR0_17, 0x1D000000);
-	mtsdram(DDR0_18, 0x1D1D1D1D);
-	mtsdram(DDR0_19, 0x1D1D1D1D);
-	mtsdram(DDR0_20, 0x0B0B0B0B);
-	mtsdram(DDR0_21, 0x0B0B0B0B);
-#ifdef CONFIG_DDR_ECC
-	mtsdram(DDR0_22, ECC_RAM);
-#else
-	mtsdram(DDR0_22, NO_ECC_RAM);
-#endif
-
-	mtsdram(DDR0_23, 0x00000000);
-	mtsdram(DDR0_24, 0x01020001);
-	mtsdram(DDR0_26, 0x2D930517);
-	mtsdram(DDR0_27, 0x00008236);
-	mtsdram(DDR0_28, 0x00000000);
-	mtsdram(DDR0_31, 0x00000000);
-	mtsdram(DDR0_42, 0x01000006);
-	mtsdram(DDR0_44, 0x00000003);
-	mtsdram(DDR0_02, 0x00000001);
-	wait_for_dlllock();
-	mtsdram(DDR0_00, 0x40000000);  /* Zero init bit */
-
-	/*
-	 * Program tlb entries for this size (dynamic)
-	 */
-	remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20);
-	program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
-
-	/*
-	 * Setup 2nd TLB with same physical address but different virtual
-	 * address with cache enabled. This is done for fast ECC generation.
-	 */
-	program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0);
-
-#ifdef CONFIG_DDR_ECC
-	/*
-	 * If ECC is enabled, initialize the parity bits.
-	 */
-	program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size);
-#endif
-
-	return (dram_size);
-}