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author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-04-05 13:02:43 +0200 |
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committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-04-05 13:02:43 +0200 |
commit | 677e62f43235de9a1701204d7bcea0fb3d233fa1 (patch) | |
tree | 39cfac114059b9e3f8b4c949da614b0475fff890 /cpu/arm920t | |
parent | 36003268968949110ef145d9f2eaf8439c96d25b (diff) | |
download | bootable_bootloader_goldelico_gta04-677e62f43235de9a1701204d7bcea0fb3d233fa1.zip bootable_bootloader_goldelico_gta04-677e62f43235de9a1701204d7bcea0fb3d233fa1.tar.gz bootable_bootloader_goldelico_gta04-677e62f43235de9a1701204d7bcea0fb3d233fa1.tar.bz2 |
arm: update co-processor 15 access
import system.h from linux
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'cpu/arm920t')
-rw-r--r-- | cpu/arm920t/cpu.c | 69 |
1 files changed, 13 insertions, 56 deletions
diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c index 1b9cde6..83ee3f3 100644 --- a/cpu/arm920t/cpu.c +++ b/cpu/arm920t/cpu.c @@ -32,43 +32,12 @@ #include <common.h> #include <command.h> #include <arm920t.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - static void cp_delay (void) { volatile int i; @@ -77,18 +46,6 @@ static void cp_delay (void) for (i = 0; i < 100; i++); } -/* See also ARM920T Technical reference Manual */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ - -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ - - int cpu_init (void) { /* @@ -116,7 +73,7 @@ int cleanup_before_linux (void) /* turn off I/D-cache */ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); + i &= ~(CR_C | CR_I); asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); /* flush I/D-cache */ @@ -138,23 +95,23 @@ void icache_enable (void) { ulong reg; - reg = read_p15_c1 (); /* get control reg. */ + reg = get_cr (); /* get control reg. */ cp_delay (); - write_p15_c1 (reg | C1_IC); + set_cr (reg | CR_I); } void icache_disable (void) { ulong reg; - reg = read_p15_c1 (); + reg = get_cr (); cp_delay (); - write_p15_c1 (reg & ~C1_IC); + set_cr (reg & ~CR_I); } int icache_status (void) { - return (read_p15_c1 () & C1_IC) != 0; + return (get_cr () & CR_I) != 0; } #ifdef USE_920T_MMU @@ -163,23 +120,23 @@ void dcache_enable (void) { ulong reg; - reg = read_p15_c1 (); + reg = get_cr (); cp_delay (); - write_p15_c1 (reg | C1_DC); + set_cr (reg | CR_C); } void dcache_disable (void) { ulong reg; - reg = read_p15_c1 (); + reg = get_cr (); cp_delay (); - reg &= ~C1_DC; - write_p15_c1 (reg); + reg &= ~CR_C; + set_cr (reg); } int dcache_status (void) { - return (read_p15_c1 () & C1_DC) != 0; + return (get_cr () & CR_C) != 0; } #endif |