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authorPaul Gortmaker <paul.gortmaker@windriver.com>2009-07-23 17:10:55 -0400
committerKim Phillips <kim.phillips@freescale.com>2009-07-27 18:35:53 -0500
commitfe613cdd4eb2c5b257a60d8dfb7759742318c28a (patch)
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parentbe9b56df02168ca97562d6b9ec791136e4cd925a (diff)
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sbc8349: combine HRCW flash and u-boot image flash
Up to this point in time, the sbc8349 board was storing the u-boot image in flash 2x. One for the HRCW value at the beginning of flash (0xff80_0000), and once close to the end of flash (0xfff8_0000) for the actual image that got executed. This moves the TEXT_BASE to be the beginning of flash, which makes the second copy of the image redundant, and frees up the flash from the end of the environment storage to the end of the flash device itself. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/README.sbc834930
1 files changed, 20 insertions, 10 deletions
diff --git a/doc/README.sbc8349 b/doc/README.sbc8349
index a0ac638..908e768 100644
--- a/doc/README.sbc8349
+++ b/doc/README.sbc8349
@@ -21,15 +21,22 @@ Flash Details:
The flash type is intel 28F640Jx (4096x16) [one device]. Base address
is 0xFF80_0000 which is also where the Hardware Reset Configuration
-Word (HRCW) is stored. Caution should be used to not overwrite the
-HRCW, or "CF RCW" with a Wind River ICE will be required to restore
-the HRCW and allow the board to enter background mode for further
-steps in the flash process.
+Word (HRCW) is stored. Caution should be used to not reset the
+board without having a valid HRCW in place (i.e. erased flash) as
+then a Wind River ICE will be required to restore the HRCW and flash
+image.
Restoring a corrupted or missing flash image:
=============================================
+Note that U-boot versions up to and including 2009.06 had essentially
+two copies of u-boot in flash; one at the very beginning, which set
+the HRCW, and one at the very end, which was the image that was run.
+As of this point in time, the two have been combined into just one
+at the beginning of flash, which provides both the HRCW, and the image
+that is executed. This frees up the remainder of flash for other uses.
+Use of the u-boot command "fli" will indicate what parts are in use.
Details for storing U-boot to flash using a Wind River ICE can be found
on page 19 of the board manual (request ERG-00328-001). The following
is a summary of that information:
@@ -39,9 +46,9 @@ is a summary of that information:
- Select the appropriate flash type (listed above)
- Prepare a u-boot image by using the Wind River Convert utility;
by using "Convert and Add file" on the ELF file from your build.
- Convert from FFF0_0000 to FFFF_FFFF (or to FFF3_FFFF if you are
- trying to preserve your old environment settings).
- - Set the start address of the erase/flash process to FFF0_0000
+ Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are
+ trying to preserve your old environment settings and user flash).
+ - Set the start address of the erase/flash process to FF80_0000
- Set the target RAM required to 64kB.
- Select sectors for erasing (see note on enviroment below)
- Select Erase and Reprogram.
@@ -59,7 +66,7 @@ beginning with "SCGA TSEC1" and "SCGA TSEC2". This allows you to
use all the remaining register file content.
If you wish to preserve your prior U-Boot environment settings,
-then convert (and erase to) 0xFFF3FFFF instead of 0xFFFFFFFF.
+then convert (and erase to) 0xFF83FFFF instead of 0xFFFFFFFF.
The size for converting (and erasing) must be at least as large
as u-boot.bin.
@@ -73,10 +80,13 @@ has been copied to the TFTP server, the commands are:
tftp 200000 u-boot.bin
protect off all
- erase fff00000 fff3ffff
- cp.b 200000 fff00000 3ffff
+ erase ff800000 ff83ffff
+ cp.b 200000 ff800000 40000
protect on all
+You may wish to do a "md ff800000 20" operation as a prefix and postfix
+to the above steps to inspect/compare the HRCW before/after as an extra
+safety check before resetting the board upon completion of the reflash.
PCI:
====