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| author | Jon Loeliger <jdl@freescale.com> | 2007-07-05 19:52:35 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2007-07-07 20:30:36 -0500 |
| commit | 49cf7e8ee7ef943fdfe866ce28410b0bfbf6a26c (patch) | |
| tree | 15c093e1452b7b7dc3854da115004f631b01f288 /include/configs/CPCI2DP.h | |
| parent | de8b2a6e33298dcdb10bdda48db25e53c3089eba (diff) | |
| download | bootable_bootloader_goldelico_gta04-49cf7e8ee7ef943fdfe866ce28410b0bfbf6a26c.zip bootable_bootloader_goldelico_gta04-49cf7e8ee7ef943fdfe866ce28410b0bfbf6a26c.tar.gz bootable_bootloader_goldelico_gta04-49cf7e8ee7ef943fdfe866ce28410b0bfbf6a26c.tar.bz2 | |
include/configs: Use new CONFIG_CMD_* in various C* named board config files.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Diffstat (limited to 'include/configs/CPCI2DP.h')
| -rw-r--r-- | include/configs/CPCI2DP.h | 26 |
1 files changed, 15 insertions, 11 deletions
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 56fd9a6..def2646 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -54,16 +54,20 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_BSP +#define CONFIG_CMD_EEPROM + +#undef CONFIG_CMD_NET -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -80,7 +84,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -216,7 +220,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif |