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| author | Jon Loeliger <jdl@freescale.com> | 2007-07-07 20:40:43 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2007-07-07 20:40:43 -0500 |
| commit | 3c3227f3c737502311b25b72084573901cbbf17d (patch) | |
| tree | 5cc88e215dd11437cf1faf1c40b68239d13e19ce /include/configs/DP405.h | |
| parent | 49cf7e8ee7ef943fdfe866ce28410b0bfbf6a26c (diff) | |
| download | bootable_bootloader_goldelico_gta04-3c3227f3c737502311b25b72084573901cbbf17d.zip bootable_bootloader_goldelico_gta04-3c3227f3c737502311b25b72084573901cbbf17d.tar.gz bootable_bootloader_goldelico_gta04-3c3227f3c737502311b25b72084573901cbbf17d.tar.bz2 | |
include/configs: Use new CONFIG_CMD_* in various D* named board config files.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Diffstat (limited to 'include/configs/DP405.h')
| -rw-r--r-- | include/configs/DP405.h | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 2ae794d..b50d4f9 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -55,17 +55,20 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -87,7 +90,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -235,7 +238,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif |