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| author | Tony Li <tony.li@freescale.com> | 2007-08-17 10:35:59 +0800 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2007-08-16 23:12:11 -0500 |
| commit | 14778585d1389d86d5846efec29e5fce892680ce (patch) | |
| tree | 29e9cb3245ee88798ad96cb62d7e675a7a5ca173 /include/configs/MPC8360EMDS.h | |
| parent | 35cc4e4823668e8745854899cfaedd4489beb0ef (diff) | |
| download | bootable_bootloader_goldelico_gta04-14778585d1389d86d5846efec29e5fce892680ce.zip bootable_bootloader_goldelico_gta04-14778585d1389d86d5846efec29e5fce892680ce.tar.gz bootable_bootloader_goldelico_gta04-14778585d1389d86d5846efec29e5fce892680ce.tar.bz2 | |
mpc83xx: Split PIB init code from pci.c and add Qoc3 ATM card support
The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c
And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board.
Signed-off-by Tony Li <tony.li@freescale.com>
Diffstat (limited to 'include/configs/MPC8360EMDS.h')
| -rw-r--r-- | include/configs/MPC8360EMDS.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 4b32a14..094b66e 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -32,6 +32,8 @@ #define CONFIG_MPC83XX 1 /* MPC83XX family */ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ +#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ +#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ /* * System Clock Setup @@ -88,6 +90,7 @@ #define CFG_SICRL 0x40000000 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R /* * IMMR new address @@ -309,13 +312,13 @@ /* * CS4 on Local Bus, to PIB */ -#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */ +#define CFG_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */ #define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ /* * CS5 on Local Bus, to PIB */ -#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */ +#define CFG_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */ #define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ /* |