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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-12-02 16:08:39 -0600 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-23 17:03:13 -0600 |
| commit | 5af0fdd81c3370c3a51421208fda568bdcbbec23 (patch) | |
| tree | 5fbd9f1b25951176fdaaa9d7eb76dd486930e6e5 /include/configs/MPC8536DS.h | |
| parent | a6e04c344ad1eefd47a75484441b385da815b8df (diff) | |
| download | bootable_bootloader_goldelico_gta04-5af0fdd81c3370c3a51421208fda568bdcbbec23.zip bootable_bootloader_goldelico_gta04-5af0fdd81c3370c3a51421208fda568bdcbbec23.tar.gz bootable_bootloader_goldelico_gta04-5af0fdd81c3370c3a51421208fda568bdcbbec23.tar.bz2 | |
85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards
Introduce a new define to seperate out the virtual address that PCI
memory is at from the physical address. In most situations these are
mapped 1:1. However any code accessing the bus should use VIRT.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/configs/MPC8536DS.h')
| -rw-r--r-- | include/configs/MPC8536DS.h | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index b2a7d9e..d537940 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -357,32 +357,36 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 |