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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-12-02 16:08:37 -0600 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-23 17:03:13 -0600 |
| commit | 5f91ef6acdbadec33e0192049e2b24a1d9692f1d (patch) | |
| tree | 29582e5722c2b16d2ef9506e1155f11e7d3af3f6 /include/configs/MPC8536DS.h | |
| parent | 10795f42cb94e71bcb262b615084f69dd886399a (diff) | |
| download | bootable_bootloader_goldelico_gta04-5f91ef6acdbadec33e0192049e2b24a1d9692f1d.zip bootable_bootloader_goldelico_gta04-5f91ef6acdbadec33e0192049e2b24a1d9692f1d.tar.gz bootable_bootloader_goldelico_gta04-5f91ef6acdbadec33e0192049e2b24a1d9692f1d.tar.bz2 | |
85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/MPC8536DS.h')
| -rw-r--r-- | include/configs/MPC8536DS.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index e280311..b2a7d9e 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -360,7 +360,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ @@ -368,7 +368,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ @@ -376,7 +376,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ @@ -384,7 +384,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ @@ -424,8 +424,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE + #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ #endif |