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| author | Haiying Wang <Haiying.Wang@freescale.com> | 2009-05-20 12:30:41 -0400 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-06-12 17:17:02 -0500 |
| commit | 3bd8e532b5de20647aeaff94a1cbf33fb8b897b9 (patch) | |
| tree | cc587d893bea49ecaeee7f1c2ed14d3522e70c4f /include/configs/MPC8569MDS.h | |
| parent | e8efef7c1b457442583a8b9d38d8a5b667661616 (diff) | |
| download | bootable_bootloader_goldelico_gta04-3bd8e532b5de20647aeaff94a1cbf33fb8b897b9.zip bootable_bootloader_goldelico_gta04-3bd8e532b5de20647aeaff94a1cbf33fb8b897b9.tar.gz bootable_bootloader_goldelico_gta04-3bd8e532b5de20647aeaff94a1cbf33fb8b897b9.tar.bz2 | |
85xx: Add UEC6 and UEC8 at SGMII mode for MPC8569MDS
On MPC8569MDS board, UCC6 and UCC8 can be configured to work at SGMII mode via
UEM on PB board. Since MPC8569 supports up to 4 Gigabit Ethernet ports, we
disable UEC6 and UEC8 by default.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/MPC8569MDS.h')
| -rw-r--r-- | include/configs/MPC8569MDS.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index c97ea2f..27044f7 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -365,6 +365,31 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH4 */ + +#undef CONFIG_UEC_ETH6 /* GETH6 */ +#define CONFIG_HAS_ETH5 + +#ifdef CONFIG_UEC_ETH6 +#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ +#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC6_PHY_ADDR 4 +#define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII +#endif /* CONFIG_UEC_ETH6 */ + +#undef CONFIG_UEC_ETH8 /* GETH8 */ +#define CONFIG_HAS_ETH7 + +#ifdef CONFIG_UEC_ETH8 +#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ +#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC8_PHY_ADDR 6 +#define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII +#endif /* CONFIG_UEC_ETH8 */ + #endif /* CONFIG_QE */ #if defined(CONFIG_PCI) |