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| author | Kumar Gala <galak@kernel.crashing.org> | 2010-12-17 06:53:52 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-01-14 01:32:20 -0600 |
| commit | 18ea5551307866af06eb7628ec05b1959212efa0 (patch) | |
| tree | 7871c2bce046a93958b5a3704f44cb8acc2ab889 /include/configs/MPC8572DS.h | |
| parent | a4aafcc990c12816cfd4644e5c003d8556b6236b (diff) | |
| download | bootable_bootloader_goldelico_gta04-18ea5551307866af06eb7628ec05b1959212efa0.zip bootable_bootloader_goldelico_gta04-18ea5551307866af06eb7628ec05b1959212efa0.tar.gz bootable_bootloader_goldelico_gta04-18ea5551307866af06eb7628ec05b1959212efa0.tar.bz2 | |
powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe code
Remove duplicated code in MPC8572DS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Chenhui Zhao <b26998@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/MPC8572DS.h')
| -rw-r--r-- | include/configs/MPC8572DS.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 8cdcbea..9ec02cc 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -467,6 +467,7 @@ */ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ +#define CONFIG_SYS_PCIE3_NAME "ULI" #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 @@ -486,6 +487,7 @@ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 @@ -505,6 +507,7 @@ #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |