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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-01-23 14:22:12 -0600 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-23 17:08:28 -0600 |
| commit | 72a9414a8e21e9536822c7353bc08d21ce5ad53d (patch) | |
| tree | 840821484d1525c7f37bce65dc5e16ddc4f85276 /include/configs/MPC8572DS.h | |
| parent | 2fc7eb0cfc608c9369001d57a0411af5e6a58f7c (diff) | |
| download | bootable_bootloader_goldelico_gta04-72a9414a8e21e9536822c7353bc08d21ce5ad53d.zip bootable_bootloader_goldelico_gta04-72a9414a8e21e9536822c7353bc08d21ce5ad53d.tar.gz bootable_bootloader_goldelico_gta04-72a9414a8e21e9536822c7353bc08d21ce5ad53d.tar.bz2 | |
85xx: Use BR_ADDR macro for NAND chipselects
Use the new BR_ADDR macro to properly setup the address field of the
localbus chipselects used by NAND.
This allows us to deal with 36-bit phys on these boards in the future.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/MPC8572DS.h')
| -rw-r--r-- | include/configs/MPC8572DS.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 0277a42..332a0e3 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -275,7 +275,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ @@ -292,20 +292,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ +#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ +#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ |