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| author | Haiying Wang <Haiying.Wang@freescale.com> | 2009-01-13 16:29:28 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-13 16:58:46 -0600 |
| commit | b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6 (patch) | |
| tree | 86bc278f77095fe7d3279605e972eb45007e976c /include/configs/MPC8572DS.h | |
| parent | 950264317eb9594b2b5ee2fb65206200a1c6007a (diff) | |
| download | bootable_bootloader_goldelico_gta04-b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6.zip bootable_bootloader_goldelico_gta04-b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6.tar.gz bootable_bootloader_goldelico_gta04-b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6.tar.bz2 | |
Some changes of TLB entry setting for MPC8572DS
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)
- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Diffstat (limited to 'include/configs/MPC8572DS.h')
| -rw-r--r-- | include/configs/MPC8572DS.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 37c3f42..6c7a364 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -92,6 +92,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) /* DDR Setup */ +#define CONFIG_SYS_DDR_TLB_START 9 #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |