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| author | wdenk <wdenk> | 2004-09-09 17:44:35 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-09-09 17:44:35 +0000 |
| commit | 1d6f97209ee1efc60e37b983046e3189f359e22a (patch) | |
| tree | 3114bdfc74120813fee73e85028f201dddd36605 /include/configs/PPChameleonEVB.h | |
| parent | eedcd078fe1434d93b84322c4e14c52f80282a41 (diff) | |
| download | bootable_bootloader_goldelico_gta04-1d6f97209ee1efc60e37b983046e3189f359e22a.zip bootable_bootloader_goldelico_gta04-1d6f97209ee1efc60e37b983046e3189f359e22a.tar.gz bootable_bootloader_goldelico_gta04-1d6f97209ee1efc60e37b983046e3189f359e22a.tar.bz2 | |
Fix SysClk handling for PPChameleon and CATcenter boards
Diffstat (limited to 'include/configs/PPChameleonEVB.h')
| -rw-r--r-- | include/configs/PPChameleonEVB.h | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index b1f41a1..03020f2 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -102,8 +102,8 @@ #define CONFIG_MII 1 /* MII PHY management */ #ifndef CONFIG_EXT_PHY -#define CONFIG_PHY_ADDR 0 /* EMAC0 PHY address */ -#define CONFIG_PHY1_ADDR 1 /* EMAC1 PHY address */ +#define CONFIG_PHY_ADDR 0 /* EMAC0 PHY address */ +#define CONFIG_PHY1_ADDR 1 /* EMAC1 PHY address */ #else #define CONFIG_PHY_ADDR 2 /* PHY address */ #endif @@ -514,7 +514,6 @@ #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ - #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -535,7 +534,7 @@ #define CFG_GPIO0_OSRH 0x40000550 #define CFG_GPIO0_OSRL 0x00000110 #define CFG_GPIO0_ISR1H 0x00000000 -/*#define CFG_GPIO0_ISR1L 0x15555445*/ +/*#define CFG_GPIO0_ISR1L 0x15555445*/ #define CFG_GPIO0_ISR1L 0x15555444 #define CFG_GPIO0_TSRH 0x00000000 #define CFG_GPIO0_TSRL 0x00000000 @@ -551,8 +550,9 @@ #define CONFIG_NO_SERIAL_EEPROM -/*#undef CONFIG_NO_SERIAL_EEPROM*/ + /*--------------------------------------------------------------------*/ + #ifdef CONFIG_NO_SERIAL_EEPROM /* @@ -677,7 +677,6 @@ #define PLL_PCIDIV_3 0x00000002 #define PLL_PCIDIV_4 0x00000003 - #ifdef CONFIG_PPCHAMELEON_CLK_25 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ @@ -745,24 +744,24 @@ #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) /* Model HI */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 #define CFG_OPB_FREQ 55555555 /* Model ME */ #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 #define CFG_OPB_FREQ 66666666 #else /* Model BA (default) */ -#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 -#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 +#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 +#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 #define CFG_OPB_FREQ 66666666 #endif -#endif +#endif /* CONFIG_NO_SERIAL_EEPROM */ -#define CONFIG_JFFS2_NAND 0 /* jffs2 on nand support */ +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ #define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */ #define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */ #define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */ |