Re-factoring the legacy NAND code (legacy NAND now only in board-specific

code and in SoC code). Boards using the old way have CFG_NAND_LEGACY and
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a added. Build breakage for
NETTA.ERR and NETTA_ISDN - will go away when the new NAND support is
implemented for these boards.

1 files changed, 17 insertions, 86 deletions

diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index c406c8f..88e6db4 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -188,36 +188,31 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+/*
+ * nand device 1 on dave (PPChameleonEVB) needs more time,
+ * so we just introduce additional wait in nand_wait(),
+ * effectively for both devices.
+ */
+#define PPCHAMELON_NAND_TIMER_HACK
 
-/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
-#define CONFIG_NEW_NAND_CODE
 #define CFG_NAND0_BASE 0xFF400000
 #define CFG_NAND1_BASE 0xFF000000
 #define CFG_NAND_BASE_LIST	{ CFG_NAND0_BASE, CFG_NAND1_BASE }
 #define NAND_BIG_DELAY_US	25
 #define CFG_MAX_NAND_DEVICE	2	/* Max number of NAND devices */
-#define SECTORSIZE 512
-#define NAND_NO_RB
 
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1
 
 #define CFG_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
+#define CFG_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
 #define CFG_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
 #define CFG_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
-#define CFG_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
 
 #define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
+#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 #define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
 #define CFG_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
-#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 
-#ifdef CONFIG_NEW_NAND_CODE
 #define MACRO_NAND_DISABLE_CE(nandptr) do \
 { \
 	switch((unsigned long)nandptr) \
@@ -293,83 +288,19 @@
 		break; \
 	} \
 } while(0)
-#else
-#define NAND_DISABLE_CE(nand) do \
-{ \
-	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
-		break; \
-	} \
-} while(0)
 
-#define NAND_ENABLE_CE(nand) do \
-{ \
-	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
-		break; \
-	} \
-} while(0)
+#if 0
+#define SECTORSIZE 512
+#define NAND_NO_RB
 
-#define NAND_CTL_CLRALE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
-		break; \
-	} \
-} while(0)
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
 
-#define NAND_CTL_SETALE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
-		break; \
-	} \
-} while(0)
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
 
-#define NAND_CTL_CLRCLE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
-		break; \
-	} \
-} while(0)
 
-#define NAND_CTL_SETCLE(nandptr) do { \
-	switch((unsigned long)nandptr) { \
-	case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
-		break; \
-	case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
-		break; \
-	} \
-} while(0)
-#endif /* !CONFIG_NEW_NAND_CODE */
 
 #ifdef NAND_NO_RB
 /* constant delay (see also tR in the datasheet) */
@@ -385,7 +316,7 @@
 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
+#endif
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------