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| author | David Brownell <david-b@pacbell.net> | 2009-07-16 18:40:55 -0700 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-08-03 09:26:26 +0200 |
| commit | 06bffc6ea52d4b390843d295d438b2037d12e5fd (patch) | |
| tree | 689ea76a23daa57493debfc4fbbf11984bab7271 /include/configs/at91rm9200ek.h | |
| parent | 301b7db88fbdf7d118efb79b371b2527a2c31868 (diff) | |
| download | bootable_bootloader_goldelico_gta04-06bffc6ea52d4b390843d295d438b2037d12e5fd.zip bootable_bootloader_goldelico_gta04-06bffc6ea52d4b390843d295d438b2037d12e5fd.tar.gz bootable_bootloader_goldelico_gta04-06bffc6ea52d4b390843d295d438b2037d12e5fd.tar.bz2 | |
rm9200 lowevel_init: don't touch reserved/readonly registers
For some reason the AT91rm9200 lowlevel init writes to a bunch of
reserved or read-only addresses. All the boards seem to define the
value-to-be-written values as zero ... but they shouldn't actually
be writing *anything* there.
No documented erratum justifies these accesses. It looks like maybe
some pre-release BDI-2000 setup code has been carried along by cargo
cult programming since at least late 2004 (per GIT history).
Here's a patch disabling what seems to be bogosity. Tested on a
csb337; there were no behavioral changes.
Signed-off-by: David Brownell <david-b@pacbell.net>
on RM9200ek
Tested-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'include/configs/at91rm9200ek.h')
| -rw-r--r-- | include/configs/at91rm9200ek.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index 58ec94a..b4f075e 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -56,11 +56,6 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ -#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 -#define CONFIG_SYS_MC_PUP_VAL 0x00000000 -#define CONFIG_SYS_MC_PUER_VAL 0x00000000 -#define CONFIG_SYS_MC_ASR_VAL 0x00000000 -#define CONFIG_SYS_MC_AASR_VAL 0x00000000 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ |