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| author | Stefan Roese <sr@denx.de> | 2007-08-14 15:00:42 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-08-14 15:00:42 +0200 |
| commit | 34886bbea20b577e8bdef81f3831319f1876b9b7 (patch) | |
| tree | 06d3819c6f50eda7079645da8db458956a5781f3 /include/ppc405.h | |
| parent | 273db7e1bdd1937e32f1d4507321bb721ebd3118 (diff) | |
| parent | 779e975117a75e91fcebe226a63104dbfb924ab1 (diff) | |
| download | bootable_bootloader_goldelico_gta04-34886bbea20b577e8bdef81f3831319f1876b9b7.zip bootable_bootloader_goldelico_gta04-34886bbea20b577e8bdef81f3831319f1876b9b7.tar.gz bootable_bootloader_goldelico_gta04-34886bbea20b577e8bdef81f3831319f1876b9b7.tar.bz2 | |
Merge with /home/stefan/git/u-boot/zeus
Diffstat (limited to 'include/ppc405.h')
| -rw-r--r-- | include/ppc405.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/ppc405.h b/include/ppc405.h index e4522e7..0c7bf3e 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -541,6 +541,18 @@ #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) +#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_1) +#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) /* * PLL Voltage Controlled Oscillator (VCO) definitions @@ -1228,6 +1240,8 @@ #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) +#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0) +#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0) #ifndef __ASSEMBLY__ |