diff options
| author | Stefan Roese <sr@denx.de> | 2007-06-06 11:42:13 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-06-06 11:42:13 +0200 |
| commit | c440bfe6d6d92d66478a7e84402b31f48413617b (patch) | |
| tree | 7919ffbc5fdf5a1bb7dddf066ae904aad1058135 /include/ppc405.h | |
| parent | e3cbe1f93c5722f8ebbad468e30c069a2b511097 (diff) | |
| download | bootable_bootloader_goldelico_gta04-c440bfe6d6d92d66478a7e84402b31f48413617b.zip bootable_bootloader_goldelico_gta04-c440bfe6d6d92d66478a7e84402b31f48413617b.tar.gz bootable_bootloader_goldelico_gta04-c440bfe6d6d92d66478a7e84402b31f48413617b.tar.bz2 | |
ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board
This patch adds NAND booting support for the AMCC Acadia eval board.
Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.
I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:
=> bootstrap 267 nor ;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand ;to configure the board for 267MHz NNAND booting
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/ppc405.h')
| -rw-r--r-- | include/ppc405.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/ppc405.h b/include/ppc405.h index fffae4d..71ad12e 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -556,6 +556,11 @@ #define sdricintstat 0x4510 #define SDR_NAND0_NDEN 0x80000000 +#define SDR_NAND0_NDBTEN 0x40000000 +#define SDR_NAND0_NDBADR_MASK 0x30000000 +#define SDR_NAND0_NDBPG_MASK 0x0f000000 +#define SDR_NAND0_NDAREN 0x00800000 +#define SDR_NAND0_NDRBEN 0x00400000 #define SDR_ULTRA0_NDGPIOBP 0x80000000 #define SDR_ULTRA0_CSN_MASK 0x78000000 @@ -563,6 +568,9 @@ #define SDR_ULTRA0_CSNSEL1 0x20000000 #define SDR_ULTRA0_CSNSEL2 0x10000000 #define SDR_ULTRA0_CSNSEL3 0x08000000 +#define SDR_ULTRA0_EBCRDYEN 0x04000000 +#define SDR_ULTRA0_SPISSINEN 0x02000000 +#define SDR_ULTRA0_NFSRSTEN 0x01000000 #define SDR_ULTRA1_LEDNENABLE 0x40000000 |