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| author | Stefan Roese <sr@denx.de> | 2009-10-19 14:06:23 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-23 16:04:36 +0200 |
| commit | 5e47f9535f53fd4cc05f32fb6166870f976fbb4e (patch) | |
| tree | 68b7e4f2a7167fac1d056de8bcf0b9d5fb4769eb /include/ppc440.h | |
| parent | 92b8964bed0d1b779d9e26be4e16755b5c635415 (diff) | |
| download | bootable_bootloader_goldelico_gta04-5e47f9535f53fd4cc05f32fb6166870f976fbb4e.zip bootable_bootloader_goldelico_gta04-5e47f9535f53fd4cc05f32fb6166870f976fbb4e.tar.gz bootable_bootloader_goldelico_gta04-5e47f9535f53fd4cc05f32fb6166870f976fbb4e.tar.bz2 | |
ppc4xx: Add function to check and dynamically change PCI sync clock
PPC440EP(x)/PPC440GR(x):
In asynchronous PCI mode, the synchronous PCI clock must meet
certain requirements. The following equation describes the
relationship that must be maintained between the asynchronous PCI
clock and synchronous PCI clock. Select an appropriate PCI:PLB
ratio to maintain the relationship:
AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
This patch now adds a function to check and reconfigure the sync
PCI clock to meet this requirement. This is in preparation for
some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this
function to not violate the PCI clocking rules.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/ppc440.h')
| -rw-r--r-- | include/ppc440.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index fe0db93..e54a977 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1701,9 +1701,14 @@ #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ #endif /* CONFIG_440GX */ -#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define CPR0_ICFG_RLI_MASK 0x80000000 #define CPR0_SPCID_SPCIDV0_MASK 0x03000000 +#define CPR0_SPCID_SPCIDV0_DIV1 0x01000000 +#define CPR0_SPCID_SPCIDV0_DIV2 0x02000000 +#define CPR0_SPCID_SPCIDV0_DIV3 0x03000000 +#define CPR0_SPCID_SPCIDV0_DIV4 0x00000000 #define CPR0_PERD_PERDV0_MASK 0x07000000 #endif |