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authorStefan Roese <sr@denx.de>2006-11-29 12:03:57 +0100
committerStefan Roese <sr@denx.de>2006-11-29 12:03:57 +0100
commit4e26f1074c3ac1bd8fd094f0dc4a1c4a0b15a592 (patch)
tree086d6b6dc6d8b01d3fe5e9f2495f1d65ad32f2dd /include/ppc440.h
parente59581c56ab5d6e0207ddac3b2c1d55cb36ec706 (diff)
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[PATCH] include/ppc440.h minor error affecting interrupts
Fixed include/ppc440.c for UIC address Bug Corrects bug affecting the addresses for the universal interrupt controller UIC2 and UIC3 on the PPC440 Epx, GRx, and SPE chips. Signed-off-by: Jeff Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/ppc440.h')
-rw-r--r--include/ppc440.h36
1 files changed, 18 insertions, 18 deletions
diff --git a/include/ppc440.h b/include/ppc440.h
index 407daae..50f4ec4 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1350,26 +1350,26 @@
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UIC2_DCR_BASE 0xe0
-#define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */
-#define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */
-#define uic2er (UIC0_DCR_BASE+0x2) /* UIC2 enable */
-#define uic2cr (UIC0_DCR_BASE+0x3) /* UIC2 critical */
-#define uic2pr (UIC0_DCR_BASE+0x4) /* UIC2 polarity */
-#define uic2tr (UIC0_DCR_BASE+0x5) /* UIC2 triggering */
-#define uic2msr (UIC0_DCR_BASE+0x6) /* UIC2 masked status */
-#define uic2vr (UIC0_DCR_BASE+0x7) /* UIC2 vector */
-#define uic2vcr (UIC0_DCR_BASE+0x8) /* UIC2 vector configuration */
+#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
+#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
+#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
+#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
+#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
+#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
+#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
+#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
+#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
#define UIC3_DCR_BASE 0xf0
-#define uic3sr (UIC1_DCR_BASE+0x0) /* UIC3 status-Read Clear */
-#define uic3srs (UIC0_DCR_BASE+0x1) /* UIC3 status-Read Set */
-#define uic3er (UIC1_DCR_BASE+0x2) /* UIC3 enable */
-#define uic3cr (UIC1_DCR_BASE+0x3) /* UIC3 critical */
-#define uic3pr (UIC1_DCR_BASE+0x4) /* UIC3 polarity */
-#define uic3tr (UIC1_DCR_BASE+0x5) /* UIC3 triggering */
-#define uic3msr (UIC1_DCR_BASE+0x6) /* UIC3 masked status */
-#define uic3vr (UIC1_DCR_BASE+0x7) /* UIC3 vector */
-#define uic3vcr (UIC1_DCR_BASE+0x8) /* UIC3 vector configuration */
+#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
+#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
+#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
+#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
+#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
+#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
+#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
+#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
+#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
#endif /* CONFIG_440SPE */
#if defined(CONFIG_440GX)