diff options
| -rwxr-xr-x | MAKEALL | 1 | ||||
| -rw-r--r-- | Makefile | 6 | ||||
| -rw-r--r-- | board/freescale/mpc8315erdb/config.mk | 8 | ||||
| -rw-r--r-- | board/freescale/mpc8315erdb/mpc8315erdb.c | 42 | ||||
| -rw-r--r-- | board/freescale/mpc8315erdb/sdram.c | 9 | ||||
| -rw-r--r-- | doc/README.mpc8315erdb | 29 | ||||
| -rw-r--r-- | include/configs/MPC8315ERDB.h | 95 |
7 files changed, 167 insertions, 23 deletions
@@ -362,6 +362,7 @@ LIST_83xx=" \ MPC8313ERDB_33 \ MPC8313ERDB_NAND_66 \ MPC8315ERDB \ + MPC8315ERDB_NAND \ MPC8323ERDB \ MPC832XEMDS \ MPC832XEMDS_ATM \ @@ -2261,8 +2261,12 @@ MPC8313ERDB_NAND_66_config: unconfig echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \ fi ; +MPC8315ERDB_NAND_config \ MPC8315ERDB_config: unconfig - @$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale + @if [ "$(findstring _NAND_,$@)" ] ; then \ + ln -sf mpc8313erdb nand_spl/board/freescale/mpc8315erdb ; \ + fi ; + @$(MKCONFIG) -t $(@:_config=) MPC8315ERDB ppc mpc83xx mpc8315erdb freescale MPC8323ERDB_config: unconfig @$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale diff --git a/board/freescale/mpc8315erdb/config.mk b/board/freescale/mpc8315erdb/config.mk index f768264..bf972fb 100644 --- a/board/freescale/mpc8315erdb/config.mk +++ b/board/freescale/mpc8315erdb/config.mk @@ -1 +1,9 @@ +ifndef NAND_SPL +ifeq ($(CONFIG_MK_NAND), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +endif +endif + +ifndef TEXT_BASE TEXT_BASE = 0xFE000000 +endif diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index dea4d6f..d5e71dc 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -32,6 +32,8 @@ #include <mpc83xx.h> #include <netdev.h> #include <asm/io.h> +#include <ns16550.h> +#include <nand.h> DECLARE_GLOBAL_DATA_PTR; @@ -45,6 +47,8 @@ int board_early_init_f(void) return 0; } +#ifndef CONFIG_NAND_SPL + static u8 read_board_info(void) { u8 val8; @@ -220,3 +224,41 @@ int board_eth_init(bd_t *bis) cpu_eth_init(bis); /* Initialize TSECs first */ return pci_eth_init(bis); } + +#else /* CONFIG_NAND_SPL */ + +int checkboard(void) +{ + puts("Board: Freescale MPC8315ERDB\n"); + return 0; +} + +void board_init_f(ulong bootflag) +{ + board_early_init_f(); + NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + puts("NAND boot... "); + init_timebase(); + initdram(0); + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (gd->flags & GD_FLG_SILENT) + return; + + if (c == '\n') + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); + + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); +} + +#endif /* CONFIG_NAND_SPL */ diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c index ead7b1e..fe8ec1e 100644 --- a/board/freescale/mpc8315erdb/sdram.c +++ b/board/freescale/mpc8315erdb/sdram.c @@ -54,6 +54,7 @@ static void resume_from_sleep(void) * This is useful for faster booting in configs where the RAM is unlikely * to be changed, or for things like NAND booting where space is tight. */ +#ifndef CONFIG_SYS_RAMBOOT static long fixed_sdram(void) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; @@ -68,7 +69,7 @@ static long fixed_sdram(void) * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], * or the DDR2 controller may fail to initialize correctly. */ - udelay(50000); + __udelay(50000); im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; @@ -100,6 +101,12 @@ static long fixed_sdram(void) return msize; } +#else +static long fixed_sdram(void) +{ + return CONFIG_SYS_DDR_SIZE * 1024 * 1024; +} +#endif /* CONFIG_SYS_RAMBOOT */ phys_size_t initdram(int board_type) { diff --git a/doc/README.mpc8315erdb b/doc/README.mpc8315erdb index 7d476d0..b32132d 100644 --- a/doc/README.mpc8315erdb +++ b/doc/README.mpc8315erdb @@ -15,6 +15,18 @@ Freescale MPC8315ERDB Board 4321 4321 (where the '*' indicates the position of the tab of the switch.) + To boot the image at the beginning of NAND flash, use these + DIP switch settings for S3 S4: + + +------+ +------+ + | * | | *** | + | *** | | * | + +------+ ON +------+ ON + 4321 4321 + (where the '*' indicates the position of the tab of the switch.) + + When booting from NAND, use u-boot-nand.bin, not u-boot.bin. + 2. Memory Map The memory map looks like this: @@ -26,6 +38,9 @@ Freescale MPC8315ERDB Board 0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M + When booting from NAND, NAND flash is CS0 and NOR flash + is CS1. + 3. Definitions 3.1 Explanation of NEW definitions in: @@ -43,13 +58,15 @@ Freescale MPC8315ERDB Board export CROSS_COMPILE=your-cross-compiler-prefix- make distclean - make MPC8315ERDB_config + make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin) make all 5. Downloading and Flashing Images 5.1 Reflash U-boot Image using U-boot + NOR flash: + tftp 40000 u-boot.bin protect off all erase fe000000 fe1fffff @@ -60,6 +77,15 @@ Freescale MPC8315ERDB Board You have to supply the correct byte count with 'xxxx' from the TFTP result log. + NAND flash: + + =>tftpboot $loadaddr <filename> + =>nand erase 0 0x80000 + =>nand write $loadaddr 0 0x80000 + + ...where 0x80000 is the filesize rounded up to + the next 0x20000 increment. + 5.2 Downloading and Booting Linux Kernel Ensure that all networking-related environment variables are set @@ -76,5 +102,4 @@ Freescale MPC8315ERDB Board 6 Notes - Booting from NAND flash is not yet supported. The console baudrate for MPC8315ERDB is 115200bps. diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 79376b3..cfed4ca 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -25,6 +25,11 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0x00100000 +#endif + /* * High Level Configuration Options */ @@ -51,20 +56,29 @@ HRCWL_SVCOD_DIV_2 |\ HRCWL_CSB_TO_CLKIN_2X1 |\ HRCWL_CORE_TO_CSB_3X1) -#define CONFIG_SYS_HRCW_HIGH (\ +#define CONFIG_SYS_HRCW_HIGH_BASE (\ HRCWH_PCI_HOST |\ HRCWH_PCI1_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ HRCWH_BOOTSEQ_DISABLE |\ HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ HRCWH_TSEC1M_IN_RGMII |\ HRCWH_TSEC2M_IN_RGMII |\ HRCWH_BIG_ENDIAN |\ HRCWH_LALE_NORMAL) +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_ROM_LOC_NAND_SP_8BIT |\ + HRCWH_RL_EXT_NAND) +#else +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY) +#endif + /* * System IO Config */ @@ -79,6 +93,10 @@ */ #define CONFIG_SYS_IMMR 0xE0000000 +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR +#endif + /* * Arbiter Setup */ @@ -161,12 +179,6 @@ */ #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ @@ -200,10 +212,10 @@ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ -#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ +#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ +#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -223,18 +235,31 @@ /* * NAND Flash on the Local Bus */ -#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ + +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#else +#define CONFIG_SYS_NAND_BASE 0xE0600000 +#endif + #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ +#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -243,9 +268,31 @@ | OR_FCM_EHTR ) /* 0xFFFF8396 */ +#ifdef CONFIG_NAND_U_BOOT +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM +#endif + #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM + +#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ + !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + /* * Serial Port */ @@ -254,7 +301,7 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} @@ -408,7 +455,16 @@ /* * Environment */ -#ifndef CONFIG_SYS_RAMBOOT +#if defined(CONFIG_NAND_U_BOOT) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET (512 * 1024) + #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) + #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_RANGE) +#elif !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ @@ -442,7 +498,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_PCI -#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif @@ -504,7 +560,8 @@ /* FLASH: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |