diff options
Diffstat (limited to 'arch/sh/include/asm')
| -rw-r--r-- | arch/sh/include/asm/cpu_sh3.h | 6 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh4.h | 2 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh7706.h | 53 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh7722.h | 38 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh7750.h | 16 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh7757.h | 218 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh7780.h | 21 | ||||
| -rw-r--r-- | arch/sh/include/asm/zimage.h | 41 |
8 files changed, 319 insertions, 76 deletions
diff --git a/arch/sh/include/asm/cpu_sh3.h b/arch/sh/include/asm/cpu_sh3.h index 6db38a2..385f5dc 100644 --- a/arch/sh/include/asm/cpu_sh3.h +++ b/arch/sh/include/asm/cpu_sh3.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * (C) Copyright 2007-2009 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> * * This program is free software; you can redistribute it and/or @@ -31,7 +31,9 @@ #define CACHE_OC_NUM_ENTRIES 256 #define CACHE_OC_ENTRY_SHIFT 4 -#if defined(CONFIG_CPU_SH7710) +#if defined(CONFIG_CPU_SH7706) +#include <asm/cpu_sh7706.h> +#elif defined(CONFIG_CPU_SH7710) #include <asm/cpu_sh7710.h> #elif defined(CONFIG_CPU_SH7720) #include <asm/cpu_sh7720.h> diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h index fdcebd6..9b29d3a 100644 --- a/arch/sh/include/asm/cpu_sh4.h +++ b/arch/sh/include/asm/cpu_sh4.h @@ -44,6 +44,8 @@ # include <asm/cpu_sh7722.h> #elif defined (CONFIG_CPU_SH7723) # include <asm/cpu_sh7723.h> +#elif defined (CONFIG_CPU_SH7757) +# include <asm/cpu_sh7757.h> #elif defined (CONFIG_CPU_SH7763) # include <asm/cpu_sh7763.h> #elif defined (CONFIG_CPU_SH7780) diff --git a/arch/sh/include/asm/cpu_sh7706.h b/arch/sh/include/asm/cpu_sh7706.h new file mode 100644 index 0000000..d093f88 --- /dev/null +++ b/arch/sh/include/asm/cpu_sh7706.h @@ -0,0 +1,53 @@ +#ifndef _ASM_CPU_SH7706_H_ +#define _ASM_CPU_SH7706_H_ + +#define CACHE_OC_NUM_WAYS 4 +#define CCR_CACHE_INIT 0x0000000D + +/* MMU and Cache control */ +#define MMUCR 0xFFFFFFE0 +#define CCR 0xFFFFFFEC + +/* PFC */ +#define PACR 0xA4050100 +#define PBCR 0xA4050102 +#define PCCR 0xA4050104 +#define PETCR 0xA4050106 + +/* Port Data Registers */ +#define PADR 0xA4050120 +#define PBDR 0xA4050122 +#define PCDR 0xA4050124 + +/* BSC */ +#define FRQCR 0xffffff80 +#define BCR1 0xffffff60 +#define BCR2 0xffffff62 +#define WCR1 0xffffff64 +#define WCR2 0xffffff66 +#define MCR 0xffffff68 + +/* SDRAM controller */ +#define DCR 0xffffff6a +#define RTCSR 0xffffff6e +#define RTCNT 0xffffff70 +#define RTCOR 0xffffff72 +#define RFCR 0xffffff74 +#define SDMR 0xFFFFD000 +#define CS3_R 0xFFFFE460 + +/* SCIF */ +#define SCSMR_2 0xA4000150 +#define SCIF0_BASE SCSMR_2 + +/* Timer */ +#define TSTR0 0xFFFFFE92 +#define TSTR TSTR0 +#define TCNT0 0xFFFFFE98 +#define TCR0 0xFFFFFE9C + +/* On chip oscillator circuits */ +#define WTCNT 0xFFFFFF84 +#define WTCSR 0xFFFFFF86 + +#endif /* _ASM_CPU_SH7706_H_ */ diff --git a/arch/sh/include/asm/cpu_sh7722.h b/arch/sh/include/asm/cpu_sh7722.h index 0975b78..3157dcb 100644 --- a/arch/sh/include/asm/cpu_sh7722.h +++ b/arch/sh/include/asm/cpu_sh7722.h @@ -325,44 +325,6 @@ #define SPICR1 0xA4420030 /* SCIF */ -/* -#define SCSMR 0xFFE00000 -#define SCBRR 0xFFE00004 -#define SCSCR 0xFFE00008 -#define SCFTDR 0xFFE0000C -#define SCFSR 0xFFE00010 -#define SCFRDR 0xFFE00014 -#define SCFCR 0xFFE00018 -#define SCFDR 0xFFE0001C -#define SCLSR 0xFFE00024 -#define SCSMR1 0xFFE10000 -#define SCBRR1 0xFFE10004 -#define SCSCR1 0xFFE10008 -#define SCFTDR1 0xFFE1000C -#define SCFSR1 0xFFE10010 -#define SCFRDR1 0xFFE10014 -#define SCFCR1 0xFFE10018 -#define SCFDR1 0xFFE1001C -#define SCLSR1 0xFFE10024 -#define SCSMR2 0xFFE20000 -#define SCBRR2 0xFFE20004 -#define SCSCR2 0xFFE20008 -#define SCFTDR2 0xFFE2000C -#define SCFSR2 0xFFE20010 -#define SCFRDR2 0xFFE20014 -#define SCFCR2 0xFFE20018 -#define SCFDR2 0xFFE2001C -#define SCLSR2 0xFFE20024 -#define SCSMR3 0xFFE30000 -#define SCBRR3 0xFFE30004 -#define SCSCR3 0xFFE30008 -#define SCFTDR3 0xFFE3000C -#define SCFSR3 0xFFE30010 -#define SCFRDR3 0xFFE30014 -#define SCFCR3 0xFFE30018 -#define SCFDR3 0xFFE3001C -#define SCLSR3 0xFFE30024 -*/ #define SCIF0_BASE 0xFFE00000 /* SIM */ diff --git a/arch/sh/include/asm/cpu_sh7750.h b/arch/sh/include/asm/cpu_sh7750.h index 4e43a46..b3e8424 100644 --- a/arch/sh/include/asm/cpu_sh7750.h +++ b/arch/sh/include/asm/cpu_sh7750.h @@ -166,26 +166,10 @@ /* SCI */ #define SCSMR1 0xFFE00000 -#define SCBRR1 0xFFE00004 -#define SCSCR1 0xFFE00008 -#define SCTDR1 0xFFE0000C -#define SCSSR1 0xFFE00010 -#define SCRDR1 0xFFE00014 -#define SCSCMR1 0xFFE00018 -#define SCSPTR1 0xFFE0001C #define SCF0_BASE SCSMR1 /* SCIF */ #define SCSMR2 0xFFE80000 -#define SCBRR2 0xFFE80004 -#define SCSCR2 0xFFE80008 -#define SCFTDR2 0xFFE8000C -#define SCFSR2 0xFFE80010 -#define SCFRDR2 0xFFE80014 -#define SCFCR2 0xFFE80018 -#define SCFDR2 0xFFE8001C -#define SCSPTR2 0xFFE80020 -#define SCLSR2 0xFFE80024 #define SCIF1_BASE SCSMR2 /* H-UDI */ diff --git a/arch/sh/include/asm/cpu_sh7757.h b/arch/sh/include/asm/cpu_sh7757.h new file mode 100644 index 0000000..17a6537 --- /dev/null +++ b/arch/sh/include/asm/cpu_sh7757.h @@ -0,0 +1,218 @@ +/* + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CPU_SH7757_H_ +#define _ASM_CPU_SH7757_H_ + +#define CCR 0xFF00001C +#define WTCNT 0xFFCC0000 +#define CCR_CACHE_INIT 0x0000090b +#define CACHE_OC_NUM_WAYS 1 + +#ifndef __ASSEMBLY__ /* put C only stuff in this section */ +/* MMU */ +struct mmu_regs { + unsigned int reserved[4]; + unsigned int mmucr; +}; +#define MMU_BASE ((struct mmu_regs *)0xff000000) + +/* Watchdog */ +#define WTCSR0 0xffcc0002 +#define WRSTCSR_R 0xffcc0003 +#define WRSTCSR_W 0xffcc0002 +#define WTCSR_PREFIX 0xa500 +#define WRSTCSR_PREFIX 0x6900 +#define WRSTCSR_WOVF_PREFIX 0x9600 + +/* SCIF */ +#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */ +#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */ +#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */ + +/* SerMux */ +#define SMR0 0xfe470000 + +/* TMU0 */ +#define TSTR 0xFE430004 +#define TOCR 0xFE430000 +#define TSTR0 0xFE430004 +#define TCOR0 0xFE430008 +#define TCNT0 0xFE43000C +#define TCR0 0xFE430010 +#define TCOR1 0xFE430014 +#define TCNT1 0xFE430018 +#define TCR1 0xFE43001C +#define TCOR2 0xFE430020 +#define TCNT2 0xFE430024 +#define TCR2 0xFE430028 +#define TCPR2 0xFE43002C + +/* ETHER, GETHER MAC address */ +struct ether_mac_regs { + unsigned int reserved[114]; + unsigned int mahr; + unsigned int reserved2; + unsigned int malr; +}; +#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400) +#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00) +#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000) +#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800) + +/* GETHER */ +struct gether_control_regs { + unsigned int gbecont; +}; +#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100) +#define GBECONT_RMII1 0x00020000 +#define GBECONT_RMII0 0x00010000 + +/* USB0/1 */ +struct usb_common_regs { + unsigned short reserved[129]; + unsigned short suspmode; +}; +#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000) +#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000) + +struct usb0_phy_regs { + unsigned short reset; + unsigned short reserved[4]; + unsigned short portsel; +}; +#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000) + +struct usb1_port_regs { + unsigned int port1sel; + unsigned int reserved; + unsigned int usb1intsts; +}; +#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000) + +struct usb1_alignment_regs { + unsigned int ehcidatac; /* 0xfe4fe018 */ + unsigned int reserved[63]; + unsigned int ohcidatac; +}; +#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018) + +/* GCTRL, GRA */ +struct gctrl_regs { + unsigned int wprotect; + unsigned int gplldiv; + unsigned int gracr2; /* GRA */ + unsigned int gracr3; /* GRA */ + unsigned int reserved[4]; + unsigned int fcntcr1; + unsigned int fcntcr2; + unsigned int reserved2[2]; + unsigned int gpll1div; + unsigned int vcompsel; + unsigned int reserved3[62]; + unsigned int fdlmon; + unsigned int reserved4[2]; + unsigned int flcrmon; + unsigned int reserved5[944]; + unsigned int spibootcan; +}; +#define GCTRL_BASE ((struct gctrl_regs *)0xffc10000) + +/* PCIe setup */ +struct pcie_setup_regs { + unsigned int pbictl0; + unsigned int gradevctl; + unsigned int reserved[2]; + unsigned int bmcinf[6]; + unsigned int reserved2[118]; + unsigned int idset[2]; + unsigned int subidset; + unsigned int reserved3[2]; + unsigned int linkconfset[4]; + unsigned int trsid; + unsigned int reserved4[6]; + unsigned int toutset; + unsigned int reserved5[7]; + unsigned int lad0; + unsigned int ladmsk0; + unsigned int lad1; + unsigned int ladmsk1; + unsigned int lad2; + unsigned int ladmsk2; + unsigned int lad3; + unsigned int ladmsk3; + unsigned int lad4; + unsigned int ladmsk4; + unsigned int lad5; + unsigned int ladmsk5; + unsigned int reserved6[94]; + unsigned int vdmrxvid[2]; + unsigned int reserved7; + unsigned int pbiintfr; + unsigned int pbiinten; + unsigned int msimap; + unsigned int barmap; + unsigned int baracsize; + unsigned int advserest; + unsigned int pbictl3; + unsigned int reserved8[8]; + unsigned int pbictl1; + unsigned int scratch0; + unsigned int reserved9[6]; + unsigned int pbictl2; + unsigned int reserved10; + unsigned int pbirev; +}; +#define PCIE_SETUP_BASE ((struct pcie_setup_regs *)0xffca1000) + +struct pcie_system_bus_regs { + unsigned int reserved[3]; + unsigned int endictl0; + unsigned int endictl1; +}; +#define PCIE_SYSTEM_BUS_BASE ((struct pcie_system_bus_regs *)0xffca1600) + + +/* PCIe-Bridge */ +struct pciebrg_regs { + unsigned short ctrl_h8s; + unsigned short reserved[7]; + unsigned short cp_addr; + unsigned short reserved2; + unsigned short cp_data; + unsigned short reserved3; + unsigned short cp_ctrl; +}; +#define PCIEBRG_BASE ((struct pciebrg_regs *)0xffd60000) + +/* CPU version */ +#define CCN_PRR 0xff000044 +#define prr_mask(_val) ((_val >> 4) & 0xff) +#define PRR_SH7757_B0 0x10 +#define PRR_SH7757_C0 0x11 + +#define is_sh7757_b0(_val) \ +({ \ + int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; \ + __ret; \ +}) +#endif /* ifndef __ASSEMBLY__ */ + +#endif /* _ASM_CPU_SH7757_H_ */ diff --git a/arch/sh/include/asm/cpu_sh7780.h b/arch/sh/include/asm/cpu_sh7780.h index d4f824e..e9c59fe 100644 --- a/arch/sh/include/asm/cpu_sh7780.h +++ b/arch/sh/include/asm/cpu_sh7780.h @@ -333,27 +333,8 @@ #define RYRAR 0xFFE80054 /* Serial Communication Interface with FIFO */ -#define SCIF0_BASE SCSMR0 #define SCSMR0 0xFFE00000 -#define SCBRR0 0xFFE00004 -#define SCSCR0 0xFFE00008 -#define SCFSR0 0xFFE00010 -#define SCFCR0 0xFFE00018 -#define SCTFDR0 0xFFE0001C -#define SCRFDR0 0xFFE00020 -#define SCSPTR0 0xFFE00024 -#define SCLSR0 0xFFE00028 -#define SCRER0 0xFFE0002C -#define SCSMR1 0xFFE10000 -#define SCBRR1 0xFFE10004 -#define SCSCR1 0xFFE10008 -#define SCFSR1 0xFFE10010 -#define SCFCR1 0xFFE10018 -#define SCTFDR1 0xFFE1001C -#define SCRFDR1 0xFFE10020 -#define SCSPTR1 0xFFE10024 -#define SCLSR1 0xFFE10028 -#define SCRER1 0xFFE1002C +#define SCIF0_BASE SCSMR0 /* Serial I/O with FIFO */ #define SIMDR 0xFFE20000 diff --git a/arch/sh/include/asm/zimage.h b/arch/sh/include/asm/zimage.h new file mode 100644 index 0000000..33a680b --- /dev/null +++ b/arch/sh/include/asm/zimage.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2010 + * Renesas Solutions Corp. + * Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ZIMAGE_H_ +#define _ASM_ZIMAGE_H_ + +#define MOUNT_ROOT_RDONLY 0x000 +#define RAMDISK_FLAGS 0x004 +#define ORIG_ROOT_DEV 0x008 +#define LOADER_TYPE 0x00c +#define INITRD_START 0x010 +#define INITRD_SIZE 0x014 +#define COMMAND_LINE 0x100 + +#define RD_PROMPT (1<<15) +#define RD_DOLOAD (1<<14) +#define CMD_ARG_RD_PROMPT "prompt_ramdisk=" +#define CMD_ARG_RD_DOLOAD "load_ramdisk=" + +#endif |