diff options
Diffstat (limited to 'board')
29 files changed, 2862 insertions, 500 deletions
diff --git a/board/goldelico/beagle-hybrid/Makefile b/board/goldelico/beagle-hybrid/Makefile new file mode 100644 index 0000000..d5e90c6 --- /dev/null +++ b/board/goldelico/beagle-hybrid/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := beaglehyb.o ../gta04/TD028TTEC1.o ../gta04/jbt6k74.o ../gta04/backlight.o ../gta04/status.o ../gta04/tsc2007.o ../gta04/dssfb.o ../gta04/gps.o ../gta04/shutdown.o ../gta04/commands.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +#########################################################################
\ No newline at end of file diff --git a/board/goldelico/beagle-hybrid/beaglehyb.c b/board/goldelico/beagle-hybrid/beaglehyb.c new file mode 100644 index 0000000..7fbe8d2 --- /dev/null +++ b/board/goldelico/beagle-hybrid/beaglehyb.c @@ -0,0 +1,24 @@ +#include <common.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include "../../ti/beagle/beagle.h" +#include "beaglehyb.h" + +// make us initialize using both pinmux sets + +void muxinit(void) +{ + MUX_BEAGLE(); + MUX_BEAGLE_HYBRID(); +} + +#undef MUX_BEAGLE +#define MUX_BEAGLE() muxinit() + +// take the original beagle.c code +#include "../../ti/beagle/beagle.c" diff --git a/board/goldelico/beagle-hybrid/beaglehyb.h b/board/goldelico/beagle-hybrid/beaglehyb.h new file mode 100644 index 0000000..71470f8 --- /dev/null +++ b/board/goldelico/beagle-hybrid/beaglehyb.h @@ -0,0 +1,18 @@ +#define MUX_BEAGLE_HYBRID() \ +MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*GPIO_130 -> MMC2_CLK*/\ +MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*GPIO_131 -> MMC2_CMD*/\ +MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*GPIO_132 -> MMC2_DAT0*/\ +MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*GPIO_133 -> MMC2_DAT1*/\ +MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*GPIO_134 -> MMC2_DAT2*/\ +MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*GPIO_135 -> MMC2_DAT3*/\ +MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136 - AUX */\ +MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137 - POWER */\ +MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | DIS | M4)) /*GPIO_138 - EXT-ANT */\ +MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139 - RS232 EXT */\ +MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156 - GPS ON(0)/OFF(1)*/\ +MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157 - PENIRQ */\ +MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | EN | M4)) /*GPIO_158 - DOUT */\ +MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | DIS | M4)) /*GPIO_159 - DIN - pulled up */\ +MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ +MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | EN | M4)) /*GPIO_161 - CS */\ +MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | EN | M4)) /*GPIO_162 - SCL */ diff --git a/board/goldelico/beagle-hybrid/config.mk b/board/goldelico/beagle-hybrid/config.mk new file mode 100644 index 0000000..cf055db --- /dev/null +++ b/board/goldelico/beagle-hybrid/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2006 +# Texas Instruments, <www.ti.com> +# +# Beagle Board uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/goldelico/gta04/COMMANDS b/board/goldelico/gta04/COMMANDS new file mode 100644 index 0000000..01fa68e --- /dev/null +++ b/board/goldelico/gta04/COMMANDS @@ -0,0 +1,22 @@ +new uBoot commands: + +status in[it] setup GPIOs +status ge[t] get button status +status se[t] hh set LEDs to lower 4 bit +status se[t] increment last state, i.e. make LEDs count +status mi[rror] read button status and mirror to LEDs until a key is pressed +status bl[ink] blink LEDs + +lcm in[it] initialize subsystem (DSS, GPIOs etc.) +lcm ba[cklight] dd set backlight level (0..255) +lcm po[wer] dd set power level (0..2) +lcm on set lcm on +lcm of[f] set lcm off + +gps on | of[f] control GPS receiver (and initialize UART) +gps re[ad] read GPS NMEA from UART until a key is pressed + +tsc init initialize/enable TSC2007 through I2C2 +tsc get read current ADC values (incl. internal temp and AUX/photosensor) +tsc lo[op] read x/y coordinates +tsc ch[oose] somehow allow to define receptive fields and use the result to select different boot options diff --git a/board/goldelico/gta04/Makefile b/board/goldelico/gta04/Makefile new file mode 100644 index 0000000..9fd3d3d --- /dev/null +++ b/board/goldelico/gta04/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := gta04.o ../gta04/TD028TTEC1.o ../gta04/jbt6k74.o ../gta04/backlight.o ../gta04/status.o ../gta04/tsc2007.o ../gta04/dssfb.o ../gta04/gps.o ../gta04/shutdown.o ../gta04/commands.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +#########################################################################
\ No newline at end of file diff --git a/board/goldelico/gta04/TD028TTEC1.c b/board/goldelico/gta04/TD028TTEC1.c new file mode 100644 index 0000000..217e088 --- /dev/null +++ b/board/goldelico/gta04/TD028TTEC1.c @@ -0,0 +1,236 @@ +/* u-boot driver for the tpo TD028TTEC1 LCM + * + * Copyright (C) 2006-2007 by OpenMoko, Inc. + * Author: Harald Welte <laforge@openmoko.org> + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* modified by hns@goldelico.com + * now is just a SPI/GPIO driver to the serial interface of the TD028TTEC1 + + *** should all this code be moved to drivers/misc or drivers/video ? + + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include "TD028TTEC1.h" + +#if 0 +#define DEBUGP(x, args...) printf("%s: " x, __FUNCTION__, ## args); +#define DEBUGPC(x, args...) printf(x, ## args); +#define VERIFY(VAL) if(SPI_READ() != (VAL)) { printf("expected: %d found: %d\n", VAL, SPI_READ()); return 1; } +#else +#define DEBUGP(x, args...) do { } while (0) +#define DEBUGPC(x, args...) do { } while (0) +#define VERIFY(VAL) if(SPI_READ() != (VAL)) { return 1; } +#endif + +#if defined(_BEAGLE_) + +#define GPIO_CS 161 +#define GPIO_SCL 162 +#define GPIO_DIN 159 +#define GPIO_DOUT 158 + +#define SPI_READ() (omap_get_gpio_datain(GPIO_DIN)) +#define SPI_CS(bit) (omap_set_gpio_dataout(GPIO_CS, bit)) +#define SPI_SDA(bit) (omap_set_gpio_dataout(GPIO_DOUT, bit)) +#define SPI_SCL(bit) (omap_set_gpio_dataout(GPIO_SCL, bit)) + +#elif !defined(CONFIG_GTA02_REVISION) /* GTA01 */ + +#define GTA01_SCLK (1 << 7) /* GPG7 */ +#define GTA01_MOSI (1 << 6) /* GPG6 */ +#define GTA01_MISO (1 << 5) /* GPG5 */ +#define GTA01_CS (1 << 3) /* GPG3 */ + +#define SPI_READ ((immr->GPGDAT & GTA01_MISO) != 0) + +#define SPI_CS(bit) if (bit) gpio->GPGDAT |= GTA01_CS; \ + else gpio->GPGDAT &= ~GTA01_CS + +#define SPI_SDA(bit) if (bit) gpio->GPGDAT |= GTA01_MOSI; \ + else gpio->GPGDAT &= ~GTA01_MOSI + +#define SPI_SCL(bit) if (bit) gpio->GPGDAT |= GTA01_SCLK; \ + else gpio->GPGDAT &= ~GTA01_SCLK + +#else /* GTA02 */ + +extern void smedia3362_spi_cs(int); +extern void smedia3362_spi_sda(int); +extern void smedia3362_spi_scl(int); +extern void smedia3362_lcm_reset(int); + +#define SPI_READ $not$implemented$ +#define SPI_CS(b) smedia3362_spi_cs(b) +#define SPI_SDA(b) smedia3362_spi_sda(b) +#define SPI_SCL(b) smedia3362_spi_scl(b) + +#endif + + +/* 150uS minimum clock cycle, we have two of this plus our other + * instructions */ + +#define SPI_DELAY() udelay(150) + +static int jbt_spi_xfer(int wordnum, int bitlen, u_int16_t *dout) +{ +#if !defined(_BEAGLE_) + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); +#endif + u_int16_t tmpdout = 0; + int i, j; + + DEBUGP("spi_xfer: dout %08X wordnum %u bitlen %d\n", + *(uint *)dout, wordnum, bitlen); + + SPI_CS(0); + + for (i = 0; i < wordnum; i ++) { + tmpdout = dout[i]; + + for (j = 0; j < bitlen; j++) { + SPI_SCL(0); + if (tmpdout & (1 << (bitlen-1))) { + SPI_SDA(1); + DEBUGPC("1"); + VERIFY(1); + } else { + SPI_SDA(0); + DEBUGPC("0"); + VERIFY(0); + } + SPI_DELAY(); + SPI_SCL(1); + SPI_DELAY(); + tmpdout <<= 1; + } + DEBUGPC(" "); + } + DEBUGPC("\n"); + + SPI_CS(1); + + return 0; +} + +#define JBT_COMMAND 0x000 +#define JBT_DATA 0x100 + +int jbt_reg_write_nodata(struct jbt_info *jbt, u_int8_t reg) +{ + int rc; + + jbt->tx_buf[0] = JBT_COMMAND | reg; + + rc = jbt_spi_xfer(1, 9, jbt->tx_buf); + + return rc; +} + + +int jbt_reg_write(struct jbt_info *jbt, u_int8_t reg, u_int8_t data) +{ + int rc; + + jbt->tx_buf[0] = JBT_COMMAND | reg; + jbt->tx_buf[1] = JBT_DATA | data; + + rc = jbt_spi_xfer(2, 9, jbt->tx_buf); + + return rc; +} + +int jbt_reg_write16(struct jbt_info *jbt, u_int8_t reg, u_int16_t data) +{ + int rc; + + jbt->tx_buf[0] = JBT_COMMAND | reg; + jbt->tx_buf[1] = JBT_DATA | (data >> 8); + jbt->tx_buf[2] = JBT_DATA | (data & 0xff); + + rc = jbt_spi_xfer(3, 9, jbt->tx_buf); + + return rc; +} + +int jbt_reg_init(void) +{ +#if defined(_BEAGLE_) + int i; + int failed=0; + + printf("jbt_reg_init()\n"); + omap_request_gpio(GPIO_CS); + SPI_CS(1); // unselect + omap_request_gpio(GPIO_SCL); + SPI_SCL(1); // default + omap_request_gpio(GPIO_DOUT); + SPI_SDA(0); + omap_request_gpio(GPIO_DIN); +#if 1 // should have been done by MUX settings! + omap_set_gpio_direction(GPIO_CS, 0); // output + omap_set_gpio_direction(GPIO_SCL, 0); // output + omap_set_gpio_direction(GPIO_DOUT, 0); // output + omap_set_gpio_direction(GPIO_DIN, 1); // input (for read back) +#endif + + // omap_free_gpio(GPIO_DIN); + // omap_free_gpio(GPIO_DOUT); + // omap_free_gpio(GPIO_CS); + // omap_free_gpio(GPIO_SCL); + +#endif + + /* according to data sheet: wait 50ms (Tpos of LCM). However, 50ms + * seems unreliable with later LCM batches, increasing to 90ms */ + udelay(90000); + +#if defined(_BEAGLE_) + for(i=0; i<16; i++) + { // check for connection between GPIO158 -> GPIO159; since we have 10 kOhm pse. make sure that the PUP/PDN is disabled in the MUX config! + int bit=i&1; + SPI_SDA(bit); // write bit + SPI_DELAY(); +#if 1 + printf("bit: %d out: %d in: %d (%d)\n", bit, omap_get_gpio_datain(GPIO_DOUT), omap_get_gpio_datain(GPIO_DIN), SPI_READ()); +#endif + if(SPI_READ() != bit) // did not read back + failed++; + } + if(failed > 0) + { + printf("jbt_reg_init() - no correct response, assuming no connection between GPIO158 and GPIO159\n"); + return 1; + } +#endif + + printf("did jbt_reg_init()\n"); + return 0; +} + + diff --git a/board/goldelico/gta04/TD028TTEC1.h b/board/goldelico/gta04/TD028TTEC1.h new file mode 100644 index 0000000..be97640 --- /dev/null +++ b/board/goldelico/gta04/TD028TTEC1.h @@ -0,0 +1,21 @@ +#ifndef _TD028TTEC1_H +#define _TD028TTEC1_H + +#define _BEAGLE_ + +#define JBT_TX_BUF_SIZE +struct jbt_info { + u_int16_t tx_buf[4]; + struct spi_device *spi_dev; + int state; +}; + +#define JBT_COMMAND 0x000 +#define JBT_DATA 0x100 + +int jbt_reg_init(void); +int jbt_reg_write_nodata(struct jbt_info *jbt, u_int8_t reg); +int jbt_reg_write(struct jbt_info *jbt, u_int8_t reg, u_int8_t data); +int jbt_reg_write16(struct jbt_info *jbt, u_int8_t reg, u_int16_t data); + +#endif diff --git a/board/goldelico/gta04/backlight.c b/board/goldelico/gta04/backlight.c new file mode 100644 index 0000000..0e9ce24 --- /dev/null +++ b/board/goldelico/gta04/backlight.c @@ -0,0 +1,68 @@ +/* u-boot driver for the GTA04 backlight + * + * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG + * Author: H. Nikolaus Schaller <hns@goldelico.com> + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include "backlight.h" + +#define GPIO_BACKLIGHT 145 +#define USE_PWM 0 + +void backlight_set_level(int level) // 0..255 +{ +#if USE_PWM + struct gptimer *gpt_base = (struct gptimer *)OMAP34XX_GPT10; // use GPT11 for GTA04 + // writel(value, &gpt_base->registername); +#else + omap_set_gpio_dataout(GPIO_BACKLIGHT, level >= 128); // for simplicity we just have on/off + level=(level >= 128)?255:0; +#endif + printf("lcm backlight level set to %d (0..255)\n", level); +} + +int backlight_init(void) +{ +#if USE_PWM + struct gptimer *gpt_base = (struct gptimer *)OMAP34XX_GPT10; // use GPT11 for GTA04 + MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) /* switch to GPT10 */ + // writel(value, &gpt_base->registername); + // program registers +#error todo +#else + MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/ + omap_request_gpio(GPIO_BACKLIGHT); + omap_set_gpio_direction(GPIO_BACKLIGHT, 0); // output + + // omap_free_gpio(GPIO_BACKLIGHT); +#endif + printf("did backlight_init()\n"); + + return 0; +} + + diff --git a/board/goldelico/gta04/backlight.h b/board/goldelico/gta04/backlight.h new file mode 100644 index 0000000..5c299d9 --- /dev/null +++ b/board/goldelico/gta04/backlight.h @@ -0,0 +1,7 @@ +#ifndef _BACKLIGHT_H +#define _BACKLIGHT_H + +void backlight_set_level(int level); // 0..255 +int backlight_init(void); + +#endif diff --git a/board/goldelico/gta04/commands.c b/board/goldelico/gta04/commands.c new file mode 100644 index 0000000..6f2c9e3 --- /dev/null +++ b/board/goldelico/gta04/commands.c @@ -0,0 +1,607 @@ +/* u-boot extended commands for GTA04 + * + * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG + * Author: H. Nikolaus Schaller <hns@goldelico.com> + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <command.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include "backlight.h" +#include "dssfb.h" +#include "jbt6k74.h" +#include "status.h" +#include "gps.h" +#include "tsc2007.h" +#include "shutdown.h" + +/* LCM commands */ + +static int do_lcd_color(int argc, char *const argv[]) +{ + unsigned int color; + if (argc < 3) { + printf ("lcm color: missing color (0..ffffff).\n"); + return (-1); + } + color=simple_strtoul(argv[2], NULL, 16); + omap3_set_color(color); + return 0; +} + +static int do_lcd_framebuffer(int argc, char *const argv[]) +{ + void *addr; + if (argc < 3) { + printf ("lcm fb: missing address.\n"); + return (-1); + } + addr=(void *) simple_strtoul(argv[2], NULL, 16); + omap3_dss_set_fb(addr); + return 0; +} + +static int do_lcd_backlight(int argc, char *const argv[]) +{ + unsigned char level; + if (argc < 3) { + printf ("lcm backlight: missing level (0..255).\n"); + return (-1); + } + level=simple_strtoul(argv[2], NULL, 10); + backlight_set_level(level); + return 0; +} + +static int do_lcd_power(int argc, char *const argv[]) +{ + int state=JBT_STATE_NORMAL; + if (argc < 3) + { + printf ("lcm power: missing state (0..2).\n"); + return (-1); + } + state=simple_strtoul(argv[2], NULL, 10); + if(state > 2) + { + printf ("lcm power: invalid state (0..2).\n"); + return (-1); + } + jbt6k74_enter_state(state); + printf("lcm state set to %s\n", jbt_state()); + return 0; +} + +static int do_lcd_onoff(int argc, char *const argv[], int flag) +{ + jbt6k74_display_onoff(flag); + printf("display power %s\n", flag?"on":"off"); + return 0; +} + +static int do_lcd_init(int argc, char *const argv[]) +{ + return board_video_init(NULL); +} + +static int do_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int len; + + if (argc < 2) { + printf ("lcm: missing subcommand.\n"); + return (-1); + } + + len = strlen (argv[1]); + if (strncmp ("ba", argv[1], 2) == 0) { + return do_lcd_backlight (argc, argv); + } else if (strncmp ("po", argv[1], 2) == 0) { + return do_lcd_power (argc, argv); + } else if (strncmp ("of", argv[1], 2) == 0) { + return do_lcd_onoff (argc, argv, 0); + } else if (strncmp ("on", argv[1], 2) == 0) { + return do_lcd_onoff (argc, argv, 1); + } else if (strncmp ("in", argv[1], 2) == 0) { + return do_lcd_init (argc, argv); + } else if (strncmp ("co", argv[1], 2) == 0) { + return do_lcd_color (argc, argv); + } else if (strncmp ("fb", argv[1], 2) == 0) { + return do_lcd_framebuffer (argc, argv); + } else { + printf ("lcm: unknown operation: %s\n", argv[1]); + } + + return (0); +} + +U_BOOT_CMD(lcm, 3, 0, do_lcd, "LCM sub-system", + "init - initialize DSS, GPIOs and LCM controller\n" + "backlight level - set backlight level\n" + "off - switch off\n" + "on - switch on\n" + "power mode - set power mode\n" + "color hhhhhh - switch color (can be used without init)\n" + "fb address - set framebuffer address (can be used without init)\n" + ); + +/* TSC commands */ + +static int do_tsc_init(int argc, char *const argv[]) +{ + tsc2007_init(); + return 0; +} + +static int do_tsc_get(int argc, char *const argv[]) +{ + print_adc(); + printf("\n"); + return 0; +} + +static int do_tsc_loop(int argc, char *const argv[]) +{ + printf("permanently reading ADCs of TSC.\n" + "Press any key to stop\n\n"); + while (!tstc()) + { + print_adc(); + printf("\r"); + } + getc(); + printf("\n"); + return 0; +} + +static int tsc_choice=0; + +static int do_tsc_selection(int argc, char *const argv[]) +{ // tsc selection number + if (argc != 3) + { + printf ("tsc selection: missing number of selection to check for.\n"); + return (-1); + } + return tsc_choice == simple_strtoul(argv[2], NULL, 10)?0:1; +} + +static int pendown(int *x, int *y) +{ +#if 1 + int z; + int xx; + int yy; + xx=read_adc(0); + yy=read_adc(1); + z=read_adc(2); // read Z + if(z < 0) + return 0; // read error +#if 0 + printf("z=%04d x:%04d y:%04d\n", z, xx, yy); +#endif + if(x) *x=xx; + if(y) *y=yy; + udelay(10000); // reduce I2C traffic and debounce... + return z > 200; // was pressed +#else + // must be in PENIRQ mode... + return (led_get_buttons() & 0x08) == 0; +#endif +} + +static int do_tsc_choose(int argc, char *const argv[]) +{ // tsc choose cols rows + int cols; + int rows; + int x; + int y; + tsc_choice=0; // reset choice + if (argc != 4) + { + printf ("tsc choose: missing number of cols and rows.\n"); + return (-1); + } + cols=simple_strtoul(argv[2], NULL, 10); + rows=simple_strtoul(argv[3], NULL, 10); + printf("Choosing by waiting for touch.\n"); + for(y=0; y<rows; y++) + for(x=0; x<cols; x++) + printf("%d%s", 1+x+y*cols, (x+1==cols)?"\n":" "); + printf("Press touch or any key to stop\n\n"); + while (!tstc()) + { + if(pendown(NULL, NULL) && pendown(&x, &y)) + { // still pressed - should now be stable +#if 0 + printf("xy: %d/%d\n", x, y); + printf("xy: %d/%d\n", x*cols, y*rows); +#endif + x=(x*cols)/4096; + y=((4095-y)*rows)/4096; // (0,0) is lower left corner in our hardware + tsc_choice=1+x+y*cols; // return 1..rows*cols +#if 0 + while(pendown(NULL, NULL)) + { // wait for pen-up + if(tstc()) + break; + } +#endif + if(tstc()) + break; +#if 1 + printf("did choose %d/%d -> %d\n", x, y, tsc_choice); +#endif + return 0; + } + } + getc(); + return 0; +} + +static int do_tsc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int len; + + if (argc < 2) { + printf ("led: missing subcommand.\n"); + return (-1); + } + + len = strlen (argv[1]); + if (strncmp ("ge", argv[1], 2) == 0) { + return do_tsc_get (argc, argv); + } else if (strncmp ("lo", argv[1], 2) == 0) { + return do_tsc_loop (argc, argv); + } else if (strncmp ("ch", argv[1], 2) == 0) { + return do_tsc_choose (argc, argv); + } else if (strncmp ("se", argv[1], 2) == 0) { + return do_tsc_selection (argc, argv); + } else if (strncmp ("in", argv[1], 2) == 0) { + return do_tsc_init (argc, argv); + } else { + printf ("tsc: unknown operation: %s\n", argv[1]); + } + + return (0); +} + + +U_BOOT_CMD(tsc, 4, 0, do_tsc, "TSC2007 sub-system", + "in[it] - initialize TSC2007\n" + "ge[t] - read ADCs\n" + "lo[op] - loop and display x/y coordinates\n" + "ch[oose] cols rows - choose item\n" + "se[lection] p - check if item p (1 .. cols*rows) was selected\n" + ); + +/** LED commands */ + +static int do_led_init(int argc, char *const argv[]) +{ + led_init(); + return 0; +} + +static void print_buttons(int status) +{ + printf("AUX: %s Power: %s Antenna: %s Pen: %s", (status&0x01)?"on":"off", (status&0x04)?"on":"off", (status&0x02)?"EXT":"INT", (status&0x08)?"1":"0"); +} + +static int do_led_check(int argc, char *const argv[]) +{ // can be used in if construct + int state=led_get_buttons(); + if (argc < 3) + { + printf ("led check: missing mask.\n"); + return (-1); + } + state &= simple_strtoul(argv[2], NULL, 16); + return (state != 0)?0:1; +} + +static int do_led_get(int argc, char *const argv[]) +{ + int status=led_get_buttons(); + printf("button status: %01x\n", status); + print_buttons(status); + printf("\n"); + return 0; +} + +static int do_led_set(int argc, char *const argv[]) +{ // led set hh + static int state; + if(argc == 2) + state++; + else + state=simple_strtoul(argv[2], NULL, 16); + led_set_led(state); + return 0; +} + +static int do_led_loop(int argc, char *const argv[]) +{ + printf("mirroring buttons to LEDs.\n" + "Press any key to stop\n\n"); + while (!tstc() && !pendown(NULL, NULL)) + { + int state=led_get_buttons(); + print_buttons(state); + printf("\r"); + led_set_led(state); // mirror to LEDs + udelay(100000); // 0.1 seconds + } + if(tstc()) + getc(); + printf("\n"); + return 0; +} + +static int do_led_blink(int argc, char *const argv[]) +{ + int value=0; + printf("blinking LEDs.\n" + "Press any key to stop\n\n"); + while (!tstc() && !pendown(NULL, NULL)) + { + led_set_led(value++); // mirror to LEDs + udelay(100000); // 0.1 seconds + } + if(tstc()) + getc(); + return 0; +} + +static int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int len; + + if (argc < 2) { + printf ("led: missing subcommand.\n"); + return (-1); + } + + len = strlen (argv[1]); + if (strncmp ("ge", argv[1], 2) == 0) { + return do_led_get (argc, argv); + } else if (strncmp ("se", argv[1], 2) == 0) { + return do_led_set (argc, argv); + } else if (strncmp ("mi", argv[1], 2) == 0) { + return do_led_loop (argc, argv); + } else if (strncmp ("bl", argv[1], 2) == 0) { + return do_led_blink (argc, argv); + } else if (strncmp ("in", argv[1], 2) == 0) { + return do_led_init (argc, argv); + } else if (strncmp ("ch", argv[1], 2) == 0) { + return do_led_check (argc, argv); + } else { + printf ("led: unknown operation: %s\n", argv[1]); + } + + return (0); +} + + +U_BOOT_CMD(status, 3, 0, do_led, "LED and Buttons sub-system", + "init - initialize GPIOs\n" + "get - print button status\n" + "check - check button status\n" + "set value - set LEDs state\n" + "mirror - read buttons and mirror to LEDs\n" + "blink - blink LEDs\n" + ); + +/** GPS commands */ + +static int do_gps_init(int argc, char *const argv[]) +{ + return gps_init(); +} + +static int do_gps_on(int argc, char *const argv[]) +{ + // should we better send a single ongoing pulse of at least 2 32 kHz cycles? + gps_on(); + printf("GPS on\n"); + return 0; +} + +static int do_gps_off(int argc, char *const argv[]) +{ + gps_off(); + printf("GPS off\n"); + return 0; +} + +static int do_gps_echo(int argc, char *const argv[]) +{ + gps_echo(); + return 0; +} + +// FIXME: "gps cmd" to send a string + +static int do_gps(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int len; + + if (argc < 2) { + printf ("gps: missing subcommand.\n"); + return (-1); + } + + len = strlen (argv[1]); + if (strncmp ("on", argv[1], 2) == 0) { + return do_gps_on (argc, argv); + } else if (strncmp ("of", argv[1], 2) == 0) { + return do_gps_off (argc, argv); + } else if (strncmp ("in", argv[1], 2) == 0) { + return do_gps_init (argc, argv); + } else if (strncmp ("ec", argv[1], 2) == 0) { + return do_gps_echo (argc, argv); + } else { + printf ("gps: unknown operation: %s\n", argv[1]); + } + + return (0); +} + + +U_BOOT_CMD(gps, 3, 0, do_gps, "GPS sub-system", + "init - initialize GPIOs\n" + "on - enable GPS\n" + "off - disable GPS\n" + "cmd string - send string\n" + "echo - echo GPS out to console\n" + ); + +static int do_systest(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + // do mixture of gps_echo, tsc_loop, status mirror status blink + return (0); +} + +U_BOOT_CMD(systest, 2, 0, do_systest, "System Test", ""); + + +static int do_halt(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + backlight_set_level(0); + jbt6k74_enter_state(0); + jbt6k74_display_onoff(0); + shutdown(); // finally shut down power + printf ("failed to power off\n"); + return (0); +} + +U_BOOT_CMD(halt, 2, 0, do_halt, "Powerdown", ""); + + +static int do_mux(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int cols=0; + char *addr=(char *) 0x48002030; + while(addr <= (char *) 0x480025F8) { + unsigned mux=*(unsigned *) addr; + int i; + if(cols == 0) + printf("%08x", (unsigned int) addr); + for(i=1; i <= 2; i++) { + printf(" %c%d%c", (mux&8)?((mux&0x10?'U':'D')):' ', (mux&7), (mux&0x100)?'I':'O'); + mux >>= 16; + } + if(addr == (char *) 0x48002264) { + if(cols != 0) + printf("\n"); + cols=0; + addr= (char *) 0x480025DC; + } + else { + addr+=4; + if(++cols == 8) { + printf("\n"); + cols=0; + } + } + } + if(cols != 0) + printf("\n"); + return (0); +} + +U_BOOT_CMD(mux, 2, 0, do_mux, "Pinmux", ""); + + +static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + if(argc == 3) { + if (strncmp ("on", argv[1], 2) == 0) { + omap_set_gpio_dataout(simple_strtoul(argv[2], NULL, 10), 1); + return 0; + } + else if (strncmp ("of", argv[1], 2) == 0) { + omap_set_gpio_dataout(simple_strtoul(argv[2], NULL, 10), 0); + return 0; + } + else if (strncmp ("in", argv[1], 2) == 0) { + omap_set_gpio_direction(simple_strtoul(argv[2], NULL, 10), 1); + return 0; + } + else if (strncmp ("ou", argv[1], 2) == 0) { + omap_set_gpio_direction(simple_strtoul(argv[2], NULL, 10), 0); + return 0; + } + } + if(argc == 1 || argc == 3) + { // no arguments or from..to + int i=0; + int end=6*32; + int n=10; // number of columns + int col=0; + if(argc == 3) { + i=simple_strtoul(argv[1], NULL, 10); + end=simple_strtoul(argv[2], NULL, 10)+1; // include + } + for(; i<end; i++) + { + if(col == 0) + printf("%03d", i); + printf(" %d", omap_get_gpio_datain(i)); + if(++col == n) + printf("\n"), col=0; + } + if(col != 0) + printf("\n"); // last line + } + else if(argc == 2) { // n only + if(omap_get_gpio_datain(simple_strtoul(argv[1], NULL, 10))) + { + printf("1\n"); + return 1; + } + else + { + printf("0\n"); + return 0; + } + } + else { + printf ("gpio: unknown subcommand.\n"); + return (-1); + } + + return (0); +} + +U_BOOT_CMD(gpio, 3, 0, do_gpio, "GPIO sub-system", + " - print all\n" + "n - print and return state\n" + "m n - print state in given range\n" + "on n - set to 1\n" + "of[f] n - set to 0\n" + "in n - switch to input\n" + "ou[t] n - switch to out (dangerous!)\n" + ); diff --git a/board/goldelico/gta04/config.mk b/board/goldelico/gta04/config.mk new file mode 100644 index 0000000..cf055db --- /dev/null +++ b/board/goldelico/gta04/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2006 +# Texas Instruments, <www.ti.com> +# +# Beagle Board uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/goldelico/gta04/dssfb.c b/board/goldelico/gta04/dssfb.c new file mode 100644 index 0000000..582afc7 --- /dev/null +++ b/board/goldelico/gta04/dssfb.c @@ -0,0 +1,271 @@ +/* u-boot driver for the DSS and framebuffer + * + * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG + * Author: H. Nikolaus Schaller <hns@goldelico.com> + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include <asm/arch/dss.h> + +#define DVI_BACKGROUND_COLOR 0x00fadc29 // rgb(250, 220, 41) + +// configure beagle board DSS for the TD28TTEC1 + +#define DSS1_FCLK 432000000 // see figure 15-65 +#define PIXEL_CLOCK 22000000 // approx. 22 MHz (will be divided from 432 MHz) + +// all values are min ratings + +#define VDISP 640 // vertical active area +#define VFP 4 // vertical front porch +#define VS 2 // VSYNC pulse width (negative going) +#define VBP 2 // vertical back porch +#define VDS (VS+VBP) // vertical data start +#define VBL (VS+VBP+VFP) // vertical blanking period +#define VP (VDISP+VBL) // vertical cycle + +#define HDISP 480 // horizontal active area +#define HFP 24 // horizontal front porch +#define HS 8 // HSYNC pulse width (negative going) +#define HBP 8 // horizontal back porch +#define HDS (HS+HBP) // horizontal data start +#define HBL (HS+HBP+HFP) // horizontal blanking period +#define HP (HDISP+HBL) // horizontal cycle + +#if 0 +#define DEBUGP(x, args...) printf("%s: " x, __FUNCTION__, ## args); +#define DEBUGPC(x, args...) printf(x, ## args); +#else +#define DEBUGP(x, args...) do { } while (0) +#define DEBUGPC(x, args...) do { } while (0) +#endif + +static const struct panel_config lcm_cfg = +{ +.timing_h = ((HBP-1)<<20) | ((HFP-1)<<8) | ((HS-1)<<0), /* Horizantal timing */ +.timing_v = ((VBP+0)<<20) | ((VFP+0)<<8) | ((VS-1)<<0), /* Vertical timing */ +.pol_freq = (1<<17)|(0<<16)|(0<<15)|(1<<14)|(1<<13)|(1<<12)|0x28, /* Pol Freq */ +.divisor = (0x0001<<16)|(DSS1_FCLK/PIXEL_CLOCK), /* Pixel Clock divisor from dss1_fclk */ +.lcd_size = ((HDISP-1)<<0) | ((VDISP-1)<<16), /* as defined by LCM */ +.panel_type = 0x01, /* TFT */ +.data_lines = 0x03, /* 24 Bit RGB */ +.load_mode = 0x02, /* Frame Mode */ +.panel_color = DVI_BACKGROUND_COLOR +}; + +void omap3_dss_go(void) +{ // push changes from shadow register to display controller + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + u32 l = 0; + l = readl(&dispc->control); + l |= GO_LCD | GO_DIG; + writel(l, &dispc->control); + while((readl(&dispc->control) & (GO_LCD | GO_DIG)) != 0) + udelay(1000); // udelay(1000) until the bit(s) are reset by Hardware! + DEBUGP("omap3_dss_go() dispc_control: %08x\n", readl(&dispc->control)); +} + +struct gfx_regs +{ + u32 gfx_ba[2]; /* 80 */ + u32 gfx_position; /* 88 */ + u32 gfx_size; /* 8c */ + u32 reserved1[4]; + u32 gfx_attributes; /* a0 */ +#define GFX_ENABLE 0x0001 + u32 gfx_fifo_threshold; /* a4 */ + u32 gfx_fifo_size_status; /* a8 */ + u32 gfx_row_inc; /* ac */ + u32 gfx_pixel_inc; /* b0 */ + u32 gfx_window_skip; /* b4 */ + u32 gfx_table_ba; /* b8 */ +}; + +#define OMAP3_GFX_BASE (0x48050480) + +int omap3_dss_enable_fb(int flag) +{ + struct gfx_regs *gfx = (struct gfx_regs *) OMAP3_GFX_BASE; + u32 l = readl(&gfx->gfx_attributes); + if(flag) + l |= GFX_ENABLE; + else + l &= ~GFX_ENABLE; + DEBUGP("write %x to gfx_attibutes: %08x\n", l, &gfx->gfx_attributes); + writel(l, &gfx->gfx_attributes); + omap3_dss_go(); + DEBUGP("framebuffer enabled: %d\n", flag); + DEBUGP("gfx_attibutes: %08x\n", readl(&gfx->gfx_attributes)); + return 0; +} + +int omap3_dss_set_fb(void *addr) +{ // set framebuffer address + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + struct gfx_regs *gfx = (struct gfx_regs *) OMAP3_GFX_BASE; + if(addr != NULL) + { + // u32 l = readl(&dispc->control); + // l |= GO_LCD | GO_DIG; + // writel(l, &dispc->control); + // printf("write %x to gfx_attibutes: %08x\n", l, &gfx->gfx_attributes); + // writel(l, &gfx->gfx_attributes); + // printf("gfx_ba[0]: %08x\n", &gfx->gfx_ba[0]); + writel((u32) addr, &gfx->gfx_ba[0]); + writel((u32) addr, &gfx->gfx_ba[1]); + // printf("framebuffer address: %08x\n", addr); + writel(0, &gfx->gfx_position); + // printf("size_lcd: %08x\n", readl(&dispc->size_lcd)); + writel(readl(&dispc->size_lcd), &gfx->gfx_size); + writel(0x008c, &gfx->gfx_attributes); // 16x32 bit bursts + RGB16? + writel(((0x3fc << 16) + (0x3bc)), &gfx->gfx_fifo_threshold); // high & low + writel(1024, &gfx->gfx_fifo_size_status); // FIFO size in bytes + writel(1, &gfx->gfx_row_inc); + writel(1, &gfx->gfx_pixel_inc); + writel(0, &gfx->gfx_window_skip); + writel(0x807ff000, &gfx->gfx_table_ba); + omap3_dss_enable_fb(1); +#if DEBUG + { + u32 addr; + for(addr=0x48050010; addr <= 0x48050010; addr+=4) + printf("%08x: %08x\n", addr, readl(addr)); + for(addr=0x48050040; addr <= 0x48050058; addr+=4) + printf("%08x: %08x\n", addr, readl(addr)); + for(addr=0x48050410; addr <= 0x48050414; addr+=4) + printf("%08x: %08x\n", addr, readl(addr)); + for(addr=0x48050444; addr <= 0x4805048c; addr+=4) + printf("%08x: %08x\n", addr, readl(addr)); + for(addr=0x480504a0; addr <= 0x480504b8; addr+=4) + printf("%08x: %08x\n", addr, readl(addr)); + } +#endif + } + else + { // disable + omap3_dss_enable_fb(0); + } + return 0; +} + +int omap3_set_color(u32 color) +{ + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + writel(color, &dispc->default_color0); + omap3_dss_go(); + printf("background color: %06x\n", color); + return 0; +} + +/* + * Display Configuration + */ + +#define DVI_BEAGLE_ORANGE_COL 0x00FF8000 +#define VENC_HEIGHT 0x00ef +#define VENC_WIDTH 0x027f + +/* + * Configure VENC in DSS for Beagle to generate Color Bar + * + * Kindly refer to OMAP TRM for definition of these values. + */ +static const struct venc_regs venc_config_std_tv = { + .status = 0x0000001B, + .f_control = 0x00000040, + .vidout_ctrl = 0x00000000, + .sync_ctrl = 0x00008000, + .llen = 0x00008359, + .flens = 0x0000020C, + .hfltr_ctrl = 0x00000000, + .cc_carr_wss_carr = 0x043F2631, + .c_phase = 0x00000024, + .gain_u = 0x00000130, + .gain_v = 0x00000198, + .gain_y = 0x000001C0, + .black_level = 0x0000006A, + .blank_level = 0x0000005C, + .x_color = 0x00000000, + .m_control = 0x00000001, + .bstamp_wss_data = 0x0000003F, + .s_carr = 0x21F07C1F, + .line21 = 0x00000000, + .ln_sel = 0x00000015, + .l21__wc_ctl = 0x00001400, + .htrigger_vtrigger = 0x00000000, + .savid__eavid = 0x069300F4, + .flen__fal = 0x0016020C, + .lal__phase_reset = 0x00060107, + .hs_int_start_stop_x = 0x008D034E, + .hs_ext_start_stop_x = 0x000F0359, + .vs_int_start_x = 0x01A00000, + .vs_int_stop_x__vs_int_start_y = 0x020501A0, + .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, + .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, + .vs_ext_stop_y = 0x00000006, + .avid_start_stop_x = 0x03480079, + .avid_start_stop_y = 0x02040024, + .fid_int_start_x__fid_int_start_y = 0x0001008A, + .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, + .fid_ext_start_y__fid_ext_offset_y = 0x01060006, + .tvdetgp_int_start_stop_x = 0x00140001, + .tvdetgp_int_start_stop_y = 0x00010001, + .gen_ctrl = 0x00FF0000, + .output_control = 0x0000000D, + .dac_b__dac_c = 0x00000000 +}; + +/* + * Configure Timings for DVI D + */ +static const struct panel_config dvid_cfg = { + .timing_h = 0x0ff03f31, /* Horizantal timing */ + .timing_v = 0x01400504, /* Vertical timing */ + .pol_freq = 0x00007028, /* Pol Freq */ + .divisor = 0x00010006, /* 72Mhz Pixel Clock */ + .lcd_size = 0x02ff03ff, /* 1024x768 */ + .panel_type = 0x01, /* TFT */ + .data_lines = 0x03, /* 24 Bit RGB */ + .load_mode = 0x02, /* Frame Mode */ + .panel_color = DVI_BEAGLE_ORANGE_COL /* ORANGE */ +}; + +void dssfb_init(void) +{ + omap3_dss_panel_config(&lcm_cfg); // set new config + omap3_dss_enable(); // and (re)enable +} + +/* + * Configure DSS to display background color on DVID + * Configure VENC to display color bar on S-Video + */ +void display_init(void) +{ + omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH); + omap3_dss_panel_config(&dvid_cfg); +} + diff --git a/board/goldelico/gta04/dssfb.h b/board/goldelico/gta04/dssfb.h new file mode 100644 index 0000000..b4755dd --- /dev/null +++ b/board/goldelico/gta04/dssfb.h @@ -0,0 +1,32 @@ +/* u-boot driver for the DSS and framebuffer + * + * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG + * Author: H. Nikolaus Schaller <hns@goldelico.com> + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +void dssfb_init(void); + +void omap3_dss_go(void); + +int omap3_dss_enable_fb(int flag); + +int omap3_dss_set_fb(void *addr); // set framebuffer address + +int omap3_set_color(u32 color); // set background color diff --git a/board/goldelico/gta04/gps.c b/board/goldelico/gta04/gps.c new file mode 100644 index 0000000..3befeca --- /dev/null +++ b/board/goldelico/gta04/gps.c @@ -0,0 +1,99 @@ +/* u-boot driver for the GTA04 LEDs and Buttons + * + * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG + * Author: H. Nikolaus Schaller <hns@goldelico.com> + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include <ns16550.h> +#include <twl4030.h> +#include "gps.h" + +#define GPIO_GPSEXT 138 // external GPS antenna plugged in +#define GPIO_GPS_ON 156 + +int gps_init(void) +{ + extern int get_board_revision(void); +#define REVISION_XM 0 + if(get_board_revision() == REVISION_XM) { + /* Set VAUX1 to 3.3V for GTA04E display board */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX1_DEDICATED, + /*TWL4030_PM_RECEIVER_VAUX1_VSEL_33*/ 0x07, + TWL4030_PM_RECEIVER_VAUX1_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + udelay(5000); + } + omap_request_gpio(GPIO_GPS_ON); + omap_set_gpio_direction(GPIO_GPS_ON, 0); // output + omap_request_gpio(GPIO_GPSEXT); + omap_set_gpio_direction(GPIO_GPSEXT, 1); // input + return 0; +} + +void gps_on(void) +{ + omap_set_gpio_dataout(GPIO_GPS_ON, 1); + if(omap_get_gpio_datain(GPIO_GPSEXT)) + printf("external antenna\n"); + else + printf("internal antenna\n"); +} + +void gps_off(void) +{ + omap_set_gpio_dataout(GPIO_GPS_ON, 0); +} + +static int lastant=-1; + +void gps_echo(void) +{ + #define MODE_X_DIV 16 + int baudrate=9600; + int divisor=(CONFIG_SYS_NS16550_CLK + (baudrate * (MODE_X_DIV / 2))) / (MODE_X_DIV * baudrate); + NS16550_reinit((NS16550_t)CONFIG_SYS_NS16550_COM2, divisor); // initialize UART + while (1) + { // echo in both directions + int ant=omap_get_gpio_datain(GPIO_GPSEXT); + if(ant != lastant) + { // changed + if(ant) + printf("external antenna\n"); + else + printf("internal antenna\n"); + lastant=ant; + } + if(NS16550_tstc((NS16550_t)CONFIG_SYS_NS16550_COM2)) + putc(NS16550_getc((NS16550_t)CONFIG_SYS_NS16550_COM2)); // from GPS to console + // fixme: until we press ctl-C + if(tstc()) + break; // NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, getc()); + } + getc(); + printf("\n"); +} + diff --git a/board/goldelico/gta04/gps.h b/board/goldelico/gta04/gps.h new file mode 100644 index 0000000..937beb0 --- /dev/null +++ b/board/goldelico/gta04/gps.h @@ -0,0 +1,11 @@ +#ifndef _GPS_H +#define _GPS_H + +int gps_init(void); + +void gps_on(void); +void gps_off(void); + +void gps_echo(void); + +#endif diff --git a/board/goldelico/gta04/gta04.c b/board/goldelico/gta04/gta04.c new file mode 100644 index 0000000..0d7fd66 --- /dev/null +++ b/board/goldelico/gta04/gta04.c @@ -0,0 +1,24 @@ +#include <common.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include "../../ti/beagle/beagle.h" +#include "gta04.h" + +// make us initialize using both pinmux sets + +void muxinit(void) +{ + MUX_BEAGLE(); + MUX_BEAGLE_GTA04(); +} + +#undef MUX_BEAGLE +#define MUX_BEAGLE() muxinit() + +// take the original beagle.c code +#include "../../ti/beagle/beagle.c" diff --git a/board/goldelico/gta04/gta04.h b/board/goldelico/gta04/gta04.h new file mode 100644 index 0000000..fc5823b --- /dev/null +++ b/board/goldelico/gta04/gta04.h @@ -0,0 +1,18 @@ +#define MUX_BEAGLE_GTA04() \ +MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*GPIO_130 -> MMC2_CLK*/\ +MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*GPIO_131 -> MMC2_CMD*/\ +MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*GPIO_132 -> MMC2_DAT0*/\ +MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*GPIO_133 -> MMC2_DAT1*/\ +MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*GPIO_134 -> MMC2_DAT2*/\ +MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*GPIO_135 -> MMC2_DAT3*/\ +MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136 - AUX */\ +MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137 - POWER */\ +MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | DIS | M4)) /*GPIO_138 - EXT-ANT */\ +MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139 - RS232 EXT */\ +MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156 - GPS ON(0)/OFF(1)*/\ +MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157 - PENIRQ */\ +MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | EN | M4)) /*GPIO_158 - DOUT */\ +MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | DIS | M4)) /*GPIO_159 - DIN - pulled up */\ +MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ +MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | EN | M4)) /*GPIO_161 - CS */\ +MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | EN | M4)) /*GPIO_162 - SCL */ diff --git a/board/goldelico/gta04/jbt6k74.c b/board/goldelico/gta04/jbt6k74.c new file mode 100644 index 0000000..4e6a2e0 --- /dev/null +++ b/board/goldelico/gta04/jbt6k74.c @@ -0,0 +1,337 @@ +/* u-boot driver for the tpo JBT6K74-AS LCM ASIC + * + * Copyright (C) 2006-2007 by OpenMoko, Inc. + * Author: Harald Welte <laforge@openmoko.org> + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* modified by hns@goldelico.com + * to separate jbt commands from communication (throgh SPI or GPIOs) + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include <asm/arch/dss.h> +#include <twl4030.h> +#include "dssfb.h" +#include "jbt6k74.h" + +#if 1 +#define DEBUGP(x, args...) printf("%s: " x, __FUNCTION__, ## args); +#define DEBUGPC(x, args...) printf(x, ## args); +#else +#define DEBUGP(x, args...) do { } while (0) +#define DEBUGPC(x, args...) do { } while (0) +#endif + + +enum jbt_register { + JBT_REG_SLEEP_IN = 0x10, + JBT_REG_SLEEP_OUT = 0x11, + + JBT_REG_DISPLAY_OFF = 0x28, + JBT_REG_DISPLAY_ON = 0x29, + + JBT_REG_RGB_FORMAT = 0x3a, + JBT_REG_QUAD_RATE = 0x3b, + + JBT_REG_POWER_ON_OFF = 0xb0, + JBT_REG_BOOSTER_OP = 0xb1, + JBT_REG_BOOSTER_MODE = 0xb2, + JBT_REG_BOOSTER_FREQ = 0xb3, + JBT_REG_OPAMP_SYSCLK = 0xb4, + JBT_REG_VSC_VOLTAGE = 0xb5, + JBT_REG_VCOM_VOLTAGE = 0xb6, + JBT_REG_EXT_DISPL = 0xb7, + JBT_REG_OUTPUT_CONTROL = 0xb8, + JBT_REG_DCCLK_DCEV = 0xb9, + JBT_REG_DISPLAY_MODE1 = 0xba, + JBT_REG_DISPLAY_MODE2 = 0xbb, + JBT_REG_DISPLAY_MODE = 0xbc, + JBT_REG_ASW_SLEW = 0xbd, + JBT_REG_DUMMY_DISPLAY = 0xbe, + JBT_REG_DRIVE_SYSTEM = 0xbf, + + JBT_REG_SLEEP_OUT_FR_A = 0xc0, + JBT_REG_SLEEP_OUT_FR_B = 0xc1, + JBT_REG_SLEEP_OUT_FR_C = 0xc2, + JBT_REG_SLEEP_IN_LCCNT_D = 0xc3, + JBT_REG_SLEEP_IN_LCCNT_E = 0xc4, + JBT_REG_SLEEP_IN_LCCNT_F = 0xc5, + JBT_REG_SLEEP_IN_LCCNT_G = 0xc6, + + JBT_REG_GAMMA1_FINE_1 = 0xc7, + JBT_REG_GAMMA1_FINE_2 = 0xc8, + JBT_REG_GAMMA1_INCLINATION = 0xc9, + JBT_REG_GAMMA1_BLUE_OFFSET = 0xca, + + JBT_REG_BLANK_CONTROL = 0xcf, + JBT_REG_BLANK_TH_TV = 0xd0, + JBT_REG_CKV_ON_OFF = 0xd1, + JBT_REG_CKV_1_2 = 0xd2, + JBT_REG_OEV_TIMING = 0xd3, + JBT_REG_ASW_TIMING_1 = 0xd4, + JBT_REG_ASW_TIMING_2 = 0xd5, + + JBT_REG_HCLOCK_VGA = 0xec, + JBT_REG_HCLOCK_QVGA = 0xed, + +}; + +static const char *jbt_state_names[] = { + [JBT_STATE_DEEP_STANDBY] = "deep-standby", + [JBT_STATE_SLEEP] = "sleep", + [JBT_STATE_NORMAL] = "normal", +}; + +static struct jbt_info _jbt, *jbt = &_jbt; + +const char *jbt_state(void) +{ + return jbt_state_names[jbt->state]; +} + +static int jbt_init_regs(struct jbt_info *jbt) +{ + int rc; + + DEBUGP("entering\n"); + + rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE1, 0x01); + rc |= jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE2, 0x00); + rc |= jbt_reg_write(jbt, JBT_REG_RGB_FORMAT, 0x60); + rc |= jbt_reg_write(jbt, JBT_REG_DRIVE_SYSTEM, 0x10); + rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_OP, 0x56); + rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_MODE, 0x33); + rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11); + rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11); + rc |= jbt_reg_write(jbt, JBT_REG_OPAMP_SYSCLK, 0x02); + rc |= jbt_reg_write(jbt, JBT_REG_VSC_VOLTAGE, 0x2b); + rc |= jbt_reg_write(jbt, JBT_REG_VCOM_VOLTAGE, 0x40); + rc |= jbt_reg_write(jbt, JBT_REG_EXT_DISPL, 0x03); + rc |= jbt_reg_write(jbt, JBT_REG_DCCLK_DCEV, 0x04); + /* + * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement + * to avoid red / blue flicker + */ + rc |= jbt_reg_write(jbt, JBT_REG_ASW_SLEW, 0x04); + rc |= jbt_reg_write(jbt, JBT_REG_DUMMY_DISPLAY, 0x00); + + rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_A, 0x11); + rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_B, 0x11); + rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_C, 0x11); + rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040); + rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0); + rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020); + rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0); + + rc |= jbt_reg_write16(jbt, JBT_REG_GAMMA1_FINE_1, 0x5533); + rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_FINE_2, 0x00); + rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_INCLINATION, 0x00); + rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00); + rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00); + + rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_VGA, 0x1f0); + rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL, 0x02); + rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804); + rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804); + + rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF, 0x01); + rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2, 0x0000); + + rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING, 0x0d0e); + rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1, 0x11a4); + rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2, 0x0e); + +#if 0 + rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff); + rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff); +#endif + + if(rc) + printf("jbt_init_regs() failed\n"); + else + printf("did jbt_init_regs()\n"); + return rc; +} + +static int standby_to_sleep(struct jbt_info *jbt) +{ + int rc; + + DEBUGP("entering\n"); + + /* three times command zero */ + rc = jbt_reg_write_nodata(jbt, 0x00); + udelay(1000); + rc = jbt_reg_write_nodata(jbt, 0x00); + udelay(1000); + rc = jbt_reg_write_nodata(jbt, 0x00); + udelay(1000); + + /* deep standby out */ + rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x17); + + return rc; +} + +static int sleep_to_normal(struct jbt_info *jbt) +{ + int rc; + DEBUGP("entering\n"); + + /* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */ + rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x80); + + /* Quad mode off */ + rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x00); + + /* AVDD on, XVDD on */ + rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x16); + + /* Output control */ + rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0xfff9); + + /* Sleep mode off */ + rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_OUT); + + /* at this point we have like 50% grey */ + + /* initialize register set */ + rc |= jbt_init_regs(jbt); + return rc; +} + +static int normal_to_sleep(struct jbt_info *jbt) +{ + int rc; + DEBUGP("entering\n"); + + rc = jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF); + rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0x8002); + rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_IN); + + return rc; +} + +static int sleep_to_standby(struct jbt_info *jbt) +{ + DEBUGP("entering\n"); + return jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x00); +} + +/* frontend function */ +int jbt6k74_enter_state(enum jbt_state new_state) +{ + int rc = -EINVAL; + + DEBUGP("entering(old_state=%u, new_state=%u)\n", jbt->state, new_state); + + switch (jbt->state) { + case JBT_STATE_DEEP_STANDBY: + switch (new_state) { + case JBT_STATE_DEEP_STANDBY: + rc = 0; + break; + case JBT_STATE_SLEEP: + rc = standby_to_sleep(jbt); + break; + case JBT_STATE_NORMAL: + /* first transition into sleep */ + rc = standby_to_sleep(jbt); + /* then transition into normal */ + rc |= sleep_to_normal(jbt); + break; + } + break; + case JBT_STATE_SLEEP: + switch (new_state) { + case JBT_STATE_SLEEP: + rc = 0; + break; + case JBT_STATE_DEEP_STANDBY: + rc = sleep_to_standby(jbt); + break; + case JBT_STATE_NORMAL: + rc = sleep_to_normal(jbt); + break; + } + break; + case JBT_STATE_NORMAL: + switch (new_state) { + case JBT_STATE_NORMAL: + rc = 0; + break; + case JBT_STATE_DEEP_STANDBY: + /* first transition into sleep */ + rc = normal_to_sleep(jbt); + /* then transition into deep standby */ + rc |= sleep_to_standby(jbt); + break; + case JBT_STATE_SLEEP: + rc = normal_to_sleep(jbt); + break; + } + break; + } + if(rc) + printf("jbt6k74_enter_state() failed.\n"); + else + jbt->state=new_state; + return rc; +} + +int jbt6k74_display_onoff(int on) +{ + DEBUGP("entering\n"); + if (on) + return jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_ON); + else + return jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF); +} + +int board_video_init(GraphicDevice *pGD) +{ + extern int get_board_revision(void); +#define REVISION_XM 0 + if(get_board_revision() == REVISION_XM) { + /* Set VAUX1 to 3.3V for GTA04E display board */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX1_DEDICATED, + /*TWL4030_PM_RECEIVER_VAUX1_VSEL_33*/ 0x07, + TWL4030_PM_RECEIVER_VAUX1_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + udelay(5000); + } + if(jbt_reg_init()) // initialize SPI + { + printf("No LCM connected\n"); + return 1; + } + dssfb_init(); + backlight_init(); // initialize backlight + + printf("did board_video_init()\n"); + return 0; +} + diff --git a/board/goldelico/gta04/jbt6k74.h b/board/goldelico/gta04/jbt6k74.h new file mode 100644 index 0000000..170873f --- /dev/null +++ b/board/goldelico/gta04/jbt6k74.h @@ -0,0 +1,19 @@ +#ifndef _JBT6K74_H +#define _JBT6K74_H + +#include <video_fb.h> +#include "TD028TTEC1.h" +#include "backlight.h" + +enum jbt_state { + JBT_STATE_DEEP_STANDBY, + JBT_STATE_SLEEP, + JBT_STATE_NORMAL, +}; + +int jbt6k74_display_onoff(int on); +int jbt6k74_enter_state(enum jbt_state new_state); +const char *jbt_state(void); +int board_video_init(GraphicDevice *pGD); + +#endif diff --git a/board/goldelico/gta04/shutdown.c b/board/goldelico/gta04/shutdown.c new file mode 100644 index 0000000..4348b60 --- /dev/null +++ b/board/goldelico/gta04/shutdown.c @@ -0,0 +1,52 @@ +/* u-boot driver for the GTA04 shutdown + * + * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG + * Author: H. Nikolaus Schaller <hns@goldelico.com> + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include <twl4030.h> +#include "shutdown.h" + +void shutdown(void) +{ + u8 val = 0; + printf("shutting down by writing DEVOFF register of TPS65950\n"); + if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val, + TWL4030_PM_MASTER_P1_SW_EVENTS)) { + printf("Error:TWL4030: failed to read the power register\n"); + printf("Could not initialize hardware reset\n"); + } else { + val |= TWL4030_PM_MASTER_SW_EVENTS_DEVOFF; + if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, val, + TWL4030_PM_MASTER_P1_SW_EVENTS)) { + printf("Error:TWL4030: failed to write the power register\n"); + printf("Could not initialize hardware reset\n"); + } + } + // CHECKME: do we have to write PM_MASTER_P2 and _P3? +} + diff --git a/board/goldelico/gta04/shutdown.h b/board/goldelico/gta04/shutdown.h new file mode 100644 index 0000000..a14695c --- /dev/null +++ b/board/goldelico/gta04/shutdown.h @@ -0,0 +1,29 @@ +/* u-boot extended commands for GTA04 + * + * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG + * Author: H. Nikolaus Schaller <hns@goldelico.com> + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _SHUTDOWN_H +#define _SHUTDOWN_H + +void shutdown(void); + +#endif diff --git a/board/goldelico/gta04/status.c b/board/goldelico/gta04/status.c new file mode 100644 index 0000000..db2f65e --- /dev/null +++ b/board/goldelico/gta04/status.c @@ -0,0 +1,143 @@ +/* u-boot driver for the GTA04 LEDs and Buttons + * + * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG + * Author: H. Nikolaus Schaller <hns@goldelico.com> + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include "status.h" + +static int isGTA04 = 0; + +// we can't include "beagle.h" +/* BeagleBoard revisions */ +extern int get_board_revision(void); +#define REVISION_AXBX 0x7 +#define REVISION_CX 0x6 +#define REVISION_C4 0x5 +#define REVISION_XM 0x0 + +static int isXM = 0; + +// Note: on GTA04 the LEDs will be connected to TCA8418 and controlled through I2C +// Note: BB-XM has scrambled DSS assignment + +#define GPIO_LED_AUX_RED (isXM?88:70) // AUX +#define GPIO_LED_AUX_GREEN (isXM?89:71) // AUX +#define GPIO_LED_POWER_RED 78 // Power +#define GPIO_LED_POWER_GREEN 79 // Power +#define GPIO_LED_VIBRA (isXM?2:88) // Vibracall motor +#define GPIO_LED_UNUSED (isXM?3:89) // unused + +// Note: on GTA04 the GPIOs will be assigned differently and the state of the POWER button is only available through the TPS65950 + +#define GPIO_AUX (isGTA04?136:136) +#define GPIO_POWER 137 +#define GPIO_GPSEXT (isGTA04?138:138) // external GPS antenna is plugged in +#define GPIO_PENIRQ (isGTA04?157:157) // TSC must be set up to provide PENIRQ + +void led_set_led(int value) +{ + if(!isGTA04) { + omap_set_gpio_dataout(GPIO_LED_AUX_RED, (value&(1 << 0))); + omap_set_gpio_dataout(GPIO_LED_AUX_GREEN, (value&(1 << 1))); + omap_set_gpio_dataout(GPIO_LED_POWER_RED, (value&(1 << 3))); + omap_set_gpio_dataout(GPIO_LED_POWER_GREEN, (value&(1 << 4))); + omap_set_gpio_dataout(GPIO_LED_VIBRA, (value&(1 << 6))); + omap_set_gpio_dataout(GPIO_LED_UNUSED, (value&(1 << 7))); + } + else { + // initialize i2c controller + } +} + +int led_get_buttons(void) +{ // convert button state into led state + if(isGTA04) { + // read GPIOs and TPS65950 + } + return + ((!omap_get_gpio_datain(GPIO_AUX)) << 0) | + ((omap_get_gpio_datain(GPIO_GPSEXT)) << 1) | + ((!omap_get_gpio_datain(GPIO_POWER)) << 3) | + ((omap_get_gpio_datain(GPIO_PENIRQ)) << 4); +} + +int led_init(void) +{ + isXM = (get_board_revision() == REVISION_XM); + + if(!isGTA04) { + if(isXM) { // XM has scrambled dss assignment with respect to default ball name + MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M4)); /*GPIO */ + MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M4)); /*GPIO */ + MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M4)); /*GPIO */ + MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M4)); /*GPIO */ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | EN | M4)); /*GPIO */ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M4)); /*GPIO */ + } + else { + MUX_VAL(CP(DSS_DATA0), (IEN | PTD | EN | M4)); /*GPIO */ + MUX_VAL(CP(DSS_DATA1), (IEN | PTD | EN | M4)); /*GPIO */ + MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M4)); /*GPIO */ + MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M4)); /*GPIO */ + MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M4)); /*GPIO */ + MUX_VAL(CP(DSS_DATA17), (IEN | PTD | EN | M4)); /*GPIO */ + } + + omap_request_gpio(GPIO_LED_AUX_GREEN); + omap_request_gpio(GPIO_LED_AUX_RED); + omap_request_gpio(GPIO_LED_POWER_GREEN); + omap_request_gpio(GPIO_LED_POWER_RED); + omap_request_gpio(GPIO_LED_VIBRA); + omap_request_gpio(GPIO_LED_UNUSED); + } + + omap_request_gpio(GPIO_AUX); + omap_request_gpio(GPIO_POWER); + omap_request_gpio(GPIO_GPSEXT); + omap_request_gpio(GPIO_PENIRQ); + + if(!isGTA04) { + omap_set_gpio_direction(GPIO_LED_AUX_GREEN, 0); // output + omap_set_gpio_direction(GPIO_LED_AUX_RED, 0); // output + omap_set_gpio_direction(GPIO_LED_POWER_GREEN, 0); // output + omap_set_gpio_direction(GPIO_LED_POWER_RED, 0); // output + omap_set_gpio_direction(GPIO_LED_VIBRA, 0); // output + omap_set_gpio_direction(GPIO_LED_UNUSED, 0); // output + } + + omap_set_gpio_direction(GPIO_AUX, 1); // input + omap_set_gpio_direction(GPIO_POWER, 1); // input + omap_set_gpio_direction(GPIO_AUX, 1); // input + omap_set_gpio_direction(GPIO_GPSEXT, 1); // input + + // when sould we do omap_free_gpio(GPIO_LED_AUX_GREEN); + printf("did led_init()\n"); + + return 0; +} + diff --git a/board/goldelico/gta04/status.h b/board/goldelico/gta04/status.h new file mode 100644 index 0000000..4e80753 --- /dev/null +++ b/board/goldelico/gta04/status.h @@ -0,0 +1,9 @@ +#ifndef _LED_H +#define _LED_H + +int led_init(void); + +void led_set_led(int value); +int led_get_buttons(void); + +#endif diff --git a/board/goldelico/gta04/tsc2007.c b/board/goldelico/gta04/tsc2007.c new file mode 100644 index 0000000..72e64bf --- /dev/null +++ b/board/goldelico/gta04/tsc2007.c @@ -0,0 +1,143 @@ +/* u-boot driver for the TSC2007 connected to I2C2 + * + * Copyright (C) 2010 by Golden Delicious Computers GmbH&Co. KG + * Author: H. Nikolaus Schaller <hns@goldelico.com> + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include <i2c.h> +#include "tsc2007.h" + +#define TSC2007_BUS 2 // I2C2 +#define TSC2007_ADDRESS 0x48 + +// command byte definitions: +// channel selection and power down + +#define TSC2007_TEMP0 0x00 +#define TSC2007_AUX 0x20 +#define TSC2007_TEMP1 0x40 +#define TSC2007_ACTX 0x80 +#define TSC2007_ACTY 0x90 +#define TSC2007_ACTXY 0xA0 +#define TSC2007_X 0xc0 +#define TSC2007_Y 0xd0 +#define TSC2007_Z1 0xe0 +#define TSC2007_Z2 0xf0 + +#define TSC2007_POWER_DOWN 0x00 // must be sent once after power up +#define TSC2007_ADC_ON 0x04 +#define TSC2007_ADC_OFF_PENIRQ 0x08 + +#define TSC2007_12Bit2MHz 0x00 +#define TSC2007_8Bit4MHz 0x02 + +// setup command + +#define TSC2007_SETUP 0xb0 + +#define TSC2007_USE_MAV 0x00 +#define TSC2007_BYPASS_MAV 0x02 + +#define TSC2007_50kPUP 0x00 +#define TSC2007_90kPUP 0x01 + +/* + int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) + int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +*/ + +int tsc2007_cmd(int cmd) +{ // send command + unsigned char buf[16]; + buf[0]=cmd; + if (i2c_write(TSC2007_ADDRESS, cmd, 1, buf, 0)) // write 1 byte command + { + printf ("Error writing the TSC.\n"); + return 1; + } + return 0; +} + +int tsc2007_init(void) +{ + int rc=0; + if(i2c_set_bus_num(TSC2007_BUS-1)) + { + printf ("could not select I2C2\n"); + return 1; + } + + rc = tsc2007_cmd(TSC2007_SETUP|TSC2007_USE_MAV|TSC2007_50kPUP); + rc |= tsc2007_cmd(TSC2007_POWER_DOWN); + + if(rc) + printf("did tsc2007_init() failed.\n"); + else + printf("did tsc2007_init()\n"); + + return 0; +} + +int read_adc(int adcnum) +{ // read ADC and return value in range 0..4095 + unsigned char c; + unsigned char buf[16]; + static int cmd[]={ + TSC2007_X, + TSC2007_Y, + TSC2007_Z1, + TSC2007_Z2, + TSC2007_TEMP0, + TSC2007_TEMP1, + TSC2007_AUX, + TSC2007_AUX + }; + c=cmd[adcnum%8] | TSC2007_ADC_ON | TSC2007_12Bit2MHz; +// printf("send %02x\n", c); + if (i2c_read(TSC2007_ADDRESS, c, 1, buf, 1)) + { + printf ("Error reading the TSC.\n"); + return -1; + } + return ((unsigned)buf[0]) << 4; // read 1 byte only + +// return (buf[0]<<4)+(buf[1]>>4); // 12 bit +} + +void print_adc(void) +{ + printf("0:%04u 1:%04u 2:%04u 3:%04u 4:%04u 5:%04u 6:%04u 7:%04u", + read_adc(0), + read_adc(1), + read_adc(2), + read_adc(3), + read_adc(4), + read_adc(5), + read_adc(6), + read_adc(7)); +} + diff --git a/board/goldelico/gta04/tsc2007.h b/board/goldelico/gta04/tsc2007.h new file mode 100644 index 0000000..fc85159 --- /dev/null +++ b/board/goldelico/gta04/tsc2007.h @@ -0,0 +1,8 @@ +#ifndef _TSC2007_H +#define _TSC2007_H + +int tsc2007_init(void); +int read_adc(int adcnum); +void print_adc(void); + +#endif diff --git a/board/ti/beagle/Makefile b/board/ti/beagle/Makefile index 3b4aaac..f5454b1 100644 --- a/board/ti/beagle/Makefile +++ b/board/ti/beagle/Makefile @@ -46,4 +46,4 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend -######################################################################### +#########################################################################
\ No newline at end of file diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index d9b6f01..4eabe27 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -67,13 +67,13 @@ static struct { int board_init(void) { DECLARE_GLOBAL_DATA_PTR; - + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ /* board id for Linux */ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE; /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - + return 0; } @@ -91,19 +91,19 @@ int board_init(void) int get_board_revision(void) { int revision; - + if (!omap_request_gpio(171) && !omap_request_gpio(172) && !omap_request_gpio(173)) { - + omap_set_gpio_direction(171, 1); omap_set_gpio_direction(172, 1); omap_set_gpio_direction(173, 1); - + revision = omap_get_gpio_datain(173) << 2 | - omap_get_gpio_datain(172) << 1 | - omap_get_gpio_datain(171); - + omap_get_gpio_datain(172) << 1 | + omap_get_gpio_datain(171); + omap_free_gpio(171); omap_free_gpio(172); omap_free_gpio(173); @@ -111,7 +111,7 @@ int get_board_revision(void) printf("Error: unable to acquire board revision GPIOs\n"); revision = -1; } - + return revision; } @@ -124,19 +124,19 @@ int get_board_revision(void) unsigned int get_expansion_id(void) { i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS); - + /* return BEAGLE_NO_EEPROM if eeprom doesn't respond */ if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) { i2c_set_bus_num(TWL4030_I2C_BUS); return BEAGLE_NO_EEPROM; } - + /* read configuration data */ i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config, - sizeof(expansion_config)); - + sizeof(expansion_config)); + i2c_set_bus_num(TWL4030_I2C_BUS); - + return expansion_config.device_vendor; } @@ -148,110 +148,110 @@ int misc_init_r(void) { struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; - + switch (get_board_revision()) { - case REVISION_AXBX: - printf("Beagle Rev Ax/Bx\n"); - setenv("beaglerev", "AxBx"); - setenv("mpurate", "600"); - break; - case REVISION_CX: - printf("Beagle Rev C1/C2/C3\n"); - setenv("beaglerev", "Cx"); - setenv("mpurate", "600"); - MUX_BEAGLE_C(); - break; - case REVISION_C4: - printf("Beagle Rev C4\n"); - setenv("beaglerev", "C4"); - setenv("mpurate", "720"); - MUX_BEAGLE_C(); - /* Set VAUX2 to 1.8V for EHCI PHY */ - twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, - TWL4030_PM_RECEIVER_VAUX2_VSEL_18, - TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, - TWL4030_PM_RECEIVER_DEV_GRP_P1); - break; - case REVISION_XM: - printf("Beagle xM Rev A\n"); - setenv("beaglerev", "xMA"); - setenv("mpurate", "1000"); - MUX_BEAGLE_XM(); - /* Set VAUX2 to 1.8V for EHCI PHY */ - twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, - TWL4030_PM_RECEIVER_VAUX2_VSEL_18, - TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, - TWL4030_PM_RECEIVER_DEV_GRP_P1); - break; - default: - printf("Beagle unknown 0x%02x\n", get_board_revision()); + case REVISION_AXBX: + printf("Beagle Rev Ax/Bx\n"); + setenv("beaglerev", "AxBx"); + setenv("mpurate", "600"); + break; + case REVISION_CX: + printf("Beagle Rev C1/C2/C3\n"); + setenv("beaglerev", "Cx"); + setenv("mpurate", "600"); + MUX_BEAGLE_C(); + break; + case REVISION_C4: + printf("Beagle Rev C4\n"); + setenv("beaglerev", "C4"); + setenv("mpurate", "720"); + MUX_BEAGLE_C(); + /* Set VAUX2 to 1.8V for EHCI PHY */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, + TWL4030_PM_RECEIVER_VAUX2_VSEL_18, + TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + break; + case REVISION_XM: + printf("Beagle xM Rev A\n"); + setenv("beaglerev", "xMA"); + setenv("mpurate", "1000"); + MUX_BEAGLE_XM(); + /* Set VAUX2 to 1.8V for EHCI PHY */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, + TWL4030_PM_RECEIVER_VAUX2_VSEL_18, + TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + break; + default: + printf("Beagle unknown 0x%02x\n", get_board_revision()); } - + switch (get_expansion_id()) { - case TINCANTOOLS_ZIPPY: - printf("Recognized Tincantools Zippy board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_TINCANTOOLS_ZIPPY(); - setenv("buddy", "zippy"); - break; - case TINCANTOOLS_ZIPPY2: - printf("Recognized Tincantools Zippy2 board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_TINCANTOOLS_ZIPPY(); - setenv("buddy", "zippy2"); - break; - case TINCANTOOLS_TRAINER: - printf("Recognized Tincantools Trainer board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - MUX_TINCANTOOLS_ZIPPY(); - MUX_TINCANTOOLS_TRAINER(); - setenv("buddy", "trainer"); - break; - case TINCANTOOLS_SHOWDOG: - printf("Recognized Tincantools Showdow board (rev %d %s)\n", - expansion_config.revision, - expansion_config.fab_revision); - /* Place holder for DSS2 definition for showdog lcd */ - setenv("defaultdisplay", "showdoglcd"); - setenv("buddy", "showdog"); - break; - case KBADC_BEAGLEFPGA: - printf("Recognized KBADC Beagle FPGA board\n"); - MUX_KBADC_BEAGLEFPGA(); - setenv("buddy", "beaglefpga"); - break; - case BEAGLE_NO_EEPROM: - printf("No EEPROM on expansion board\n"); - setenv("buddy", "none"); - break; - default: - printf("Unrecognized expansion board: %x\n", - expansion_config.device_vendor); - setenv("buddy", "unknown"); + case TINCANTOOLS_ZIPPY: + printf("Recognized Tincantools Zippy board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + MUX_TINCANTOOLS_ZIPPY(); + setenv("buddy", "zippy"); + break; + case TINCANTOOLS_ZIPPY2: + printf("Recognized Tincantools Zippy2 board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + MUX_TINCANTOOLS_ZIPPY(); + setenv("buddy", "zippy2"); + break; + case TINCANTOOLS_TRAINER: + printf("Recognized Tincantools Trainer board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + MUX_TINCANTOOLS_ZIPPY(); + MUX_TINCANTOOLS_TRAINER(); + setenv("buddy", "trainer"); + break; + case TINCANTOOLS_SHOWDOG: + printf("Recognized Tincantools Showdow board (rev %d %s)\n", + expansion_config.revision, + expansion_config.fab_revision); + /* Place holder for DSS2 definition for showdog lcd */ + setenv("defaultdisplay", "showdoglcd"); + setenv("buddy", "showdog"); + break; + case KBADC_BEAGLEFPGA: + printf("Recognized KBADC Beagle FPGA board\n"); + MUX_KBADC_BEAGLEFPGA(); + setenv("buddy", "beaglefpga"); + break; + case BEAGLE_NO_EEPROM: + printf("No EEPROM on expansion board\n"); + setenv("buddy", "none"); + break; + default: + printf("Unrecognized expansion board: %x\n", + expansion_config.device_vendor); + setenv("buddy", "unknown"); } - + if (expansion_config.content == 1) setenv(expansion_config.env_var, expansion_config.env_setting); - + twl4030_power_init(); twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); - + /* Configure GPIOs to output */ writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | - GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); - + GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); + /* Set GPIOs */ writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1, - &gpio6_base->setdataout); + &gpio6_base->setdataout); writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | - GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); - + GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); + dieid_num_r(); - + return 0; } diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h index b22b653..10853d8 100644 --- a/board/ti/beagle/beagle.h +++ b/board/ti/beagle/beagle.h @@ -50,411 +50,411 @@ const omap3_sysinfo sysinfo = { * The commented string gives the final mux configuration for that pin */ #define MUX_BEAGLE() \ - /*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\ - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - /*DSS*/\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ - /*CAMERA*/\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ - /*Audio Interface */\ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ - /*Expansion card */\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ - /*Wireless LAN */\ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ - MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ - /*Bluetooth*/\ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\ - MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\ - MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\ - MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\ - MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\ - /*Modem Interface */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \ - MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\ - MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\ - MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\ - MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ - MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\ - MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\ - /*Serial Interface*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ - MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ - MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ - MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\ - /* USB EHCI (port 2) */\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA2*/\ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA7*/\ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA4*/\ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA5*/\ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA6*/\ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA3*/\ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\ - /*Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\ - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ +/*SDRC*/\ +MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ +MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ +MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ +MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ +MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ +MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ +MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ +MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ +MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ +MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ +MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ +MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ +MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ +MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ +MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ +MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ +MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ +MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ +MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ +MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ +MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ +MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ +MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ +MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ +MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ +MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ +MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ +MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ +MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ +MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ +MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ +MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ +MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ +MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ +MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ +MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ +MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ +/*GPMC*/\ +MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ +MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ +MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ +MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ +MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ +MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ +MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ +MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ +MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ +MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ +MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ +MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ +MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ +MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ +MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ +MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ +MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ +MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ +MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ +MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ +MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ +MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ +MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ +MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ +MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ +MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ +MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ +MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ +MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ +MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ +MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ +MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ +MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\ +MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\ +MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\ +MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\ +MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\ +MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ +MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ +MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ +MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ +MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ +MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ +MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ +MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ +/*DSS*/\ +MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ +MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ +MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ +MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ +MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ +MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ +MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ +MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ +MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ +MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ +MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ +MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ +MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ +MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ +MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ +MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ +MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ +MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ +MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ +MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ +MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ +MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ +MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ +MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ +MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ +MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ +MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ +MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ +/*CAMERA*/\ +MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ +MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ +MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ +MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ +MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ +MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ +MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ +MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ +MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ +MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ +MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ +MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ +MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ +MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ +MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ +MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ +MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ +MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ +MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ +MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ +MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ +MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ +MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ +MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ +/*Audio Interface */\ +MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ +MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ +MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ +MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ +/*Expansion card */\ +MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ +MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ +MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ +MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ +MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ +MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ +MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ +MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ +MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ +MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ +/*Wireless LAN */\ +MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ +MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\ +MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\ +MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\ +MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\ +MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\ +MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\ +MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ +MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\ +MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ +/*Bluetooth*/\ +MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\ +MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ +MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ +MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\ +MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\ +MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\ +MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\ +MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\ +/*Modem Interface */\ +MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ +MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \ +MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \ +MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ +MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\ +MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\ +MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\ +MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\ +MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ +MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\ +MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\ +MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ +MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ +MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\ +MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\ +/*Serial Interface*/\ +MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ +MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ +MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ +MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ +MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ +MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ +MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ +MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ +MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ +MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ +MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ +MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ +MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ +MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ +MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ +MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ +MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ +MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ +MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ +MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ +MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ +MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ +MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ +MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ +MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\ +MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\ +MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\ +MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\ +MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ +MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ +MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\ +/* USB EHCI (port 2) */\ +MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA2*/\ +MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA7*/\ +MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA4*/\ +MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA5*/\ +MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA6*/\ +MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA3*/\ +MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\ +MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\ +MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\ +MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\ +MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\ +MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\ +/*Control and debug */\ +MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ +MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ +MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ +MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ +MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\ +MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\ +MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ +MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ +MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ +MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \ +MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ +MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\ +MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ +MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\ +MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\ +MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\ +MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\ +MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\ +MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\ +MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\ +MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\ +MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\ +MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\ +MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\ +MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\ +MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ +MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ +MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ +MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ +MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ +MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ +MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ +MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ +MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ +MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ +MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ +MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ +MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ +MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ +MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ +MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ +MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ +MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ +MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ +MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ +MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ +MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ +MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ +MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ +MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ +MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ +MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ +MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ +MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ +MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ +MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ +MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ +MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ +MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ +MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ +MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ +MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ +MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ +MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ +MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ +MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ +MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ +MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ +MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ +MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ +MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ +MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ +MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ +MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ +MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ +MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ +MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ +MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ +MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ +MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ +MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ +MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ +MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ +MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ +MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ +MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ +MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ +MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ +MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ +MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ #define MUX_BEAGLE_C() \ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/ +MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ +MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ +MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ +MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ +MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ +MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/ #define MUX_BEAGLE_XM() \ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | EN | M4)) /*GPIO_56*/\ - MUX_VAL(CP(GPMC_WAIT0), (IDIS | PTU | EN | M4)) /*GPIO_63*/\ - MUX_VAL(CP(MMC1_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_129*/\ - MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\ - MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\ - MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\ - MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\ - MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\ - MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ +MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | EN | M4)) /*GPIO_56*/\ +MUX_VAL(CP(GPMC_WAIT0), (IDIS | PTU | EN | M4)) /*GPIO_63*/\ +MUX_VAL(CP(MMC1_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_129*/\ +MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\ +MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ +MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ +MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ +MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ +MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ +MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ +MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ +MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ +MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ +MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ +MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ +MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) /*safe_mode*/\ +MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\ +MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\ +MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\ +MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\ +MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\ +MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\ +MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\ +MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\ +MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\ +MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\ +MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\ +MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ #define MUX_TINCANTOOLS_ZIPPY() \ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\ - MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | EN | M1)) /*MCSPI4_CLK*/\ - MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\ - MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M1)) /*MCSPI4_SIMO*/\ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) /*MCSPI4_SOMI*/\ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) /*MCSPI4_CS0*/\ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/ +MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ +MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ +MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ +MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ +MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ +MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ +MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\ +MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\ +MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\ +MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\ +MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | EN | M1)) /*MCSPI4_CLK*/\ +MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\ +MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M1)) /*MCSPI4_SIMO*/\ +MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) /*MCSPI4_SOMI*/\ +MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) /*MCSPI4_CS0*/\ +MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\ +MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\ +MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ +MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/ #define MUX_TINCANTOOLS_TRAINER() \ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\ - MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\ - MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ - MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ - MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) /*GPIO_140*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) /*GPIO_141*/\ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) /*GPIO_162*/ +MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ +MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\ +MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\ +MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\ +MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\ +MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\ +MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\ +MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ +MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\ +MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ +MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) /*GPIO_140*/\ +MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) /*GPIO_141*/\ +MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) /*GPIO_162*/ #define MUX_KBADC_BEAGLEFPGA() \ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | DIS | M1)) /*MCSPI4_CLK*/\ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | EN | M1)) /*MCSPI4_SOMI*/\ - MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/ +MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | DIS | M1)) /*MCSPI4_CLK*/\ +MUX_VAL(CP(MCBSP1_DX), (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\ +MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | EN | M1)) /*MCSPI4_SOMI*/\ +MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/ #endif |