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-rw-r--r--cpu/mpc83xx/cpu.c85
-rw-r--r--cpu/mpc83xx/spd_sdram.c43
-rw-r--r--cpu/mpc85xx/cpu.c47
-rw-r--r--cpu/mpc85xx/cpu_init.c4
-rw-r--r--cpu/mpc85xx/ddr-gen1.c33
-rw-r--r--cpu/mpc86xx/cpu.c88
-rw-r--r--cpu/mpc86xx/cpu_init.c3
-rw-r--r--cpu/mpc8xxx/ddr/ddr3_dimm_params.c2
8 files changed, 34 insertions, 271 deletions
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index c4331ae..e38a372 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -276,91 +276,6 @@ void watchdog_reset (void)
}
#endif
-#if defined(CONFIG_DDR_ECC)
-void dma_init(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile dma83xx_t *dma = &immap->dma;
- volatile u32 status = swab32(dma->dmasr0);
- volatile u32 dmamr0 = swab32(dma->dmamr0);
-
- debug("DMA-init\n");
-
- /* initialize DMASARn, DMADAR and DMAABCRn */
- dma->dmadar0 = (u32)0;
- dma->dmasar0 = (u32)0;
- dma->dmabcr0 = 0;
-
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- /* clear CS bit */
- dmamr0 &= ~DMA_CHANNEL_START;
- dma->dmamr0 = swab32(dmamr0);
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- /* while the channel is busy, spin */
- while(status & DMA_CHANNEL_BUSY) {
- status = swab32(dma->dmasr0);
- }
-
- debug("DMA-init end\n");
-}
-
-uint dma_check(void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile dma83xx_t *dma = &immap->dma;
- volatile u32 status = swab32(dma->dmasr0);
- volatile u32 byte_count = swab32(dma->dmabcr0);
-
- /* while the channel is busy, spin */
- while (status & DMA_CHANNEL_BUSY) {
- status = swab32(dma->dmasr0);
- }
-
- if (status & DMA_CHANNEL_TRANSFER_ERROR) {
- printf ("DMA Error: status = %x @ %d\n", status, byte_count);
- }
-
- return status;
-}
-
-int dma_xfer(void *dest, u32 count, void *src)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile dma83xx_t *dma = &immap->dma;
- volatile u32 dmamr0;
-
- /* initialize DMASARn, DMADAR and DMAABCRn */
- dma->dmadar0 = swab32((u32)dest);
- dma->dmasar0 = swab32((u32)src);
- dma->dmabcr0 = swab32(count);
-
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- /* init direct transfer, clear CS bit */
- dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
- DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
- DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
-
- dma->dmamr0 = swab32(dmamr0);
-
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- /* set CS to start DMA transfer */
- dmamr0 |= DMA_CHANNEL_START;
- dma->dmamr0 = swab32(dmamr0);
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
-
- return ((int)dma_check());
-}
-#endif /*CONFIG_DDR_ECC*/
-
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 4704d20..0f61180 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -64,13 +64,6 @@ void board_add_ram_info(int use_default)
}
#ifdef CONFIG_SPD_EEPROM
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
-extern void dma_init(void);
-extern uint dma_check(void);
-extern int dma_xfer(void *dest, uint count, void *src);
-#endif
-
#ifndef CONFIG_SYS_READ_SPD
#define CONFIG_SYS_READ_SPD i2c_read
#endif
@@ -830,7 +823,7 @@ long int spd_sdram()
}
#endif /* CONFIG_SPD_EEPROM */
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Use timebase counter, get_timer() is not availabe
* at this point of initialization yet.
@@ -863,7 +856,6 @@ static __inline__ unsigned long get_tbms (void)
/*
* Initialize all of memory for ECC, then enable errors.
*/
-/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
void ddr_enable_ecc(unsigned int dram_size)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
@@ -872,46 +864,21 @@ void ddr_enable_ecc(unsigned int dram_size)
register u64 *p;
register uint size;
unsigned int pattern[2];
-#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
- uint i;
-#endif
+
icache_enable();
t_start = get_tbms();
pattern[0] = 0xdeadbeef;
pattern[1] = 0xdeadbeef;
-#if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
+ dma_meminit(pattern[0], dram_size);
+#else
debug("ddr init: CPU FP write method\n");
size = dram_size;
for (p = 0; p < (u64*)(size); p++) {
ppcDWstore((u32*)p, pattern);
}
__asm__ __volatile__ ("sync");
-#else
- debug("ddr init: DMA method\n");
- size = 0x2000;
- for (p = 0; p < (u64*)(size); p++) {
- ppcDWstore((u32*)p, pattern);
- }
- __asm__ __volatile__ ("sync");
-
- /* Initialise DMA for direct transfer */
- dma_init();
- /* Start DMA to transfer */
- dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
- dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
- dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
- dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
- dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
- dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
- dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
- dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
- dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
- dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
-
- for (i = 1; i < dram_size / 0x800000; i++) {
- dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
- }
#endif
t_end = get_tbms();
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index d88c564..28c6119 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -264,53 +264,6 @@ reset_85xx_watchdog(void)
}
#endif /* CONFIG_WATCHDOG */
-#if defined(CONFIG_DDR_ECC)
-void dma_init(void) {
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
-
- dma->satr = 0x00040000;
- dma->datr = 0x00040000;
- dma->sr = 0xffffffff; /* clear any errors */
- asm("sync; isync; msync");
- return;
-}
-
-uint dma_check(void) {
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
- volatile uint status = dma->sr;
-
- /* While the channel is busy, spin */
- while((status & 4) == 4) {
- status = dma->sr;
- }
-
- /* clear MR[CS] channel start bit */
- dma->mr &= 0x00000001;
- asm("sync;isync;msync");
-
- if (status != 0) {
- printf ("DMA Error: status = %x\n", status);
- }
- return status;
-}
-
-int dma_xfer(void *dest, uint count, void *src) {
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
-
- dma->dar = (uint) dest;
- dma->sar = (uint) src;
- dma->bcr = count;
- dma->mr = 0xf000004;
- asm("sync;isync;msync");
- dma->mr = 0xf000005;
- asm("sync;isync;msync");
- return dma_check();
-}
-#endif
-
/*
* Configures a UPM. The function requires the respective MxMR to be set
* before calling this function. "size" is the number or entries, not a sizeof.
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index c98dd8d..41de694 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -261,7 +261,9 @@ void cpu_init_f (void)
#if defined(CONFIG_MPC8536)
fsl_serdes_init();
#endif
-
+#if defined(CONFIG_FSL_DMA)
+ dma_init();
+#endif
}
diff --git a/cpu/mpc85xx/ddr-gen1.c b/cpu/mpc85xx/ddr-gen1.c
index e24c9af..54437dd 100644
--- a/cpu/mpc85xx/ddr-gen1.c
+++ b/cpu/mpc85xx/ddr-gen1.c
@@ -66,10 +66,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
}
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void dma_init(void);
-extern uint dma_check(void);
-extern int dma_xfer(void *dest, uint count, void *src);
-
/*
* Initialize all of memory for ECC, then enable errors.
*/
@@ -77,36 +73,9 @@ extern int dma_xfer(void *dest, uint count, void *src);
void
ddr_enable_ecc(unsigned int dram_size)
{
- uint *p = 0;
- uint i = 0;
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
- dma_init();
-
- for (*p = 0; p < (uint *)(8 * 1024); p++) {
- if (((unsigned int)p & 0x1f) == 0) {
- ppcDcbz((unsigned long) p);
- }
- *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
- if (((unsigned int)p & 0x1c) == 0x1c) {
- ppcDcbf((unsigned long) p);
- }
- }
-
- dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
- dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
- dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
- dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
- dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
- dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
- dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
- dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
- dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
- dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
-
- for (i = 1; i < dram_size / 0x800000; i++) {
- dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
- }
+ dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
/*
* Enable errors for ECC.
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index d47cc5e..bc64286 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -31,6 +31,21 @@
#include <tsec.h>
#include <asm/fsl_law.h>
+struct cpu_type cpu_type_list [] = {
+ CPU_TYPE_ENTRY(8610, 8610),
+ CPU_TYPE_ENTRY(8641, 8641),
+ CPU_TYPE_ENTRY(8641D, 8641D),
+};
+
+struct cpu_type *identify_cpu(u32 ver)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
+ if (cpu_type_list[i].soc_ver == ver)
+ return &cpu_type_list[i];
+
+ return NULL;
+}
/*
* Default board reset function
@@ -53,6 +68,7 @@ checkcpu(void)
char buf1[32], buf2[32];
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
+ struct cpu_type *cpu;
uint msscr0 = mfspr(MSSCR0);
svr = get_svr();
@@ -62,20 +78,13 @@ checkcpu(void)
puts("CPU: ");
- switch (ver) {
- case SVR_8641:
- puts("8641");
- break;
- case SVR_8641D:
- puts("8641D");
- break;
- case SVR_8610:
- puts("8610");
- break;
- default:
+ cpu = identify_cpu(ver);
+ if (cpu) {
+ puts(cpu->name);
+ } else {
puts("Unknown");
- break;
}
+
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
puts("Core: ");
@@ -177,61 +186,6 @@ watchdog_reset(void)
}
#endif /* CONFIG_WATCHDOG */
-
-#if defined(CONFIG_DDR_ECC)
-void
-dma_init(void)
-{
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
-
- dma->satr = 0x00040000;
- dma->datr = 0x00040000;
- dma->sr = 0xffffffff; /* clear any errors */
- asm("sync; isync");
-}
-
-uint
-dma_check(void)
-{
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
- volatile uint status = dma->sr;
-
- /* While the channel is busy, spin */
- while ((status & 4) == 4) {
- status = dma->sr;
- }
-
- /* clear MR[CS] channel start bit */
- dma->mr &= 0x00000001;
- asm("sync;isync");
-
- if (status != 0) {
- printf("DMA Error: status = %x\n", status);
- }
- return status;
-}
-
-int
-dma_xfer(void *dest, uint count, void *src)
-{
- volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
- volatile fsl_dma_t *dma = &dma_base->dma[0];
-
- dma->dar = (uint) dest;
- dma->sar = (uint) src;
- dma->bcr = count;
- dma->mr = 0xf000004;
- asm("sync;isync");
- dma->mr = 0xf000005;
- asm("sync;isync");
- return dma_check();
-}
-
-#endif /* CONFIG_DDR_ECC */
-
-
/*
* Print out the state of various machine registers.
* Currently prints out LAWs, BR0/OR0, and BATs
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 49528aa..341e815 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -113,6 +113,9 @@ void cpu_init_f(void)
memctl->or7 = CONFIG_SYS_OR7_PRELIM;
memctl->br7 = CONFIG_SYS_BR7_PRELIM;
#endif
+#if defined(CONFIG_FSL_DMA)
+ dma_init();
+#endif
/* enable the timebase bit in HID0 */
set_hid0(get_hid0() | 0x4000000);
diff --git a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index 8d686ac..13d234e 100644
--- a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -68,7 +68,7 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd)
if ((spd->organization & 0x7) < 4)
nbit_sdram_width = (spd->organization & 0x7) + 2;
- bsize = 1 << (nbit_sdram_cap_bsize - 3
+ bsize = 1ULL << (nbit_sdram_cap_bsize - 3
+ nbit_primary_bus_width - nbit_sdram_width);
debug("DDR: DDR III rank density = 0x%08x\n", bsize);
generated by cgit v1.1 at 2024-07-31 02:07:52 +0000