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-rw-r--r--include/asm-ppc/immap_512x.h4
-rw-r--r--include/asm-ppc/mpc512x.h2
-rw-r--r--include/configs/aria.h22
-rw-r--r--include/configs/mecp5123.h23
-rw-r--r--include/configs/mpc5121ads.h30
5 files changed, 37 insertions, 44 deletions
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
index 24e6c69..79cdd80 100644
--- a/include/asm-ppc/immap_512x.h
+++ b/include/asm-ppc/immap_512x.h
@@ -341,6 +341,10 @@ typedef struct ddr512x {
u32 res2[0x3AD];
} ddr512x_t;
+/* MDDRC SYS CFG and Timing CFG0 Registers */
+#define MDDRC_SYS_CFG_EN 0xF0000000
+#define MDDRC_SYS_CFG_CMD_MASK 0x10000000
+#define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF
/*
* DMA/Messaging Unit
diff --git a/include/asm-ppc/mpc512x.h b/include/asm-ppc/mpc512x.h
index 20456f5..8ef0d9c 100644
--- a/include/asm-ppc/mpc512x.h
+++ b/include/asm-ppc/mpc512x.h
@@ -50,7 +50,7 @@ static inline void sync_law(volatile void *addr)
/*
* Prototypes
*/
-extern long int fixed_sdram(void);
+extern long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz);
extern int mpc5121_diu_init(void);
extern void ide_set_reset(int idereset);
diff --git a/include/configs/aria.h b/include/configs/aria.h
index 4211113..2938eac 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -126,7 +126,7 @@
#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \
(1 << 30) | /* CKE */ \
(1 << 29) | /* CLK_ON */ \
- (1 << 28) | /* CMD_MODE */ \
+ (0 << 28) | /* CMD_MODE */ \
(4 << 25) | /* DRAM_ROW_SELECT */ \
(3 << 21) | /* DRAM_BANK_SELECT */ \
(0 << 18) | /* SELF_REF_EN */ \
@@ -143,16 +143,12 @@
(0 << 0) /* FIFO_UV_EN */ \
)
-#define CONFIG_SYS_MDDRC_SYS_CFG_RUN (CONFIG_SYS_MDDRC_SYS_CFG & ~(1 << 28))
+#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189
#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863
-#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
-#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x030C3D2E
-
-#define CONFIG_SYS_MICRON_NOP 0x01380000
-#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400
+#define CONFIG_SYS_DDRCMD_NOP 0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \
(0 << 22) | /* DRAM_CS */ \
(0 << 21) | /* DRAM_RAS */ \
@@ -172,7 +168,7 @@
)
#define CONFIG_SYS_MICRON_EMR2 0x01020000
#define CONFIG_SYS_MICRON_EMR3 0x01030000
-#define CONFIG_SYS_MICRON_RFSH 0x01080000
+#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \
(0 << 22) | /* DRAM_CS */ \
@@ -196,10 +192,10 @@
* Backward compatible definitions,
* so we do not have to change cpu/mpc512x/fixed_sdram.c
*/
-#define CONFIG_SYS_MICRON_EM2 (CONFIG_SYS_MICRON_EMR2)
-#define CONFIG_SYS_MICRON_EM3 (CONFIG_SYS_MICRON_EMR3)
-#define CONFIG_SYS_MICRON_EN_DLL (CONFIG_SYS_MICRON_EMR)
-#define CONFIG_SYS_MICRON_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
+#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
+#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
+#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
/* DDR Priority Manager Configuration */
#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index 1ecae00..e194c8f 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -111,22 +111,19 @@
* [09:05] DRAM tRP:
* [04:00] DRAM tRPA
*/
-#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00
-#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00
+#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
+#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
-#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
-#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E
-
-#define CONFIG_SYS_MICRON_NOP 0x01380000
-#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400
-#define CONFIG_SYS_MICRON_EM2 0x01020000
-#define CONFIG_SYS_MICRON_EM3 0x01030000
-#define CONFIG_SYS_MICRON_EN_DLL 0x01010000
-#define CONFIG_SYS_MICRON_RFSH 0x01080000
+
+#define CONFIG_SYS_DDRCMD_NOP 0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
+#define CONFIG_SYS_DDRCMD_EM2 0x01020000
+#define CONFIG_SYS_DDRCMD_EM3 0x01030000
+#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
+#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
-#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780
/* DDR Priority Manager Configuration */
#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 76f174d..0c871c9 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -131,28 +131,24 @@
* [04:00] DRAM tRPA
*/
#ifdef CONFIG_MPC5121ADS_REV2
-#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00
-#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00
+#define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00
#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168
#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864
#else
-#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00
-#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00
-#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
+#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
#endif
-#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
-#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E
-
-#define CONFIG_SYS_MICRON_NOP 0x01380000
-#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400
-#define CONFIG_SYS_MICRON_EM2 0x01020000
-#define CONFIG_SYS_MICRON_EM3 0x01030000
-#define CONFIG_SYS_MICRON_EN_DLL 0x01010000
-#define CONFIG_SYS_MICRON_RFSH 0x01080000
+#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
+
+#define CONFIG_SYS_DDRCMD_NOP 0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
+#define CONFIG_SYS_DDRCMD_EM2 0x01020000
+#define CONFIG_SYS_DDRCMD_EM3 0x01030000
+#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
+#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
-#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780
/* DDR Priority Manager Configuration */
#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
generated by cgit v1.1 at 2024-11-06 02:38:49 +0000