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-rw-r--r--include/asm-blackfin/config.h3
-rw-r--r--include/asm-blackfin/global_data.h1
-rw-r--r--include/asm-ppc/immap_512x.h4
-rw-r--r--include/common.h5
-rw-r--r--include/configs/MPC8610HPCD.h2
-rw-r--r--include/configs/MPC8641HPCN.h2
-rw-r--r--include/configs/P1_P2_RDB.h87
-rw-r--r--include/configs/amcc-common.h2
-rw-r--r--include/configs/galaxy5200.h2
-rw-r--r--include/configs/mcc200.h2
-rw-r--r--include/configs/sbc8349.h2
-rw-r--r--include/configs/sbc8641d.h2
-rw-r--r--include/configs/sequoia.h6
-rw-r--r--include/configs/vme8349.h2
-rw-r--r--include/fdt_support.h2
-rw-r--r--include/ppc440.h7
-rw-r--r--include/ppc4xx.h2
17 files changed, 112 insertions, 21 deletions
diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h
index 25794dd..327843d 100644
--- a/include/asm-blackfin/config.h
+++ b/include/asm-blackfin/config.h
@@ -18,6 +18,9 @@
# define CONFIG_BFIN_SCRATCH_REG retn
#endif
+/* Relocation to SDRAM works on all Blackfin boards */
+#define CONFIG_RELOC_FIXUP_WORKS
+
/* Make sure the structure is properly aligned */
#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h
index 3194b72..b78b04c 100644
--- a/include/asm-blackfin/global_data.h
+++ b/include/asm-blackfin/global_data.h
@@ -44,7 +44,6 @@ typedef struct global_data {
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
phys_size_t ram_size; /* RAM size */
- unsigned long reloc_off; /* Relocation Offset */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
index bdc6ff2..95350fd 100644
--- a/include/asm-ppc/immap_512x.h
+++ b/include/asm-ppc/immap_512x.h
@@ -215,8 +215,8 @@ typedef struct clk512x {
#define CLOCK_SCCR2_DIU_EN 0x80000000
#define CLOCK_SCCR2_AXE_EN 0x40000000
#define CLOCK_SCCR2_MEM_EN 0x20000000
-#define CLOCK_SCCR2_USB2_EN 0x10000000
-#define CLOCK_SCCR2_USB1_EN 0x08000000
+#define CLOCK_SCCR2_USB1_EN 0x10000000
+#define CLOCK_SCCR2_USB2_EN 0x08000000
#define CLOCK_SCCR2_I2C_EN 0x04000000
#define CLOCK_SCCR2_BDLC_EN 0x02000000
#define CLOCK_SCCR2_SDHC_EN 0x01000000
diff --git a/include/common.h b/include/common.h
index f7c93bf..7df9afa 100644
--- a/include/common.h
+++ b/include/common.h
@@ -719,4 +719,9 @@ int cpu_release(int nr, int argc, char *argv[]);
#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
+/* Pull in stuff for the build system */
+#ifdef DO_DEPS_ONLY
+# include <environment.h>
+#endif
+
#endif /* __COMMON_H_ */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 7619328..7cb4ccd 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -102,8 +102,6 @@
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
-#define MPC86xx_DDR_SDRAM_CLK_CNTL
-
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index b0ae25c..a46f7c8 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -141,8 +141,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
-#define MPC86xx_DDR_SDRAM_CLK_CNTL
-
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 8e97ad0..310242e 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -43,6 +43,22 @@
#define CONFIG_P2020
#endif
+#ifdef CONFIG_MK_NAND
+#define CONFIG_NAND_U_BOOT 1
+#define CONFIG_RAMBOOT_NAND 1
+#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
+#endif
+
+#ifdef CONFIG_MK_SDCARD
+#define CONFIG_RAMBOOT_SDCARD 1
+#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
+#endif
+
+#ifdef CONFIG_MK_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH 1
+#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
@@ -82,16 +98,34 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_MEMTEST_END 0x1fffffff
#define CONFIG_PANIC_HANG /* do not reset board on panic */
+ /*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE (512 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */
/* CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
/* CONFIG_SYS_IMMR */
+
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
+#else
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#endif
+
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
@@ -158,6 +192,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
+ || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
@@ -177,7 +218,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
+#ifndef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE 0xffa00000
+#else
+#define CONFIG_SYS_NAND_BASE 0xfff00000
+#endif
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE 1
@@ -187,6 +232,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
/* NAND flash config */
#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
@@ -202,10 +256,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
| OR_FCM_TRLX \
| OR_FCM_EHTR)
+#ifdef CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
+#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
+#endif
#define CONFIG_SYS_VSC7385_BASE 0xffb00000
@@ -371,14 +432,26 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+ #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
+ #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+ #define CONFIG_ENV_SIZE 0x2000
+#endif
#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+ #define CONFIG_ENV_IS_IN_FLASH 1
+ #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+ #define CONFIG_ENV_ADDR 0xfff80000
+ #else
+ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+ #endif
+ #define CONFIG_ENV_SIZE 0x2000
+ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 51128a3..8cd97b8 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -156,6 +156,8 @@
*/
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
+/* Update size in "reg" property of NOR FLASH device tree nodes */
+#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
/*
* Booting and default environment
diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h
index 3b67ea9..931acfb 100644
--- a/include/configs/galaxy5200.h
+++ b/include/configs/galaxy5200.h
@@ -210,7 +210,7 @@
/* Chip Select configuration for NAND flash */
#define CONFIG_SYS_CS1_START 0x20000000
#define CONFIG_SYS_CS1_SIZE 0x90000
-#define CONFIG_SYS_CS1_CFG 0x0002d900
+#define CONFIG_SYS_CS1_CFG 0x00025b00
/* Chip Select configuration for Epson S1D13513 */
#define CONFIG_SYS_CS3_START 0x10000000
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index e5812ee..7ef6385 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -398,7 +398,7 @@
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
-#elif
+#else
#error "Wrong QUART expander number."
#endif
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index bf7cf82..4dea27d 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -304,7 +304,7 @@
#define CONFIG_SYS_I2C1_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET
-/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
/* TSEC */
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 2865df5..682d241 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -121,8 +121,6 @@
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM
-#define MPC86xx_DDR_SDRAM_CLK_CNTL
-
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 89acacc..9605ce2 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -243,6 +243,11 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
+
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_AD7414 1 /* use AD7414 */
@@ -300,6 +305,7 @@
/*
* Commands additional to the ones defined in amcc-common.h
*/
+#define CONFIG_CMD_CHIP_CONFIG
#define CONFIG_CMD_DTT
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NAND
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index d0690fe..f9db73b 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -224,7 +224,7 @@
#define CONFIG_SYS_I2C1_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET
-/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 16734c5..0a9dd0d 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -79,5 +79,7 @@ void ft_pci_setup(void *blob, bd_t *bd);
void set_working_fdt_addr(void *addr);
int fdt_resize(void *blob);
+int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size);
+
#endif /* ifdef CONFIG_OF_LIBFDT */
#endif /* ifndef __FDT_SUPPORT_H */
diff --git a/include/ppc440.h b/include/ppc440.h
index fe0db93..e54a977 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1701,9 +1701,14 @@
#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
#endif /* CONFIG_440GX */
-#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define CPR0_ICFG_RLI_MASK 0x80000000
#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
+#define CPR0_SPCID_SPCIDV0_DIV1 0x01000000
+#define CPR0_SPCID_SPCIDV0_DIV2 0x02000000
+#define CPR0_SPCID_SPCIDV0_DIV3 0x03000000
+#define CPR0_SPCID_SPCIDV0_DIV4 0x00000000
#define CPR0_PERD_PERDV0_MASK 0x07000000
#endif
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 3bff00a..5024db4 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -221,6 +221,8 @@ static inline void set_mcsr(u32 val)
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
}
+int ppc4xx_pci_sync_clock_config(u32 async);
+
#endif /* __ASSEMBLY__ */
/* for multi-cpu support */
generated by cgit v1.1 at 2024-11-06 02:19:10 +0000