diff options
Diffstat (limited to 'u-boot/board/renesas')
31 files changed, 4837 insertions, 0 deletions
diff --git a/u-boot/board/renesas/MigoR/Makefile b/u-boot/board/renesas/MigoR/Makefile new file mode 100644 index 0000000..3529810 --- /dev/null +++ b/u-boot/board/renesas/MigoR/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (C) 2007 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# Copyright (C) 2007 +# Kenati Technologies, Inc. +# +# board/MigoR/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := migo_r.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/u-boot/board/renesas/MigoR/lowlevel_init.S b/u-boot/board/renesas/MigoR/lowlevel_init.S new file mode 100644 index 0000000..e32a7af --- /dev/null +++ b/u-boot/board/renesas/MigoR/lowlevel_init.S @@ -0,0 +1,208 @@ +/* + * Copyright (C) 2007-2008 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * Copyright (C) 2007 + * Kenati Technologies, Inc. + * + * board/MigoR/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +#include <asm/processor.h> +#include <asm/macro.h> + +/* + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. + * + * (Note: As no stack is available, no subroutines can be called...). + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + write32 CCR_A, CCR_D ! Address of Cache Control Register + ! Instruction Cache Invalidate + + write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register + ! TI == TLB Invalidate bit + + write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0 + + write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2 + + write16 PFC_PULCR_A, PFC_PULCR_D + + write16 PFC_DRVCR_A, PFC_DRVCR_D + + write16 SBSCR_A, SBSCR_D + + write16 PSCR_A, PSCR_D + + write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register) + ! 0xA507 -> timer_STOP / WDT_CLK = max + + write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register) + ! 0x5A00 -> Clear + + write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register) + ! 0xA504 -> timer_STOP / CLK = 500ms + + write32 DLLFRQ_A, DLLFRQ_D ! 20080115 + ! 20080115 + + write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register + ! 20080115 + + write32 CCR_A, CCR_D_2 ! Address of Cache Control Register + ! ?? + +bsc_init: + write32 CMNCR_A, CMNCR_D + + write32 CS0BCR_A, CS0BCR_D + + write32 CS4BCR_A, CS4BCR_D + + write32 CS5ABCR_A, CS5ABCR_D + + write32 CS5BBCR_A, CS5BBCR_D + + write32 CS6ABCR_A, CS6ABCR_D + + write32 CS0WCR_A, CS0WCR_D + + write32 CS4WCR_A, CS4WCR_D + + write32 CS5AWCR_A, CS5AWCR_D + + write32 CS5BWCR_A, CS5BWCR_D + + write32 CS6AWCR_A, CS6AWCR_D + + ! SDRAM initialization + write32 SDCR_A, SDCR_D + + write32 SDWCR_A, SDWCR_D + + write32 SDPCR_A, SDPCR_D + + write32 RTCOR_A, RTCOR_D + + write32 RTCNT_A, RTCNT_D + + write32 RTCSR_A, RTCSR_D + + write32 RFCR_A, RFCR_D + + write8 SDMR3_A, SDMR3_D + + ! BL bit off (init = ON) (?!?) + + stc sr, r0 ! BL bit off(init=ON) + mov.l SR_MASK_D, r1 + and r1, r0 + ldc r0, sr + + rts + mov #0, r0 + + .align 4 + +CCR_A: .long CCR +MMUCR_A: .long MMUCR +MSTPCR0_A: .long MSTPCR0 +MSTPCR2_A: .long MSTPCR2 +PFC_PULCR_A: .long PULCR +PFC_DRVCR_A: .long DRVCR +SBSCR_A: .long SBSCR +PSCR_A: .long PSCR +RWTCSR_A: .long RWTCSR +RWTCNT_A: .long RWTCNT +FRQCR_A: .long FRQCR +PLLCR_A: .long PLLCR +DLLFRQ_A: .long DLLFRQ + +CCR_D: .long 0x00000800 +CCR_D_2: .long 0x00000103 +MMUCR_D: .long 0x00000004 +MSTPCR0_D: .long 0x00001001 +MSTPCR2_D: .long 0xffffffff +PFC_PULCR_D: .long 0x6000 +PFC_DRVCR_D: .long 0x0464 +FRQCR_D: .long 0x07033639 +PLLCR_D: .long 0x00005000 +DLLFRQ_D: .long 0x000004F6 + +CMNCR_A: .long CMNCR +CMNCR_D: .long 0x0000001B +CS0BCR_A: .long CS0BCR +CS0BCR_D: .long 0x24920400 +CS4BCR_A: .long CS4BCR +CS4BCR_D: .long 0x00003400 +CS5ABCR_A: .long CS5ABCR +CS5ABCR_D: .long 0x24920400 +CS5BBCR_A: .long CS5BBCR +CS5BBCR_D: .long 0x24920400 +CS6ABCR_A: .long CS6ABCR +CS6ABCR_D: .long 0x24920400 + +CS0WCR_A: .long CS0WCR +CS0WCR_D: .long 0x00000380 +CS4WCR_A: .long CS4WCR +CS4WCR_D: .long 0x00110080 +CS5AWCR_A: .long CS5AWCR +CS5AWCR_D: .long 0x00000300 +CS5BWCR_A: .long CS5BWCR +CS5BWCR_D: .long 0x00000300 +CS6AWCR_A: .long CS6AWCR +CS6AWCR_D: .long 0x00000300 + +SDCR_A: .long SBSC_SDCR +SDCR_D: .long 0x80160809 +SDWCR_A: .long SBSC_SDWCR +SDWCR_D: .long 0x0014450C +SDPCR_A: .long SBSC_SDPCR +SDPCR_D: .long 0x00000087 +RTCOR_A: .long SBSC_RTCOR +RTCNT_A: .long SBSC_RTCNT +RTCNT_D: .long 0xA55A0012 +RTCOR_D: .long 0xA55A001C +RTCSR_A: .long SBSC_RTCSR +RFCR_A: .long SBSC_RFCR +RFCR_D: .long 0xA55A0221 +RTCSR_D: .long 0xA55A009a +SDMR3_A: .long 0xFE581180 +SDMR3_D: .long 0x0 + +SR_MASK_D: .long 0xEFFFFF0F + + .align 2 + +SBSCR_D: .word 0x0044 +PSCR_D: .word 0x0000 +RWTCSR_D_1: .word 0xA507 +RWTCSR_D_2: .word 0xA504 +RWTCNT_D: .word 0x5A00 diff --git a/u-boot/board/renesas/MigoR/migo_r.c b/u-boot/board/renesas/MigoR/migo_r.c new file mode 100644 index 0000000..75b653f --- /dev/null +++ b/u-boot/board/renesas/MigoR/migo_r.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * Copyright (C) 2007 + * Kenati Technologies, Inc. + * + * board/MigoR/migo_r.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("BOARD: Renesas MigoR\n"); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state (unsigned short value) +{ +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/u-boot/board/renesas/ap325rxa/Makefile b/u-boot/board/renesas/ap325rxa/Makefile new file mode 100644 index 0000000..5a2a0f3 --- /dev/null +++ b/u-boot/board/renesas/ap325rxa/Makefile @@ -0,0 +1,51 @@ +######################################################################### +# +# Copyright (C) 2008 Renesas Solutions Corp. +# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +# +# board/ap325rxa/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := ap325rxa.o cpld-ap325rxa.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/u-boot/board/renesas/ap325rxa/ap325rxa.c b/u-boot/board/renesas/ap325rxa/ap325rxa.c new file mode 100644 index 0000000..758e6f4 --- /dev/null +++ b/u-boot/board/renesas/ap325rxa/ap325rxa.c @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* PRI control register */ +#define PRPRICR5 0xFF800048 /* LMB */ +#define PRPRICR5_D 0x2a + +/* FPGA control */ +#define FPGA_NAND_CTL 0xB410020C +#define FPGA_NAND_RST 0x0008 +#define FPGA_NAND_INIT 0x0000 +#define FPGA_NAND_RST_WAIT 10000 + +/* I/O port data */ +#define PACR_D 0x0000 +#define PBCR_D 0x0000 +#define PCCR_D 0x1000 +#define PDCR_D 0x0000 +#define PECR_D 0x0410 +#define PFCR_D 0xffff +#define PGCR_D 0x0000 +#define PHCR_D 0x5011 +#define PJCR_D 0x4400 +#define PKCR_D 0x7c00 +#define PLCR_D 0x0000 +#define PMCR_D 0x0000 +#define PNCR_D 0x0000 +#define PQCR_D 0x0000 +#define PRCR_D 0x0000 +#define PSCR_D 0x0000 +#define PTCR_D 0x0010 +#define PUCR_D 0x0fff +#define PVCR_D 0xffff +#define PWCR_D 0x0000 +#define PXCR_D 0x7500 +#define PYCR_D 0x0000 +#define PZCR_D 0x5540 + +/* Pin Function Controler data */ +#define PSELA_D 0x1410 +#define PSELB_D 0x0140 +#define PSELC_D 0x0000 +#define PSELD_D 0x0400 + +/* I/O Buffer Hi-Z data */ +#define HIZCRA_D 0x0000 +#define HIZCRB_D 0x1000 +#define HIZCRC_D 0x0000 +#define HIZCRD_D 0x0000 + +/* Module select reg data */ +#define MSELCRA_D 0x0014 +#define MSELCRB_D 0x0018 + +/* Module Stop reg Data */ +#define MSTPCR2_D 0xFFD9F280 + +/* CPLD loader */ +extern void init_cpld(void); + +int checkboard(void) +{ + puts("BOARD: AP325RXA\n"); + return 0; +} + +int board_init(void) +{ + /* Pin Function Controler Init */ + outw(PSELA_D, PSELA); + outw(PSELB_D, PSELB); + outw(PSELC_D, PSELC); + outw(PSELD_D, PSELD); + + /* I/O Buffer Hi-Z Init */ + outw(HIZCRA_D, HIZCRA); + outw(HIZCRB_D, HIZCRB); + outw(HIZCRC_D, HIZCRC); + outw(HIZCRD_D, HIZCRD); + + /* Module select reg Init */ + outw(MSELCRA_D, MSELCRA); + outw(MSELCRB_D, MSELCRB); + + /* Module Stop reg Init */ + outl(MSTPCR2_D, MSTPCR2); + + /* I/O ports */ + outw(PACR_D, PACR); + outw(PBCR_D, PBCR); + outw(PCCR_D, PCCR); + outw(PDCR_D, PDCR); + outw(PECR_D, PECR); + outw(PFCR_D, PFCR); + outw(PGCR_D, PGCR); + outw(PHCR_D, PHCR); + outw(PJCR_D, PJCR); + outw(PKCR_D, PKCR); + outw(PLCR_D, PLCR); + outw(PMCR_D, PMCR); + outw(PNCR_D, PNCR); + outw(PQCR_D, PQCR); + outw(PRCR_D, PRCR); + outw(PSCR_D, PSCR); + outw(PTCR_D, PTCR); + outw(PUCR_D, PUCR); + outw(PVCR_D, PVCR); + outw(PWCR_D, PWCR); + outw(PXCR_D, PXCR); + outw(PYCR_D, PYCR); + outw(PZCR_D, PZCR); + + /* PRI control register Init */ + outl(PRPRICR5_D, PRPRICR5); + + /* cpld init */ + init_cpld(); + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state(unsigned short value) +{ +} + +void ide_set_reset(int idereset) +{ + outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */ + udelay(FPGA_NAND_RST_WAIT); + outw(FPGA_NAND_INIT, FPGA_NAND_CTL); +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/u-boot/board/renesas/ap325rxa/cpld-ap325rxa.c b/u-boot/board/renesas/ap325rxa/cpld-ap325rxa.c new file mode 100644 index 0000000..16fadcb --- /dev/null +++ b/u-boot/board/renesas/ap325rxa/cpld-ap325rxa.c @@ -0,0 +1,206 @@ +/*************************************************************** + * Project: + * CPLD SlaveSerial Configuration via embedded microprocessor. + * + * Copyright info: + * + * This is free software; you can redistribute it and/or modify + * it as you like. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Description: + * + * This is the main source file that will allow a microprocessor + * to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II, + * and Spartan-II devices via the SlaveSerial Configuration Mode. + * This code is discussed in Xilinx Application Note, XAPP502. + * + * History: + * 3-October-2001 MN/MP - Created + * 20-August-2008 Renesas Solutions - Modified to SH7723 + ****************************************************************/ + +#include <common.h> + +/* Serial */ +#define SCIF_BASE 0xffe00000 /* SCIF0 */ +#define SCSMR (vu_short *)(SCIF_BASE + 0x00) +#define SCBRR (vu_char *)(SCIF_BASE + 0x04) +#define SCSCR (vu_short *)(SCIF_BASE + 0x08) +#define SC_TDR (vu_char *)(SCIF_BASE + 0x0C) +#define SC_SR (vu_short *)(SCIF_BASE + 0x10) +#define SCFCR (vu_short *)(SCIF_BASE + 0x18) +#define RFCR (vu_long *)0xFE400020 + +#define SCSCR_INIT 0x0038 +#define SCSCR_CLR 0x0000 +#define SCFCR_INIT 0x0006 +#define SCSMR_INIT 0x0080 +#define RFCR_CLR 0xA400 +#define SCI_TD_E 0x0020 +#define SCI_TDRE_CLEAR 0x00df + +#define BPS_SETTING_VALUE 1 /* 12.5MHz */ +#define WAIT_RFCR_COUNTER 500 + +/* CPLD data size */ +#define CPLD_DATA_SIZE 169216 + +/* out */ +#define CPLD_PFC_ADR ((vu_short *)0xA4050112) + +#define CPLD_PROG_ADR ((vu_char *)0xA4050132) +#define CPLD_PROG_DAT 0x80 + +/* in */ +#define CPLD_INIT_ADR ((vu_char *)0xA4050132) +#define CPLD_INIT_DAT 0x40 +#define CPLD_DONE_ADR ((vu_char *)0xA4050132) +#define CPLD_DONE_DAT 0x20 + +#define HIZCRB ((vu_short *)0xA405015A) + +/* data */ +#define CPLD_NOMAL_START 0xA0A80000 +#define CPLD_SAFE_START 0xA0AC0000 +#define MODE_SW (vu_char *)0xA405012A + +static void init_cpld_loader(void) +{ + + *SCSCR = SCSCR_CLR; + *SCFCR = SCFCR_INIT; + *SCSMR = SCSMR_INIT; + + *SCBRR = BPS_SETTING_VALUE; + + *RFCR = RFCR_CLR; /* Refresh counter clear */ + + while (*RFCR < WAIT_RFCR_COUNTER) + ; + + *SCFCR = 0x0; /* RTRG=00, TTRG=00 */ + /* MCE=0,TFRST=0,RFRST=0,LOOP=0 */ + *SCSCR = SCSCR_INIT; +} + +static int check_write_ready(void) +{ + u16 status = *SC_SR; + return status & SCI_TD_E; +} + +static void write_cpld_data(char ch) +{ + while (!check_write_ready()) + ; + + *SC_TDR = ch; + *SC_SR; + *SC_SR = SCI_TDRE_CLEAR; +} + +static int delay(void) +{ + int i; + int c = 0; + for (i = 0; i < 200; i++) { + c = *(volatile int *)0xa0000000; + } + return c; +} + +/*********************************************************************** + * + * Function: slave_serial + * + * Description: Initiates SlaveSerial Configuration. + * Calls ShiftDataOut() to output serial data + * + ***********************************************************************/ +static void slave_serial(void) +{ + int i; + unsigned char *flash; + + *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ + delay(); + + /* + * Toggle Program Pin by Toggling Program_OE bit + * This is accomplished by writing to the Program Register in the CPLD + * + * NOTE: The Program_OE bit should be driven high to bring the Virtex + * Program Pin low. Likewise, it should be driven low + * to bring the Virtex Program Pin to High-Z + */ + + *CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */ + delay(); + + /* + * Bring Program High-Z + * (Drive Program_OE bit low to bring Virtex Program Pin to High-Z + */ + + /* Program_OE bit Low brings the Virtex Program Pin to High Z: */ + *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ + + while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0) + delay(); + + /* Begin Slave-Serial Configuration */ + flash = (unsigned char *)CPLD_NOMAL_START; + + for (i = 0; i < CPLD_DATA_SIZE; i++) + write_cpld_data(*flash++); +} + +/*********************************************************************** + * + * Function: check_done_bit + * + * Description: This function takes monitors the CPLD Input Register + * by checking the status of the DONE bit in that Register. + * By doing so, it monitors the Xilinx Virtex device's DONE + * Pin to see if configuration bitstream has been properly + * loaded + * + ***********************************************************************/ +static void check_done_bit(void) +{ + while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT)) + ; +} + +/*********************************************************************** + * + * Function: init_cpld + * + * Description: Begins Slave Serial configuration of Xilinx FPGA + * + ***********************************************************************/ +void init_cpld(void) +{ + /* Init serial device */ + init_cpld_loader(); + + if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */ + return; + + *HIZCRB = 0x0000; + *CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */ + + /* write CPLD data from NOR flash to device */ + slave_serial(); + + /* + * Monitor the DONE bit in the CPLD Input Register to see if + * configuration successful + */ + + check_done_bit(); +} diff --git a/u-boot/board/renesas/ap325rxa/lowlevel_init.S b/u-boot/board/renesas/ap325rxa/lowlevel_init.S new file mode 100644 index 0000000..04cfef1 --- /dev/null +++ b/u-boot/board/renesas/ap325rxa/lowlevel_init.S @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * + * board/ap325rxa/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/processor.h> +#include <asm/macro.h> + +/* + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. + * + * (Note: As no stack is available, no subroutines can be called...). + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + write16 DRVCRA_A, DRVCRA_D + + write16 DRVCRB_A, DRVCRB_D + + write16 RWTCSR_A, RWTCSR_D1 + + write16 RWTCNT_A, RWTCNT_D + + write16 RWTCSR_A, RWTCSR_D2 + + write32 FRQCR_A, FRQCR_D + + write32 CMNCR_A, CMNCR_D + + write32 CS0BCR_A, CS0BCR_D + + write32 CS4BCR_A, CS4BCR_D + + write32 CS5ABCR_A, CS5ABCR_D + + write32 CS5BBCR_A, CS5BBCR_D + + write32 CS6ABCR_A, CS6ABCR_D + + write32 CS6BBCR_A, CS6BBCR_D + + write32 CS0WCR_A, CS0WCR_D + + write32 CS4WCR_A, CS4WCR_D + + write32 CS5AWCR_A, CS5AWCR_D + + write32 CS5BWCR_A, CS5BWCR_D + + write32 CS6AWCR_A, CS6AWCR_D + + write32 CS6BWCR_A, CS6BWCR_D + + write32 SBSC_SDCR_A, SBSC_SDCR_D1 + + write32 SBSC_SDWCR_A, SBSC_SDWCR_D + + write32 SBSC_SDPCR_A, SBSC_SDPCR_D + + write32 SBSC_RTCSR_A, SBSC_RTCSR_D + + write32 SBSC_RTCNT_A, SBSC_RTCNT_D + + write32 SBSC_RTCOR_A, SBSC_RTCOR_D + + write8 SBSC_SDMR3_A1, SBSC_SDMR3_D + + write8 SBSC_SDMR3_A2, SBSC_SDMR3_D + + mov.l SLEEP_CNT, r1 +2: tst r1, r1 + nop + bf/s 2b + dt r1 + + write8 SBSC_SDMR3_A3, SBSC_SDMR3_D + + write32 SBSC_SDCR_A, SBSC_SDCR_D2 + + write32 CCR_A, CCR_D + + ! BL bit off (init = ON) (?!?) + + stc sr, r0 ! BL bit off(init=ON) + mov.l SR_MASK_D, r1 + and r1, r0 + ldc r0, sr + + rts + mov #0, r0 + + .align 2 + +DRVCRA_A: .long DRVCRA +DRVCRB_A: .long DRVCRB +DRVCRA_D: .word 0x4555 +DRVCRB_D: .word 0x0005 + +RWTCSR_A: .long RWTCSR +RWTCNT_A: .long RWTCNT +FRQCR_A: .long FRQCR +RWTCSR_D1: .word 0xa507 +RWTCSR_D2: .word 0xa504 +RWTCNT_D: .word 0x5a00 +.align 2 +FRQCR_D: .long 0x0b04474a + +SBSC_SDCR_A: .long SBSC_SDCR +SBSC_SDWCR_A: .long SBSC_SDWCR +SBSC_SDPCR_A: .long SBSC_SDPCR +SBSC_RTCSR_A: .long SBSC_RTCSR +SBSC_RTCNT_A: .long SBSC_RTCNT +SBSC_RTCOR_A: .long SBSC_RTCOR +SBSC_SDMR3_A1: .long 0xfe510000 +SBSC_SDMR3_A2: .long 0xfe500242 +SBSC_SDMR3_A3: .long 0xfe5c0042 + +SBSC_SDCR_D1: .long 0x92810112 +SBSC_SDCR_D2: .long 0x92810912 +SBSC_SDWCR_D: .long 0x05162482 +SBSC_SDPCR_D: .long 0x00300087 +SBSC_RTCSR_D: .long 0xa55a0212 +SBSC_RTCNT_D: .long 0xa55a0000 +SBSC_RTCOR_D: .long 0xa55a0040 +SBSC_SDMR3_D: .long 0x00 + +CMNCR_A: .long CMNCR +CS0BCR_A: .long CS0BCR +CS4BCR_A: .long CS4BCR +CS5ABCR_A: .long CS5ABCR +CS5BBCR_A: .long CS5BBCR +CS6ABCR_A: .long CS6ABCR +CS6BBCR_A: .long CS6BBCR +CS0WCR_A: .long CS0WCR +CS4WCR_A: .long CS4WCR +CS5AWCR_A: .long CS5AWCR +CS5BWCR_A: .long CS5BWCR +CS6AWCR_A: .long CS6AWCR +CS6BWCR_A: .long CS6BWCR + +CMNCR_D: .long 0x00000013 +CS0BCR_D: .long 0x24920400 +CS4BCR_D: .long 0x24920400 +CS5ABCR_D: .long 0x24920400 +CS5BBCR_D: .long 0x7fff0600 +CS6ABCR_D: .long 0x24920400 +CS6BBCR_D: .long 0x24920600 +CS0WCR_D: .long 0x00000480 +CS4WCR_D: .long 0x00000480 +CS5AWCR_D: .long 0x00000380 +CS5BWCR_D: .long 0x00000080 +CS6AWCR_D: .long 0x00000300 +CS6BWCR_D: .long 0x00000540 + +CCR_A: .long 0xff00001c +CCR_D: .long 0x0000090d + +SLEEP_CNT: .long 0x00000800 +SR_MASK_D: .long 0xEFFFFF0F diff --git a/u-boot/board/renesas/r2dplus/Makefile b/u-boot/board/renesas/r2dplus/Makefile new file mode 100644 index 0000000..7d92354 --- /dev/null +++ b/u-boot/board/renesas/r2dplus/Makefile @@ -0,0 +1,47 @@ +# +# Copyright (C) 2007,2008 +# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := r2dplus.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/u-boot/board/renesas/r2dplus/lowlevel_init.S b/u-boot/board/renesas/r2dplus/lowlevel_init.S new file mode 100644 index 0000000..f3392f0 --- /dev/null +++ b/u-boot/board/renesas/r2dplus/lowlevel_init.S @@ -0,0 +1,118 @@ +/* + * modified from SH-IPL+g (init-r0p751rlc0011rl.S) + * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz) + * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +*/ + +#include <config.h> +#include <version.h> + +#include <asm/processor.h> +#include <asm/macro.h> + + .global lowlevel_init + .text + .align 2 + +lowlevel_init: + + write32 CCR_A, CCR_D_D + + write32 MMUCR_A, MMUCR_D + + write32 BCR1_A, BCR1_D + + write16 BCR2_A, BCR2_D + + write16 BCR3_A, BCR3_D + + write32 BCR4_A, BCR4_D + + write32 WCR1_A, WCR1_D + + write32 WCR2_A, WCR2_D + + write32 WCR3_A, WCR3_D + + write16 PCR_A, PCR_D + + write16 LED_A, LED_D + + write32 MCR_A, MCR_D1 + + write16 RTCNT_A, RTCNT_D + + write16 RTCOR_A, RTCOR_D + + write16 RFCR_A, RFCR_D + + write16 RTCSR_A, RTCSR_D + + write8 SDMR3_A, SDMR3_D0 + + /* Wait DRAM refresh 30 times */ + mov.l RFCR_A, r1 + mov #30, r3 +1: + mov.w @r1, r0 + extu.w r0, r2 + cmp/hi r3, r2 + bf 1b + + write32 MCR_A, MCR_D2 + + write8 SDMR3_A, SDMR3_D1 + + write32 IRLMASK_A, IRLMASK_D + + write32 CCR_A, CCR_D_E + + rts + nop + + .align 2 +CCR_A: .long CCR /* Cache Control Register */ +CCR_D_D: .long 0x0808 /* Flush the cache, disable */ +CCR_D_E: .long 0x8000090B + +FRQCR_A: .long FRQCR /* FRQCR Address */ +FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */ +BCR1_A: .long BCR1 /* BCR1 Address */ +BCR1_D: .long 0x00180008 +BCR2_A: .long BCR2 /* BCR2 Address */ +BCR2_D: .long 0xabe8 +BCR3_A: .long BCR3 /* BCR3 Address */ +BCR3_D: .long 0x0000 +BCR4_A: .long BCR4 /* BCR4 Address */ +BCR4_D: .long 0x00000010 +WCR1_A: .long WCR1 /* WCR1 Address */ +WCR1_D: .long 0x33343333 +WCR2_A: .long WCR2 /* WCR2 Address */ +WCR2_D: .long 0xcff86fbf +WCR3_A: .long WCR3 /* WCR3 Address */ +WCR3_D: .long 0x07777707 +LED_A: .long 0x04000036 /* LED Address */ +LED_D: .long 0xFF /* LED Data */ +RTCNT_A: .long RTCNT /* RTCNT Address */ +RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ +.align 2 +RTCOR_A: .long RTCOR /* RTCOR Address */ +RTCOR_D: .word 0xA534 /* RTCOR Write Code */ +.align 2 +RTCSR_A: .long RTCSR /* RTCSR Address */ +RTCSR_D: .word 0xA510 /* RTCSR Write Code */ +.align 2 +SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ +SDMR3_D0: .long 0x55 +SDMR3_D1: .long 0x00 +MCR_A: .long MCR /* MCR Address */ +MCR_D1: .long 0x081901F4 /* MRSET:'0' */ +MCR_D2: .long 0x481901F4 /* MRSET:'1' */ +RFCR_A: .long RFCR /* RFCR Address */ +RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ +PCR_A: .long PCR /* PCR Address */ +PCR_D: .long 0x0000 +MMUCR_A: .long MMUCR /* MMUCCR Address */ +MMUCR_D: .long 0x00000000 /* MMUCCR Data */ +IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */ +IRLMASK_D: .long 0x00000000 /* IRLMASK Data */ diff --git a/u-boot/board/renesas/r2dplus/r2dplus.c b/u-boot/board/renesas/r2dplus/r2dplus.c new file mode 100644 index 0000000..b70395d --- /dev/null +++ b/u-boot/board/renesas/r2dplus/r2dplus.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2007,2008 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ide.h> +#include <netdev.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/pci.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("BOARD: Renesas Solutions R2D Plus\n"); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +#define FPGA_BASE 0xA4000000 +#define FPGA_CFCTL (FPGA_BASE + 0x04) +#define CFCTL_EN (0x432) +#define FPGA_CFPOW (FPGA_BASE + 0x06) +#define CFPOW_ON (0x02) +#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A) +#define CFCDINTCLR_EN (0x01) + +void ide_set_reset(int idereset) +{ + /* if reset = 1 IDE reset will be asserted */ + if (idereset) { + outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */ + outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */ + outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */ + } +} + +static struct pci_controller hose; +void pci_init_board(void) +{ + pci_sh7751_init(&hose); +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/u-boot/board/renesas/r7780mp/Makefile b/u-boot/board/renesas/r7780mp/Makefile new file mode 100644 index 0000000..14c5e42 --- /dev/null +++ b/u-boot/board/renesas/r7780mp/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2007,2008 Nobuhiro Iwamatsu +# +# board/r7780mp/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := r7780mp.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/u-boot/board/renesas/r7780mp/lowlevel_init.S b/u-boot/board/renesas/r7780mp/lowlevel_init.S new file mode 100644 index 0000000..bbea621 --- /dev/null +++ b/u-boot/board/renesas/r7780mp/lowlevel_init.S @@ -0,0 +1,371 @@ +/* + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu + * + * u-boot/board/r7780mp/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/processor.h> +#include <asm/macro.h> + +/* + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. + * + * (Note: As no stack is available, no subroutines can be called...). + */ + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + write32 CCR_A, CCR_D /* Address of Cache Control Register */ + /* Instruction Cache Invalidate */ + + write32 FRQCR_A, FRQCR_D /* Frequency control register */ + + /* pin_multi_setting */ + write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1 + + write32 BBG_PMSR1_A, BBG_PMSR1_D + + write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2 + + write32 BBG_PMSR2_A, BBG_PMSR2_D + + write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3 + + write32 BBG_PMSR3_A, BBG_PMSR3_D + + write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4 + + write32 BBG_PMSR4_A, BBG_PMSR4_D + + write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG + + write32 BBG_PMSRG_A, BBG_PMSRG_D + + /* cpg_setting */ + write32 FRQCR_A, FRQCR_D + + write32 DLLCSR_A, DLLCSR_D + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + /* wait 200us */ + mov.l REPEAT0_R3, r3 + mov #0, r2 +repeat0: + add #1, r2 + cmp/hs r3, r2 + bf repeat0 + nop + + /* bsc_setting */ + write32 MMSELR_A, MMSELR_D + + write32 BCR_A, BCR_D + + write32 CS0BCR_A, CS0BCR_D + + write32 CS1BCR_A, CS1BCR_D + + write32 CS2BCR_A, CS2BCR_D + + write32 CS4BCR_A, CS4BCR_D + + write32 CS5BCR_A, CS5BCR_D + + write32 CS6BCR_A, CS6BCR_D + + write32 CS0WCR_A, CS0WCR_D + + write32 CS1WCR_A, CS1WCR_D + + write32 CS2WCR_A, CS2WCR_D + + write32 CS4WCR_A, CS4WCR_D + + write32 CS5WCR_A, CS5WCR_D + + write32 CS6WCR_A, CS6WCR_D + + write32 CS5PCR_A, CS5PCR_D + + write32 CS6PCR_A, CS6PCR_D + + /* ddr_setting */ + /* wait 200us */ + mov.l REPEAT0_R3, r3 + mov #0, r2 +repeat1: + add #1, r2 + cmp/hs r3, r2 + bf repeat1 + nop + + mov.l MIM_U_A, r0 + mov.l MIM_U_D, r1 + synco + mov.l r1, @r0 + synco + + mov.l MIM_L_A, r0 + mov.l MIM_L_D0, r1 + synco + mov.l r1, @r0 + synco + + mov.l STR_L_A, r0 + mov.l STR_L_D, r1 + synco + mov.l r1, @r0 + synco + + mov.l SDR_L_A, r0 + mov.l SDR_L_D, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + nop + + mov.l SCR_L_A, r0 + mov.l SCR_L_D0, r1 + synco + mov.l r1, @r0 + synco + + mov.l SCR_L_A, r0 + mov.l SCR_L_D1, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l EMRS_A, r0 + mov.l EMRS_D, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l MRS1_A, r0 + mov.l MRS1_D, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l SCR_L_A, r0 + mov.l SCR_L_D2, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l SCR_L_A, r0 + mov.l SCR_L_D3, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l SCR_L_A, r0 + mov.l SCR_L_D4, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l MRS2_A, r0 + mov.l MRS2_D, r1 + synco + mov.l r1, @r0 + synco + + nop + nop + nop + + mov.l SCR_L_A, r0 + mov.l SCR_L_D5, r1 + synco + mov.l r1, @r0 + synco + + /* wait 200us */ + mov.l REPEAT0_R1, r3 + mov #0, r2 +repeat2: + add #1, r2 + cmp/hs r3, r2 + bf repeat2 + + synco + + mov.l MIM_L_A, r0 + mov.l MIM_L_D1, r1 + synco + mov.l r1, @r0 + synco + + rts + nop + .align 4 + +RWTCSR_D_1: .word 0xA507 +RWTCSR_D_2: .word 0xA507 +RWTCNT_D: .word 0x5A00 + .align 2 + +BBG_PMMR_A: .long 0xFF800010 +BBG_PMSR1_A: .long 0xFF800014 +BBG_PMSR2_A: .long 0xFF800018 +BBG_PMSR3_A: .long 0xFF80001C +BBG_PMSR4_A: .long 0xFF800020 +BBG_PMSRG_A: .long 0xFF800024 + +BBG_PMMR_D_PMSR1: .long 0xffffbffd +BBG_PMSR1_D: .long 0x00004002 +BBG_PMMR_D_PMSR2: .long 0xfc21a7ff +BBG_PMSR2_D: .long 0x03de5800 +BBG_PMMR_D_PMSR3: .long 0xfffffff8 +BBG_PMSR3_D: .long 0x00000007 +BBG_PMMR_D_PMSR4: .long 0xdffdfff9 +BBG_PMSR4_D: .long 0x20020006 +BBG_PMMR_D_PMSRG: .long 0xffffffff +BBG_PMSRG_D: .long 0x00000000 + +FRQCR_A: .long FRQCR +DLLCSR_A: .long 0xffc40010 +FRQCR_D: .long 0x40233035 +DLLCSR_D: .long 0x00000000 + +/* for DDR-SDRAM */ +MIM_U_A: .long MIM_1 +MIM_L_A: .long MIM_2 +SCR_U_A: .long SCR_1 +SCR_L_A: .long SCR_2 +STR_U_A: .long STR_1 +STR_L_A: .long STR_2 +SDR_U_A: .long SDR_1 +SDR_L_A: .long SDR_2 + +EMRS_A: .long 0xFEC02000 +MRS1_A: .long 0xFEC00B08 +MRS2_A: .long 0xFEC00308 + +MIM_U_D: .long 0x00004000 +MIM_L_D0: .long 0x03e80009 +MIM_L_D1: .long 0x03e80209 +SCR_L_D0: .long 0x3 +SCR_L_D1: .long 0x2 +SCR_L_D2: .long 0x2 +SCR_L_D3: .long 0x4 +SCR_L_D4: .long 0x4 +SCR_L_D5: .long 0x0 +STR_L_D: .long 0x000f0000 +SDR_L_D: .long 0x00000400 +EMRS_D: .long 0x0 +MRS1_D: .long 0x0 +MRS2_D: .long 0x0 + +/* Cache Controller */ +CCR_A: .long CCR +MMUCR_A: .long MMUCR +RWTCNT_A: .long WTCNT + +CCR_D: .long 0x0000090b +CCR_D_2: .long 0x00000103 +MMUCR_D: .long 0x00000004 +MSTPCR0_D: .long 0x00001001 +MSTPCR2_D: .long 0xffffffff + +/* local Bus State Controller */ +MMSELR_A: .long MMSELR +BCR_A: .long BCR +CS0BCR_A: .long CS0BCR +CS1BCR_A: .long CS1BCR +CS2BCR_A: .long CS2BCR +CS4BCR_A: .long CS4BCR +CS5BCR_A: .long CS5BCR +CS6BCR_A: .long CS6BCR +CS0WCR_A: .long CS0WCR +CS1WCR_A: .long CS1WCR +CS2WCR_A: .long CS2WCR +CS4WCR_A: .long CS4WCR +CS5WCR_A: .long CS5WCR +CS6WCR_A: .long CS6WCR +CS5PCR_A: .long CS5PCR +CS6PCR_A: .long CS6PCR + +MMSELR_D: .long 0xA5A50003 +BCR_D: .long 0x00000000 +CS0BCR_D: .long 0x77777770 +CS1BCR_D: .long 0x77777670 +CS2BCR_D: .long 0x77777770 +CS4BCR_D: .long 0x77777770 +CS5BCR_D: .long 0x77777670 +CS6BCR_D: .long 0x77777770 +CS0WCR_D: .long 0x00020006 +CS1WCR_D: .long 0x00232304 +CS2WCR_D: .long 0x7777770F +CS4WCR_D: .long 0x7777770F +CS5WCR_D: .long 0x00101006 +CS6WCR_D: .long 0x77777703 +CS5PCR_D: .long 0x77000000 +CS6PCR_D: .long 0x77000000 + +REPEAT0_R3: .long 0x00002000 +REPEAT0_R1: .long 0x0000200 diff --git a/u-boot/board/renesas/r7780mp/r7780mp.c b/u-boot/board/renesas/r7780mp/r7780mp.c new file mode 100644 index 0000000..0b80099 --- /dev/null +++ b/u-boot/board/renesas/r7780mp/r7780mp.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ide.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <netdev.h> +#include "r7780mp.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ +#if defined(CONFIG_R7780MP) + puts("BOARD: Renesas Solutions R7780MP\n"); +#else + puts("BOARD: Renesas Solutions R7780RP\n"); +#endif + return 0; +} + +int board_init(void) +{ + /* SCIF Enable */ + writew(0x0, PHCR); + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state(unsigned short value) +{ + +} + +void ide_set_reset(int idereset) +{ + /* if reset = 1 IDE reset will be asserted */ + if (idereset) { + writew(0x432, FPGA_CFCTL); +#if defined(CONFIG_R7780MP) + writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW); +#else + writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW); +#endif + writew(0x01, FPGA_CFCDINTCLR); + } +} + +static struct pci_controller hose; +void pci_init_board(void) +{ + pci_sh7780_init(&hose); +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/u-boot/board/renesas/r7780mp/r7780mp.h b/u-boot/board/renesas/r7780mp/r7780mp.h new file mode 100644 index 0000000..476a413 --- /dev/null +++ b/u-boot/board/renesas/r7780mp/r7780mp.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2007 Nobuhiro Iwamatsu + * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> + * + * u-boot/board/r7780mp/r7780mp.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BOARD_R7780MP_R7780MP_H_ +#define _BOARD_R7780MP_R7780MP_H_ + +/* R7780MP's FPGA register map */ +#define FPGA_BASE 0xa4000000 +#define FPGA_IRLMSK (FPGA_BASE + 0x00) +#define FPGA_IRLMON (FPGA_BASE + 0x02) +#define FPGA_IRLPRI1 (FPGA_BASE + 0x04) +#define FPGA_IRLPRI2 (FPGA_BASE + 0x06) +#define FPGA_IRLPRI3 (FPGA_BASE + 0x08) +#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A) +#define FPGA_RSTCTL (FPGA_BASE + 0x0C) +#define FPGA_PCIBD (FPGA_BASE + 0x0E) +#define FPGA_PCICD (FPGA_BASE + 0x10) +#define FPGA_EXTGIO (FPGA_BASE + 0x16) +#define FPGA_IVDRMON (FPGA_BASE + 0x18) +#define FPGA_IVDRCR (FPGA_BASE + 0x1A) +#define FPGA_OBLED (FPGA_BASE + 0x1C) +#define FPGA_OBSW (FPGA_BASE + 0x1E) +#define FPGA_TPCTL (FPGA_BASE + 0x100) +#define FPGA_TPDCKCTL (FPGA_BASE + 0x102) +#define FPGA_TPCLR (FPGA_BASE + 0x104) +#define FPGA_TPXPOS (FPGA_BASE + 0x106) +#define FPGA_TPYPOS (FPGA_BASE + 0x108) +#define FPGA_DBSW (FPGA_BASE + 0x200) +#define FPGA_VERSION (FPGA_BASE + 0x700) +#define FPGA_CFCTL (FPGA_BASE + 0x300) +#define FPGA_CFPOW (FPGA_BASE + 0x302) +#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304) +#define FPGA_PMR (FPGA_BASE + 0x900) + +#endif /* _BOARD_R7780RP_R7780RP_H_ */ diff --git a/u-boot/board/renesas/rsk7203/Makefile b/u-boot/board/renesas/rsk7203/Makefile new file mode 100644 index 0000000..f908ba0 --- /dev/null +++ b/u-boot/board/renesas/rsk7203/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2007,2008 Nobuhiro Iwamatsu +# Copyright (C) 2008 Renesas Solutions Corp. +# +# u-boot/board/rsk7203/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).o + +OBJS := rsk7203.o +SOBJS := lowlevel_init.o + +LIB := $(addprefix $(obj),$(LIB)) +OBJS := $(addprefix $(obj),$(OBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/u-boot/board/renesas/rsk7203/lowlevel_init.S b/u-boot/board/renesas/rsk7203/lowlevel_init.S new file mode 100644 index 0000000..30ef5ab --- /dev/null +++ b/u-boot/board/renesas/rsk7203/lowlevel_init.S @@ -0,0 +1,213 @@ +/* + * Copyright (C) 2008 Nobuhiro Iwamatsu + * Copyright (C) 2008 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <version.h> + +#include <asm/processor.h> +#include <asm/macro.h> + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + /* Cache setting */ + write32 CCR1_A ,CCR1_D + + /* ConfigurePortPins */ + write16 PECRL3_A, PECRL3_D + + write16 PCCRL4_A, PCCRL4_D0 + + write16 PECRL4_A, PECRL4_D0 + + write16 PEIORL_A, PEIORL_D0 + + write16 PCIORL_A, PCIORL_D + + write16 PFCRH2_A, PFCRH2_D + + write16 PFCRH3_A, PFCRH3_D + + write16 PFCRH1_A, PFCRH1_D + + write16 PFIORH_A, PFIORH_D + + write16 PECRL1_A, PECRL1_D0 + + write16 PEIORL_A, PEIORL_D1 + + /* Configure Operating Frequency */ + write16 WTCSR_A, WTCSR_D0 + + write16 WTCSR_A, WTCSR_D1 + + write16 WTCNT_A, WTCNT_D + + /* Set clock mode*/ + write16 FRQCR_A, FRQCR_D + + /* Configure Bus And Memory */ +init_bsc_cs0: + write16 PCCRL4_A, PCCRL4_D1 + + write16 PECRL1_A, PECRL1_D1 + + write32 CMNCR_A, CMNCR_D + + write32 CS0BCR_A, CS0BCR_D + + write32 CS0WCR_A, CS0WCR_D + +init_bsc_cs1: + write16 PECRL4_A, PECRL4_D1 + + write32 CS1WCR_A, CS1WCR_D + +init_sdram: + write16 PCCRL2_A, PCCRL2_D + + write16 PCCRL4_A, PCCRL4_D2 + + write16 PCCRL1_A, PCCRL1_D + + write16 PCCRL3_A, PCCRL3_D + + write32 CS3BCR_A, CS3BCR_D + + write32 CS3WCR_A, CS3WCR_D + + write32 SDCR_A, SDCR_D + + write32 RTCOR_A, RTCOR_D + + write32 RTCSR_A, RTCSR_D + + /* wait 200us */ + mov.l REPEAT_D, r3 + mov #0, r2 +repeat0: + add #1, r2 + cmp/hs r3, r2 + bf repeat0 + nop + + mov.l SDRAM_MODE, r1 + mov #0, r0 + mov.l r0, @r1 + + nop + rts + + .align 4 + +CCR1_A: .long CCR1 +CCR1_D: .long 0x0000090B +PCCRL4_A: .long 0xFFFE3910 +PCCRL4_D0: .word 0x0000 +.align 2 +PECRL4_A: .long 0xFFFE3A10 +PECRL4_D0: .word 0x0000 +.align 2 +PECRL3_A: .long 0xFFFE3A12 +PECRL3_D: .word 0x0000 +.align 2 +PEIORL_A: .long 0xFFFE3A06 +PEIORL_D0: .word 0x1C00 +PEIORL_D1: .word 0x1C02 +PCIORL_A: .long 0xFFFE3906 +PCIORL_D: .word 0x4000 +.align 2 +PFCRH2_A: .long 0xFFFE3A8C +PFCRH2_D: .word 0x0000 +.align 2 +PFCRH3_A: .long 0xFFFE3A8A +PFCRH3_D: .word 0x0000 +.align 2 +PFCRH1_A: .long 0xFFFE3A8E +PFCRH1_D: .word 0x0000 +.align 2 +PFIORH_A: .long 0xFFFE3A84 +PFIORH_D: .word 0x0729 +.align 2 +PECRL1_A: .long 0xFFFE3A16 +PECRL1_D0: .word 0x0033 +.align 2 + + +WTCSR_A: .long 0xFFFE0000 +WTCSR_D0: .word 0xA518 +WTCSR_D1: .word 0xA51D +WTCNT_A: .long 0xFFFE0002 +WTCNT_D: .word 0x5A84 +.align 2 +FRQCR_A: .long 0xFFFE0010 +FRQCR_D: .word 0x0104 +.align 2 + +PCCRL4_D1: .word 0x0010 +PECRL1_D1: .word 0x0133 + +CMNCR_A: .long 0xFFFC0000 +CMNCR_D: .long 0x00001810 +CS0BCR_A: .long 0xFFFC0004 +CS0BCR_D: .long 0x10000400 +CS0WCR_A: .long 0xFFFC0028 +CS0WCR_D: .long 0x00000B41 +PECRL4_D1: .word 0x0100 +.align 2 +CS1WCR_A: .long 0xFFFC002C +CS1WCR_D: .long 0x00000B01 +PCCRL4_D2: .word 0x0011 +.align 2 +PCCRL3_A: .long 0xFFFE3912 +PCCRL3_D: .word 0x0011 +.align 2 +PCCRL2_A: .long 0xFFFE3914 +PCCRL2_D: .word 0x1111 +.align 2 +PCCRL1_A: .long 0xFFFE3916 +PCCRL1_D: .word 0x1010 +PDCRL4_A: .long 0xFFFE3990 +PDCRL4_D: .word 0x0011 +.align 2 +PDCRL3_A: .long 0xFFFE3992 +PDCRL3_D: .word 0x00011 +.align 2 +PDCRL2_A: .long 0xFFFE3994 +PDCRL2_D: .word 0x1111 +.align 2 +PDCRL1_A: .long 0xFFFE3996 +PDCRL1_D: .word 0x1000 +.align 2 +CS3BCR_A: .long 0xFFFC0010 +CS3BCR_D: .long 0x00004400 +CS3WCR_A: .long 0xFFFC0034 +CS3WCR_D: .long 0x00002892 +SDCR_A: .long 0xFFFC004C +SDCR_D: .long 0x00000809 +RTCOR_A: .long 0xFFFC0058 +RTCOR_D: .long 0xA55A0041 +RTCSR_A: .long 0xFFFC0050 +RTCSR_D: .long 0xa55a0010 + +SDRAM_MODE: .long 0xFFFC5040 +REPEAT_D: .long 0x00009C40 diff --git a/u-boot/board/renesas/rsk7203/rsk7203.c b/u-boot/board/renesas/rsk7203/rsk7203.c new file mode 100644 index 0000000..06552c0 --- /dev/null +++ b/u-boot/board/renesas/rsk7203/rsk7203.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2008 Nobuhiro Iwamatsu + * Copyright (C) 2008 Renesas Solutions Corp. + * + * u-boot/board/rsk7203/rsk7203.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <net.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("BOARD: Renesas Technology RSK7203\n"); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state(unsigned short value) +{ +} + +/* + * The RSK board has the SMSC9118 wired up 'incorrectly'. + * Byte-swapping is necessary, and so poor performance is inevitable. + * This problem cannot evade by the swap function of CHIP, this can + * evade by software Byte-swapping. + * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push + * functions necessary to solve this problem. + */ +u32 pkt_data_pull(struct eth_device *dev, u32 addr) +{ + volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); + return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\ + | swab16(*(addr_16 + 1)); +} + +void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) +{ + addr += dev->iobase; + *(volatile u16 *)(addr + 2) = swab16((u16)val); + *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/u-boot/board/renesas/sh7757lcr/Makefile b/u-boot/board/renesas/sh7757lcr/Makefile new file mode 100644 index 0000000..e2e46ba --- /dev/null +++ b/u-boot/board/renesas/sh7757lcr/Makefile @@ -0,0 +1,43 @@ +# +# Copyright (C) 2011 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := sh7757lcr.o spi-boot.o +SOBJS := lowlevel_init.o + +$(LIB): $(obj).depend $(COBJS) $(SOBJS) + $(call cmd_link_o_target, $(COBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/u-boot/board/renesas/sh7757lcr/lowlevel_init.S b/u-boot/board/renesas/sh7757lcr/lowlevel_init.S new file mode 100644 index 0000000..ab1aa49 --- /dev/null +++ b/u-boot/board/renesas/sh7757lcr/lowlevel_init.S @@ -0,0 +1,558 @@ +/* + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/processor.h> +#include <asm/macro.h> + +.macro or32, addr, data + mov.l \addr, r1 + mov.l \data, r0 + mov.l @r1, r2 + or r2, r0 + mov.l r0, @r1 +.endm + +.macro wait_DBCMD + mov.l DBWAIT_A, r0 + mov.l @r0, r1 +.endm + + .global lowlevel_init + .section .spiboot1.text + .align 2 + +lowlevel_init: + + /*------- GPIO -------*/ + write8 PGDR_A, PGDR_D /* eMMC power off */ + + write16 PACR_A, PACR_D + write16 PBCR_A, PBCR_D + write16 PCCR_A, PCCR_D + write16 PDCR_A, PDCR_D + write16 PECR_A, PECR_D + write16 PFCR_A, PFCR_D + write16 PGCR_A, PGCR_D + write16 PHCR_A, PHCR_D + write16 PICR_A, PICR_D + write16 PJCR_A, PJCR_D + write16 PKCR_A, PKCR_D + write16 PLCR_A, PLCR_D + write16 PMCR_A, PMCR_D + write16 PNCR_A, PNCR_D + write16 POCR_A, POCR_D + write16 PQCR_A, PQCR_D + write16 PRCR_A, PRCR_D + write16 PSCR_A, PSCR_D + write16 PTCR_A, PTCR_D + write16 PUCR_A, PUCR_D + write16 PVCR_A, PVCR_D + write16 PWCR_A, PWCR_D + write16 PXCR_A, PXCR_D + write16 PYCR_A, PYCR_D + write16 PZCR_A, PZCR_D + write16 PSEL0_A, PSEL0_D + write16 PSEL1_A, PSEL1_D + write16 PSEL2_A, PSEL2_D + write16 PSEL3_A, PSEL3_D + write16 PSEL4_A, PSEL4_D + write16 PSEL5_A, PSEL5_D + write16 PSEL6_A, PSEL6_D + write16 PSEL7_A, PSEL7_D + write16 PSEL8_A, PSEL8_D + + bra exit_gpio + nop + + .align 4 + +/*------- GPIO -------*/ +PGDR_A: .long 0xffec0040 +PACR_A: .long 0xffec0000 +PBCR_A: .long 0xffec0002 +PCCR_A: .long 0xffec0004 +PDCR_A: .long 0xffec0006 +PECR_A: .long 0xffec0008 +PFCR_A: .long 0xffec000a +PGCR_A: .long 0xffec000c +PHCR_A: .long 0xffec000e +PICR_A: .long 0xffec0010 +PJCR_A: .long 0xffec0012 +PKCR_A: .long 0xffec0014 +PLCR_A: .long 0xffec0016 +PMCR_A: .long 0xffec0018 +PNCR_A: .long 0xffec001a +POCR_A: .long 0xffec001c +PQCR_A: .long 0xffec0020 +PRCR_A: .long 0xffec0022 +PSCR_A: .long 0xffec0024 +PTCR_A: .long 0xffec0026 +PUCR_A: .long 0xffec0028 +PVCR_A: .long 0xffec002a +PWCR_A: .long 0xffec002c +PXCR_A: .long 0xffec002e +PYCR_A: .long 0xffec0030 +PZCR_A: .long 0xffec0032 +PSEL0_A: .long 0xffec0070 +PSEL1_A: .long 0xffec0072 +PSEL2_A: .long 0xffec0074 +PSEL3_A: .long 0xffec0076 +PSEL4_A: .long 0xffec0078 +PSEL5_A: .long 0xffec007a +PSEL6_A: .long 0xffec007c +PSEL7_A: .long 0xffec0082 +PSEL8_A: .long 0xffec0084 + +PGDR_D: .long 0x80 +PACR_D: .long 0x0000 +PBCR_D: .long 0x0001 +PCCR_D: .long 0x0000 +PDCR_D: .long 0x0000 +PECR_D: .long 0x0000 +PFCR_D: .long 0x0000 +PGCR_D: .long 0x0000 +PHCR_D: .long 0x0000 +PICR_D: .long 0x0000 +PJCR_D: .long 0x0000 +PKCR_D: .long 0x0003 +PLCR_D: .long 0x0000 +PMCR_D: .long 0x0000 +PNCR_D: .long 0x0000 +POCR_D: .long 0x0000 +PQCR_D: .long 0xc000 +PRCR_D: .long 0x0000 +PSCR_D: .long 0x0000 +PTCR_D: .long 0x0000 +#if defined(CONFIG_SH7757_OFFSET_SPI) +PUCR_D: .long 0x0055 +#else +PUCR_D: .long 0x0000 +#endif +PVCR_D: .long 0x0000 +PWCR_D: .long 0x0000 +PXCR_D: .long 0x0000 +PYCR_D: .long 0x0000 +PZCR_D: .long 0x0000 +PSEL0_D: .long 0xfe00 +PSEL1_D: .long 0x0000 +PSEL2_D: .long 0x3000 +PSEL3_D: .long 0xff00 +PSEL4_D: .long 0x771f +PSEL5_D: .long 0x0ffc +PSEL6_D: .long 0x00ff +PSEL7_D: .long 0xfc00 +PSEL8_D: .long 0x0000 + + .align 2 + +exit_gpio: + mov #0, r14 + mova 2f, r0 + mov.l PC_MASK, r1 + tst r0, r1 + bf 2f + + bra exit_pmb + nop + + .align 2 + +/* If CPU runs on SDRAM, PC is 0x8???????. */ +PC_MASK: .long 0x20000000 + +2: + mov #1, r14 + + mov.l EXPEVT_A, r0 + mov.l @r0, r0 + mov.l EXPEVT_POWER_ON_RESET, r1 + cmp/eq r0, r1 + bt 1f + + /* + * If EXPEVT value is manual reset or tlb multipul-hit, + * initialization of DDR3IF is not necessary. + */ + bra exit_ddr + nop + +1: + /* For Core Reset */ + mov.l DBACEN_A, r0 + mov.l @r0, r0 + cmp/eq #0, r0 + bt 3f + + /* + * If DBACEN == 1(DBSC was already enabled), we have to avoid the + * initialization of DDR3-SDRAM. + */ + bra exit_ddr + nop + +3: + /*------- DDR3IF -------*/ + /* oscillation stabilization time */ + wait_timer WAIT_OSC_TIME + + /* step 3 */ + write32 DBCMD_A, DBCMD_RSTL_VAL + wait_timer WAIT_30US + + /* step 4 */ + write32 DBCMD_A, DBCMD_PDEN_VAL + + /* step 5 */ + write32 DBKIND_A, DBKIND_D + + /* step 6 */ + write32 DBCONF_A, DBCONF_D + write32 DBTR0_A, DBTR0_D + write32 DBTR1_A, DBTR1_D + write32 DBTR2_A, DBTR2_D + write32 DBTR3_A, DBTR3_D + write32 DBTR4_A, DBTR4_D + write32 DBTR5_A, DBTR5_D + write32 DBTR6_A, DBTR6_D + write32 DBTR7_A, DBTR7_D + write32 DBTR8_A, DBTR8_D + write32 DBTR9_A, DBTR9_D + write32 DBTR10_A, DBTR10_D + write32 DBTR11_A, DBTR11_D + write32 DBTR12_A, DBTR12_D + write32 DBTR13_A, DBTR13_D + write32 DBTR14_A, DBTR14_D + write32 DBTR15_A, DBTR15_D + write32 DBTR16_A, DBTR16_D + write32 DBTR17_A, DBTR17_D + write32 DBTR18_A, DBTR18_D + write32 DBTR19_A, DBTR19_D + write32 DBRNK0_A, DBRNK0_D + + /* step 7 */ + write32 DBPDCNT3_A, DBPDCNT3_D + + /* step 8 */ + write32 DBPDCNT1_A, DBPDCNT1_D + write32 DBPDCNT2_A, DBPDCNT2_D + write32 DBPDLCK_A, DBPDLCK_D + write32 DBPDRGA_A, DBPDRGA_D + write32 DBPDRGD_A, DBPDRGD_D + + /* step 9 */ + wait_timer WAIT_30US + + /* step 10 */ + write32 DBPDCNT0_A, DBPDCNT0_D + + /* step 11 */ + wait_timer WAIT_30US + wait_timer WAIT_30US + + /* step 12 */ + write32 DBCMD_A, DBCMD_WAIT_VAL + wait_DBCMD + + /* step 13 */ + write32 DBCMD_A, DBCMD_RSTH_VAL + wait_DBCMD + + /* step 14 */ + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + + /* step 15 */ + write32 DBCMD_A, DBCMD_PDXT_VAL + + /* step 16 */ + write32 DBCMD_A, DBCMD_MRS2_VAL + + /* step 17 */ + write32 DBCMD_A, DBCMD_MRS3_VAL + + /* step 18 */ + write32 DBCMD_A, DBCMD_MRS1_VAL + + /* step 19 */ + write32 DBCMD_A, DBCMD_MRS0_VAL + + /* step 20 */ + write32 DBCMD_A, DBCMD_ZQCL_VAL + + write32 DBCMD_A, DBCMD_REF_VAL + write32 DBCMD_A, DBCMD_REF_VAL + wait_DBCMD + + /* step 21 */ + write32 DBADJ0_A, DBADJ0_D + write32 DBADJ1_A, DBADJ1_D + write32 DBADJ2_A, DBADJ2_D + + /* step 22 */ + write32 DBRFCNF0_A, DBRFCNF0_D + write32 DBRFCNF1_A, DBRFCNF1_D + write32 DBRFCNF2_A, DBRFCNF2_D + + /* step 23 */ + write32 DBCALCNF_A, DBCALCNF_D + + /* step 24 */ + write32 DBRFEN_A, DBRFEN_D + write32 DBCMD_A, DBCMD_SRXT_VAL + + /* step 25 */ + write32 DBACEN_A, DBACEN_D + + /* step 26 */ + wait_DBCMD + + /* enable DDR-ECC */ + write32 ECD_ECDEN_A, ECD_ECDEN_D + write32 ECD_INTSR_A, ECD_INTSR_D + write32 ECD_SPACER_A, ECD_SPACER_D + write32 ECD_MCR_A, ECD_MCR_D + + bra exit_ddr + nop + + .align 4 + +EXPEVT_A: .long 0xff000024 +EXPEVT_POWER_ON_RESET: .long 0x00000000 + +/*------- DDR3IF -------*/ +DBCMD_A: .long 0xfe800018 +DBKIND_A: .long 0xfe800020 +DBCONF_A: .long 0xfe800024 +DBTR0_A: .long 0xfe800040 +DBTR1_A: .long 0xfe800044 +DBTR2_A: .long 0xfe800048 +DBTR3_A: .long 0xfe800050 +DBTR4_A: .long 0xfe800054 +DBTR5_A: .long 0xfe800058 +DBTR6_A: .long 0xfe80005c +DBTR7_A: .long 0xfe800060 +DBTR8_A: .long 0xfe800064 +DBTR9_A: .long 0xfe800068 +DBTR10_A: .long 0xfe80006c +DBTR11_A: .long 0xfe800070 +DBTR12_A: .long 0xfe800074 +DBTR13_A: .long 0xfe800078 +DBTR14_A: .long 0xfe80007c +DBTR15_A: .long 0xfe800080 +DBTR16_A: .long 0xfe800084 +DBTR17_A: .long 0xfe800088 +DBTR18_A: .long 0xfe80008c +DBTR19_A: .long 0xfe800090 +DBRNK0_A: .long 0xfe800100 +DBPDCNT0_A: .long 0xfe800200 +DBPDCNT1_A: .long 0xfe800204 +DBPDCNT2_A: .long 0xfe800208 +DBPDCNT3_A: .long 0xfe80020c +DBPDLCK_A: .long 0xfe800280 +DBPDRGA_A: .long 0xfe800290 +DBPDRGD_A: .long 0xfe8002a0 +DBADJ0_A: .long 0xfe8000c0 +DBADJ1_A: .long 0xfe8000c4 +DBADJ2_A: .long 0xfe8000c8 +DBRFCNF0_A: .long 0xfe8000e0 +DBRFCNF1_A: .long 0xfe8000e4 +DBRFCNF2_A: .long 0xfe8000e8 +DBCALCNF_A: .long 0xfe8000f4 +DBRFEN_A: .long 0xfe800014 +DBACEN_A: .long 0xfe800010 +DBWAIT_A: .long 0xfe80001c + +WAIT_OSC_TIME: .long 6000 +WAIT_30US: .long 13333 + +DBCMD_RSTL_VAL: .long 0x20000000 +DBCMD_PDEN_VAL: .long 0x1000d73c +DBCMD_WAIT_VAL: .long 0x0000d73c +DBCMD_RSTH_VAL: .long 0x2100d73c +DBCMD_PDXT_VAL: .long 0x110000c8 +DBCMD_MRS0_VAL: .long 0x28000930 +DBCMD_MRS1_VAL: .long 0x29000004 +DBCMD_MRS2_VAL: .long 0x2a000008 +DBCMD_MRS3_VAL: .long 0x2b000000 +DBCMD_ZQCL_VAL: .long 0x03000200 +DBCMD_REF_VAL: .long 0x0c000000 +DBCMD_SRXT_VAL: .long 0x19000000 +DBKIND_D: .long 0x00000007 +DBCONF_D: .long 0x0f030a01 +DBTR0_D: .long 0x00000007 +DBTR1_D: .long 0x00000006 +DBTR2_D: .long 0x00000000 +DBTR3_D: .long 0x00000007 +DBTR4_D: .long 0x00070007 +DBTR5_D: .long 0x0000001b +DBTR6_D: .long 0x00000014 +DBTR7_D: .long 0x00000005 +DBTR8_D: .long 0x00000015 +DBTR9_D: .long 0x00000006 +DBTR10_D: .long 0x00000008 +DBTR11_D: .long 0x00000007 +DBTR12_D: .long 0x0000000e +DBTR13_D: .long 0x00000056 +DBTR14_D: .long 0x00000006 +DBTR15_D: .long 0x00000004 +DBTR16_D: .long 0x00150002 +DBTR17_D: .long 0x000c0017 +DBTR18_D: .long 0x00000200 +DBTR19_D: .long 0x00000040 +DBRNK0_D: .long 0x00000001 +DBPDCNT0_D: .long 0x00000001 +DBPDCNT1_D: .long 0x00000001 +DBPDCNT2_D: .long 0x00000000 +DBPDCNT3_D: .long 0x00004010 +DBPDLCK_D: .long 0x0000a55a +DBPDRGA_D: .long 0x00000028 +DBPDRGD_D: .long 0x00017100 + +DBADJ0_D: .long 0x00000000 +DBADJ1_D: .long 0x00000000 +DBADJ2_D: .long 0x18061806 +DBRFCNF0_D: .long 0x000001ff +DBRFCNF1_D: .long 0x08001000 +DBRFCNF2_D: .long 0x00000000 +DBCALCNF_D: .long 0x0000ffff +DBRFEN_D: .long 0x00000001 +DBACEN_D: .long 0x00000001 + +/*------- DDR-ECC -------*/ +ECD_ECDEN_A: .long 0xffc1012c +ECD_ECDEN_D: .long 0x00000001 +ECD_INTSR_A: .long 0xfe900024 +ECD_INTSR_D: .long 0xffffffff +ECD_SPACER_A: .long 0xfe900018 +ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING +ECD_MCR_A: .long 0xfe900010 +ECD_MCR_D: .long 0x00000001 + + .align 2 +exit_ddr: + +#if defined(CONFIG_SH_32BIT) + /*------- set PMB -------*/ + write32 PASCR_A, PASCR_29BIT_D + write32 MMUCR_A, MMUCR_D + + /***************************************************************** + * ent virt phys v sz c wt + * 0 0xa0000000 0x00000000 1 128M 0 1 + * 1 0xa8000000 0x48000000 1 128M 0 1 + * 5 0x88000000 0x48000000 1 128M 1 1 + */ + write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D + write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D + write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D + write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D + write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D + write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D + + write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D + + write32 PASCR_A, PASCR_INIT + mov.l DUMMY_ADDR, r0 + icbi @r0 +#endif /* if defined(CONFIG_SH_32BIT) */ + +exit_pmb: + /* CPU is running on ILRAM? */ + mov r14, r0 + tst #1, r0 + bt 1f + + mov.l _bss_start, r15 + mov.l _spiboot_main, r0 +100: bsrf r0 + nop + + .align 2 +_spiboot_main: .long (spiboot_main - (100b + 4)) +_bss_start: .long bss_start + +1: + + write32 CCR_A, CCR_D + + rts + nop + + .align 4 + +#if defined(CONFIG_SH_32BIT) +/*------- set PMB -------*/ +PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) +PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) +PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) +PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) +PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) +PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) +PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) +PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) +PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) +PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) +PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) +PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) +PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) +PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) +PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) +PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) + +PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) +PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) +PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) +PMB_ADDR_NOT_USE_D: .long 0x00000000 + +PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) +PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) +PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) + +/* ppn ub v s1 s0 c wt */ +PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) +PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) + +PASCR_A: .long 0xff000070 +DUMMY_ADDR: .long 0xa0000000 +PASCR_29BIT_D: .long 0x00000000 +PASCR_INIT: .long 0x80000080 +MMUCR_A: .long 0xff000010 +MMUCR_D: .long 0x00000004 /* clear ITLB */ +#endif /* CONFIG_SH_32BIT */ + +CCR_A: .long CCR +CCR_D: .long CCR_CACHE_INIT diff --git a/u-boot/board/renesas/sh7757lcr/sh7757lcr.c b/u-boot/board/renesas/sh7757lcr/sh7757lcr.c new file mode 100644 index 0000000..a62be24 --- /dev/null +++ b/u-boot/board/renesas/sh7757lcr/sh7757lcr.c @@ -0,0 +1,454 @@ +/* + * Copyright (C) 2011 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <spi_flash.h> + +int checkboard(void) +{ + puts("BOARD: R0P7757LC0030RL board\n"); + + return 0; +} + +static void init_gctrl(void) +{ + struct gctrl_regs *gctrl = GCTRL_BASE; + unsigned long graofst; + + graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; + writel(graofst | 0x20000f00, &gctrl->gracr3); +} + +static int init_pcie_bridge_from_spi(void *buf, size_t size) +{ + struct spi_flash *spi; + int ret; + unsigned long pcie_addr; + + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!spi) { + printf("%s: spi_flash probe error.\n", __func__); + return 1; + } + + if (is_sh7757_b0()) + pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0; + else + pcie_addr = SH7757LCR_PCIEBRG_ADDR; + + ret = spi_flash_read(spi, pcie_addr, size, buf); + if (ret) { + printf("%s: spi_flash read error.\n", __func__); + spi_flash_free(spi); + return 1; + } + spi_flash_free(spi); + + return 0; +} + +static void init_pcie_bridge(void) +{ + struct pciebrg_regs *pciebrg = PCIEBRG_BASE; + struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; + int i; + unsigned char *data; + unsigned short tmp; + unsigned long pcie_size; + + if (!(readw(&pciebrg->ctrl_h8s) & 0x0001)) + return; + + if (is_sh7757_b0()) + pcie_size = SH7757LCR_PCIEBRG_SIZE_B0; + else + pcie_size = SH7757LCR_PCIEBRG_SIZE; + + data = malloc(pcie_size); + if (!data) { + printf("%s: malloc error.\n", __func__); + return; + } + if (init_pcie_bridge_from_spi(data, pcie_size)) { + free(data); + return; + } + + if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff && + data[3] == 0xff) { + free(data); + printf("%s: skipped initialization\n", __func__); + return; + } + + writew(0xa501, &pciebrg->ctrl_h8s); /* reset */ + writew(0x0000, &pciebrg->cp_ctrl); + writew(0x0000, &pciebrg->cp_addr); + + for (i = 0; i < pcie_size; i += 2) { + tmp = (data[i] << 8) | data[i + 1]; + writew(tmp, &pciebrg->cp_data); + } + + writew(0xa500, &pciebrg->ctrl_h8s); /* start */ + if (!is_sh7757_b0()) + writel(0x00000001, &pcie_setup->pbictl3); + + free(data); +} + +static void init_usb_phy(void) +{ + struct usb_common_regs *common0 = USB0_COMMON_BASE; + struct usb_common_regs *common1 = USB1_COMMON_BASE; + struct usb0_phy_regs *phy = USB0_PHY_BASE; + struct usb1_port_regs *port = USB1_PORT_BASE; + struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; + + writew(0x0100, &phy->reset); /* set reset */ + /* port0 = USB0, port1 = USB1 */ + writew(0x0002, &phy->portsel); + writel(0x0001, &port->port1sel); /* port1 = Host */ + writew(0x0111, &phy->reset); /* clear reset */ + + writew(0x4000, &common0->suspmode); + writew(0x4000, &common1->suspmode); + +#if defined(__LITTLE_ENDIAN) + writel(0x00000000, &align->ehcidatac); + writel(0x00000000, &align->ohcidatac); +#endif +} + +static void set_mac_to_sh_eth_register(int channel, char *mac_string) +{ + struct ether_mac_regs *ether; + unsigned char mac[6]; + unsigned long val; + + eth_parse_enetaddr(mac_string, mac); + + if (!channel) + ether = ETHER0_MAC_BASE; + else + ether = ETHER1_MAC_BASE; + + val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; + writel(val, ðer->mahr); + val = (mac[4] << 8) | mac[5]; + writel(val, ðer->malr); +} + +static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) +{ + struct ether_mac_regs *ether; + unsigned char mac[6]; + unsigned long val; + + eth_parse_enetaddr(mac_string, mac); + + if (!channel) + ether = GETHER0_MAC_BASE; + else + ether = GETHER1_MAC_BASE; + + val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; + writel(val, ðer->mahr); + val = (mac[4] << 8) | mac[5]; + writel(val, ðer->malr); +} + +/***************************************************************** + * This PMB must be set on this timing. The lowlevel_init is run on + * Area 0(phys 0x00000000), so we have to map it. + * + * The new PMB table is following: + * ent virt phys v sz c wt + * 0 0xa0000000 0x40000000 1 128M 0 1 + * 1 0xa8000000 0x48000000 1 128M 0 1 + * 2 0xb0000000 0x50000000 1 128M 0 1 + * 3 0xb8000000 0x58000000 1 128M 0 1 + * 4 0x80000000 0x40000000 1 128M 1 1 + * 5 0x88000000 0x48000000 1 128M 1 1 + * 6 0x90000000 0x50000000 1 128M 1 1 + * 7 0x98000000 0x58000000 1 128M 1 1 + */ +static void set_pmb_on_board_init(void) +{ + struct mmu_regs *mmu = MMU_BASE; + + /* clear ITLB */ + writel(0x00000004, &mmu->mmucr); + + /* delete PMB for SPIBOOT */ + writel(0, PMB_ADDR_BASE(0)); + writel(0, PMB_DATA_BASE(0)); + + /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ + /* ppn ub v s1 s0 c wt */ + writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); + writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); + writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); + writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); + writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); + writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); + writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); + writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); + writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); + writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); + writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); + writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); +} + +int board_init(void) +{ + struct gether_control_regs *gether = GETHER_CONTROL_BASE; + + set_pmb_on_board_init(); + + /* enable RMII's MDIO (disable GRMII's MDIO) */ + writel(0x00030000, &gether->gbecont); + + init_gctrl(); + init_usb_phy(); + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + printf(" Physical address\n"); + printf(" 0x%08x - 0x%08x : Accessible Space as ECC Area\n", + SH7757LCR_SDRAM_PHYS_TOP, + SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1); + printf(" 0x%08x - 0x%08x : No Access Area\n", + SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE, + SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1); + printf(" 0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n", + SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2, + SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 + + SH7757LCR_SDRAM_DVC_SIZE - 1); + printf(" 0x%08x - 0x%08x : Non-ECC Area for G200eR2\n", + SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET, + SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff); + + return 0; +} + +static int get_sh_eth_mac_raw(unsigned char *buf, int size) +{ + struct spi_flash *spi; + int ret; + + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (spi == NULL) { + printf("%s: spi_flash probe error.\n", __func__); + return 1; + } + + ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf); + if (ret) { + printf("%s: spi_flash read error.\n", __func__); + spi_flash_free(spi); + return 1; + } + spi_flash_free(spi); + + return 0; +} + +static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) +{ + memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)], + SH7757LCR_ETHERNET_MAC_SIZE); + mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ + + return 0; +} + +static void init_ethernet_mac(void) +{ + char mac_string[64]; + char env_string[64]; + int i; + unsigned char *buf; + + buf = malloc(256); + if (!buf) { + printf("%s: malloc error.\n", __func__); + return; + } + get_sh_eth_mac_raw(buf, 256); + + /* Fast Ethernet */ + for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) { + get_sh_eth_mac(i, mac_string, buf); + if (i == 0) + setenv("ethaddr", mac_string); + else { + sprintf(env_string, "eth%daddr", i); + setenv(env_string, mac_string); + } + + set_mac_to_sh_eth_register(i, mac_string); + } + + /* Gigabit Ethernet */ + for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) { + get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf); + sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH); + setenv(env_string, mac_string); + + set_mac_to_sh_giga_eth_register(i, mac_string); + } + + free(buf); +} + +static void init_pcie(void) +{ + struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE; + struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE; + + writel(0x00000ff2, &pcie_setup->ladmsk0); + writel(0x00000001, &pcie_setup->barmap); + writel(0xffcaa000, &pcie_setup->lad0); + writel(0x00030000, &pcie_sysbus->endictl0); + writel(0x00000003, &pcie_sysbus->endictl1); + writel(0x00000004, &pcie_setup->pbictl2); +} + +static void finish_spiboot(void) +{ + struct gctrl_regs *gctrl = GCTRL_BASE; + /* + * SH7757 B0 does not use LBSC. + * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0. + * This setting is not cleared by manual reset, So we have to set it + * to 0. + */ + writel(0x00000000, &gctrl->spibootcan); +} + +int board_late_init(void) +{ + init_ethernet_mac(); + init_pcie_bridge(); + init_pcie(); + finish_spiboot(); + + return 0; +} + +int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct gctrl_regs *gctrl = GCTRL_BASE; + unsigned long graofst; + + writel(0xfedcba98, &gctrl->wprotect); + graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24; + writel(graofst | 0xa0000f00, &gctrl->gracr3); + + return 0; +} + +U_BOOT_CMD( + sh_g200, 1, 1, do_sh_g200, + "enable sh-g200", + "enable SH-G200 bus (disable PCIe-G200)" +); + +int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i, ret; + char mac_string[256]; + struct spi_flash *spi; + unsigned char *buf; + + if (argc != 5) { + buf = malloc(256); + if (!buf) { + printf("%s: malloc error.\n", __func__); + return 1; + } + + get_sh_eth_mac_raw(buf, 256); + + /* print current MAC address */ + for (i = 0; i < 4; i++) { + get_sh_eth_mac(i, mac_string, buf); + if (i < 2) + printf(" ETHERC ch%d = %s\n", i, mac_string); + else + printf("GETHERC ch%d = %s\n", i-2, mac_string); + } + free(buf); + return 0; + } + + /* new setting */ + memset(mac_string, 0xff, sizeof(mac_string)); + sprintf(mac_string, "%s\t%s\t%s\t%s", + argv[1], argv[2], argv[3], argv[4]); + + /* write MAC data to SPI rom */ + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!spi) { + printf("%s: spi_flash probe error.\n", __func__); + return 1; + } + + ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, + SH7757LCR_SPI_SECTOR_SIZE); + if (ret) { + printf("%s: spi_flash erase error.\n", __func__); + return 1; + } + + ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI, + sizeof(mac_string), mac_string); + if (ret) { + printf("%s: spi_flash write error.\n", __func__); + spi_flash_free(spi); + return 1; + } + spi_flash_free(spi); + + puts("The writing of the MAC address to SPI ROM was completed.\n"); + + return 0; +} + +U_BOOT_CMD( + write_mac, 5, 1, do_write_mac, + "write MAC address for ETHERC/GETHERC", + "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n" +); diff --git a/u-boot/board/renesas/sh7757lcr/spi-boot.c b/u-boot/board/renesas/sh7757lcr/spi-boot.c new file mode 100644 index 0000000..823844e --- /dev/null +++ b/u-boot/board/renesas/sh7757lcr/spi-boot.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License. See the file "COPYING.LIB" in the main + * directory of this archive for more details. + */ + +#include <common.h> + +#define CONFIG_RAM_BOOT_PHYS 0x4ef80000 +#if defined(CONFIG_SH7757_OFFSET_SPI) +#define CONFIG_SPI_ADDR 0x00010000 +#else +#define CONFIG_SPI_ADDR 0x00000000 +#endif +#define CONFIG_SPI_LENGTH 0x00030000 +#define CONFIG_RAM_BOOT 0x8ef80000 + +#define SPIWDMADR 0xFE001018 +#define SPIWDMCNTR 0xFE001020 +#define SPIDMCOR 0xFE001028 +#define SPIDMINTSR 0xFE001188 +#define SPIDMINTMR 0xFE001190 + +#define SPIDMINTSR_DMEND 0x00000004 + +#define TBR 0xFE002000 +#define RBR 0xFE002000 + +#define CR1 0xFE002008 +#define CR2 0xFE002010 +#define CR3 0xFE002018 +#define CR4 0xFE002020 + +/* CR1 */ +#define SPI_TBE 0x80 +#define SPI_TBF 0x40 +#define SPI_RBE 0x20 +#define SPI_RBF 0x10 +#define SPI_PFONRD 0x08 +#define SPI_SSDB 0x04 +#define SPI_SSD 0x02 +#define SPI_SSA 0x01 + +/* CR2 */ +#define SPI_RSTF 0x80 +#define SPI_LOOPBK 0x40 +#define SPI_CPOL 0x20 +#define SPI_CPHA 0x10 +#define SPI_L1M0 0x08 + +/* CR4 */ +#define SPI_TBEI 0x80 +#define SPI_TBFI 0x40 +#define SPI_RBEI 0x20 +#define SPI_RBFI 0x10 +#define SPI_SSS 0x01 + +#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val +#define spi_read(addr) (*(volatile unsigned long *)(addr)) + +/* M25P80 */ +#define M25_READ 0x03 + +#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) +static void __uses_spiboot2 spi_reset(void) +{ + spi_write(0xfe, CR1); + + spi_write(0, SPIDMCOR); + spi_write(0x00, CR1); + + spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ + spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); +} + +static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, + unsigned long len) +{ + spi_write(M25_READ, TBR); + spi_write((addr >> 16) & 0xFF, TBR); + spi_write((addr >> 8) & 0xFF, TBR); + spi_write(addr & 0xFF, TBR); + + spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); + spi_write((unsigned long)buf, SPIWDMADR); + spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); + spi_write(1, SPIDMCOR); + + spi_write(0xff, CR3); + spi_write(spi_read(CR1) | SPI_SSDB, CR1); + spi_write(spi_read(CR1) | SPI_SSA, CR1); + + while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) + ; +} + +void __uses_spiboot2 spiboot_main(void) +{ + void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; + + spi_reset(); + spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, + CONFIG_SPI_LENGTH); + + _start(); +} + diff --git a/u-boot/board/renesas/sh7757lcr/u-boot.lds b/u-boot/board/renesas/sh7757lcr/u-boot.lds new file mode 100644 index 0000000..a88d781 --- /dev/null +++ b/u-boot/board/renesas/sh7757lcr/u-boot.lds @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * Copyright (C) 2011 + * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + * entry and reloct_dst will be provided via ldflags + */ + . = .; + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + arch/sh/cpu/sh4/start.o (.text) + *(.spiboot1.text) + *(.spiboot2.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + PROVIDE (__u_boot_cmd_start = .); + .u_boot_cmd : + { + *(.u_boot_cmd) + . = ALIGN(4); + } + PROVIDE (__u_boot_cmd_end = .); + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss (NOLOAD) : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (_end = .); +} diff --git a/u-boot/board/renesas/sh7763rdp/Makefile b/u-boot/board/renesas/sh7763rdp/Makefile new file mode 100644 index 0000000..5f37700 --- /dev/null +++ b/u-boot/board/renesas/sh7763rdp/Makefile @@ -0,0 +1,51 @@ +# +# Copyright (C) 2008 Renesas Solutions Corp. +# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> +# Copyright (C) 2007 Kenati Technologies, Inc. +# +# board/sh7763rdp/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := sh7763rdp.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/u-boot/board/renesas/sh7763rdp/lowlevel_init.S b/u-boot/board/renesas/sh7763rdp/lowlevel_init.S new file mode 100644 index 0000000..5b18200 --- /dev/null +++ b/u-boot/board/renesas/sh7763rdp/lowlevel_init.S @@ -0,0 +1,274 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * Copyright (C) 2007 Kenati Technologies, Inc. + * + * board/sh7763rdp/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +#include <asm/processor.h> +#include <asm/macro.h> + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */ + + write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */ + + write32 WDTBST_A, WDTBST_D /* + * 0xFFCC0008 + * Watchdog Base Stop Time Register + */ + + write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */ + /* Instruction Cache Invalidate */ + + write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */ + /* TI == TLB Invalidate bit */ + + write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */ + + write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */ + + write32 RAMCR_A, RAMCR_D + + mov.l MMSELR_A, r1 + mov.l MMSELR_D, r0 + synco + mov.l r0, @r1 + + mov.l @r1, r2 /* execute two reads after setting MMSELR */ + mov.l @r1, r2 + synco + + /* issue memory read */ + mov.l DDRSD_START_A, r1 /* memory address to read*/ + mov.l @r1, r0 + synco + + write32 MIM8_A, MIM8_D + + write32 MIMC_A, MIMC_D1 + + write32 STRC_A, STRC_D + + write32 SDR4_A, SDR4_D + + write32 MIMC_A, MIMC_D2 + + nop + nop + nop + + write32 SCR4_A, SCR4_D3 + + write32 SCR4_A, SCR4_D2 + + write32 SDMR02000_A, SDMR02000_D + + write32 SDMR00B08_A, SDMR00B08_D + + write32 SCR4_A, SCR4_D2 + + write32 SCR4_A, SCR4_D4 + + nop + nop + nop + nop + + write32 SCR4_A, SCR4_D4 + + nop + nop + nop + nop + + write32 SDMR00308_A, SDMR00308_D + + write32 MIMC_A, MIMC_D3 + + mov.l SCR4_A, r1 + mov.l SCR4_D1, r0 + mov.l DELAY60_D, r3 + +delay_loop_60: + mov.l r0, @r1 + dt r3 + bf delay_loop_60 + nop + + write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */ + +bsc_init: + write32 BCR_A, BCR_D + + write32 CS0BCR_A, CS0BCR_D + + write32 CS1BCR_A, CS1BCR_D + + write32 CS2BCR_A, CS2BCR_D + + write32 CS4BCR_A, CS4BCR_D + + write32 CS5BCR_A, CS5BCR_D + + write32 CS6BCR_A, CS6BCR_D + + write32 CS0WCR_A, CS0WCR_D + + write32 CS1WCR_A, CS1WCR_D + + write32 CS2WCR_A, CS2WCR_D + + write32 CS4WCR_A, CS4WCR_D + + write32 CS5WCR_A, CS5WCR_D + + write32 CS6WCR_A, CS6WCR_D + + write32 CS5PCR_A, CS5PCR_D + + write32 CS6PCR_A, CS6PCR_D + + mov.l DELAY200_D, r3 + +delay_loop_200: + dt r3 + bf delay_loop_200 + nop + + write16 PSEL0_A, PSEL0_D + + write16 PSEL1_A, PSEL1_D + + write32 ICR0_A, ICR0_D + + stc sr, r0 /* BL bit off(init=ON) */ + mov.l SR_MASK_D, r1 + and r1, r0 + ldc r0, sr + + rts + nop + + .align 2 + +DELAY60_D: .long 60 +DELAY200_D: .long 17800 + +CCR_A: .long 0xFF00001C +MMUCR_A: .long 0xFF000010 +RAMCR_A: .long 0xFF000074 + +/* Low power mode control */ +MSTPCR0_A: .long 0xFFC80030 +MSTPCR1_A: .long 0xFFC80038 + +/* RWBT */ +WDTST_A: .long 0xFFCC0000 +WDTCSR_A: .long 0xFFCC0004 +WDTBST_A: .long 0xFFCC0008 + +/* BSC */ +MMSELR_A: .long 0xFE600020 +BCR_A: .long 0xFF801000 +CS0BCR_A: .long 0xFF802000 +CS1BCR_A: .long 0xFF802010 +CS2BCR_A: .long 0xFF802020 +CS4BCR_A: .long 0xFF802040 +CS5BCR_A: .long 0xFF802050 +CS6BCR_A: .long 0xFF802060 +CS0WCR_A: .long 0xFF802008 +CS1WCR_A: .long 0xFF802018 +CS2WCR_A: .long 0xFF802028 +CS4WCR_A: .long 0xFF802048 +CS5WCR_A: .long 0xFF802058 +CS6WCR_A: .long 0xFF802068 +CS5PCR_A: .long 0xFF802070 +CS6PCR_A: .long 0xFF802080 +DDRSD_START_A: .long 0xAC000000 + +/* INTC */ +ICR0_A: .long 0xFFD00000 + +/* DDR I/F */ +MIM8_A: .long 0xFE800008 +MIMC_A: .long 0xFE80000C +SCR4_A: .long 0xFE800014 +STRC_A: .long 0xFE80001C +SDR4_A: .long 0xFE800034 +SDMR00308_A: .long 0xFE900308 +SDMR00B08_A: .long 0xFE900B08 +SDMR02000_A: .long 0xFE902000 + +/* GPIO */ +PSEL0_A: .long 0xFFEF0070 +PSEL1_A: .long 0xFFEF0072 + +CCR_CACHE_ICI_D:.long 0x00000800 +CCR_CACHE_D_2: .long 0x00000103 +MMU_CONTROL_TI_D:.long 0x00000004 +RAMCR_D: .long 0x00000200 +MSTPCR0_D: .long 0x00000000 +MSTPCR1_D: .long 0x00000000 + +MMSELR_D: .long 0xa5a50000 +BCR_D: .long 0x00000000 +CS0BCR_D: .long 0x77777770 +CS1BCR_D: .long 0x77777670 +CS2BCR_D: .long 0x77777670 +CS4BCR_D: .long 0x77777670 +CS5BCR_D: .long 0x77777670 +CS6BCR_D: .long 0x77777670 +CS0WCR_D: .long 0x7777770F +CS1WCR_D: .long 0x22000002 +CS2WCR_D: .long 0x7777770F +CS4WCR_D: .long 0x7777770F +CS5WCR_D: .long 0x7777770F +CS6WCR_D: .long 0x7777770F +CS5PCR_D: .long 0x77000000 +CS6PCR_D: .long 0x77000000 +ICR0_D: .long 0x00E00000 +MIM8_D: .long 0x00000000 +MIMC_D1: .long 0x01d10008 +MIMC_D2: .long 0x01d10009 +MIMC_D3: .long 0x01d10209 +SCR4_D1: .long 0x00000001 +SCR4_D2: .long 0x00000002 +SCR4_D3: .long 0x00000003 +SCR4_D4: .long 0x00000004 +STRC_D: .long 0x000f3980 +SDR4_D: .long 0x00000300 +SDMR00308_D: .long 0x00000000 +SDMR00B08_D: .long 0x00000000 +SDMR02000_D: .long 0x00000000 +PSEL0_D: .word 0x00000001 +PSEL1_D: .word 0x00000244 +SR_MASK_D: .long 0xEFFFFF0F +WDTST_D: .long 0x5A000FFF +WDTCSR_D: .long 0xA5000000 +WDTBST_D: .long 0x55000000 diff --git a/u-boot/board/renesas/sh7763rdp/sh7763rdp.c b/u-boot/board/renesas/sh7763rdp/sh7763rdp.c new file mode 100644 index 0000000..9f44b9a --- /dev/null +++ b/u-boot/board/renesas/sh7763rdp/sh7763rdp.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> + * Copyright (C) 2007 Kenati Technologies, Inc. + * + * board/sh7763rdp/sh7763rdp.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CPU_CMDREG 0xB1000006 +#define PDCR 0xffef0006 +#define PECR 0xffef0008 +#define PFCR 0xffef000a +#define PGCR 0xffef000c +#define PHCR 0xffef000e +#define PJCR 0xffef0012 +#define PKCR 0xffef0014 +#define PLCR 0xffef0016 +#define PMCR 0xffef0018 +#define PSEL1 0xffef0072 +#define PSEL2 0xffef0074 +#define PSEL3 0xffef0076 + +int checkboard(void) +{ + puts("BOARD: Renesas SH7763 RDP\n"); + return 0; +} + +int board_init(void) +{ + vu_short dat; + + /* Enable mode */ + writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG); + + /* GPIO Setting (eth1) */ + dat = inw(PSEL1); + writew(((dat & ~0xff00) | 0x2400), PSEL1); + writew(0, PFCR); + writew(0, PGCR); + writew(0, PHCR); + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +void led_set_state(unsigned short value) +{ +} diff --git a/u-boot/board/renesas/sh7785lcr/Makefile b/u-boot/board/renesas/sh7785lcr/Makefile new file mode 100644 index 0000000..e404fa6 --- /dev/null +++ b/u-boot/board/renesas/sh7785lcr/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := sh7785lcr.o selfcheck.o rtl8169_mac.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/u-boot/board/renesas/sh7785lcr/lowlevel_init.S b/u-boot/board/renesas/sh7785lcr/lowlevel_init.S new file mode 100644 index 0000000..24a0ecd --- /dev/null +++ b/u-boot/board/renesas/sh7785lcr/lowlevel_init.S @@ -0,0 +1,376 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <version.h> +#include <asm/processor.h> +#include <asm/macro.h> + +#include <asm/processor.h> + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + wait_timer WAIT_200US + wait_timer WAIT_200US + + /*------- LBSC -------*/ + write32 MMSELR_A, MMSELR_D + + /*------- DBSC2 -------*/ + write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D + write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D + write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D + write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D + write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1 + write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2 + wait_timer WAIT_200US + + write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H + wait_timer WAIT_200US + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2 + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3 + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1 + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF + write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2 + wait_timer WAIT_200US + + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2 + write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 + + write32 DBSC2_DBEN_A, DBSC2_DBEN_D + write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D + write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D + write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D + wait_timer WAIT_200US + + /*------- GPIO -------*/ + write16 PACR_A, PXCR_D + write16 PBCR_A, PXCR_D + write16 PCCR_A, PXCR_D + write16 PDCR_A, PXCR_D + write16 PECR_A, PXCR_D + write16 PFCR_A, PXCR_D + write16 PGCR_A, PXCR_D + write16 PHCR_A, PHCR_D + write16 PJCR_A, PJCR_D + write16 PKCR_A, PKCR_D + write16 PLCR_A, PXCR_D + write16 PMCR_A, PMCR_D + write16 PNCR_A, PNCR_D + write16 PPCR_A, PXCR_D + write16 PQCR_A, PXCR_D + write16 PRCR_A, PXCR_D + + write8 PEPUPR_A, PEPUPR_D + write8 PHPUPR_A, PHPUPR_D + write8 PJPUPR_A, PJPUPR_D + write8 PKPUPR_A, PKPUPR_D + write8 PLPUPR_A, PLPUPR_D + write8 PMPUPR_A, PMPUPR_D + write8 PNPUPR_A, PNPUPR_D + write16 PPUPR1_A, PPUPR1_D + write16 PPUPR2_A, PPUPR2_D + write16 P1MSELR_A, P1MSELR_D + write16 P2MSELR_A, P2MSELR_D + + /*------- LBSC -------*/ + write32 BCR_A, BCR_D + write32 CS0BCR_A, CS0BCR_D + write32 CS0WCR_A, CS0WCR_D + write32 CS1BCR_A, CS1BCR_D + write32 CS1WCR_A, CS1WCR_D + write32 CS4BCR_A, CS4BCR_D + write32 CS4WCR_A, CS4WCR_D + + mov.l PASCR_A, r0 + mov.l @r0, r2 + mov.l PASCR_32BIT_MODE, r1 + tst r1, r2 + bt lbsc_29bit + + write32 CS2BCR_A, CS_USB_BCR_D + write32 CS2WCR_A, CS_USB_WCR_D + write32 CS3BCR_A, CS_SD_BCR_D + write32 CS3WCR_A, CS_SD_WCR_D + write32 CS5BCR_A, CS_I2C_BCR_D + write32 CS5WCR_A, CS_I2C_WCR_D + write32 CS6BCR_A, CS0BCR_D + write32 CS6WCR_A, CS0WCR_D + bra lbsc_end + nop + +lbsc_29bit: + write32 CS5BCR_A, CS_USB_BCR_D + write32 CS5WCR_A, CS_USB_WCR_D + write32 CS6BCR_A, CS_SD_BCR_D + write32 CS6WCR_A, CS_SD_WCR_D + +lbsc_end: +#if defined(CONFIG_SH_32BIT) + /*------- set PMB -------*/ + write32 PASCR_A, PASCR_29BIT_D + write32 MMUCR_A, MMUCR_D + + /***************************************************************** + * ent virt phys v sz c wt + * 0 0xa0000000 0x00000000 1 64M 0 0 + * 1 0xa4000000 0x04000000 1 16M 0 0 + * 2 0xa6000000 0x08000000 1 16M 0 0 + * 9 0x88000000 0x48000000 1 128M 1 1 + * 10 0x90000000 0x50000000 1 128M 1 1 + * 11 0x98000000 0x58000000 1 128M 1 1 + * 13 0xa8000000 0x48000000 1 128M 0 0 + * 14 0xb0000000 0x50000000 1 128M 0 0 + * 15 0xb8000000 0x58000000 1 128M 0 0 + */ + write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D + write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D + write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D + write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D + write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D + write32 PMB_DATA_USB_A, PMB_DATA_USB_D + write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D + write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D + write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D + write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D + write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D + write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D + write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D + write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D + write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D + write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D + write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D + write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D + + write32 PASCR_A, PASCR_INIT + mov.l DUMMY_ADDR, r0 + icbi @r0 +#endif + + write32 CCR_A, CCR_D + + rts + nop + + .align 4 + +/*------- GPIO -------*/ +/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */ +PXCR_D: .word 0x0000 + +PHCR_D: .word 0x00c0 +PJCR_D: .word 0xc3fc +PKCR_D: .word 0x03ff +PMCR_D: .word 0xffff +PNCR_D: .word 0xf0c3 + +PEPUPR_D: .long 0xff +PHPUPR_D: .long 0x00 +PJPUPR_D: .long 0x00 +PKPUPR_D: .long 0x00 +PLPUPR_D: .long 0x00 +PMPUPR_D: .long 0xfc +PNPUPR_D: .long 0x00 +PPUPR1_D: .word 0xffbf +PPUPR2_D: .word 0xff00 +P1MSELR_D: .word 0x3780 +P2MSELR_D: .word 0x0000 + +#define GPIO_BASE 0xffe70000 +PACR_A: .long GPIO_BASE + 0x00 +PBCR_A: .long GPIO_BASE + 0x02 +PCCR_A: .long GPIO_BASE + 0x04 +PDCR_A: .long GPIO_BASE + 0x06 +PECR_A: .long GPIO_BASE + 0x08 +PFCR_A: .long GPIO_BASE + 0x0a +PGCR_A: .long GPIO_BASE + 0x0c +PHCR_A: .long GPIO_BASE + 0x0e +PJCR_A: .long GPIO_BASE + 0x10 +PKCR_A: .long GPIO_BASE + 0x12 +PLCR_A: .long GPIO_BASE + 0x14 +PMCR_A: .long GPIO_BASE + 0x16 +PNCR_A: .long GPIO_BASE + 0x18 +PPCR_A: .long GPIO_BASE + 0x1a +PQCR_A: .long GPIO_BASE + 0x1c +PRCR_A: .long GPIO_BASE + 0x1e +PEPUPR_A: .long GPIO_BASE + 0x48 +PHPUPR_A: .long GPIO_BASE + 0x4e +PJPUPR_A: .long GPIO_BASE + 0x50 +PKPUPR_A: .long GPIO_BASE + 0x52 +PLPUPR_A: .long GPIO_BASE + 0x54 +PMPUPR_A: .long GPIO_BASE + 0x56 +PNPUPR_A: .long GPIO_BASE + 0x58 +PPUPR1_A: .long GPIO_BASE + 0x60 +PPUPR2_A: .long GPIO_BASE + 0x62 +P1MSELR_A: .long GPIO_BASE + 0x80 +P2MSELR_A: .long GPIO_BASE + 0x82 + +MMSELR_A: .long 0xfc400020 +#if defined(CONFIG_SH_32BIT) +MMSELR_D: .long 0xa5a50005 +#else +MMSELR_D: .long 0xa5a50002 +#endif + +/*------- DBSC2 -------*/ +#define DBSC2_BASE 0xfe800000 +DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c +DBSC2_DBEN_A: .long DBSC2_BASE + 0x10 +DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14 +DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20 +DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30 +DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34 +DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38 +DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40 +DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44 +DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48 +DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c +DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50 +DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54 +DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60 +DDR_DUMMY_ACCESS_A: .long 0x40000000 + +DBSC2_DBCONF_D: .long 0x00630002 +DBSC2_DBTR0_D: .long 0x050b1f04 +DBSC2_DBTR1_D: .long 0x00040204 +DBSC2_DBTR2_D: .long 0x02100308 +DBSC2_DBFREQ_D1: .long 0x00000000 +DBSC2_DBFREQ_D2: .long 0x00000100 +DBSC2_DBDICODTOCD_D:.long 0x000f0907 + +DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003 +DBSC2_DBCMDCNT_D_PALL: .long 0x00000002 +DBSC2_DBCMDCNT_D_REF: .long 0x00000004 + +DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000 +DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000 +DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006 +DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386 +DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952 +DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852 + +DBSC2_DBEN_D: .long 0x00000001 + +DBSC2_DBPDCNT0_D3: .long 0x00000080 +DBSC2_DBRFCNT1_D: .long 0x00000926 +DBSC2_DBRFCNT2_D: .long 0x00fe00fe +DBSC2_DBRFCNT0_D: .long 0x00010000 + +WAIT_200US: .long 33333 + +/*------- LBSC -------*/ +PASCR_A: .long 0xff000070 +PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */ + +BCR_A: .long BCR +CS0BCR_A: .long CS0BCR +CS0WCR_A: .long CS0WCR +CS1BCR_A: .long CS1BCR +CS1WCR_A: .long CS1WCR +CS2BCR_A: .long CS2BCR +CS2WCR_A: .long CS2WCR +CS3BCR_A: .long CS3BCR +CS3WCR_A: .long CS3WCR +CS4BCR_A: .long CS4BCR +CS4WCR_A: .long CS4WCR +CS5BCR_A: .long CS5BCR +CS5WCR_A: .long CS5WCR +CS6BCR_A: .long CS6BCR +CS6WCR_A: .long CS6WCR + +BCR_D: .long 0x80000003 +CS0BCR_D: .long 0x22222340 +CS0WCR_D: .long 0x00111118 +CS1BCR_D: .long 0x11111100 +CS1WCR_D: .long 0x33333303 +CS4BCR_D: .long 0x11111300 +CS4WCR_D: .long 0x00101012 + +/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */ +CS_USB_BCR_D: .long 0x11111200 +CS_USB_WCR_D: .long 0x00020004 + +/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ +CS_SD_BCR_D: .long 0x00000300 +CS_SD_WCR_D: .long 0x00030108 + +/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */ +CS_I2C_BCR_D: .long 0x11111100 +CS_I2C_WCR_D: .long 0x00000003 + +#if defined(CONFIG_SH_32BIT) +/*------- set PMB -------*/ +PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0) +PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1) +PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2) +PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9) +PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10) +PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11) +PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13) +PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14) +PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15) + +PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0) +PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4) +PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6) +PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) +PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90) +PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98) +PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) +PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0) +PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8) + +PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0) +PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1) +PMB_DATA_USB_A: .long PMB_DATA_BASE(2) +PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9) +PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10) +PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11) +PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13) +PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14) +PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15) + +/* ppn ub v s1 s0 c wt */ +PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1) +PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1) +PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1) +PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) +PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1) +PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1) + +DUMMY_ADDR: .long 0xa0000000 +PASCR_29BIT_D: .long 0x00000000 +PASCR_INIT: .long 0x80000080 /* check booting mode */ +MMUCR_A: .long 0xff000010 +MMUCR_D: .long 0x00000004 /* clear ITLB */ +#endif /* CONFIG_SH_32BIT */ + +CCR_A: .long 0xff00001c +CCR_D: .long 0x0000090b diff --git a/u-boot/board/renesas/sh7785lcr/rtl8169.h b/u-boot/board/renesas/sh7785lcr/rtl8169.h new file mode 100644 index 0000000..ca9c0bd --- /dev/null +++ b/u-boot/board/renesas/sh7785lcr/rtl8169.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define PCIREG_8(_adr) (*(volatile unsigned char *)(_adr)) +#define PCIREG_32(_adr) (*(volatile unsigned long *)(_adr)) +#define PCI_PAR PCIREG_32(0xfe0401c0) +#define PCI_PDR PCIREG_32(0xfe040220) +#define PCI_CR PCIREG_32(0xfe040100) +#define PCI_CONF1 PCIREG_32(0xfe040004) + +#define HIGH 1 +#define LOW 0 + +#define PCI_PROG 0x80 +#define PCI_EEP_ADDRESS (unsigned short)0x0007 +#define PCI_MAC_ADDRESS_SIZE 3 + +#define TIME1 100 +#define TIME2 20000 + +#define BIT_DUMMY 0 +#define MAC_EEP_READ 1 +#define MAC_EEP_WRITE 2 +#define MAC_EEP_ERACE 3 +#define MAC_EEP_EWEN 4 +#define MAC_EEP_EWDS 5 + +/* RTL8169 */ +const unsigned short EEPROM_W_Data_8169_A[] = { + 0x8129, 0x10ec, 0x8169, 0x1154, 0x032b, + 0x4020, 0xa101 +}; +const unsigned short EEPROM_W_Data_8169_B[] = { + 0x4d15, 0xf7c2, 0x8000, 0x0000, 0x0000, 0x1300, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 +}; diff --git a/u-boot/board/renesas/sh7785lcr/rtl8169_mac.c b/u-boot/board/renesas/sh7785lcr/rtl8169_mac.c new file mode 100644 index 0000000..e15013f --- /dev/null +++ b/u-boot/board/renesas/sh7785lcr/rtl8169_mac.c @@ -0,0 +1,344 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include "rtl8169.h" + +static unsigned char *PCI_MEMR; + +static void mac_delay(unsigned int cnt) +{ + udelay(cnt); +} + +static void mac_pci_setup(void) +{ + unsigned long pci_data; + + PCI_PAR = 0x00000010; + PCI_PDR = 0x00001000; + PCI_PAR = 0x00000004; + pci_data = PCI_PDR; + PCI_PDR = pci_data | 0x00000007; + PCI_PAR = 0x00000010; + + PCI_MEMR = (unsigned char *)((PCI_PDR | 0xFE240050) & 0xFFFFFFF0); +} + +static void EECS(int level) +{ + unsigned char data = *PCI_MEMR; + + if (level) + *PCI_MEMR = data | 0x08; + else + *PCI_MEMR = data & 0xf7; +} + +static void EECLK(int level) +{ + unsigned char data = *PCI_MEMR; + + if (level) + *PCI_MEMR = data | 0x04; + else + *PCI_MEMR = data & 0xfb; +} + +static void EEDI(int level) +{ + unsigned char data = *PCI_MEMR; + + if (level) + *PCI_MEMR = data | 0x02; + else + *PCI_MEMR = data & 0xfd; +} + +static inline void sh7785lcr_bitset(unsigned short bit) +{ + if (bit) + EEDI(HIGH); + else + EEDI(LOW); + + EECLK(LOW); + mac_delay(TIME1); + EECLK(HIGH); + mac_delay(TIME1); + EEDI(LOW); +} + +static inline unsigned char sh7785lcr_bitget(void) +{ + unsigned char bit; + + EECLK(LOW); + mac_delay(TIME1); + bit = *PCI_MEMR & 0x01; + EECLK(HIGH); + mac_delay(TIME1); + + return bit; +} + +static inline void sh7785lcr_setcmd(unsigned char command) +{ + sh7785lcr_bitset(BIT_DUMMY); + switch (command) { + case MAC_EEP_READ: + sh7785lcr_bitset(1); + sh7785lcr_bitset(1); + sh7785lcr_bitset(0); + break; + case MAC_EEP_WRITE: + sh7785lcr_bitset(1); + sh7785lcr_bitset(0); + sh7785lcr_bitset(1); + break; + case MAC_EEP_ERACE: + sh7785lcr_bitset(1); + sh7785lcr_bitset(1); + sh7785lcr_bitset(1); + break; + case MAC_EEP_EWEN: + sh7785lcr_bitset(1); + sh7785lcr_bitset(0); + sh7785lcr_bitset(0); + break; + case MAC_EEP_EWDS: + sh7785lcr_bitset(1); + sh7785lcr_bitset(0); + sh7785lcr_bitset(0); + break; + default: + break; + } +} + +static inline unsigned short sh7785lcr_getdt(void) +{ + unsigned short data = 0; + int i; + + sh7785lcr_bitget(); /* DUMMY */ + for (i = 0 ; i < 16 ; i++) { + data <<= 1; + data |= sh7785lcr_bitget(); + } + return data; +} + +static inline void sh7785lcr_setadd(unsigned short address) +{ + sh7785lcr_bitset(address & 0x0020); /* A5 */ + sh7785lcr_bitset(address & 0x0010); /* A4 */ + sh7785lcr_bitset(address & 0x0008); /* A3 */ + sh7785lcr_bitset(address & 0x0004); /* A2 */ + sh7785lcr_bitset(address & 0x0002); /* A1 */ + sh7785lcr_bitset(address & 0x0001); /* A0 */ +} + +static inline void sh7785lcr_setdata(unsigned short data) +{ + sh7785lcr_bitset(data & 0x8000); + sh7785lcr_bitset(data & 0x4000); + sh7785lcr_bitset(data & 0x2000); + sh7785lcr_bitset(data & 0x1000); + sh7785lcr_bitset(data & 0x0800); + sh7785lcr_bitset(data & 0x0400); + sh7785lcr_bitset(data & 0x0200); + sh7785lcr_bitset(data & 0x0100); + sh7785lcr_bitset(data & 0x0080); + sh7785lcr_bitset(data & 0x0040); + sh7785lcr_bitset(data & 0x0020); + sh7785lcr_bitset(data & 0x0010); + sh7785lcr_bitset(data & 0x0008); + sh7785lcr_bitset(data & 0x0004); + sh7785lcr_bitset(data & 0x0002); + sh7785lcr_bitset(data & 0x0001); +} + +static void sh7785lcr_datawrite(const unsigned short *data, unsigned short address, + unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) { + EECS(HIGH); + EEDI(LOW); + mac_delay(TIME1); + + sh7785lcr_setcmd(MAC_EEP_WRITE); + sh7785lcr_setadd(address++); + sh7785lcr_setdata(*(data + i)); + + EECLK(LOW); + EEDI(LOW); + EECS(LOW); + mac_delay(TIME2); + } +} + +static void sh7785lcr_macerase(void) +{ + unsigned int i; + unsigned short pci_address = 7; + + for (i = 0; i < 3; i++) { + EECS(HIGH); + EEDI(LOW); + mac_delay(TIME1); + sh7785lcr_setcmd(MAC_EEP_ERACE); + sh7785lcr_setadd(pci_address++); + mac_delay(TIME1); + EECLK(LOW); + EEDI(LOW); + EECS(LOW); + } + + mac_delay(TIME2); + + printf("\n\nErace End\n"); + for (i = 0; i < 10; i++) + mac_delay(TIME2); +} + +static void sh7785lcr_macwrite(unsigned short *data) +{ + sh7785lcr_macerase(); + + sh7785lcr_datawrite(EEPROM_W_Data_8169_A, 0x0000, 7); + sh7785lcr_datawrite(data, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); + sh7785lcr_datawrite(EEPROM_W_Data_8169_B, 0x000a, 54); +} + +void sh7785lcr_macdtrd(unsigned char *buf, unsigned short address, unsigned int count) +{ + unsigned int i; + unsigned short wk; + + for (i = 0 ; i < count; i++) { + EECS(HIGH); + EEDI(LOW); + mac_delay(TIME1); + sh7785lcr_setcmd(MAC_EEP_READ); + sh7785lcr_setadd(address++); + wk = sh7785lcr_getdt(); + + *buf++ = (unsigned char)(wk & 0xff); + *buf++ = (unsigned char)((wk >> 8) & 0xff); + EECLK(LOW); + EEDI(LOW); + EECS(LOW); + } +} + +static void sh7785lcr_macadrd(unsigned char *buf) +{ + *PCI_MEMR = PCI_PROG; + + sh7785lcr_macdtrd(buf, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); +} + +static void sh7785lcr_eepewen(void) +{ + *PCI_MEMR = PCI_PROG; + mac_delay(TIME1); + EECS(LOW); + EECLK(LOW); + EEDI(LOW); + EECS(HIGH); + mac_delay(TIME1); + + sh7785lcr_setcmd(MAC_EEP_EWEN); + sh7785lcr_bitset(1); + sh7785lcr_bitset(1); + sh7785lcr_bitset(BIT_DUMMY); + sh7785lcr_bitset(BIT_DUMMY); + sh7785lcr_bitset(BIT_DUMMY); + sh7785lcr_bitset(BIT_DUMMY); + + EECLK(LOW); + EEDI(LOW); + EECS(LOW); + mac_delay(TIME1); +} + +void mac_write(unsigned short *data) +{ + mac_pci_setup(); + sh7785lcr_eepewen(); + sh7785lcr_macwrite(data); +} + +void mac_read(void) +{ + unsigned char data[6]; + + mac_pci_setup(); + sh7785lcr_macadrd(data); + printf("Mac = %02x:%02x:%02x:%02x:%02x:%02x\n", + data[0], data[1], data[2], data[3], data[4], data[5]); +} + +int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + unsigned char mac[6]; + char *s, *e; + + if (argc != 2) + return cmd_usage(cmdtp); + + s = argv[1]; + + for (i = 0; i < 6; i++) { + mac[i] = s ? simple_strtoul(s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + mac_write((unsigned short *)mac); + + return 0; +} + +U_BOOT_CMD( + setmac, 2, 1, do_set_mac, + "write MAC address for RTL8110SCL", + "\n" + "setmac <mac address> - write MAC address for RTL8110SCL" +); + +int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 1) + return cmd_usage(cmdtp); + + mac_read(); + + return 0; +} + +U_BOOT_CMD( + printmac, 1, 1, do_print_mac, + "print MAC address for RTL8110", + "\n" + " - print MAC address for RTL8110" +); diff --git a/u-boot/board/renesas/sh7785lcr/selfcheck.c b/u-boot/board/renesas/sh7785lcr/selfcheck.c new file mode 100644 index 0000000..6d92c83 --- /dev/null +++ b/u-boot/board/renesas/sh7785lcr/selfcheck.c @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/pci.h> + +#if defined(CONFIG_CPU_32BIT) +#define NOCACHE_OFFSET 0x00000000 +#else +#define NOCACHE_OFFSET 0xa0000000 +#endif +#define PLD_LEDCR (0x04000008 + NOCACHE_OFFSET) +#define PLD_SWSR (0x0400000a + NOCACHE_OFFSET) +#define PLD_VERSR (0x0400000c + NOCACHE_OFFSET) + +#define SM107_DEVICEID (0x13e00060 + NOCACHE_OFFSET) + +static void wait_ms(unsigned long time) +{ + while (time--) + udelay(1000); +} + +static void test_pld(void) +{ + printf("PLD version = %04x\n", readb(PLD_VERSR)); +} + +static void test_sm107(void) +{ + printf("SM107 device ID = %04x\n", readl(SM107_DEVICEID)); +} + +static void test_led(void) +{ + printf("turn on LEDs 3, 5, 7, 9\n"); + writeb(0x55, PLD_LEDCR); + wait_ms(2000); + printf("turn on LEDs 4, 6, 8, 10\n"); + writeb(0xaa, PLD_LEDCR); + wait_ms(2000); + writeb(0x00, PLD_LEDCR); +} + +static void test_dipsw(void) +{ + printf("Please DIPSW set = B'0101\n"); + while (readb(PLD_SWSR) != 0x05) { + if (ctrlc()) + return; + } + printf("Please DIPSW set = B'1010\n"); + while (readb(PLD_SWSR) != 0x0A) { + if (ctrlc()) + return; + } + printf("DIPSW OK\n"); +} + +static void test_net(void) +{ + unsigned long data; + + writel(0x80000000, 0xfe0401c0); + data = readl(0xfe040220); + if (data == 0x816910ec) + printf("Ethernet OK\n"); + else + printf("Ethernet NG, data = %08x\n", (unsigned int)data); +} + +static void test_sata(void) +{ + unsigned long data; + + writel(0x80000800, 0xfe0401c0); + data = readl(0xfe040220); + if (data == 0x35121095) + printf("SATA OK\n"); + else + printf("SATA NG, data = %08x\n", (unsigned int)data); +} + +static void test_pci(void) +{ + writel(0x80001800, 0xfe0401c0); + printf("PCI CN1 ID = %08x\n", readl(0xfe040220)); + + writel(0x80001000, 0xfe0401c0); + printf("PCI CN2 ID = %08x\n", readl(0xfe040220)); +} + +int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *cmd; + + if (argc != 2) + return cmd_usage(cmdtp); + + cmd = argv[1]; + switch (cmd[0]) { + case 'a': /* all */ + test_pld(); + test_led(); + test_dipsw(); + test_sm107(); + test_net(); + test_sata(); + test_pci(); + break; + case 'p': /* pld or pci */ + if (cmd[1] == 'l') + test_pld(); + else + test_pci(); + break; + case 'l': /* led */ + test_led(); + break; + case 'd': /* dipsw */ + test_dipsw(); + break; + case 's': /* sm107 or sata */ + if (cmd[1] == 'm') + test_sm107(); + else + test_sata(); + break; + case 'n': /* net */ + test_net(); + break; + default: + return cmd_usage(cmdtp); + } + + return 0; +} + +U_BOOT_CMD( + hwtest, 2, 1, do_hw_test, + "hardware test for R0P7785LC0011RL board", + "\n" + "hwtest all - test all hardware\n" + "hwtest pld - output PLD version\n" + "hwtest led - turn on LEDs\n" + "hwtest dipsw - test DIP switch\n" + "hwtest sm107 - output SM107 version\n" + "hwtest net - check RTL8110 ID\n" + "hwtest sata - check SiI3512 ID\n" + "hwtest pci - output PCI slot device ID" +); diff --git a/u-boot/board/renesas/sh7785lcr/sh7785lcr.c b/u-boot/board/renesas/sh7785lcr/sh7785lcr.c new file mode 100644 index 0000000..904e755 --- /dev/null +++ b/u-boot/board/renesas/sh7785lcr/sh7785lcr.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/pci.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n"); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +static struct pci_controller hose; +void pci_init_board(void) +{ + pci_sh7780_init(&hose); +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +#if defined(CONFIG_SH_32BIT) +int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + /* clear ITLB */ + writel(0x00000004, 0xff000010); + + /* delete PMB for peripheral */ + writel(0, PMB_ADDR_BASE(0)); + writel(0, PMB_DATA_BASE(0)); + writel(0, PMB_ADDR_BASE(1)); + writel(0, PMB_DATA_BASE(1)); + writel(0, PMB_ADDR_BASE(2)); + writel(0, PMB_DATA_BASE(2)); + + /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ + writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8)); + writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8)); + writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12)); + writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12)); + + return 0; +} + +U_BOOT_CMD( + pmb, 1, 1, do_pmb, + "pmb - PMB setting\n", + "\n" + " - PMB setting for all SDRAM mapping" +); +#endif |