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* ppc/85xx: Fix compile err when PCI disabled on P1_P2_RDBPrabhakar Kushwaha2011-01-193-7/+14
| | | | | | | | | u-boot cannot be compiled after disabling CONFIG_PCI. Place PCI related codes under #ifdef CONFIG_PCI Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p4080: Fix warning in serdes code from early use of hwconfigYork Sun2011-01-191-3/+14
| | | | | | | Hwconfig is called before relocating. Use the new hwconfig APIs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* corenet_ds: Extend board specific parametersYork Sun2011-01-192-78/+84
| | | | | | | | | Extend board specific parameters to include cpo, write leveling override Extend write leveling sample to 0xf Adding rcw overrid for quad-rank RDIMMs Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Implement workaround for erratum DDR-A003York Sun2011-01-194-1/+103
| | | | | | | | Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM. Also adding polling after enabling DDR controller to ensure completion. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Enable unique mode registers and dynamic ODT for DDR3York Sun2011-01-195-55/+596
| | | | | | | | | | | | | | | | | | Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Adding more registers and optionsYork Sun2011-01-194-26/+27
| | | | | | | | | | | | | This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* corenet_ds: Enable ECC for corenet_dsYork Sun2011-01-191-1/+1
| | | | | | | | ECC can be turned on/off by hwconfig without recompiling. So enable it by default. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8xxx: Enable ECC on/off control in hwconfigYork Sun2011-01-192-3/+13
| | | | | | | | | | | | | | Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file, ECC can be turned on/off by this switch. If this switch is omitted, it is ON by default. Updated hwconfig calls to use local buffer. Syntax is hwconfig=fsl_ddr:ecc=on Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8xxx: Display RDIMM if detectedYork Sun2011-01-191-12/+8
| | | | | | | Print a message when a RDIMM is detected. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headersKumar Gala2011-01-196-70/+236
| | | | | | | | | | | Add new headers that capture common defines for a given SoC/processor rather than duplicating that information in board config.h and random other places. Eventually this should be handled by Kconfig & defconfigs Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR initKumar Gala2011-01-193-78/+154
| | | | | | | | | | | | | | | | | | | | | | | | | There are several users of the hwconfig APIs (8xxx DDR) before we have the environment properly setup. This causes issues because of the numerous ways the environment might be accessed because of the non-volatile memory it might be stored in. Additionally the access might be so early that memory isn't even properly setup for us. Towards resolving these issues we provide versions of all the hwconfig APIs that can be passed in a buffer to parse and leave it to the caller to determine how to allocate and populate the buffer. We use the _f naming convention for these new APIs even though they are perfectly useable after relocation and the environment being ready. We also now warn if the non-f APIs are called before the environment is ready to allow users to address the issues. Finally, we convert the 8xxx DDR code to utilize the new APIs to hopefully address the issue once and for all. We have the 8xxx DDR code create a buffer on the stack and populate it via getenv_f(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/p2040: Add various p2040 specific informationKumar Gala2011-01-195-2/+74
| | | | | | | | | | Add P2040 SoC specific information: * SERDES Table * Added p2040 to cpu_type_list and SVR list * Added number of LAWs for p2040 * Set CONFIG_MAX_CPUS to 4 for p2040 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p5020: Add various p5020 specific informationKumar Gala2011-01-193-0/+258
| | | | | | | | | Add P5020 SoC specific information: * SERDES Table * LIODN setup * Portal configuration Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p3041: Add various p3041 specific informationKumar Gala2011-01-193-0/+258
| | | | | | | | | Add P3041 SoC specific information: * SERDES Table * LIODN setup * Portal configuration Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add Support for Freescale P1014 ProcessorPoonam Aggrwal2011-01-195-3/+8
| | | | | | | | | | | | The P1014 is similar to the P1010 processor with the following differences: - 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC) - no eCAN interface. (P1010 has 2 eCAN interfaces) - Two SGMII interface (P1010 has 3 SGMII) - No secure boot Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add Support for Freescale P1010 ProcessorPoonam Aggrwal2011-01-195-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Key Features include of the P1010: * e500v2 core frequency operation of 500 to 800 MHz * Power consumption less than 5.0 W at 800 MHz core speed * Dual SATA 3 Gbps controllers with integrated PHY * Dual PCI Express controllers * Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs) * TCP/IP acceleration and classification capabilities * IEEE 1588 support * Lossless flow control * RGMII, SGMII * DDR3 with support for a 32-bit data interface (40 bits including ECC), up to 800 MHz data rate 32/16-bit DDR3 memory controller * Dedicated security engine featuring trusted boot * TDM interface * Dual controller area networks (FlexCAN) controller * SD/MMC card controller supporting booting from Flash cards * USB 2.0 host and device controller with an on-chip, high-speed PHY * Integrated Flash controller (IFC) * Power Management Controller (PMC) * Four-channel, general-purpose DMA controller * I2C controller * Serial peripheral interface (SPI) controller with master and slave support * System timers including a periodic interrupt timer, real-time clock, software watchdog timer, and four general-purpose timers * Dual DUARTs Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDRPrabhakar2011-01-191-1/+1
| | | | | | | | | CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET. It should be as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* powerpc/85xx: Move RESET_VECTOR_ADDRESS into config.hKumar Gala2011-01-1913-94/+37
| | | | | | | | | | | Rather than defining it config.mk we can set it in config.h and remove config.mk from several boards that don't need it. We mimic what 4xx does and introduce CONFIG_RESET_VECTOR_ADDRESS for config.h to set. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* 8xxx/ddr: add support to only compute the ddr sdram sizeHaiying Wang2011-01-193-9/+40
| | | | | | | | | This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in case that the DDR SDRAM is initialized in the 2nd stage uboot and should not be intialized again in the final stage uboot. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-01-17149-7586/+2041
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| * powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)Kumar Gala2011-01-144-2/+13
| | | | | | | | | | | | | | | | | | Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus monitor timeout. Set timeout to maximum to avoid. Based on a patch from Lan Chunhe <b25806@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080)Kumar Gala2011-01-144-0/+8
| | | | | | | | | | | | | | CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)Kumar Gala2011-01-144-1/+11
| | | | | | | | | | | | | | CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Bump up the CONFIG_SYS_BOOTM_LEN to 16M on FSL 85xx boardsKumar Gala2011-01-1414-11/+24
| | | | | | | | | | | | | | CONFIG_SYS_BOOTMAPSZ has been 16M on these boards for some time so we should also allow the kernel image to be up to 16M decompressed. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr codeKumar Gala2011-01-143-18/+25
| | | | | | | | | | | | | | | | Move the parsing of hwconfig to determine if to use spd into common code so we can share it across all boards instead of duplicating it everywhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)Roy Zang2011-01-143-0/+12
| | | | | | | | | | | | | | | | | | | | False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)Roy Zang2011-01-143-0/+9
| | | | | | | | | | | | | | | | | | | | | | The default value of the SRS, VS18 and VS30 and ADMAS fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one. Clear these bits out when we read HOSTCAPBLT. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)Jerry Huang2011-01-143-3/+16
| | | | | | | | | | | | | | | | | | Do not issue a manual asynchronous CMD12. Instead, use a (software) synchronous CMD12 or AUTOCMD12 to abort data transfer. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add SRIO support to P2020DSLi Yang2011-01-141-1/+23
| | | | | | | | | | | | | | | | The P2020 has 2 SRIO ports and they are useable on the P2020 DS board. Enable them using the common SRIO init code. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/86xx: Convert SBC8641 to use common SRIO init codeKumar Gala2011-01-142-7/+9
| | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| * powerpc/86xx: Convert MPC8641HPCN to use common SRIO init codeKumar Gala2011-01-142-21/+14
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/86xx: Enable common SRIO init codeKumar Gala2011-01-143-3/+15
| | | | | | | | | | | | | | | | Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Convert MPC8569MDS to use common SRIO init codeKumar Gala2011-01-142-6/+9
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Convert MPC8568MDS to use common SRIO init codeKumar Gala2011-01-142-6/+9
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Convert MPC8548CDS to use common SRIO init codeKumar Gala2011-01-143-16/+13
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/8xxx: Refactor SRIO initialization into common codeKumar Gala2011-01-149-56/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
| * fsl_pci: Update PCIe boot ouputPeter Tyser2011-01-142-19/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe codeKumar Gala2011-01-141-116/+2
| | | | | | | | | | | | | | Remove duplicated code in corenet_ds boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe codeKumar Gala2011-01-142-45/+13
| | | | | | | | | | | | | | | | | | Remove duplicated code in SBC8548 board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| * powerpc/86xx: Rework SBC8641 pci_init_board to use common FSL PCIe codeKumar Gala2011-01-142-65/+2
| | | | | | | | | | | | | | | | | | Remove duplicated code in SBC8641 board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> CC: Paul Gortmaker <paul.gortmaker@windriver.com>
| * powerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe codeKumar Gala2011-01-143-65/+19
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8610HPCD board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe codeKumar Gala2011-01-143-62/+4
| | | | | | | | | | | | | | | | Remove duplicated code in P1_P2_RDB boards and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-143-41/+3
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8569MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8568MDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-143-40/+16
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8568MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework TQM boards pci_init_board to use common FSL PCIe codeKumar Gala2011-01-142-37/+13
| | | | | | | | | | | | | | | | Remove duplicated code in TQM 85xx boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> CC: wd@denx.de
| * powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe codeKumar Gala2011-01-145-137/+13
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8xxx XES boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> CC: Peter Tyser <ptyser@xes-inc.com>
| * powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-143-42/+14
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8548CDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe codeKumar Gala2011-01-143-53/+3
| | | | | | | | | | | | | | | | Remove duplicated code in MPC8641HPCN board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8536DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-142-102/+17
| | | | | | | | | | | | | | Remove duplicated code in MPC8536DS board and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Rework MPC8544DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-143-84/+30
| | | | | | | | | | | | | | | | | | | | | | | | Remove duplicated code in MPC8544DS board and utilize the common fsl_pcie_init_ctrl(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. We don't use the full fsl_pcie_init_ctrl() since we have to handle PCIE3 specially to setup the additional memory map region and we utilize a single LAW to cover the controller. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-08-11 15:11:05 +0000