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* powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headersKumar Gala2011-01-191-21/+1
| | | | | | | | | | | Add new headers that capture common defines for a given SoC/processor rather than duplicating that information in board config.h and random other places. Eventually this should be handled by Kconfig & defconfigs Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/p2040: Add various p2040 specific informationKumar Gala2011-01-191-2/+2
| | | | | | | | | | Add P2040 SoC specific information: * SERDES Table * Added p2040 to cpu_type_list and SVR list * Added number of LAWs for p2040 * Set CONFIG_MAX_CPUS to 4 for p2040 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add Support for Freescale P1014 ProcessorPoonam Aggrwal2011-01-191-1/+1
| | | | | | | | | | | | The P1014 is similar to the P1010 processor with the following differences: - 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC) - no eCAN interface. (P1010 has 2 eCAN interfaces) - Two SGMII interface (P1010 has 3 SGMII) - No secure boot Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add Support for Freescale P1010 ProcessorPoonam Aggrwal2011-01-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Key Features include of the P1010: * e500v2 core frequency operation of 500 to 800 MHz * Power consumption less than 5.0 W at 800 MHz core speed * Dual SATA 3 Gbps controllers with integrated PHY * Dual PCI Express controllers * Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs) * TCP/IP acceleration and classification capabilities * IEEE 1588 support * Lossless flow control * RGMII, SGMII * DDR3 with support for a 32-bit data interface (40 bits including ECC), up to 800 MHz data rate 32/16-bit DDR3 memory controller * Dedicated security engine featuring trusted boot * TDM interface * Dual controller area networks (FlexCAN) controller * SD/MMC card controller supporting booting from Flash cards * USB 2.0 host and device controller with an on-chip, high-speed PHY * Integrated Flash controller (IFC) * Power Management Controller (PMC) * Four-channel, general-purpose DMA controller * I2C controller * Serial peripheral interface (SPI) controller with master and slave support * System timers including a periodic interrupt timer, real-time clock, software watchdog timer, and four general-purpose timers * Dual DUARTs Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-01-173-22/+202
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| * fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)Roy Zang2011-01-141-0/+5
| | | | | | | | | | | | | | | | | | | | | | The default value of the SRS, VS18 and VS30 and ADMAS fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one. Clear these bits out when we read HOSTCAPBLT. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)Jerry Huang2011-01-141-1/+9
| | | | | | | | | | | | | | | | | | Do not issue a manual asynchronous CMD12. Instead, use a (software) synchronous CMD12 or AUTOCMD12 to abort data transfer. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_pci: Update PCIe boot ouputPeter Tyser2011-01-141-18/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/fsl-pci: Add generic code to setup PCIe controllersKumar Gala2011-01-141-0/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixupKumar Gala2011-01-142-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
| * fsl_esdhc: Fix esdhc disabled problem on some platformsChenhui Zhao2011-01-141-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | Some new platform's esdhc pins don't share with other function. The eSDHC shouldn't be disabled, even if "esdhc" isn't defined in hwconfig env variable. Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem. Signed-off-by: Chenhui Zhao <b26998@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2011-01-171-22/+90
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| * | pca953x: support 16-pin devicesChris Packham2011-01-101-22/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for for the PCA9535/PCA9539 family of gpio devices which have 16 output pins. To let the driver know which devices are 16-pin it is necessary to define CONFIG_SYS_I2C_PCA953X_WIDTH in your board config file. This is used to create an array of {chip, ngpio} tuples that are used to determine the width of a particular chip. For backwards compatibility it is assumed that any chip not defined in CONFIG_SYS_I2C_PCA953X_WIDTH has 8 pins. Acked-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
* | | mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()Lei Wen2011-01-122-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch sync with David's patch on Linux for handling nand_scan_ident. commit 5e81e88a4c140586d9212999cea683bcd66a15c6 Author: David Woodhouse <David.Woodhouse@intel.com> Date: Fri Feb 26 18:32:56 2010 +0000 mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident() Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Lei Wen <leiwen@marvell.com>
* | | NAND: add the ability to directly write yaffs imageLei Wen2011-01-121-8/+55
| | | | | | | | | | | | | | | | | | | | | This patch add addition suffix to nand write to give the uboot the power to directly burn the yaffs image to nand. Signed-off-by: Lei Wen <leiwen@marvell.com>
* | | nand: fix bug with multiple NAND devices if CONFIG_MTD_DEVICE is defined.Alexander Holler2011-01-121-1/+1
| |/ |/| | | | | | | | | The variable i has to be static, otherwise it would be always zero. Signed-off-by: Alexander Holler <holler@ahsoftware.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2011-01-122-127/+763
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| * | sh: serial_sh: Fix build in serial_shNobuhiro Iwamatsu2011-01-111-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The serial of ap325rxa has it of two kinds, and the setting of the clock is different. Because there was a problem by function to judge serial kind, this revised it. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | sh: sh7722: Fix multiple definition of PSDR in serial_shNobuhiro Iwamatsu2011-01-111-0/+1
| | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | sh: serial: Update serial driver for SHNobuhiro Iwamatsu2011-01-112-127/+762
| | | | | | | | | | | | | | | | | | | | | | | | I copied the setting of CPU from Linux kernel and commonized it. By this, we can communalize a kernel and information. And added the serial setting of many CPU's. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | add AM29F400BB to table of supported legacy flashsDavid Müller2011-01-111-0/+18
|/ / | | | | | | | | Signed-off-by: David Mueller <d.mueller@elsoft.ch> Signed-off-by: Stefan Roese <sr@denx.de>
* | LAN91C*: Change chip names to fit the eth_device struct sizeYanjun Yang2011-01-101-2/+2
| | | | | | | | | | | | | | | | The eth_device.name field length is limited by NAMESIZE, which is 16 defined in include/net.h. Unfortunately, two of the names in lan91c96.c are beyond that. Signed-off-by: YanJun Yang <yangyj.ee@gmail.com>
* | ftgmac100: support of gigabit eth ftgmac100Macpaul Lin2011-01-093-0/+826
|/ | | | | | | Add Faraday's ftgmac100 (gigabit ethernet) MAC controller's driver. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* miiphy: convert to linux/mii.hMike Frysinger2011-01-0918-200/+179
| | | | | | | | The include/miiphy.h header duplicates a lot of things from linux/mii.h. So punt all the things that overlap to keep the API simple and to make merging between U-Boot and Linux simpler. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* cfi_flash: avoid flash_verbose when possibleMike Frysinger2011-01-091-0/+6
| | | | | | | The flash_verbose logic is only used by the CFI MTD layer, so if we aren't using that, disable the logic completely. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'next' of ../nextWolfgang Denk2010-12-2222-70/+1313
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| * MTD/NAND: fix nand_base.c to use get_timer() correctlyReinhard Meyer2010-12-171-6/+9
| | | | | | | | | | | | | | | | | | This is part of the timer cleanup effort. In the future we only use get_timer() in its intended way to program timeout loops. reset_timer() shall not be used anymore. Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
| * nand: constify id/manu tablesMike Frysinger2010-12-172-5/+5
| | | | | | | | | | | | These id tables need not be writable. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * RTC driver for PT7C4338 chip.Priyanka Jain2010-12-172-0/+145
| | | | | | | | | | | | | | | | | | | | | | PT7C4338 chip is being manufactured by Pericom Technology Inc. It is a serial real-time clock which provides: 1)Low-power clock/calendar. 2)Programmable square-wave output. It has 56 bytes of nonvolatile RAM. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: Timur Tabi <timur@freescale.com>
| * Merge branch 'next' of git://www.denx.de/git/u-boot-cfi-flash into nextWolfgang Denk2010-12-171-3/+58
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| | * cfi_flash: Add optional config register write to cfi-detectionStefan Roese2010-12-171-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the possibility to (optinally) write to the flash configuration register. The Intel style CFI chips support such a register that can be used to configure the operation mode to a non-default value. This method will be used by the t3corp board, which needs to configure the DS617 Xilinx flash for async read mode. Signed-off-by: Stefan Roese <sr@denx.de>
| | * cfi_flash: Use flash_read32() in sector_erased()Stefan Roese2010-12-171-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function sector_erased() is modified to not use pointer access, but to use the correct accessor functions. This fixes a problem on the t3corp board with the Xilinx DS617 flash chips. Here a board specific accessor function is needed to read from flash in 32bit mode. This patch enables such an operation mode. Signed-off-by: Stefan Roese <sr@denx.de>
| | * cfi_flash: Fix problems with status/id read modeStefan Roese2010-12-171-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds some calls to set the flash chip in the read-status- register- or read-id-mode before the corresponding register is read back. This problem was detected while porting the common CFI driver to support the Xilinx DS617 flash chips. Signed-off-by: Stefan Roese <sr@denx.de>
| * | sf: winbond: add support for W25Q16/32/128 partsWojtek Skulski2010-12-171-10/+29
| | | | | | | | | | | | | | | | | | | | | While we're here, cut out the useless id defines too. Signed-off-by: Wojtek Skulski <skulski@pas.rochester.edu> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | sf: new driver for EON devicesChong Huang2010-12-174-0/+280
| |/ | | | | | | | | | | Signed-off-by: Chong Huang <chuang@ucrobotics.com> Signed-off-by: Haitao Zhang <minipanda@linuxrobot.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Serial: Add UART support for Marvell ARMADA 100 SoCs.Prafulla Wadaskar2010-12-161-2/+3
| | | | | | | | | | | | | | | | ARMADA 100 SoCs has NS16550 compatible UART peripheral This patch enables the same for ARMADA100 platforms Signed-off-by: Mahavir Jain <mjain@marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macroPrafulla Wadaskar2010-12-161-2/+6
| | | | | | | | | | | | | | | | | | | | On some processors this ier register configuration is different for ex. Marvell Armada100 This patch introduce CONFIG_SYS_NS16550_IER macro support to unconditionally initialize this register. Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * gpio: Add Multi-Function-Pin configuration driver for Marvell SoCsPrafulla Wadaskar2010-12-162-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the Marvell SoCs has Multi Function Pin (MFP) configuration registers For ex. ARMADA100. These registers are programmed to expose the specific functionality associated with respective SoC Pins This driver provides configuration APIs, using them, configuration need to be done in board specific code for ex- following code configures MFPs 107 and 108 for UART_TX/RX functionality int board_early_init_f(void) { u32 mfp_cfg[] = { /* Console on UART1 */ MFP107_UART1_RXD, MFP108_UART1_TXD, MFP_EOC /*End of configureation*/ }; /* configure MFP's */ mfp_config(mfp_cfg); return 0; } Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * Merge branch 'master' of ../master into nextWolfgang Denk2010-12-168-27/+536
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| * | OMAP3: SPI driverDirk Behme2010-12-113-0/+470
| | | | | | | | | | | | | | | | | | CC: Ruslan N. Araslanov <byaaka@yandex.ru> Signed-off-by: Ruslan Araslanov <ruslan.araslanov@vitecmm.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | ARMV7: OMAP4: twl6030 add battery charging supportBalaji T K2010-12-111-2/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add battery charging support twl6030 driver. Add support for battery voltage and current measurements. Add command to get battery status and start/stop battery charging from USB. Signed-off-by: Balaji T K <balajitk@ti.com> Tested-by: Steve Sakoman <steve.sakoman@linaro.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | Merge branch 'next' of git://git.denx.de/u-boot-arm into nextWolfgang Denk2010-11-301-1/+40
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| | * | da850: Add RMII support for EMACSudhakar Rajashekhara2010-11-301-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is a port of the work by Sudhakar Rajeshekhara in commit ab3effbcad8851cc65dc5241a01c064d2030a3b2 of git://arago-project.org/git/people/sandeep/u-boot-davinci.git. The da850 UI board has on it an RMII PHY which can be used if the MDC line to the MII PHY on the baseboard is disabled and the RMII PHY is enabled by configuring the values of some GPIO pins on the IO expander of the UI board. This patch implements disabling that line via GPIO2[6], configuring the UI board's IO expander and setting only the pinmux settings that are needed for RMII operation. Tested on da850evm by adding a define for CONFIG_DRIVER_TI_EMAC_USE_RMII. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> CC: Sandeep Paulraj <s-paulraj@ti.com> CC: Ben Warren <biggerbadderben@gmail.com> CC: Mike Frysinger <vapier@gentoo.org> CC: Sughosh Ganu <urwithsughosh@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | pl01x: use C structs and readl/writelRabin Vincent2010-11-302-39/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use C structs for registers, and use readl/writel instead of custom accessors. Acked-by: Michael Brandt <michael.brandt@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
| * | | add Xilinx_abort_fn to Xilinx_Spartan3_Slave_Serial_fnsWolfgang Wegner2010-11-301-0/+6
| |/ / | | | | | | | | | | | | | | | | | | | | | Currently the hardware was left in an undefined state in case Spartan3 serial load failed. This patch adds Xilinx_abort_fn to give the board a possibility to clean up in this case. Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
* | | Move DECLARE_GLOBAL_DATA_PTR to file scopeJohn Rigby2010-12-214-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It can be optimised out by the compiler otherwise resulting in obscure errors like a board not booting. This has been documented in README since 2006 when these were first fixed up for GCC 4.x. Signed-off-by: John Rigby <john.rigby@linaro.org> Fix some additional places. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-By: Albert ARIBAUD <albert.aribaud@free.fr>
* | | fsl_esdhc: Fix the voltage validation processLi Yang2010-12-181-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code use all the voltage range support by the host controller to do the validation. This will cause problem when the host supports Low Voltage Range. Change the validation voltage to be based on board setup. Signed-off-by: Li Yang <leoli@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | fsl_esdhc: Fix max clock frequencyJerry Huang2010-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The max clock of MMC is 52MHz Signed-off-by: Jerry Huang <Changm-Ming.Huang@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | fsl_esdhc: Use mmc_set_clock to set initial speedJerry Huang2010-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After booting the u-boot, and first using some SD card (such as Sandisk 2G SD card), because the field 'clock' of struct mmc is zero, this will cause the read transfer is always active and SDHC DATA line is always active, therefore, driver can't handle the next command. Therefore, we use mmc_set_clock to setup both the data structure and HW to the initial clock speed of 400000Hz. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | video/mx3fb: fix clock dividerStefano Babic2010-12-171-1/+1
| |/ |/| | | | | | | | | | | | | | | | | | | Fix clock divider for COM57H5M10XRC display. The previous setting caused flicker. Tested on Qong (EVBLite with COM57H5M10XRC). Signed-off-by: Stefano Babic <sbabic@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
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