From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/sandburst/common/flash.c | 12 ++++++------ board/sandburst/common/ppc440gx_i2c.c | 20 ++++++++++---------- board/sandburst/common/ppc440gx_i2c.h | 2 +- board/sandburst/common/sb_common.c | 24 ++++++++++++------------ board/sandburst/karef/config.mk | 2 +- board/sandburst/karef/init.S | 16 ++++++++-------- board/sandburst/karef/karef.c | 22 +++++++++++----------- board/sandburst/metrobox/config.mk | 2 +- board/sandburst/metrobox/init.S | 16 ++++++++-------- board/sandburst/metrobox/metrobox.c | 16 ++++++++-------- 10 files changed, 66 insertions(+), 66 deletions(-) (limited to 'board/sandburst') diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c index 762fb73..dd712e3 100644 --- a/board/sandburst/common/flash.c +++ b/board/sandburst/common/flash.c @@ -41,9 +41,9 @@ #endif /* DEBUG */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { +static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { {0xfff80000} /* Boot Flash */ }; @@ -65,7 +65,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data); unsigned long flash_init (void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; unsigned short index = 0; int i; @@ -74,7 +74,7 @@ unsigned long flash_init (void) DEBUGF("FLASH: Index: %d\n", index); /* Init: no FLASHes known */ - for (i=0; i CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return -1; } @@ -502,7 +502,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c index 1e3dffb..9af6b8d 100644 --- a/board/sandburst/common/ppc440gx_i2c.c +++ b/board/sandburst/common/ppc440gx_i2c.c @@ -43,8 +43,8 @@ #define IIC_NOK_TOUT 6 /* Transfer timeout */ #define IIC_TIMEOUT 1 /* 1 second */ -#if defined(CFG_I2C_NOPROBES) -static uchar i2c_no_probes[] = CFG_I2C_NOPROBES; +#if defined(CONFIG_SYS_I2C_NOPROBES) +static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; #endif static void _i2c_bus1_reset (void) @@ -105,7 +105,7 @@ void i2c1_init (int speed, int slaveadd) unsigned long freqOPB; int val, divisor; -#ifdef CFG_I2C_INIT_BOARD +#ifdef CONFIG_SYS_I2C_INIT_BOARD /* call board specific i2c bus reset routine before accessing the */ /* environment, which might be in a chip on that bus. For details */ /* about this problem see doc/I2C_Edge_Conditions. */ @@ -384,7 +384,7 @@ int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len) } -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of @@ -397,7 +397,7 @@ int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len) * hidden in the chip address. */ if( alen > 0 ) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) { printf( "I2c read: failed %d\n", ret); @@ -422,7 +422,7 @@ int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len) xaddr[3] = addr & 0xFF; } -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of @@ -435,7 +435,7 @@ int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len) * hidden in the chip address. */ if( alen > 0 ) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); @@ -465,13 +465,13 @@ void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val) int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int j; -#if defined(CFG_I2C_NOPROBES) +#if defined(CONFIG_SYS_I2C_NOPROBES) int k, skip; #endif puts ("Valid chip addresses:"); for(j = 0; j < 128; j++) { -#if defined(CFG_I2C_NOPROBES) +#if defined(CONFIG_SYS_I2C_NOPROBES) skip = 0; for (k = 0; k < sizeof(i2c_no_probes); k++){ if (j == i2c_no_probes[k]){ @@ -488,7 +488,7 @@ int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } putc ('\n'); -#if defined(CFG_I2C_NOPROBES) +#if defined(CONFIG_SYS_I2C_NOPROBES) puts ("Excluded chip addresses:"); for( k = 0; k < sizeof(i2c_no_probes); k++ ) printf(" %02X", i2c_no_probes[k] ); diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h index 10000f5..328abd6 100644 --- a/board/sandburst/common/ppc440gx_i2c.h +++ b/board/sandburst/common/ppc440gx_i2c.h @@ -32,7 +32,7 @@ #ifdef CONFIG_HARD_I2C -#define I2C_BUS1_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000500) +#define I2C_BUS1_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500) #define I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR #define IIC_MDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF) #define IIC_SDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSDBUF) diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index 51b1c75..f6ea16f 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -43,7 +43,7 @@ int sbcommon_get_master(void) { ppc440_gpio_regs_t *gpio_regs; - gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) { return 0; @@ -63,7 +63,7 @@ int sbcommon_secondary_present(void) { ppc440_gpio_regs_t *gpio_regs; - gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES) return 0; @@ -84,7 +84,7 @@ unsigned short sbcommon_get_serial_number(void) /* Get the board serial number from eeprom */ /* Initialize I2C */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* Read 256 bytes in EEPROM */ i2c_read (0x50, 0, 1, buff, 0x100); @@ -218,11 +218,11 @@ phys_size_t initdram (int board_type) * * ************************************************************************/ -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("Testing SDRAM: "); @@ -340,7 +340,7 @@ int pci_pre_init(struct pci_controller * hose ) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { /*--------------------------------------------------------------------------+ @@ -355,7 +355,7 @@ void pci_target_init(struct pci_controller * hose ) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); out32r( PCIX0_PIM0LAH, 0 ); out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); @@ -364,12 +364,12 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* @@ -405,7 +405,7 @@ void board_get_enetaddr (uchar * enet) if (0 == macaddr_idx) { /* Initialize I2C */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* Read 256 bytes in EEPROM */ i2c_read (0x50, 0, 1, buff, 0x100); diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk index 65c1e48..f2f94c5 100644 --- a/board/sandburst/karef/config.mk +++ b/board/sandburst/karef/config.mk @@ -39,5 +39,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S index b1d47a4..3198dfd 100644 --- a/board/sandburst/karef/init.S +++ b/board/sandburst/karef/init.S @@ -90,12 +90,12 @@ tlbtab: tlbtab_start tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) tlbtab_end diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c index 72ce976..7909d34 100644 --- a/board/sandburst/karef/karef.c +++ b/board/sandburst/karef/karef.c @@ -65,7 +65,7 @@ int board_early_init_f (void) mtsdr(sdr_pfc0, 0x00103E00); /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; @@ -93,7 +93,7 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | + mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. @@ -259,8 +259,8 @@ int checkboard (void) KAREF_FPGA_REGS_ST *karef_ps; OFEM_FPGA_REGS_ST *ofem_ps; - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; scan_id = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK) @@ -319,7 +319,7 @@ int checkboard (void) /* Fix the ack in the bme 32 */ udelay(5000); - out32(CFG_BME32_BASE + 0x0000000C, 0x00000001); + out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001); asm("eieio"); @@ -335,7 +335,7 @@ int misc_init_f (void) { /* Turn on i2c bus 1 */ puts ("I2C1: "); - i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); puts ("ready\n"); /* Turn on fans 3 & 4 */ @@ -397,8 +397,8 @@ int misc_init_r (void) } if( getenv("fakeled")) { - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK; karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK; setenv("bootdelay", "-1"); @@ -417,7 +417,7 @@ void ide_set_reset(int on) { KAREF_FPGA_REGS_ST *karef_ps; /* TODO: ide reset */ - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; if (on) { karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; @@ -440,7 +440,7 @@ void fpga_init(void) /* Ensure we have power all around */ udelay(500); - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; tmp = SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK | SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK | @@ -470,7 +470,7 @@ void fpga_init(void) SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK | SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK; - ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; ofem_ps->reset_ul = tmp; ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT; diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk index 91aee2f..565e826 100644 --- a/board/sandburst/metrobox/config.mk +++ b/board/sandburst/metrobox/config.mk @@ -34,5 +34,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S index e398f00..ccdec46 100644 --- a/board/sandburst/metrobox/init.S +++ b/board/sandburst/metrobox/init.S @@ -88,12 +88,12 @@ tlbtab: tlbtab_start tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) tlbtab_end diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c index c38850d..c3c4459 100644 --- a/board/sandburst/metrobox/metrobox.c +++ b/board/sandburst/metrobox/metrobox.c @@ -55,7 +55,7 @@ int board_early_init_f (void) mtsdr(sdr_pfc0, 0x00103E00); /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; @@ -83,7 +83,7 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | + mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. @@ -246,7 +246,7 @@ int checkboard (void) unsigned char opto_rev, opto_id; OPTO_FPGA_REGS_ST *opto_ps; - opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; opto_rev = (unsigned char)((opto_ps->revision_ul & SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) @@ -286,7 +286,7 @@ int checkboard (void) /* Fix the ack in the bme 32 */ udelay(5000); - out32(CFG_BME32_BASE + 0x0000000C, 0x00000001); + out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001); asm("eieio"); @@ -302,7 +302,7 @@ int misc_init_f (void) { /* Turn on i2c bus 1 */ puts ("I2C1: "); - i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); puts ("ready\n"); /* Turn on fans */ @@ -323,7 +323,7 @@ int misc_init_r (void) unsigned char opto_rev; OPTO_FPGA_REGS_ST *opto_ps; - opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; if(NULL != getenv("secondserial")) { puts("secondserial is set, switching to second serial port\n"); @@ -387,7 +387,7 @@ int misc_init_r (void) void ide_set_reset(int on) { OPTO_FPGA_REGS_ST *opto_ps; - opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; if (on) { /* assert RESET */ opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; @@ -412,7 +412,7 @@ void fpga_init(void) /* * Take appropriate hw bits out of reset */ - opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; tmp = SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK | -- cgit v1.1