From 92988a21ad4c4c9504295ccb580c9f806134471b Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Mon, 26 Mar 2012 20:55:28 +0200 Subject: added boot script files to repository --- board/syteco/jadecpu/Makefile | 55 -------- board/syteco/jadecpu/config.mk | 1 - board/syteco/jadecpu/jadecpu.c | 177 ----------------------- board/syteco/jadecpu/lowlevel_init.S | 265 ----------------------------------- 4 files changed, 498 deletions(-) delete mode 100644 board/syteco/jadecpu/Makefile delete mode 100644 board/syteco/jadecpu/config.mk delete mode 100644 board/syteco/jadecpu/jadecpu.c delete mode 100644 board/syteco/jadecpu/lowlevel_init.S (limited to 'board/syteco') diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile deleted file mode 100644 index 30818d2..0000000 --- a/board/syteco/jadecpu/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Stelian Pop -# Lead Tech Design -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += jadecpu.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/syteco/jadecpu/config.mk b/board/syteco/jadecpu/config.mk deleted file mode 100644 index 617603d..0000000 --- a/board/syteco/jadecpu/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x10000000 diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c deleted file mode 100644 index 69476f8..0000000 --- a/board/syteco/jadecpu/jadecpu.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * (c) 2010 Graf-Syteco, Matthias Weisser - * - * - * (C) Copyright 2007, mycable GmbH - * Carsten Schneider , Alexander Bigga - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *) - MB86R0x_CCNT_BASE; - - /* We select mode 0 for group 2 and mode 1 for group 4 */ - writel(0x00000010, &ccnt->cmux_md); - - gd->flags = 0; - gd->bd->bi_arch_number = MACH_TYPE_JADECPU; - gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000; - - icache_enable(); - - return 0; -} - -static void setup_display_power(uint32_t pwr_bit, char *pwm_opts, - unsigned long pwm_base) -{ - struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) - MB86R0x_GPIO_BASE; - struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base; - const char *e; - - writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2); - - e = getenv(pwm_opts); - if (e != NULL) { - const char *s; - uint32_t freq, init; - - freq = 0; - init = 0; - - s = strchr(e, 'f'); - if (s != NULL) - freq = simple_strtol(s + 2, NULL, 0); - - s = strchr(e, 'i'); - if (s != NULL) - init = simple_strtol(s + 2, NULL, 0); - - if (freq > 0) { - writel(CONFIG_MB86R0x_IOCLK / 1000 / freq, - &pwm->bcr); - writel(1002, &pwm->tpr); - writel(1, &pwm->pr); - writel(init * 10 + 1, &pwm->dr); - writel(1, &pwm->cr); - writel(1, &pwm->sr); - } - } -} - -int board_late_init(void) -{ - struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) - MB86R0x_GPIO_BASE; - uint32_t in_word; - -#ifdef CONFIG_VIDEO_MB86R0xGDC - /* Check if we have valid display settings and turn on power if so */ - /* Display 0 */ - if (getenv("gs_dsp_0_param") || getenv("videomode")) - setup_display_power((1 << 3), "gs_dsp_0_pwm", - MB86R0x_PWM0_BASE); - - /* The corresponding GPIO is always an output */ - writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2); - - /* Display 1 */ - if (getenv("gs_dsp_1_param") || getenv("videomode1")) - setup_display_power((1 << 4), "gs_dsp_1_pwm", - MB86R0x_PWM1_BASE); - - /* The corresponding GPIO is always an output */ - writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2); -#endif /* CONFIG_VIDEO_MB86R0xGDC */ - - /* 5V enable */ - writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1); - writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1); - - /* We have special boot options if told by GPIOs */ - in_word = readl(&gpio->gpdr1); - - if ((in_word & 0xC0) == 0xC0) { - setenv("stdin", "serial"); - setenv("stdout", "serial"); - setenv("stderr", "serial"); - setenv("preboot", "run gs_slow_boot"); - } else if ((in_word & 0xC0) != 0) { - setenv("stdout", "vga"); - setenv("gs_bootcmd", "mw.l 0x40000000 0 1024; usb start;" - "fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;" - "bootelf 0x40000000; bootelf 0x10080000"); - setenv("preboot", "run gs_slow_boot"); - } else { - setenv("stdin", "serial"); - setenv("stdout", "serial"); - setenv("stderr", "serial"); - if (getenv("gs_devel")) { - setenv("preboot", "run gs_slow_boot"); - } else { - setenv("gs_bootcmd", "bootelf 0x10080000"); - setenv("preboot", "run gs_fast_boot"); - } - } - - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -/* - * DRAM configuration - */ -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM, - PHYS_SDRAM_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = gd->ram_size; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S deleted file mode 100644 index 5ad4dce..0000000 --- a/board/syteco/jadecpu/lowlevel_init.S +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2007, mycable GmbH - * Carsten Schneider , Alexander Bigga - * - * (C) Copyright 2003, ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -/* Set up the platform, once the cpu has been initialized */ -.globl lowlevel_init -lowlevel_init: -/* - * Initialize Clock Reset Generator (CRG) - */ - - ldr r0, =MB86R0x_CRG_BASE - - /* Not change the initial value that is set by external pin.*/ -WAIT_PLL: - ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */ - tst r2, #MB86R0x_CRG_CRPR_PLLRDY - beq WAIT_PLL - - /* Set clock gate control */ - ldr r1, =CONFIG_SYS_CRG_CRHA_INIT - str r1, [r0, #CRG_CRHA] - ldr r1, =CONFIG_SYS_CRG_CRPA_INIT - str r1, [r0, #CRG_CRPA] - ldr r1, =CONFIG_SYS_CRG_CRPB_INIT - str r1, [r0, #CRG_CRPB] - ldr r1, =CONFIG_SYS_CRG_CRHB_INIT - str r1, [r0, #CRG_CRHB] - ldr r1, =CONFIG_SYS_CRG_CRAM_INIT - str r1, [r0, #CRG_CRAM] - -/* - * Initialize External Bus Interface - */ - ldr r0, =MB86R0x_MEMC_BASE - - ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT - str r1, [r0, #MEMC_MCFMODE0] - ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT - str r1, [r0, #MEMC_MCFMODE2] - ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT - str r1, [r0, #MEMC_MCFMODE4] - - ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT - str r1, [r0, #MEMC_MCFTIM0] - ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT - str r1, [r0, #MEMC_MCFTIM2] - ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT - str r1, [r0, #MEMC_MCFTIM4] - - ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT - str r1, [r0, #MEMC_MCFAREA0] - ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT - str r1, [r0, #MEMC_MCFAREA2] - ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT - str r1, [r0, #MEMC_MCFAREA4] - -/* - * Initialize DDR2 Controller - */ - - /* Wait for PLL LOCK up time or more */ - wait_timer 20 - - /* - * (2) Initialize DDRIF - */ - ldr r0, =MB86R0x_DDR2_BASE - ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT - strh r1, [r0, #DDR2_DRIMS] - - /* - * (3) Wait for 20MCKPs(120nsec) or more - */ - wait_timer 20 - - /* - * (4) IRESET/IUSRRST release - */ - ldr r0, =MB86R0x_CCNT_BASE - ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1 - str r1, [r0, #CCNT_CDCRC] - - /* - * (5) Wait for 20MCKPs(120nsec) or more - */ - wait_timer 20 - - /* - * (6) IDLLRST release - */ - ldr r0, =MB86R0x_CCNT_BASE - ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2 - str r1, [r0, #CCNT_CDCRC] - - /* - * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec) - */ - wait_timer 33536 - - /* - * (9) MCKE ON - */ - ldr r0, =MB86R0x_DDR2_BASE - ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT - strh r1, [r0, #DDR2_DRCA] - ldr r1, =MB86R0x_DDR2_DRCI_INIT - strh r1, [r0, #DDR2_DRIC] - - /* - * (10) Initialize SDRAM - */ - - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - wait_timer 67 /* 400ns wait */ - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - wait_timer 200 - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - wait_timer 18 /* 105ns wait */ - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - wait_timer 200 /* MRS to OCD: 200clock */ - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT - strh r1, [r0, #DDR2_DRCM] - - ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT - strh r1, [r0, #DDR2_DRCST1] - - ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT - strh r1, [r0, #DDR2_DRCST2] - - ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT - strh r1, [r0, #DDR2_DRCR] - - ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT - strh r1, [r0, #DDR2_DRCF] - - ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT - strh r1, [r0, #DDR2_DRASR] - - /* - * (11) ODT setting - */ - ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT - strh r1, [r0, #DDR2_DROBS] - ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT - strh r1, [r0, #DDR2_DROABA] - ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT - strh r1, [r0, #DDR2_DRIBSODT1] - - /* - * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode - */ - ldr r1, =CONFIG_SYS_DDR2_DROS_INIT - strh r1, [r0, #DDR2_DROS] - ldr r1, =MB86R0x_DDR2_DRCI_NORMAL - strh r1, [r0, #DDR2_DRIC] - - mov pc, lr -- cgit v1.1