From 9acb626fc145e7327f94fd77f927dce08dd978a8 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 20 Apr 2006 08:42:42 +0200 Subject: Add MCF5282 support (without preloader) relocate ichache_State to ram u-boot can run from internal flash Add EB+MCF-EV123 board support. Add m68k Boards to MAKEALL Patch from Jens Scharsig, 08 Aug 2005 --- doc/README.m68k | 66 +++++++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 48 insertions(+), 18 deletions(-) (limited to 'doc') diff --git a/doc/README.m68k b/doc/README.m68k index d5accdd..6dea2b5 100644 --- a/doc/README.m68k +++ b/doc/README.m68k @@ -1,7 +1,12 @@ U-Boot for Motorola M68K -Last Update: January 12, 2004 +==================================================================== +History + +August 08,2005; Jens Scharsig + MCF5282 implementation without preloader +January 12, 2004; ==================================================================== This file contains status information for the port of U-Boot to the @@ -33,16 +38,8 @@ CPU specific code is located in: cpu/mcf52x2 ----------------------------- CPU specific code is located in: cpu/mcf52x2 -At the moment the code isn't fully implemented and still needs a pre-loader! -The preloader must initialize the processor and then start u-boot. The board -must be configured for a pre-loader (see 4.1) - -For the preloader, please see -http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html - -U-boot is configured to run at 0x20000 at default. This can be configured by -change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in -include/configs/M5282EVB.h. +The MCF5282 Port no longer needs a preloader and can place in external or +internal FLASH. 3. SUPPORTED BOARDs @@ -67,6 +64,27 @@ Board specific code is located in: board/m5282evb To configure the board, type: make M5272C3_config +At the moment the code isn't fully implemented and still needs a pre-loader! +The preloader must initialize the processor and then start u-boot. The board +must be configured for a pre-loader (see 4.1) + +For the preloader, please see +http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html + +U-boot is configured to run at 0x20000 at default. This can be configured by +change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in +include/configs/M5282EVB.h. + +3.2 BuS EB+MCF-EV123 +--------------------- + +Board specific code is located in: board/bus/EB+MCF-EV123 + +To configure the board, type: + +make EB+MCF-EV123_config for external FLASH +make EB+MCF-EV123_internal_config for internal FLASH + 4. CONFIGURATION OPTIONS/SETTINGS ---------------------------------- @@ -80,7 +98,6 @@ be compiled in. The start address of u-boot must be adjusted in the boards config header file (CFG_MONITOR_BASE) and Makefile (TEXT_BASE) to the load address. - 4.1 MCF5272 specific Options/Settings ------------------------------------- @@ -123,14 +140,27 @@ CFG_INT_FLASH_BASE CFG_ENET_BD_BASE -- defines the base addres of the FEC buffer descriptors +CFG_MFD + -- defines the PLL Multiplication Factor Devider + (see table 9-4 of MCF user manual) +CFG_RFD -- defines the PLL Reduce Frecuency Devider + (see table 9-4 of MCF user manual) + +CFG_CSx_BASE -- defines the base address of chip select x +CFG_CSx_SIZE -- defines the memory size (address range) of chip select x +CFG_CSx_WIDTH -- defines the bus with of chip select x +CFG_CSx_RO -- if set to 0 chip select x is read/wirte + else chipselct is read only +CFG_CSx_WS -- defines the number of wait states of chip select x + +CFG_PxDDR -- defines the contents of the Data Direction Registers +CFG_PxDAT -- defines the contents of the Data Registers +CFG_PXCNT -- defines the contents of the Port Configuration Registers + +CFG_PxPAR -- defines the function of ports + 5. COMPILER ----------- To create U-Boot the gcc-2.95.3 compiler set (m68k-elf-20030314) from uClinux.org was used. You can download it from: http://www.uclinux.org/pub/uClinux/m68k-elf-tools/ - - -Regards, - -Josef - -- cgit v1.1 From c12cffc543df621c162ba26e012c7f4ab0af496e Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 16 Jun 2006 17:04:45 +0200 Subject: Add support for CONFIG_SERIAL_MULTI on MPC5xxx Patch by Martin Krause, 8 Jun 2006 This patch supports two serial consoles on boards with a MPC5xxx CPU. The console can be switched at runtime by setting stdin, stdout and stderr to the desired serial interface (serial0 or serial1). The PSCs to be used as console port are definded by CONFIG_PSC_CONSOLE and CONFIG_PSC_CONSOLE2. See README.serial_multi for details. --- doc/README.serial_multi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'doc') diff --git a/doc/README.serial_multi b/doc/README.serial_multi index a8d48fc..40f7815 100644 --- a/doc/README.serial_multi +++ b/doc/README.serial_multi @@ -52,3 +52,29 @@ PPC4XX Specific setenv stdout serial0 setenv stderr serial0 setenv stdin serial0 + +MPC5xxx Specific +================ + +Up to two PSCs can be used as console. + +Support for hardware handshake has not been implemented yet. + +*) The first (default) console port is defined by: + #define CONFIG_PSC_CONSOLE + +*) The second (alternative) console port is defined by: + #define CONFIG_PSC_CONSOLE2 + +*) Commands to switch to the second console: + setenv stdout serial1 + setenv stderr serial1 + setenv stdin serial1 + +*) Commands to switch to the first console: + setenv stdout serial0 + setenv stderr serial0 + setenv stdin serial0 + +*) If a file descriptor is set to "serial" then the + current serial device will be used. -- cgit v1.1 From 193dd958344f9c27ed026d2e3db2a1a0a9eb5631 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 27 Jul 2006 16:14:05 +0200 Subject: AMCC bamboo (440EP) U-Boot image reduced to 384kbyte Please see doc/README.bamboo for details. Patch by Stefan Roese, 27 Jul 2006 --- doc/README.bamboo | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 doc/README.bamboo (limited to 'doc') diff --git a/doc/README.bamboo b/doc/README.bamboo new file mode 100644 index 0000000..b50be01 --- /dev/null +++ b/doc/README.bamboo @@ -0,0 +1,15 @@ +The configuration for the AMCC 440EP eval board "Bamboo" was changed +to only use 384 kbytes of FLASH for the U-Boot image. This way the +redundant environment can be saved in the remaining 2 sectors of the +same flash chip. + +Caution: With an upgrade from an earlier U-Boot version the current +environment will be erased since the environment is now saved in +different sectors. By using the following command the environment can +be saved after upgrading the U-Boot image and *before* resetting the +board: + +setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \ + 'cp.b FFF60000 FFF80000 20000' + +2006-07-27, Stefan Roese -- cgit v1.1 From a2c95a72247990dee9a03b26b4dc9fc0182c97ed Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 28 Jul 2006 18:34:58 +0200 Subject: PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance AMCC suggested to set the PMU bit to 0 for best performace on the PPC440 DDR controller. Please see doc/README.440-DDR-performance for details. Patch by Stefan Roese, 28 Jul 2006 --- doc/README.440-DDR-performance | 90 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 doc/README.440-DDR-performance (limited to 'doc') diff --git a/doc/README.440-DDR-performance b/doc/README.440-DDR-performance new file mode 100644 index 0000000..17bc747 --- /dev/null +++ b/doc/README.440-DDR-performance @@ -0,0 +1,90 @@ +AMCC suggested to set the PMU bit to 0 for best performace on the +PPC440 DDR controller. The 440er common DDR setup files (sdram.c & +spd_sdram.c) are changed accordingly. So all 440er boards using +these setup routines will automatically receive this performance +increase. + +Please see below some benchmarks done by AMCC to demonstrate this +performance changes: + + +---------------------------------------- +SDRAM0_CFG0[PMU] = 1 (U-boot default for Bamboo, Yosemite and Yellowstone) +---------------------------------------- +Stream benchmark results +------------------------------------------------------------- +This system uses 8 bytes per DOUBLE PRECISION word. +------------------------------------------------------------- +Array size = 2000000, Offset = 0 +Total memory required = 45.8 MB. +Each test is run 10 times, but only +the *best* time for each is used. +------------------------------------------------------------- +Your clock granularity/precision appears to be 1 microseconds. +Each test below will take on the order of 112345 microseconds. + (= 112345 clock ticks) +Increase the size of the arrays if this shows that you are not getting +at least 20 clock ticks per test. +------------------------------------------------------------- +WARNING -- The above is only a rough guideline. +For best results, please be sure you know the precision of your system +timer. +------------------------------------------------------------- +Function Rate (MB/s) RMS time Min time Max time +Copy: 256.7683 0.1248 0.1246 0.1250 +Scale: 246.0157 0.1302 0.1301 0.1302 +Add: 255.0316 0.1883 0.1882 0.1885 +Triad: 253.1245 0.1897 0.1896 0.1899 + + +TTCP Benchmark Results +ttcp-t: socket +ttcp-t: connect +ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5000 tcp -> +localhost +ttcp-t: 16777216 bytes in 0.28 real seconds = 454.29 Mbit/sec +++ +ttcp-t: 2048 I/O calls, msec/call = 0.14, calls/sec = 7268.57 +ttcp-t: 0.0user 0.1sys 0:00real 60% 0i+0d 0maxrss 0+2pf 3+1506csw + +---------------------------------------- +SDRAM0_CFG0[PMU] = 0 (Suggested modification) +Setting PMU = 0 provides a noticeable performance improvement *2% to +5% improvement in memory performance. +*Improves the Mbit/sec for TTCP benchmark by almost 76%. +---------------------------------------- +Stream benchmark results +------------------------------------------------------------- +This system uses 8 bytes per DOUBLE PRECISION word. +------------------------------------------------------------- +Array size = 2000000, Offset = 0 +Total memory required = 45.8 MB. +Each test is run 10 times, but only +the *best* time for each is used. +------------------------------------------------------------- +Your clock granularity/precision appears to be 1 microseconds. +Each test below will take on the order of 120066 microseconds. + (= 120066 clock ticks) +Increase the size of the arrays if this shows that you are not getting +at least 20 clock ticks per test. +------------------------------------------------------------- +WARNING -- The above is only a rough guideline. +For best results, please be sure you know the precision of your system +timer. +------------------------------------------------------------- +Function Rate (MB/s) RMS time Min time Max time +Copy: 262.5167 0.1221 0.1219 0.1223 +Scale: 258.4856 0.1238 0.1238 0.1240 +Add: 262.5404 0.1829 0.1828 0.1831 +Triad: 266.8594 0.1800 0.1799 0.1802 + +TTCP Benchmark Results +ttcp-t: socket +ttcp-t: connect +ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5000 tcp -> +localhost +ttcp-t: 16777216 bytes in 0.16 real seconds = 804.06 Mbit/sec +++ +ttcp-t: 2048 I/O calls, msec/call = 0.08, calls/sec = 12864.89 +ttcp-t: 0.0user 0.0sys 0:00real 46% 0i+0d 0maxrss 0+2pf 120+1csw + + +2006-07-28, Stefan Roese -- cgit v1.1