From d9b94f28a442b0013caef99de084d7b72e2d4607 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 25 Jul 2005 14:05:07 -0500 Subject: * Patch by Jon Loeliger, 2005-05-05 Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O --- include/configs/sbc8560.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'include/configs/sbc8560.h') diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 72a3091..5a434dc 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -210,10 +210,14 @@ #if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ - #define CONFIG_NET_MULTI 1 - #define CONFIG_PHY_BCM5421S 1 /* GigaBit Ether PHY */ - #define CONFIG_MII 1 /* MII PHY management */ - #define CONFIG_PHY_ADDR 25 /* PHY address */ +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 /* MII PHY management */ +# define CONFIG_MPC85xx_TSEC1 +# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" +# define TSEC1_PHY_ADDR 25 +# define TSEC1_PHYIDX 0 +/* Options are: TSEC0 */ +# define CONFIG_ETHPRIME "TSEC0" #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ -- cgit v1.1