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-rw-r--r--board/omap2420h4/Makefile51
-rw-r--r--board/omap2420h4/config.mk26
-rw-r--r--board/omap2420h4/omap2420h4.c598
-rw-r--r--board/omap2420h4/platform.S218
-rw-r--r--board/omap2420h4/x-load.lds54
-rw-r--r--board/omap2430sdp/Makefile51
-rw-r--r--board/omap2430sdp/config.mk28
-rw-r--r--board/omap2430sdp/omap2430sdp.c746
-rw-r--r--board/omap2430sdp/platform.S198
-rw-r--r--board/omap2430sdp/x-load.lds54
-rw-r--r--board/omap3430labrador/Makefile51
-rw-r--r--board/omap3430labrador/config.mk22
-rw-r--r--board/omap3430labrador/omap3430sdp.c753
-rw-r--r--board/omap3430labrador/platform.S360
-rw-r--r--board/omap3430labrador/x-load.lds54
-rw-r--r--board/omap3430sdp/Makefile51
-rw-r--r--board/omap3430sdp/config.mk22
-rw-r--r--board/omap3430sdp/omap3430sdp.c779
-rw-r--r--board/omap3430sdp/platform.S360
-rw-r--r--board/omap3430sdp/x-load.lds54
-rw-r--r--board/omap3530gta04/config.mk2
-rw-r--r--board/omap3evm/Makefile51
-rw-r--r--board/omap3evm/config.mk19
-rw-r--r--board/omap3evm/omap3evm.c814
-rw-r--r--board/omap3evm/platform.S435
-rw-r--r--board/omap3evm/x-load.lds54
-rw-r--r--board/overo/Makefile51
-rw-r--r--board/overo/config.mk20
-rw-r--r--board/overo/overo.c1148
-rw-r--r--board/overo/platform.S360
-rw-r--r--board/overo/x-load.lds54
-rw-r--r--common/cmd_monitor.c4
-rw-r--r--include/configs/omap3530gta04.h4
33 files changed, 5 insertions, 7541 deletions
diff --git a/board/omap2420h4/Makefile b/board/omap2420h4/Makefile
deleted file mode 100644
index e6f7629..0000000
--- a/board/omap2420h4/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := omap2420h4.o
-SOBJS := platform.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/omap2420h4/config.mk b/board/omap2420h4/config.mk
deleted file mode 100644
index 1c770f3..0000000
--- a/board/omap2420h4/config.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# (C) Copyright 2004
-# Texas Instruments, <www.ti.com>
-#
-# TI H4 board with OMAP2420 (ARM1136) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
-# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1) ES2 will be configurable
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-# CONFIG_PARTIAL_SRAM must be defined to use this.
-TEXT_BASE = 0x80e80000
-
-# Used with full SRAM boot.
-# This is either with a GP system or a signed boot image.
-# easiest, and safest way to go if you can.
-# Comment out //CONFIG_PARTIAL_SRAM for this one.
-#
-#TEXT_BASE = 0x40280000
-
diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c
deleted file mode 100644
index ef81b49..0000000
--- a/board/omap2420h4/omap2420h4.c
+++ /dev/null
@@ -1,598 +0,0 @@
-/*
- * Copyright (C) 2005 Texas Instruments.
- * Jian Zhang <jzhang@ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/omap2420.h>
-#include <asm/arch/bits.h>
-
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_info.h>
-#include <asm/arch/clocks.h>
-
-static void wait_for_command_complete(unsigned int wd_base);
-static void watchdog_init(void);
-static void peripheral_enable(void);
-static void muxSetupUART1(void);
-static u32 get_cpu_rev(void);
-
-
-/*******************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- ******************************************************/
-static inline void delay (unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init (void)
-{
- return 0;
-}
-
-#ifdef CFG_SDRAM_DDR
-void
-config_sdram_ddr(u32 rev)
-{
- /* ball D11, mode 0 */
- __raw_writeb(0x08, 0x48000032);
-
- /* SDRC_CS0 Configuration */
- if (rev == CPU_2420_2422_ES1) {
- __raw_writel(H4_2422_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING);
- } else {
- __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
- }
-
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
- __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0);
- __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
-
- /*
- * CS0 SDRC Mode Register
- * Burst length = 4 - DDR memory
- * Serial mode
- * CAS latency = 3
- */
- __raw_writel(0x00000032, SDRC_MR_0);
-
- /* SDRC DLLA control register */
- /* Delay is 90 degrees */
- if (rev == CPU_2420_2422_ES1) {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00000002, SDRC_DLLA_CTRL);
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00000002, SDRC_DLLB_CTRL);
- } else {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x
- }
-
-}
-#endif // CFG_SDRAM_DDR
-
-
-#ifdef CFG_SDRAM_COMBO
-void
-config_sdram_combo(u32 rev)
-{
-
- u32 dllctrl=0;
-
- /* ball C12, mode 0 */
- __raw_writeb(0x00, 0x480000a1);
- /* ball D11, mode 0 */
- __raw_writeb(0x00, 0x48000032);
- /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */
- __raw_writeb(0x00, 0x480000a3);
-
- /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */
- __raw_writel(0x00000012, SDRC_SYSCONFIG);
- delay(200000);
- __raw_writel(0x00000010, SDRC_SYSCONFIG);
-
- /* SDRCTriState: no Tris */
- /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
- __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
-
-
- /* CS0 SDRC Memory Configuration, */
- /* DDR-SDRAM, External SDRAM is x32bit, */
- /* Configure to MUX9: 1x8Mbx32 */
- __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
- /* CS0 SDRC Mode Register */
- /* Burst length = 4 - DDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0);
-
- /* CS1 SDRC Memory Configuration, */
- /* DDR-SDRAM, External SDRAM is x32bit, */
- /* Configure to MUX9: 1x8Mbx32 */
- __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1);
- __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1);
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_1);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
-
- /* CS1 SDRC Mode Register */
- /* Burst length = 4 - DDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_1);
-
- /* SDRC DLLA control register */
- /* Delay is 90 degrees */
- if (rev == CPU_242X_ES1)
- dllctrl = (BIT0|BIT3);
- else
- dllctrl = BIT0;
-
- if (rev == CPU_2420_2422_ES1) {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00007306, SDRC_DLLA_CTRL);
- __raw_writel(0x00007302, SDRC_DLLA_CTRL);
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */
- __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */
- }
- else {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ?
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x
- }
-}
-
-#endif // CFG_SDRAM_COMBO
-
-#ifdef CFG_SDRAM_SDR
-void
-config_sdram_sdr(u32 rev)
-{
- u32 dllctrl=0;
-
- /* ball D11, mode 0 */
- __raw_writeb(0x00, 0x48000032);
-
- __raw_writel(0x00000012, SDRC_SYSCONFIG);
- delay(200000);
- __raw_writel(0x00000010, SDRC_SYSCONFIG);
-
- /* Chip-level shared interface management */
- /* SDRCTriState: no Tris */
- /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
- /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */
- if (rev == CPU_2420_2422_ES1)
- __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING);
- else
- __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
-
- /* CS0 SDRC Memory Configuration, */
- /* DDR-SDRAM, External SDRAM is x32bit, */
- /* Configure to MUX14: 32Mbx32 */
- __raw_writel(H4_2420_SDRC_MDCFG_0_SDR, SDRC_MCFG_0); /* diff from combo case */
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
- /* CS0 SDRC Mode Register */
- /* Burst length = 2 - SDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(H4_2420_SDRC_MR_0_SDR, SDRC_MR_0); /* diff from combo case */
-
- /* SDRC DLLA control register */
- /* Enable DLL, Load counter with 115 (middle of range) */
- /* Delay is 90 degrees */
-
- if (rev == CPU_242X_ES1)
- dllctrl = (BIT0|BIT3);
- else
- dllctrl = BIT0;
-
- if (rev == CPU_2420_2422_ES1) {
- __raw_writel(0x00007306, SDRC_DLLA_CTRL);
- __raw_writel(0x00007302, SDRC_DLLA_CTRL);
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */
- __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */
- }
- else {
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x
- }
-
-}
-#endif // CFG_SDRAM_SDR
-
-#ifdef CFG_SDRAM_STACKED
-void
-config_sdram_stacked(u32 rev)
-{
-
- /* Pin Muxing for SDRC */
- __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */
- __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */
- __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */
- __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */
-
- /* configure sdrc 32 bit for COMBO ddr sdram */
- __raw_writel(0x00000010, SDRC_SYSCONFIG); /* no idle ack and RESET enable */
- delay(200000);
- __raw_writel(0x00000010, SDRC_SYSCONFIG); /* smart idle mode */
-
- /* SDRC_SHARING */
- /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */
- //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
-
- __raw_writel(0x00004900, SDRC_SHARING);
-
- /* SDRC_CS0 Configuration */
- /* None for ES2.1 */
-
- /* SDRC_CS1 Configuration */
- __raw_writel(0x00000000, SDRC_CS_CFG); /* Remap CS1 to 0x80000000 */
-
- /* Disable power down of CKE */
- __raw_writel(0x00000085, SDRC_POWER);
-
- __raw_writel(0x01A02019, SDRC_MCFG_1); /* SDRC_MCFG1 */
- __raw_writel(0x0003DD03, SDRC_RFR_CTRL1); /* SDRC_RFR_CTRL1 */
- __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1); /* SDRC_ACTIM_CTRLA0 */
- __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1); /* SDRC_ACTIM_CTRLB0 */
-
- /*Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_1);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
-
- /* CS0 SDRC Mode Register */
- /* Burst length = 4 - DDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(0x00000032, SDRC_MR_1);
- __raw_writel(0x00000020, SDRC_EMR2_1); /* weak-strength driver */
-
- /* SDRC DLLA control register */
- /* Delay is 90 degrees */
- if (rev == CPU_2420_2422_ES1) {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00007302, SDRC_DLLA_CTRL);
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00007302, SDRC_DLLB_CTRL);
- }
- else {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x
- }
-}
-#endif // CFG_SDRAM_STACKED
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called at time when only stack is available.
- **********************************************************/
-int s_init(int skip)
-{
- u32 rev;
-
- rev = get_cpu_rev();
-
- watchdog_init();
- muxSetupUART1();
- delay(100);
-
- /*DPLL out = 2x DPLL --> core clock */
- __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL);
-
- /*DPLL into low power bypass (others off) */
- __raw_writel(0x00000001, CM_CLKEN_PLL);
-
- /*MPU core clock = Core /2 = 300 */
- __raw_writel(MPU_DIV, CM_CLKSEL_MPU);
-
- /*DSPif=200, DSPif=100, IVA=200 */
- __raw_writel(DSP_DIV, CM_CLKSEL_DSP);
-
- /*GFX clock (L3/2) 50MHz */
- __raw_writel(GFX_DIV, CM_CLKSEL_GFX);
-
- /*L3=100, L4=100, DisplaySS=50 Vlync=96Mhz,ssi=100, usb=50 */
- __raw_writel(BUS_DIV, CM_CLKSEL1_CORE);
-
- /*12MHz apll src, 12/(1+1)*50=300 */
- __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);
-
- /*Valid the configuration */
- __raw_writel(0x00000001, PRCM_CLKCFG_CTRL);
- delay(1000);
-
- /*Enable DPLL=300, 96MHz APLL locked. */
- __raw_writel(0x0000000F, CM_CLKEN_PLL);
- delay(200000);
-
-#ifdef CFG_SDRAM_DDR
- config_sdram_ddr(rev);
-#elif defined(CFG_SDRAM_COMBO)
- config_sdram_combo(rev);
-#elif defined(CFG_SDRAM_SDR)
- config_sdram_sdr(rev);
-#elif defined(CFG_SDRAM_STACKED)
- config_sdram_stacked(rev);
-#else
-#error SDRAM type not supported
-#endif
-
- delay(20000);
- peripheral_enable();
- return(0);
-}
-
-/*******************************************************
- * Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
- ********************************************************/
-int misc_init_r (void)
-{
- return(0);
-}
-
-/****************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************/
-static void watchdog_init(void)
-{
-#define GP (BIT8|BIT9)
-
- /* There are 4 watch dogs. 1 secure, and 3 general purpose.
- * I would expect that the ROM takes care of the secure one,
- * but we will try also. Of the 3 GP ones, 1 can reset us
- * directly, the other 2 only generate MPU interrupts.
- */
- __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
- wait_for_command_complete(WD2_BASE);
- __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
-
-#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
- __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
- wait_for_command_complete(WD3_BASE);
- __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
-
- __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
- wait_for_command_complete(WD4_BASE);
- __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
-#endif
-
-}
-
-/******************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- ******************************************************/
-static void wait_for_command_complete(unsigned int wd_base)
-{
- int pending = 1;
- do {
- pending = __raw_readl(wd_base+WWPS);
- } while (pending);
-}
-
-
-/**********************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- **********************************************/
-int dram_init (void)
-{
- return 0;
-}
-
-/*****************************************************************
- * Routine: peripheral_enable
- * Description: Enable the clks & power for perifs (GPT2, UART1,...)
- ******************************************************************/
-static void peripheral_enable(void)
-{
- unsigned int v, if_clks=0, func_clks=0;
-
- /* Enable GP2 timer.*/
- if_clks |= BIT4;
- func_clks |= BIT4;
- v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
- __raw_writel(v, CM_CLKSEL2_CORE);
- __raw_writel(0x1, CM_CLKSEL_WKUP);
-
-#ifdef CFG_NS16550
- /* Enable UART1 clock */
- func_clks |= BIT21;
- if_clks |= BIT21;
-#endif
- v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
- __raw_writel(v,CM_ICLKEN1_CORE );
- v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
- __raw_writel(v, CM_FCLKEN1_CORE);
- delay(1000);
-
-#ifndef KERNEL_UPDATED
- {
-#define V1 0xffffffff
-#define V2 0x00000007
-
- __raw_writel(V1, CM_FCLKEN1_CORE);
- __raw_writel(V2, CM_FCLKEN2_CORE);
- __raw_writel(V1, CM_ICLKEN1_CORE);
- __raw_writel(V1, CM_ICLKEN2_CORE);
- }
-#endif
-
-}
-
-/* Pin Muxing registers used for UART1 */
-#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5)
-#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6)
-#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7)
-#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8)
-/****************************************
- * Routine: muxSetupUART1 (ostboot)
- * Description: Set up uart1 muxing
- *****************************************/
-static void muxSetupUART1(void)
-{
- volatile unsigned char *MuxConfigReg;
-
- /* UART1_CTS pin configuration, PIN = D21 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* UART1_RTS pin configuration, PIN = H21 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* UART1_TX pin configuration, PIN = L20 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-
- /* UART1_RX pin configuration, PIN = T21 */
- MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
- *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
-}
-
-int nand_init(void)
-{
- u32 rev;
-
- rev = get_cpu_rev();
-
-
- /* GPMC pin muxing */
- (*(volatile int*)0x48000070) &= 0x000000FF;
- (*(volatile int*)0x48000074) &= 0x00000000;
- (*(volatile int*)0x48000078) &= 0x00000000;
- (*(volatile int*)0x4800007C) &= 0x00000000;
- (*(volatile int*)0x48000080) &= 0xFF000000;
-
- /* GPMC_IO_DIR */
- (*(volatile int*)0x4800008C) = 0x19000000;
-
- /* GPMC Configuration */
- (*(volatile int*)0x6800A010) = 0x0000000A;
- while (((*(volatile int *)0x6800A014) & 0x00000001) == 0);
-
- (*(volatile int*)0x6800A050) = 0x00000001;
- (*(volatile int*)0x6800A060) = 0x00001800;
- (*(volatile int*)0x6800A064) = 0x00141400;
- (*(volatile int*)0x6800A068) = 0x00141400;
- (*(volatile int*)0x6800A06C) = 0x0F010F01;
- (*(volatile int*)0x6800A070) = 0x010C1414;
- (*(volatile int*)0x6800A074) = 0x00000A80;
- (*(volatile int*)0x6800A078) = 0x00000C44; //base 0x04000000
-
- (*(volatile int*)0x6800A0A8) = 0x00000000;
- delay(1000);
-#ifdef CFG_SDRAM_STACKED
- (*(volatile int*)0x6800A090) = 0x00011000;
-#else
- (*(volatile int*)0x6800A090) = 0x00011200;
-#endif
- (*(volatile int*)0x6800A094) = 0x001f1f00;
- (*(volatile int*)0x6800A098) = 0x00080802;
- (*(volatile int*)0x6800A09C) = 0x1C091C09;
- (*(volatile int*)0x6800A0A0) = 0x031A1F1F;
- (*(volatile int*)0x6800A0A4) = 0x000003C2;
- (*(volatile int*)0x6800A0A8) = 0x00000F48;
-
- if (rev != CPU_2420_2422_ES1)
- (*(volatile int*)0x6800A040) = 0x1FF0; // es2.x
-
- if (nand_chip()){
- printf("Unsupported Chip!\n");
- return 1;
- }
- return 0;
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
- u32 v;
- v = __raw_readl(TAP_IDCODE_REG);
- v = v >> 28;
- return(v+1); /* currently 2422 and 2420 match up */
-}
-
-/* optionally do something like blinking LED */
-void board_hang (void)
-{}
-
-
-
diff --git a/board/omap2420h4/platform.S b/board/omap2420h4/platform.S
deleted file mode 100644
index 5cc37e5..0000000
--- a/board/omap2420h4/platform.S
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/omap2420.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-
-_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
-
-#ifdef CONFIG_PARTIAL_SRAM
-
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
- /* Copy DPLL code into SRAM */
- adr r0, go_to_speed /* get addr of clock setting code */
- mov r2, #384 /* r2 size to copy (div by 32 bytes) */
- mov r1, r1 /* r1 <- dest address (passed in) */
- add r2, r2, r0 /* r2 <- source end address */
-next2:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- bne next2
- mov pc, lr /* back to caller */
-
-/* ****************************************************************************
- * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- * -executed from SRAM.
- * R0 = PRCM_CLKCFG_CTRL - addr of valid reg
- * R1 = CM_CLKEN_PLL - addr dpll ctlr reg
- * R2 = dpll value
- * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- ******************************************************************************/
-.global go_to_speed
- go_to_speed:
- sub sp, sp, #0x4 /* get some stack space */
- str r4, [sp] /* save r4's value */
-
- /* move into fast relock bypass */
- ldr r8, pll_ctl_add
- mov r4, #0x2
- str r4, [r8]
- ldr r4, pll_stat
-block:
- ldr r8, [r4] /* wait for bypass to take effect */
- and r8, r8, #0x3
- cmp r8, #0x1
- bne block
-
- /* set new dpll dividers _after_ in bypass */
- ldr r4, pll_div_add
- ldr r8, pll_div_val
- str r8, [r4]
-
- /* now prepare GPMC (flash) for new dpll speed */
- /* flash needs to be stable when we jump back to it */
- ldr r4, cfg3_0_addr
- ldr r8, cfg3_0_val
- str r8, [r4]
- ldr r4, cfg4_0_addr
- ldr r8, cfg4_0_val
- str r8, [r4]
- ldr r4, cfg1_0_addr
- ldr r8, [r4]
- orr r8, r8, #0x3 /* up gpmc divider */
- str r8, [r4]
-
- /* setup to 2x loop though code. The first loop pre-loads the
- * icache, the 2nd commits the prcm config, and locks the dpll
- */
- mov r4, #0x1000 /* spin spin spin */
- mov r8, #0x4 /* first pass condition & set registers */
- cmp r8, #0x4
-2:
- ldrne r8, [r3] /* DPLL lock check */
- and r8, r8, #0x7
- cmp r8, #0x2
- beq 4f
-3:
- subeq r8, r8, #0x1
- streq r8, [r0] /* commit dividers (2nd time) */
- nop
-lloop1:
- sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
- nop
- cmp r4, #0x0
- bne lloop1
- mov r4, #0x40000
- cmp r8, #0x1
- nop
- streq r2, [r1] /* lock dpll (2nd time) */
- nop
-lloop2:
- sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
- nop
- cmp r4, #0x0
- bne lloop2
- mov r4, #0x40000
- cmp r8, #0x1
- nop
- ldreq r8, [r3] /* get lock condition for dpll */
- cmp r8, #0x4 /* first time though? */
- bne 2b
- moveq r8, #0x2 /* set to dpll check condition. */
- beq 3b /* if condition not true branch */
-4:
- ldr r4, [sp]
- add sp, sp, #0x4 /* return stack space */
- mov pc, lr /* back to caller, locked */
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-cfg3_0_addr:
- .word GPMC_CONFIG3_0
-cfg3_0_val:
- .word SMNAND_GPMC_CONFIG3
-cfg4_0_addr:
- .word GPMC_CONFIG4_0
-cfg4_0_val:
- .word SMNAND_GPMC_CONFIG4
-cfg1_0_addr:
- .word GPMC_CONFIG1_0
-pll_ctl_add:
- .word CM_CLKEN_PLL
-pll_stat:
- .word CM_IDLEST_CKGEN
-pll_div_add:
- .word CM_CLKSEL1_PLL
-pll_div_val:
- .word DPLL_VAL /* DPLL setting (300MHz default) */
-#endif
-
-.globl platformsetup
-platformsetup:
- mov r3, r0 /* save skip information */
-#ifdef CONFIG_APTIX
- ldr r0, REG_SDRC_MCFG_0
- ldr r1, VAL_SDRC_MCFG_0
- str r1, [r0]
- ldr r0, REG_SDRC_MR_0
- ldr r1, VAL_SDRC_MR_0
- str r1, [r0]
- /* a ddr needs emr1 set here */
- ldr r0, REG_SDRC_SHARING
- ldr r1, VAL_SDRC_SHARING
- str r1, [r0]
- ldr r0, REG_SDRC_RFR_CTRL_0
- ldr r1, VAL_SDRC_RFR_CTRL_0
- str r1, [r0]
-
- /* little delay after init */
- mov r2, #0x1800
-1:
- subs r2, r2, #0x1
- bne 1b
-#endif
-#ifdef CONFIG_PARTIAL_SRAM
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
- mov ip, lr /* save link reg across call */
- mov r0, r3 /* pass skip info to s_init */
- bl s_init /* go setup pll,mux,memory */
- ldr ip, [sp] /* restore save ip */
- mov lr, ip /* restore link reg */
-#endif
-
- /* map interrupt controller */
- ldr r0, VAL_INTH_SETUP
- mcr p15, 0, r0, c15, c2, 4
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-REG_CONTROL_STATUS:
- .word CONTROL_STATUS
-VAL_INTH_SETUP:
- .word PERIFERAL_PORT_BASE
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
-
-
-
-
-
-
diff --git a/board/omap2420h4/x-load.lds b/board/omap2420h4/x-load.lds
deleted file mode 100644
index f664ca7..0000000
--- a/board/omap2420h4/x-load.lds
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- cpu/arm1136/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
diff --git a/board/omap2430sdp/Makefile b/board/omap2430sdp/Makefile
deleted file mode 100644
index b6c984c..0000000
--- a/board/omap2430sdp/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := omap2430sdp.o
-SOBJS := platform.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/omap2430sdp/config.mk b/board/omap2430sdp/config.mk
deleted file mode 100644
index 7bc5078..0000000
--- a/board/omap2430sdp/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2004
-# Texas Instruments, <www.ti.com>
-#
-# TI H4 board with OMAP2420 (ARM1136) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
-# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1) ES2 will be configurable
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# 2430 h4 has same mem configuration as h4.
-
-# For use with external or internal boots.
-# CONFIG_PARTIAL_SRAM must be defined to use this.
-TEXT_BASE = 0x80e80000
-
-# Used with full SRAM boot.
-# This is either with a GP system or a signed boot image.
-# easiest, and safest way to go if you can.
-# Comment out //CONFIG_PARTIAL_SRAM for this one.
-#
-#TEXT_BASE = 0x40280000
-
diff --git a/board/omap2430sdp/omap2430sdp.c b/board/omap2430sdp/omap2430sdp.c
deleted file mode 100644
index f2a7b42..0000000
--- a/board/omap2430sdp/omap2430sdp.c
+++ /dev/null
@@ -1,746 +0,0 @@
-/*
- * (C) Copyright 2004-2005
- * Texas Instruments, <www.ti.com>
- * Jian Zhang <jzhang@ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/omap2430.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_info.h>
-#include <asm/arch/clocks.h>
-
-static void wait_for_command_complete(unsigned int wd_base);
-static void watchdog_init(void);
-static void peripheral_enable(void);
-static void muxSetupAll(void);
-static u32 get_cpu_rev(void);
-static u32 get_device_type(void);
-static void prcm_init(void);
-
-
-/*******************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- ******************************************************/
-static inline void delay (unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init (void)
-{
- return 0;
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
- u32 v;
- v = __raw_readl(TAP_IDCODE_REG);
- v = v >> 28;
- return(v+1); /* currently 2422 and 2420 match up */
-}
-
-/*************************************************************
- * get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
- int mode;
- mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
- return(mode >>= 8);
-}
-
-/*************************************************************
- * Helper function to wait for the status of a register
- *************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
-{
- u32 i = 0, val;
- do {
- ++i;
- val = __raw_readl(read_addr) & read_bit_mask;
- if (val == match_value)
- return(1);
- if (i==bound)
- return(0);
- } while (1);
-}
-
-/*************************************************************
- * Support for multiple type of memory types
- *************************************************************/
-#ifdef CFG_SDRAM_DDR
-void
-config_sdram_ddr(u32 rev)
-{
- /* ball D11, mode 0 */
- __raw_writeb(0x08, 0x48000032);
-
- /* SDRC_CS0 Configuration */
- __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
-
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
- __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0);
- __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
-
- /*
- * CS0 SDRC Mode Register
- * Burst length = 4 - DDR memory
- * Serial mode
- * CAS latency = 3
- */
- __raw_writel(0x00000032, SDRC_MR_0);
-
- /* SDRC DLLA control register */
- /* Delay is 90 degrees */
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x
-
-}
-#endif // CFG_SDRAM_DDR
-
-#ifdef CFG_SDRAM_COMBO
-void
-config_sdram_combo(u32 rev)
-{
-
- u32 dllctrl=0;
-
- /* ball C12, mode 0 */
- __raw_writeb(0x00, 0x480000a1);
- /* ball D11, mode 0 */
- __raw_writeb(0x00, 0x48000032);
- /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */
- __raw_writeb(0x00, 0x480000a3);
-
- /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */
- __raw_writel(0x00000012, SDRC_SYSCONFIG);
- wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */
- __raw_writel(0x00000000, SDRC_SYSCONFIG);
-
- /* SDRCTriState: no Tris */
- /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
- if (rev == CPU_2420_2422_ES1)
- __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING);
- else
- __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
-
-
- /* CS0 SDRC Memory Configuration, */
- /* DDR-SDRAM, External SDRAM is x32bit, */
- /* Configure to MUX9: 1x8Mbx32 */
- __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
-
- /* This is reqd only for ES1 */
- if (rev == CPU_242X_ES1)
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- delay(5000);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
- /* CS0 SDRC Mode Register */
- /* Burst length = 4 - DDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0);
-
- /* CS1 SDRC Memory Configuration, */
- /* DDR-SDRAM, External SDRAM is x32bit, */
- /* Configure to MUX9: 1x8Mbx32 */
- __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1);
- __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1);
- /* This is reqd only for ES1 */
- if (rev == CPU_242X_ES1)
- __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, 0x680090d8);
- __raw_writel(CMD_PRECHARGE, 0x680090d8);
- __raw_writel(CMD_AUTOREFRESH, 0x680090d8);
- __raw_writel(CMD_AUTOREFRESH, 0x680090d8);
-
- /* CS1 SDRC Mode Register */
- /* Burst length = 4 - DDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(H4_2422_SDRC_MR_0_DDR, 0x680090b4);
-
- /* SDRC DLLA control register */
- /* Delay is 90 degrees */
-
- if (rev == CPU_242X_ES1)
- dllctrl = (BIT0|BIT3);
- else
- dllctrl = BIT0;
-
- if (rev == CPU_2420_2422_ES1) {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00007306, SDRC_DLLA_CTRL);
- __raw_writel(0x00007302, SDRC_DLLA_CTRL);
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */
- __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */
- }
- else {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x
- // __raw_writel(0x00009808, SDRC_DLLA_CTRL); // ES2.x
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ?
- __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x
- //__raw_writel(0x00009808, SDRC_DLLB_CTRL); // ES2.x
- }
-}
-
-#endif // CFG_SDRAM_COMBO
-
-#ifdef CFG_2430SDRAM_DDR
-void
-config_2430sdram_ddr(u32 rev)
-{
- u32 dllstat, dllctrl;
-
- __raw_writel(0x00000012, SDRC_SYSCONFIG);
- wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */
- __raw_writel(0x00000000, SDRC_SYSCONFIG);
-
- /* Chip-level shared interface management */
- /* SDRCTriState: no Tris */
- /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
- /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */
- __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
-
- /* CS0 SDRC Memory Configuration, */
- /* DDR-SDRAM, External SDRAM is x32bit, */
- /* Configure to MUX14: 32Mbx32 */
- __raw_writel(SDP_2430_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(SDP_2430_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
- __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
-
- __raw_writel(H4_2420_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
-
- /* Manual Command sequence */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- delay(5000);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
- /* CS0 SDRC Mode Register */
- /* Burst length = 2 - SDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(H4_2420_SDRC_MR_0_DDR, SDRC_MR_0);
-
- /* Set up SDRC DLL values for 2430 DDR */
- dllctrl = (SDP_2430_SDRC_DLLAB_CTRL & ~BIT2); /* set target ctrl val */
- __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set lock mode */
- __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set lock mode */
- delay(0x1000); /* time to track to center */
- dllstat = __raw_readl(SDRC_DLLA_STATUS) & 0xFF00; /* get status */
- dllctrl = (dllctrl & 0x00FF) | dllstat | BIT2; /* build unlock value */
- __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set unlock mode */
- __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set unlock mode */
-}
-#endif // CFG_2430SDRAM_DDR
-
-#ifdef CFG_SDRAM_STACKED
-void
-config_sdram_stacked(u32 rev)
-{
-
- /* Pin Muxing for SDRC */
- __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */
- __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */
- __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */
- __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */
-
- /* configure sdrc 32 bit for COMBO ddr sdram */
- __raw_writel(0x00000010, SDRC_SYSCONFIG); /* no idle ack and RESET enable */
- delay(200000);
- __raw_writel(0x00000010, SDRC_SYSCONFIG); /* smart idle mode */
-
- /* SDRC_SHARING */
- /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */
- //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
-
- __raw_writel(0x00004900, SDRC_SHARING);
-
- /* SDRC_CS0 Configuration */
- /* None for ES2.1 */
-
- /* SDRC_CS1 Configuration */
- __raw_writel(0x00000000, SDRC_CS_CFG); /* Remap CS1 to 0x80000000 */
-
- /* Disable power down of CKE */
- __raw_writel(0x00000085, SDRC_POWER);
-
- __raw_writel(0x01A02019, SDRC_MCFG_1); /* SDRC_MCFG1 */
- __raw_writel(0x0003DD03, SDRC_RFR_CTRL1); /* SDRC_RFR_CTRL1 */
- __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1); /* SDRC_ACTIM_CTRLA0 */
- __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1); /* SDRC_ACTIM_CTRLB0 */
-
- /*Manual Command sequence */
- __raw_writel(0x00000000, 0x680090D8);
- __raw_writel(0x00000001, 0x680090D8);
- __raw_writel(0x00000002, 0x680090D8);
- __raw_writel(0x00000002, 0x680090D8);
-
- /* CS0 SDRC Mode Register */
- /* Burst length = 4 - DDR memory */
- /* Serial mode */
- /* CAS latency = 3 */
- __raw_writel(0x00000032, 0x680090B4);
- __raw_writel(0x00000020, 0x680090BC); /* weak-strength driver */
-
- /* SDRC DLLA control register */
- /* Delay is 90 degrees */
- if (rev == CPU_2420_2422_ES1) {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00007302, SDRC_DLLA_CTRL);
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00007302, SDRC_DLLB_CTRL);
- }
- else {
- /* Enable DLL, Load counter with 115 (middle of range) */
- __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x
- /* Enable DLL, Load counter with 128 (middle of range) */
- __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x
- }
-}
-#endif // CFG_SDRAM_STACKED
-
-/*************************************************************
- * get_sys_clk_speed - determine reference oscillator speed
- * based on known 32kHz clock and gptimer.
- *************************************************************/
-u32 get_osc_clk_speed(u32 *shift)
-{
-#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */
-#define GPT_CTR OMAP24XX_GPT2+TCRR /* read counter address */
- u32 start, cstart, cend, cdiff, val;
- unsigned int v, if_clks=0, func_clks=0 ;
-
-
-
- if(__raw_readl(PRCM_CLKSRC_CTRL) & BIT7){ /* if currently /2 */
- *shift = 1;
- }else{
- *shift = 0;
- }
-
- /* enable timer2 */
- val = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* mask for sys_clk use */
- __raw_writel(val, CM_CLKSEL2_CORE); /* timer2 source to sys_clk */
- __raw_writel(BIT4, CM_ICLKEN1_CORE); /* timer2 interface clock on */
- __raw_writel(BIT4, CM_FCLKEN1_CORE); /* timer2 function clock on */
- /* Enable GP2 timer.*/
- if_clks |= BIT4;
- func_clks |= BIT4;
- v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
- __raw_writel(v,CM_ICLKEN1_CORE );
- v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
- __raw_writel(v, CM_FCLKEN1_CORE);
- __raw_writel(0, OMAP24XX_GPT2+TLDR); /* start counting at 0 */
- __raw_writel(GPT_EN, OMAP24XX_GPT2+TCLR); /* enable clock */
- /* enable 32kHz source */ /* enabled out of reset */
- /* determine sys_clk via gauging */
- start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles*/
- while(__raw_readl(S32K_CR) < start); /* dead loop till start time */
- cstart = __raw_readl(GPT_CTR); /* get start sys_clk count */
- while(__raw_readl(S32K_CR) < (start+20)); /* wait for 40 cycles */
- cend = __raw_readl(GPT_CTR); /* get end sys_clk count */
- cdiff = cend - cstart; /* get elapsed ticks */
- /* based on number of ticks assign speed */
- if(cdiff > (19000 >> *shift))
- return(S38_4M);
- else if (cdiff > (15200 >> *shift))
- return(S26M);
- else if (cdiff > (13000 >> *shift))
- return(S24M);
- else if (cdiff > (9000 >> *shift))
- return(S19_2M);
- else if (cdiff > (7600 >> *shift))
- return(S13M);
- else
- return(S12M);
-}
-
-/*********************************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
- * -- called from SRAM
- *********************************************************************************/
-void
-prcm_init()
-{
- u32 div, speed, val, div_by_2;
-
- val = __raw_readl(PRCM_CLKSRC_CTRL) & ~(BIT1 | BIT0);
-#if defined(OMAP2430_SQUARE_CLOCK_INPUT)
- __raw_writel(val, PRCM_CLKSRC_CTRL);
-#else
- __raw_writel((val | BIT0), PRCM_CLKSRC_CTRL);
-#endif
- speed = get_osc_clk_speed(&div_by_2);
- if((speed > S19_2M) && (!div_by_2)){ /* if fast && /2 off, enable it */
- val = ~(BIT6|BIT7) & __raw_readl(PRCM_CLKSRC_CTRL);
- val |= (0x2 << 6); /* divide by 2 if (24,26,38.4) -> (12/13/19.2) */
- __raw_writel(val, PRCM_CLKSRC_CTRL);
- }
-
- __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */
- __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */
- __raw_writel(0, CM_ICLKEN1_CORE);
- __raw_writel(0, CM_ICLKEN2_CORE);
-
- /*DPLL into low power bypass (others off) */
- __raw_writel(0x00000001, CM_CLKEN_PLL);
-
- __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */
- __raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */
- __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */
- __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */
- __raw_writel(MDM_DIV, CM_CLKSEL_MDM); /* set mdm dividers */
-
- div = BUS_DIV;
- __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/SSi dividers */
- delay(1000);
-
- /*13MHz apll src, PRCM 'x' DPLL rate */
- __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);
-
- /*Valid the configuration */
- __raw_writel(0x00000001, PRCM_CLKCFG_CTRL);
- delay(1000);
-
- /* set up APLLS_CLKIN per crystal */
- if (speed > S19_2M)
- speed >>= 1; /* if fast shift to /2 range */
- val = (0x2 << 23); /* default to 13Mhz for 2430c */
- if (speed == S12M)
- val = (0x3 << 23);
- else if (speed == S19_2M)
- val = (0x0 << 23);
- val |= (~(BIT23|BIT24|BIT25) & __raw_readl(CM_CLKSEL1_PLL));
- __raw_writel(val, CM_CLKSEL1_PLL);
-
- __raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */
- wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);/* wait for apll lock */
-
- delay(200000);
-}
-
-void SEC_generic(void)
-{
-/* Permission values for registers -Full fledged permissions to all */
-#define UNLOCK_1 0xFFFFFFFF
-#define UNLOCK_2 0x00000000
-#define UNLOCK_3 0x0000FFFF
- /* Protection Module Register Target APE (PM_RT)*/
- __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x68); /* REQ_INFO_PERMISSION_1 L*/
- __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
- __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
- __raw_writel(UNLOCK_2, PM_RT_APE_BASE_ADDR_ARM + 0x60); /* ADDR_MATCH_1 L*/
-
-
- __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
- __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
- __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
-
- __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
- __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
- __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
- __raw_writel(UNLOCK_2, PM_OCM_RAM_BASE_ADDR_ARM + 0x80); /* ADDR_MATCH_2 L*/
-
- /* IVA Changes */
- __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
- __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
- __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
-}
-
-/**********************************************************
- * Routine: try_unlock_sram()
- * Description: If chip is GP type, unlock the SRAM for general use.
- ***********************************************************/
-void try_unlock_sram(void)
-{
- int mode;
-
- /* if GP device unlock device SRAM for general use */
- mode = get_device_type();
-
- if ((mode == GP_DEVICE) || (mode == HS_DEVICE) || (mode == EMU_DEVICE)
- || (mode == TST_DEVICE)) {
- /* Secure or Emulation device - HS/E/T */
- SEC_generic();
- }
- return;
-}
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called at time when only stack is available.
- **********************************************************/
-
-int s_init(int skip)
-{
- u32 rev;
-
- rev = get_cpu_rev();
-
- watchdog_init();
- try_unlock_sram();
- muxSetupAll();
- delay(100);
- prcm_init();
-
-#ifdef CFG_SDRAM_DDR
- config_sdram_ddr(rev);
-#elif defined(CFG_SDRAM_COMBO)
- config_sdram_combo(rev);
-#elif defined(CFG_2430SDRAM_DDR)
- config_2430sdram_ddr(rev);
-#elif defined(CFG_SDRAM_STACKED)
- config_sdram_stacked(rev);
-#else
-#error SDRAM type not supported
-#endif
-
- delay(20000);
- peripheral_enable();
- return(0);
-}
-
-/*******************************************************
- * Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
- ********************************************************/
-int misc_init_r (void)
-{
- return(0);
-}
-
-/****************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************/
-static void watchdog_init(void)
-{
-#define GP (BIT8|BIT9)
-
- /* There are 4 watch dogs. 1 secure, and 3 general purpose.
- * I would expect that the ROM takes care of the secure one,
- * but we will try also. Of the 3 GP ones, 1 can reset us
- * directly, the other 2 only generate MPU interrupts.
- */
- __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
- wait_for_command_complete(WD2_BASE);
- __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
-
-}
-
-/******************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- ******************************************************/
-static void wait_for_command_complete(unsigned int wd_base)
-{
- int pending = 1;
- do {
- pending = __raw_readl(wd_base+WWPS);
- } while (pending);
-}
-
-
-/**********************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- **********************************************/
-int dram_init (void)
-{
- return 0;
-}
-
-/*****************************************************************
- * Routine: peripheral_enable
- * Description: Enable the clks & power for perifs (GPT2, UART1,...)
- ******************************************************************/
-static void peripheral_enable(void)
-{
- unsigned int v, if_clks=0, if_clks2 = 0, func_clks=0, func_clks2 = 0;
-
- /* Enable GP2 timer.*/
- if_clks |= BIT4;
- func_clks |= BIT4;
- v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP24XX_GPT2 */
- __raw_writel(v, CM_CLKSEL2_CORE);
- __raw_writel(0x1, CM_CLKSEL_WKUP);
-
-#ifdef CFG_NS16550
- /* Enable UART1 clock */
- func_clks |= BIT21;
- if_clks |= BIT21;
-#endif
- v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
- __raw_writel(v,CM_ICLKEN1_CORE );
- v = __raw_readl(CM_ICLKEN2_CORE) | if_clks2; /* Interface clocks on */
- __raw_writel(v, CM_ICLKEN2_CORE);
- v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
- __raw_writel(v, CM_FCLKEN1_CORE);
- v = __raw_readl(CM_FCLKEN2_CORE) | func_clks2; /* Functional Clocks on */
- __raw_writel(v, CM_FCLKEN2_CORE);
- delay(1000);
-
-}
-
-/* Do pin muxing for all the devices used in X-Loader */
-#define MUX_VAL(OFFSET,VALUE)\
- __raw_writeb(VALUE, OMAP24XX_CTRL_BASE + OFFSET);
-static void muxSetupAll(void)
-{
- /* UART 1*/
- MUX_VAL(0x00B1, 0x1B) /* uart1_cts- EN, HI, 3, ->gpio_32 */
- MUX_VAL(0x00B2, 0x1B) /* uart1_rts- EN, HI, 3, ->gpio_8 */
- MUX_VAL(0x00B3, 0x1B) /* uart1_tx- EN, HI, 3, ->gpio_9 */
- MUX_VAL(0x00B4, 0x1B) /* uart1_rx- EN, HI, 3, ->gpio_10 */
- MUX_VAL(0x0107, 0x01) /* ssi1_dat_tx- Dis, 1, ->uart1_tx */
- MUX_VAL(0x0108, 0x01) /* ssi1_flag_tx- Dis, 1, ->uart1_rts */
- MUX_VAL(0x0109, 0x01) /* ssi1_rdy_tx- Dis, 1, ->uart1_cts */
- MUX_VAL(0x010A, 0x01) /* ssi1_dat_rx- Dis, 1, ->uart1_rx */
-
- /* Mux settings for SDRC */
- MUX_VAL(0x0054, 0x1B) /* sdrc_a14 - EN, HI, 3, ->gpio_0 */
- MUX_VAL(0x0055, 0x1B) /* sdrc_a13 - EN, HI, 3, ->gpio_1 */
- MUX_VAL(0x0056, 0x00) /* sdrc_a12 - Dis, 0 */
- MUX_VAL(0x0046, 0x00) /* sdrc_ncs1 - Dis, 0 */
- MUX_VAL(0x0048, 0x00) /* sdrc_cke1 - Dis, 0 */
- /* GPMC */
- MUX_VAL(0x0030, 0x00) /* gpmc_clk - Dis, 0 */
- MUX_VAL(0x0032, 0x00) /* gpmc_ncs1- Dis, 0 */
- MUX_VAL(0x0033, 0x00) /* gpmc_ncs2- Dis, 0 */
- MUX_VAL(0x0034, 0x03) /* gpmc_ncs3- Dis, 3, ->gpio_24 */
- MUX_VAL(0x0035, 0x03) /* gpmc_ncs4- Dis, 3, ->gpio_25 */
- MUX_VAL(0x0036, 0x00) /* gpmc_ncs5- Dis, 0 */
- MUX_VAL(0x0037, 0x03) /* gpmc_ncs6- Dis, 3, ->gpio_27 */
- MUX_VAL(0x0038, 0x00) /* gpmc_ncs7- Dis, 0 */
- MUX_VAL(0x0040, 0x18) /* gpmc_wait1- Dis, 0 */
- MUX_VAL(0x0041, 0x18) /* gpmc_wait2- Dis, 0 */
- MUX_VAL(0x0042, 0x1B) /* gpmc_wait3- EN, HI, 3, ->gpio_35 */
- MUX_VAL(0x0085, 0x1B) /* gpmc_a10- EN, HI, 3, ->gpio_3 */
-}
-
-int nand_init(void)
-{
- u32 rev;
-
- /* GPMC Configuration */
- rev = get_cpu_rev();
-
- /* global settings */
- __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
- __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
- __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
-#ifdef CFG_NAND
- __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
-#endif
-
- /* Set the GPMC Vals . For NAND boot on 2430SDP, NAND is mapped at CS0
- * , NOR at CS1 and MPDB at CS5. And oneNAND boot, we map oneNAND at CS0.
- * We configure only GPMC CS0 with required values. Configiring other devices
- * at other CS in done in u-boot anyway. So we don't have to bother doing it here.
- */
- __raw_writel(0, GPMC_CONFIG7_0);
- sdelay(1000);
-
-#ifdef CFG_NAND
- __raw_writel( SMNAND_GPMC_CONFIG1, GPMC_CONFIG1_0);
- __raw_writel( SMNAND_GPMC_CONFIG2, GPMC_CONFIG2_0);
- __raw_writel( SMNAND_GPMC_CONFIG3, GPMC_CONFIG3_0);
- __raw_writel( SMNAND_GPMC_CONFIG4, GPMC_CONFIG4_0);
- __raw_writel( SMNAND_GPMC_CONFIG5, GPMC_CONFIG5_0);
- __raw_writel( SMNAND_GPMC_CONFIG6, GPMC_CONFIG6_0);
-
-#else /* CFG_ONENAND */
- __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1_0);
- __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2_0);
- __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3_0);
- __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4_0);
- __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5_0);
- __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6_0);
-#endif
-
- /* Enable the GPMC Mapping */
- __raw_writel(( ((OMAP24XX_GPMC_CS0_SIZE & 0xF)<<8) |
- ((OMAP24XX_GPMC_CS0_MAP>>24) & 0x3F) |
- (1<<6) ), GPMC_CONFIG7_0);
- sdelay(2000);
-#ifdef CFG_NAND
- if (nand_chip()){
-#ifdef CFG_PRINTF
- printf("Unsupported Chip!\n");
-#endif
- return 1;
- }
-#else
- if (onenand_chip()){
-#ifdef CFG_PRINTF
- printf("OneNAND Unsupported !\n");
-#endif
- return 1;
- }
-
-#endif
- return 0;
-}
-
-/* optionally do something like blinking LED */
-void board_hang (void)
-{ while (0) {};}
diff --git a/board/omap2430sdp/platform.S b/board/omap2430sdp/platform.S
deleted file mode 100644
index f221d7e..0000000
--- a/board/omap2430sdp/platform.S
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004-2005
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/omap2430.h>
-#include <asm/arch/clocks.h>
-
-_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
-
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
- /* Copy DPLL code into SRAM */
- adr r0, go_to_speed /* get addr of clock setting code */
- mov r2, #384 /* r2 size to copy (div by 32 bytes) */
- mov r1, r1 /* r1 <- dest address (passed in) */
- add r2, r2, r0 /* r2 <- source end address */
-next2:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- bne next2
- mov pc, lr /* back to caller */
-
-/* ****************************************************************************
- * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- * -executed from SRAM.
- * R0 = PRCM_CLKCFG_CTRL - addr of valid reg
- * R1 = CM_CLKEN_PLL - addr dpll ctlr reg
- * R2 = dpll value
- * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- ******************************************************************************/
-.global go_to_speed
- go_to_speed:
- sub sp, sp, #0x4 /* get some stack space */
- str r4, [sp] /* save r4's value */
-
- /* move into fast relock bypass */
- ldr r8, pll_ctl_add
- mov r4, #0x2
- str r4, [r8]
- ldr r4, pll_stat
-block:
- ldr r8, [r4] /* wait for bypass to take effect */
- and r8, r8, #0x3
- cmp r8, #0x1
- bne block
-
- /* set new dpll dividers _after_ in bypass */
- ldr r4, pll_div_add
- ldr r8, pll_div_val
- str r8, [r4]
-
- /* now prepare GPMC (flash) for new dpll speed */
- /* flash needs to be stable when we jump back to it */
- ldr r4, flash_cfg3_addr
- ldr r8, flash_cfg3_val
- str r8, [r4]
- ldr r4, flash_cfg4_addr
- ldr r8, flash_cfg4_val
- str r8, [r4]
- ldr r4, flash_cfg1_addr
- ldr r8, [r4]
- orr r8, r8, #0x3 /* up gpmc divider */
- str r8, [r4]
-
- /* setup to 2x loop though code. The first loop pre-loads the
- * icache, the 2nd commits the prcm config, and locks the dpll
- */
- mov r4, #0x1000 /* spin spin spin */
- mov r8, #0x4 /* first pass condition & set registers */
- cmp r8, #0x4
-2:
- ldrne r8, [r3] /* DPLL lock check */
- and r8, r8, #0x7
- cmp r8, #0x2
- beq 4f
-3:
- subeq r8, r8, #0x1
- streq r8, [r0] /* commit dividers (2nd time) */
- nop
-lloop1:
- sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
- nop
- cmp r4, #0x0
- bne lloop1
- mov r4, #0x40000
- cmp r8, #0x1
- nop
- streq r2, [r1] /* lock dpll (2nd time) */
- nop
-lloop2:
- sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
- nop
- cmp r4, #0x0
- bne lloop2
- mov r4, #0x40000
- cmp r8, #0x1
- nop
- ldreq r8, [r3] /* get lock condition for dpll */
- cmp r8, #0x4 /* first time though? */
- bne 2b
- moveq r8, #0x2 /* set to dpll check condition. */
- beq 3b /* if condition not true branch */
-4:
- ldr r4, [sp]
- add sp, sp, #0x4 /* return stack space */
- mov pc, lr /* back to caller, locked */
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-#ifdef CFG_ONENAND
-flash_cfg3_addr:
- .word GPMC_CONFIG3_0
-flash_cfg3_val:
- .word ONENAND_GPMC_CONFIG3
-flash_cfg4_addr:
- .word GPMC_CONFIG4_0
-flash_cfg4_val:
- .word ONENAND_GPMC_CONFIG4
-flash_cfg1_addr:
- .word GPMC_CONFIG1_0
-#else
-flash_cfg3_addr:
- .word GPMC_CONFIG3_0
-flash_cfg3_val:
- .word SMNAND_GPMC_CONFIG3
-flash_cfg4_addr:
- .word GPMC_CONFIG4_0
-flash_cfg4_val:
- .word SMNAND_GPMC_CONFIG4
-flash_cfg1_addr:
- .word GPMC_CONFIG1_0
-#endif
-pll_ctl_add:
- .word CM_CLKEN_PLL
-pll_stat:
- .word CM_IDLEST_CKGEN
-pll_div_add:
- .word CM_CLKSEL1_PLL
-pll_div_val:
- .word DPLL_VAL /* DPLL setting (300MHz default) */
-
-.globl platformsetup
-platformsetup:
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
- mov ip, lr /* save link reg across call */
- bl s_init /* go setup pll,mux,memory */
- ldr ip, [sp] /* restore save ip */
- mov lr, ip /* restore link reg */
-
- /* map interrupt controller */
- ldr r0, VAL_INTH_SETUP
- mcr p15, 0, r0, c15, c2, 4
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-REG_CONTROL_STATUS:
- .word CONTROL_STATUS
-VAL_INTH_SETUP:
- .word PERIFERAL_PORT_BASE
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
-
diff --git a/board/omap2430sdp/x-load.lds b/board/omap2430sdp/x-load.lds
deleted file mode 100644
index f12e8f8..0000000
--- a/board/omap2430sdp/x-load.lds
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2005 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- cpu/arm1136/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
diff --git a/board/omap3430labrador/Makefile b/board/omap3430labrador/Makefile
deleted file mode 100644
index d54b666..0000000
--- a/board/omap3430labrador/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := omap3430sdp.o
-SOBJS := platform.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/omap3430labrador/config.mk b/board/omap3430labrador/config.mk
deleted file mode 100644
index d6ad6c5..0000000
--- a/board/omap3430labrador/config.mk
+++ /dev/null
@@ -1,22 +0,0 @@
-#
-# (C) Copyright 2006
-# Texas Instruments, <www.ti.com>
-#
-# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# SDP3430 has 1 bank of 32MB or 128MB mDDR-SDRAM on CS0
-# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
-# Physical Address:
-# 8000'0000 (bank0)
-# A000'0000 (bank1) - re-mappable below CS1
-
-# For use if you want X-Loader to relocate from SRAM to DDR
-#TEXT_BASE = 0x80e80000
-
-# For XIP in 64K of SRAM or debug (GP device has it all availabe)
-# SRAM 40200000-4020FFFF base
-# initial stack at 0x4020fffc used in s_init (below xloader).
-# The run time stack is (above xloader, 2k below)
-# If any globals exist there needs to be room for them also
-TEXT_BASE = 0x40208800
diff --git a/board/omap3430labrador/omap3430sdp.c b/board/omap3430labrador/omap3430sdp.c
deleted file mode 100644
index 89d9ff1..0000000
--- a/board/omap3430labrador/omap3430sdp.c
+++ /dev/null
@@ -1,753 +0,0 @@
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- * Jian Zhang <jzhang@ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/mem.h>
-
-/* Used to index into DPLL parameter tables */
-struct dpll_param {
- unsigned int m;
- unsigned int n;
- unsigned int fsel;
- unsigned int m2;
-};
-
-typedef struct dpll_param dpll_param;
-
-#define MAX_SIL_INDEX 3
-
-/* Following functions are exported from lowlevel_init.S */
-extern dpll_param * get_mpu_dpll_param(void);
-extern dpll_param * get_iva_dpll_param(void);
-extern dpll_param * get_core_dpll_param(void);
-extern dpll_param * get_per_dpll_param(void);
-
-#define __raw_readl(a) (*(volatile unsigned int *)(a))
-#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
-#define __raw_readw(a) (*(volatile unsigned short *)(a))
-#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
-
-/*******************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- ******************************************************/
-static inline void delay(unsigned long loops)
-{
- __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0"(loops));
-}
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init (void)
-{
- return 0;
-}
-
-/*************************************************************
- * get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
- int mode;
- mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
- return(mode >>= 8);
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
- u32 cpuid=0;
- /* On ES1.0 the IDCODE register is not exposed on L4
- * so using CPU ID to differentiate
- * between ES2.0 and ES1.0.
- */
- __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
- if((cpuid & 0xf) == 0x0)
- return CPU_3430_ES1;
- else
- return CPU_3430_ES2;
-
-}
-
-/******************************************
- * cpu_is_3410(void) - returns true for 3410
- ******************************************/
-u32 cpu_is_3410(void)
-{
- int status;
- if(get_cpu_rev() < CPU_3430_ES2) {
- return 0;
- } else {
- /* read scalability status and return 1 for 3410*/
- status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
- /* Check whether MPU frequency is set to 266 MHz which
- * is nominal for 3410. If yes return true else false
- */
- if (((status >> 8) & 0x3) == 0x2)
- return 1;
- else
- return 0;
- }
-}
-
-/*****************************************************************
- * sr32 - clear & set a value in a bit range for a 32 bit address
- *****************************************************************/
-void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
-{
- u32 tmp, msk = 0;
- msk = 1 << num_bits;
- --msk;
- tmp = __raw_readl(addr) & ~(msk << start_bit);
- tmp |= value << start_bit;
- __raw_writel(tmp, addr);
-}
-
-/*********************************************************************
- * wait_on_value() - common routine to allow waiting for changes in
- * volatile regs.
- *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
-{
- u32 i = 0, val;
- do {
- ++i;
- val = __raw_readl(read_addr) & read_bit_mask;
- if (val == match_value)
- return (1);
- if (i == bound)
- return (0);
- } while (1);
-}
-
-#ifdef CFG_3430SDRAM_DDR
-/*********************************************************************
- * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
- *********************************************************************/
-void config_3430sdram_ddr(void)
-{
- /* reset sdrc controller */
- __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
- wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
- __raw_writel(0, SDRC_SYSCONFIG);
-
- /* setup sdrc to ball mux */
- __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
-
- /* set mdcfg */
- __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
-
- /* set timing */
- __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
- __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
- __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
-
- /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- delay(5000);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
- /* set mr0 */
- __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
-
- /* set up dll */
- __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
- delay(0x2000); /* give time to lock */
-
-}
-#endif // CFG_3430SDRAM_DDR
-
-/*************************************************************
- * get_sys_clk_speed - determine reference oscillator speed
- * based on known 32kHz clock and gptimer.
- *************************************************************/
-u32 get_osc_clk_speed(void)
-{
- u32 start, cstart, cend, cdiff, val;
-
- val = __raw_readl(PRM_CLKSRC_CTRL);
- /* If SYS_CLK is being divided by 2, remove for now */
- val = (val & (~BIT7)) | BIT6;
- __raw_writel(val, PRM_CLKSRC_CTRL);
-
- /* enable timer2 */
- val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
- __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
-
- /* Enable I and F Clocks for GPT1 */
- val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
- __raw_writel(val, CM_ICLKEN_WKUP);
- val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
- __raw_writel(val, CM_FCLKEN_WKUP);
-
- __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
- __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
- /* enable 32kHz source *//* enabled out of reset */
- /* determine sys_clk via gauging */
-
- start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
- while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
- cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
- while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
- cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
- cdiff = cend - cstart; /* get elapsed ticks */
-
- /* based on number of ticks assign speed */
- if (cdiff > 19000)
- return (S38_4M);
- else if (cdiff > 15200)
- return (S26M);
- else if (cdiff > 13000)
- return (S24M);
- else if (cdiff > 9000)
- return (S19_2M);
- else if (cdiff > 7600)
- return (S13M);
- else
- return (S12M);
-}
-
-/******************************************************************************
- * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
- * -- input oscillator clock frequency.
- *
- *****************************************************************************/
-void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
-{
- if(osc_clk == S38_4M)
- *sys_clkin_sel= 4;
- else if(osc_clk == S26M)
- *sys_clkin_sel = 3;
- else if(osc_clk == S19_2M)
- *sys_clkin_sel = 2;
- else if(osc_clk == S13M)
- *sys_clkin_sel = 1;
- else if(osc_clk == S12M)
- *sys_clkin_sel = 0;
-}
-
-/******************************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h
- * -- called from SRAM, or Flash (using temp SRAM stack).
- *****************************************************************************/
-void prcm_init(void)
-{
- u32 osc_clk=0, sys_clkin_sel;
- dpll_param *dpll_param_p;
- u32 clk_index, sil_index;
-
- /* Gauge the input clock speed and find out the sys_clkin_sel
- * value corresponding to the input clock.
- */
- osc_clk = get_osc_clk_speed();
- get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
-
- sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
-
- /* If the input clock is greater than 19.2M always divide/2 */
- if(sys_clkin_sel > 2) {
- sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
- clk_index = sys_clkin_sel/2;
- } else {
- sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
- clk_index = sys_clkin_sel;
- }
-
- sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
-
- /* The DPLL tables are defined according to sysclk value and
- * silicon revision. The clk_index value will be used to get
- * the values for that input sysclk from the DPLL param table
- * and sil_index will get the values for that SysClk for the
- * appropriate silicon rev.
- */
- if(cpu_is_3410())
- sil_index = 2;
- else {
- if(get_cpu_rev() == CPU_3430_ES1)
- sil_index = 0;
- else if(get_cpu_rev() == CPU_3430_ES2)
- sil_index = 1;
- }
-
- /* Unlock MPU DPLL (slows things down, and needed later) */
- sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
- wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
-
- /* Getting the base address of Core DPLL param table*/
- dpll_param_p = (dpll_param *)get_core_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
- /* CORE DPLL */
- /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
- sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
- wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
- /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
- work. write another value and then default value. */
- sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
- sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
- sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
- sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
- sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
- sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
- sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
- sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb ES1 only */
- sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
- sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
- sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
- sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
- sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
-
- /* Getting the base address to PER DPLL param table*/
- dpll_param_p = (dpll_param *)get_per_dpll_param();
- /* Moving it to the right sysclk base */
- dpll_param_p = dpll_param_p + clk_index;
- /* PER DPLL */
- sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
- wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
- sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
- sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
- sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
- sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
- sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
- sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
- sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
- sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */
- sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
-
- /* Getting the base address to MPU DPLL param table*/
- dpll_param_p = (dpll_param *)get_mpu_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
- /* MPU DPLL (unlocked already) */
- sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
- sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
- sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
- sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
-
- /* Getting the base address to IVA DPLL param table*/
- dpll_param_p = (dpll_param *)get_iva_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
- /* IVA DPLL (set to 12*20=240MHz) */
- sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
- wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
- sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
- sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
- sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
- sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
-
- /* Set up GPTimers to sys_clk source only */
- sr32(CM_CLKSEL_PER, 0, 8, 0xff);
- sr32(CM_CLKSEL_WKUP, 0, 1, 1);
-
- delay(5000);
-}
-
-/*****************************************
- * Routine: secure_unlock
- * Description: Setup security registers for access
- * (GP Device only)
- *****************************************/
-void secure_unlock(void)
-{
- /* Permission values for registers -Full fledged permissions to all */
- #define UNLOCK_1 0xFFFFFFFF
- #define UNLOCK_2 0x00000000
- #define UNLOCK_3 0x0000FFFF
- /* Protection Module Register Target APE (PM_RT)*/
- __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
- __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
- __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
- __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
-
- __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
- __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
- __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
-
- __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
- __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
- __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
- __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
-
- /* IVA Changes */
- __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
- __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
- __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
-
- __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
-}
-
-/**********************************************************
- * Routine: try_unlock_sram()
- * Description: If chip is GP type, unlock the SRAM for
- * general use.
- ***********************************************************/
-void try_unlock_memory(void)
-{
- int mode;
-
- /* if GP device unlock device SRAM for general use */
- /* secure code breaks for Secure/Emulation device - HS/E/T*/
- mode = get_device_type();
- if (mode == GP_DEVICE) {
- secure_unlock();
- }
- return;
-}
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called at time when only stack is available.
- **********************************************************/
-
-void s_init(void)
-{
- watchdog_init();
-#ifdef CONFIG_3430_AS_3410
- /* setup the scalability control register for
- * 3430 to work in 3410 mode
- */
- __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP);
-#endif
- try_unlock_memory();
- set_muxconf_regs();
- delay(100);
- prcm_init();
- per_clocks_enable();
- config_3430sdram_ddr();
-}
-
-/*******************************************************
- * Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
- ********************************************************/
-int misc_init_r (void)
-{
- return(0);
-}
-
-/******************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- ******************************************************/
-void wait_for_command_complete(unsigned int wd_base)
-{
- int pending = 1;
- do {
- pending = __raw_readl(wd_base + WWPS);
- } while (pending);
-}
-
-/****************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************/
-void watchdog_init(void)
-{
- /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
- * either taken care of by ROM (HS/EMU) or not accessible (GP).
- * We need to take care of WD2-MPU or take a PRCM reset. WD3
- * should not be running and does not generate a PRCM reset.
- */
- sr32(CM_FCLKEN_WKUP, 5, 1, 1);
- sr32(CM_ICLKEN_WKUP, 5, 1, 1);
- wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
-
- __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
- wait_for_command_complete(WD2_BASE);
- __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
-}
-
-/**********************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- **********************************************/
-int dram_init (void)
-{
- return 0;
-}
-
-/*****************************************************************
- * Routine: peripheral_enable
- * Description: Enable the clks & power for perifs (GPT2, UART1,...)
- ******************************************************************/
-void per_clocks_enable(void)
-{
- /* Enable GP2 timer. */
- sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
- sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
- sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
-
-#ifdef CFG_NS16550
-////#ifdef CONFIG_SERIAL3
- sr32(CM_FCLKEN_PER, 11, 1, 0x1);
- sr32(CM_ICLKEN_PER, 11, 1, 0x1);
-////#else
- /* Enable UART1 clocks */
- sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
- sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
-////#endif
-#endif
- delay(1000);
-}
-
-/* Set MUX for UART, GPMC, SDRC, GPIO */
-
-#define MUX_VAL(OFFSET,VALUE)\
- __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
-
-#define CP(x) (CONTROL_PADCONF_##x)
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_DEFAULT()\
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4 lab*/\
- MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5 lab*/\
- MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*sys_ndmareq1 lab*/\
- MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_IO_DIR lab*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1 lab*/\
- MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
- MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
- MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
- MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
- MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
- MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
- MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
- MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
- MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
- MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
- MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
- MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
- MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
- MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
- MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
- MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\
- MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/
-/**********************************************************
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers
- * specific to the hardware. Many pins need
- * to be moved from protect to primary mode.
- *********************************************************/
-void set_muxconf_regs(void)
-{
- MUX_DEFAULT();
-}
-
-/**********************************************************
- * Routine: nand+_init
- * Description: Set up nand for nand and jffs2 commands
- *********************************************************/
-int nand_init(void)
-{
- /* global settings */
- __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
- __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
- __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
-#ifdef CFG_NAND
- __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
-#endif
-
- /* setup CS0 for Micron NAND, leave other CS's to u-boot */
- __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
- delay(1000);
-
-#ifdef CFG_NAND
- __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
- __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
- __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
- __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
- __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
- __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
-
-#else /* CFG_ONENAND */
- __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
-#endif
-
- /* Enable the GPMC Mapping */
- __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
- ((OMAP34XX_GPMC_CS0_MAP>>24) & 0x3F) |
- (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
- delay(2000);
-
-#ifdef CFG_NAND
- if (nand_chip()){
-#ifdef CFG_PRINTF
- printf("Unsupported Chip!\n");
-#endif
- return 1;
- }
-#else
- if (onenand_chip()){
-#ifdef CFG_PRINTF
- printf("OneNAND Unsupported !\n");
-#endif
- return 1;
- }
-#endif
- return 0;
-}
-
-/* optionally do something like blinking LED */
-void board_hang (void)
-{ while (0) {};}
diff --git a/board/omap3430labrador/platform.S b/board/omap3430labrador/platform.S
deleted file mode 100644
index 5869270..0000000
--- a/board/omap3430labrador/platform.S
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004-2006
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-
-_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
-
-#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
- /* Copy DPLL code into SRAM */
- adr r0, go_to_speed /* get addr of clock setting code */
- mov r2, #384 /* r2 size to copy (div by 32 bytes) */
- mov r1, r1 /* r1 <- dest address (passed in) */
- add r2, r2, r0 /* r2 <- source end address */
-next2:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- bne next2
- mov pc, lr /* back to caller */
-
-/* ****************************************************************************
- * NOTE: 3430 X-loader currently does not use this code.
-* It could be removed its is kept for compatabily with u-boot.
- *
- * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- * -executed from SRAM.
- * R0 = CM_CLKEN_PLL-bypass value
- * R1 = CM_CLKSEL1_PLL-m, n, and divider values
- * R2 = CM_CLKSEL_CORE-divider values
- * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- *
- * Note: If core unlocks/relocks and SDRAM is running fast already it gets
- * confused. A reset of the controller gets it back. Taking away its
- * L3 when its not in self refresh seems bad for it. Normally, this code
- * runs from flash before SDR is init so that should be ok.
- ******************************************************************************/
-.global go_to_speed
- go_to_speed:
- stmfd sp!, {r4-r6}
-
- /* move into fast relock bypass */
- ldr r4, pll_ctl_add
- str r0, [r4]
-wait1:
- ldr r5, [r3] /* get status */
- and r5, r5, #0x1 /* isolate core status */
- cmp r5, #0x1 /* still locked? */
- beq wait1 /* if lock, loop */
-
- /* set new dpll dividers _after_ in bypass */
- ldr r5, pll_div_add1
- str r1, [r5] /* set m, n, m2 */
- ldr r5, pll_div_add2
- str r2, [r5] /* set l3/l4/.. dividers*/
- ldr r5, pll_div_add3 /* wkup */
- ldr r2, pll_div_val3 /* rsm val */
- str r2, [r5]
- ldr r5, pll_div_add4 /* gfx */
- ldr r2, pll_div_val4
- str r2, [r5]
- ldr r5, pll_div_add5 /* emu */
- ldr r2, pll_div_val5
- str r2, [r5]
-
- /* now prepare GPMC (flash) for new dpll speed */
- /* flash needs to be stable when we jump back to it */
- ldr r5, flash_cfg3_addr
- ldr r2, flash_cfg3_val
- str r2, [r5]
- ldr r5, flash_cfg4_addr
- ldr r2, flash_cfg4_val
- str r2, [r5]
- ldr r5, flash_cfg5_addr
- ldr r2, flash_cfg5_val
- str r2, [r5]
- ldr r5, flash_cfg1_addr
- ldr r2, [r5]
- orr r2, r2, #0x3 /* up gpmc divider */
- str r2, [r5]
-
- /* lock DPLL3 and wait a bit */
- orr r0, r0, #0x7 /* set up for lock mode */
- str r0, [r4] /* lock */
- nop /* ARM slow at this point working at sys_clk */
- nop
- nop
- nop
-wait2:
- ldr r5, [r3] /* get status */
- and r5, r5, #0x1 /* isolate core status */
- cmp r5, #0x1 /* still locked? */
- bne wait2 /* if lock, loop */
- nop
- nop
- nop
- nop
- ldmfd sp!, {r4-r6}
- mov pc, lr /* back to caller, locked */
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-/* The Nor has to be in the Flash Base CS0 for this condition to happen */
-flash_cfg1_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
-flash_cfg3_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
-flash_cfg3_val:
- .word STNOR_GPMC_CONFIG3
-flash_cfg4_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
-flash_cfg4_val:
- .word STNOR_GPMC_CONFIG4
-flash_cfg5_val:
- .word STNOR_GPMC_CONFIG5
-flash_cfg5_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
-pll_ctl_add:
- .word CM_CLKEN_PLL
-pll_div_add1:
- .word CM_CLKSEL1_PLL
-pll_div_add2:
- .word CM_CLKSEL_CORE
-pll_div_add3:
- .word CM_CLKSEL_WKUP
-pll_div_val3:
- .word (WKUP_RSM << 1)
-pll_div_add4:
- .word CM_CLKSEL_GFX
-pll_div_val4:
- .word (GFX_DIV << 0)
-pll_div_add5:
- .word CM_CLKSEL1_EMU
-pll_div_val5:
- .word CLSEL1_EMU_VAL
-
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
- mov ip, lr /* save link reg across call */
- bl s_init /* go setup pll,mux,memory */
- ldr ip, [sp] /* restore save ip */
- mov lr, ip /* restore link reg */
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-REG_CONTROL_STATUS:
- .word CONTROL_STATUS
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
-
-/* DPLL(1-4) PARAM TABLES */
-/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
- * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
- * The values are defined for all possible sysclk and for ES1 and ES2.
- */
-
-mpu_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word 0x0FE,0x07,0x05,0x01
-/* ES2 */
-.word 0x0FA,0x05,0x07,0x01
-/* 3410 */
-.word 0x085,0x05,0x07,0x01
-
-/* 13MHz */
-/* ES1 */
-.word 0x17D,0x0C,0x03,0x01
-/* ES2 */
-.word 0x1F4,0x0C,0x03,0x01
-/* 3410 */
-.word 0x10A,0x0C,0x03,0x01
-
-/* 19.2MHz */
-/* ES1 */
-.word 0x179,0x12,0x04,0x01
-/* ES2 */
-.word 0x271,0x17,0x03,0x01
-/* 3410 */
-.word 0x14C,0x17,0x03,0x01
-
-/* 26MHz */
-/* ES1 */
-.word 0x17D,0x19,0x03,0x01
-/* ES2 */
-.word 0x0FA,0x0C,0x07,0x01
-/* 3410 */
-.word 0x085,0x0C,0x07,0x01
-
-/* 38.4MHz */
-/* ES1 */
-.word 0x1FA,0x32,0x03,0x01
-/* ES2 */
-.word 0x271,0x2F,0x03,0x01
-/* 3410 */
-.word 0x14C,0x2F,0x03,0x01
-
-
-.globl get_mpu_dpll_param
-get_mpu_dpll_param:
- adr r0, mpu_dpll_param
- mov pc, lr
-
-iva_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word 0x07D,0x05,0x07,0x01
-/* ES2 */
-.word 0x0B4,0x05,0x07,0x01
-/* 3410 */
-.word 0x085,0x05,0x07,0x01
-
-/* 13MHz */
-/* ES1 */
-.word 0x0FA,0x0C,0x03,0x01
-/* ES2 */
-.word 0x168,0x0C,0x03,0x01
-/* 3410 */
-.word 0x10A,0x0C,0x03,0x01
-
-/* 19.2MHz */
-/* ES1 */
-.word 0x082,0x09,0x07,0x01
-/* ES2 */
-.word 0x0E1,0x0B,0x06,0x01
-/* 3410 */
-.word 0x14C,0x17,0x03,0x01
-
-/* 26MHz */
-/* ES1 */
-.word 0x07D,0x0C,0x07,0x01
-/* ES2 */
-.word 0x0B4,0x0C,0x07,0x01
-/* 3410 */
-.word 0x085,0x0C,0x07,0x01
-
-/* 38.4MHz */
-/* ES1 */
-.word 0x13F,0x30,0x03,0x01
-/* ES2 */
-.word 0x0E1,0x17,0x06,0x01
-/* 3410 */
-.word 0x14C,0x2F,0x03,0x01
-
-
-.globl get_iva_dpll_param
-get_iva_dpll_param:
- adr r0, iva_dpll_param
- mov pc, lr
-
-/* Core DPLL targets for L3 at 166 & L133 */
-core_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1
-/* ES2 */
-.word M_12,N_12,FSEL_12,M2_12
-/* 3410 */
-.word M_12,N_12,FSEL_12,M2_12
-
-/* 13MHz */
-/* ES1 */
-.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1
-/* ES2 */
-.word M_13,N_13,FSEL_13,M2_13
-/* 3410 */
-.word M_13,N_13,FSEL_13,M2_13
-
-/* 19.2MHz */
-/* ES1 */
-.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1
-/* ES2 */
-.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
-/* 3410 */
-.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
-
-/* 26MHz */
-/* ES1 */
-.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1
-/* ES2 */
-.word M_26,N_26,FSEL_26,M2_26
-/* 3410 */
-.word M_26,N_26,FSEL_26,M2_26
-
-/* 38.4MHz */
-/* ES1 */
-.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1
-/* ES2 */
-.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
-/* 3410 */
-.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
-
-.globl get_core_dpll_param
-get_core_dpll_param:
- adr r0, core_dpll_param
- mov pc, lr
-
-/* PER DPLL values are same for both ES1 and ES2 */
-per_dpll_param:
-/* 12MHz */
-.word 0xD8,0x05,0x07,0x09
-
-/* 13MHz */
-.word 0x1B0,0x0C,0x03,0x09
-
-/* 19.2MHz */
-.word 0xE1,0x09,0x07,0x09
-
-/* 26MHz */
-.word 0xD8,0x0C,0x07,0x09
-
-/* 38.4MHz */
-.word 0xE1,0x13,0x07,0x09
-
-.globl get_per_dpll_param
-get_per_dpll_param:
- adr r0, per_dpll_param
- mov pc, lr
-
diff --git a/board/omap3430labrador/x-load.lds b/board/omap3430labrador/x-load.lds
deleted file mode 100644
index 9402f74..0000000
--- a/board/omap3430labrador/x-load.lds
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * November 2006 - Changed to support 3430sdp device
- * Copyright (c) 2004-2006 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- cpu/omap3/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
diff --git a/board/omap3430sdp/Makefile b/board/omap3430sdp/Makefile
deleted file mode 100644
index d54b666..0000000
--- a/board/omap3430sdp/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := omap3430sdp.o
-SOBJS := platform.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/omap3430sdp/config.mk b/board/omap3430sdp/config.mk
deleted file mode 100644
index d6ad6c5..0000000
--- a/board/omap3430sdp/config.mk
+++ /dev/null
@@ -1,22 +0,0 @@
-#
-# (C) Copyright 2006
-# Texas Instruments, <www.ti.com>
-#
-# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# SDP3430 has 1 bank of 32MB or 128MB mDDR-SDRAM on CS0
-# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
-# Physical Address:
-# 8000'0000 (bank0)
-# A000'0000 (bank1) - re-mappable below CS1
-
-# For use if you want X-Loader to relocate from SRAM to DDR
-#TEXT_BASE = 0x80e80000
-
-# For XIP in 64K of SRAM or debug (GP device has it all availabe)
-# SRAM 40200000-4020FFFF base
-# initial stack at 0x4020fffc used in s_init (below xloader).
-# The run time stack is (above xloader, 2k below)
-# If any globals exist there needs to be room for them also
-TEXT_BASE = 0x40208800
diff --git a/board/omap3430sdp/omap3430sdp.c b/board/omap3430sdp/omap3430sdp.c
deleted file mode 100644
index 6ed62bc..0000000
--- a/board/omap3430sdp/omap3430sdp.c
+++ /dev/null
@@ -1,779 +0,0 @@
-/*
- * (C) Copyright 2006
- * Texas Instruments, <www.ti.com>
- * Jian Zhang <jzhang@ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <command.h>
-#include <part.h>
-#include <fat.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/mem.h>
-
-/* Used to index into DPLL parameter tables */
-struct dpll_param {
- unsigned int m;
- unsigned int n;
- unsigned int fsel;
- unsigned int m2;
-};
-
-typedef struct dpll_param dpll_param;
-
-#define MAX_SIL_INDEX 3
-
-/* Following functions are exported from lowlevel_init.S */
-extern dpll_param * get_mpu_dpll_param();
-extern dpll_param * get_iva_dpll_param();
-extern dpll_param * get_core_dpll_param();
-extern dpll_param * get_per_dpll_param();
-
-#define __raw_readl(a) (*(volatile unsigned int *)(a))
-#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
-#define __raw_readw(a) (*(volatile unsigned short *)(a))
-#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
-
-/*******************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- ******************************************************/
-static inline void delay(unsigned long loops)
-{
- __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0"(loops));
-}
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init (void)
-{
- return 0;
-}
-
-/*************************************************************
- * get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
- int mode;
- mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
- return(mode >>= 8);
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
- u32 cpuid=0;
- /* On ES1.0 the IDCODE register is not exposed on L4
- * so using CPU ID to differentiate
- * between ES2.0 and ES1.0.
- */
- __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
- if((cpuid & 0xf) == 0x0)
- return CPU_3430_ES1;
- else
- return CPU_3430_ES2;
-
-}
-
-/******************************************
- * cpu_is_3410(void) - returns true for 3410
- ******************************************/
-u32 cpu_is_3410(void)
-{
- int status;
- if(get_cpu_rev() < CPU_3430_ES2) {
- return 0;
- } else {
- /* read scalability status and return 1 for 3410*/
- status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
- /* Check whether MPU frequency is set to 266 MHz which
- * is nominal for 3410. If yes return true else false
- */
- if (((status >> 8) & 0x3) == 0x2)
- return 1;
- else
- return 0;
- }
-}
-
-/*****************************************************************
- * sr32 - clear & set a value in a bit range for a 32 bit address
- *****************************************************************/
-void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
-{
- u32 tmp, msk = 0;
- msk = 1 << num_bits;
- --msk;
- tmp = __raw_readl(addr) & ~(msk << start_bit);
- tmp |= value << start_bit;
- __raw_writel(tmp, addr);
-}
-
-/*********************************************************************
- * wait_on_value() - common routine to allow waiting for changes in
- * volatile regs.
- *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
-{
- u32 i = 0, val;
- do {
- ++i;
- val = __raw_readl(read_addr) & read_bit_mask;
- if (val == match_value)
- return (1);
- if (i == bound)
- return (0);
- } while (1);
-}
-
-#ifdef CFG_3430SDRAM_DDR
-/*********************************************************************
- * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
- *********************************************************************/
-void config_3430sdram_ddr(void)
-{
- /* reset sdrc controller */
- __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
- wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
- __raw_writel(0, SDRC_SYSCONFIG);
-
- /* setup sdrc to ball mux */
- __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
-
- /* set mdcfg */
- __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
-
- /* set timing */
- __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
- __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
- __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
-
- /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- delay(5000);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
- /* set mr0 */
- __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
-
- /* set up dll */
- __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
- delay(0x2000); /* give time to lock */
-
-}
-#endif // CFG_3430SDRAM_DDR
-
-/*************************************************************
- * get_sys_clk_speed - determine reference oscillator speed
- * based on known 32kHz clock and gptimer.
- *************************************************************/
-u32 get_osc_clk_speed(void)
-{
- u32 start, cstart, cend, cdiff, val;
-
- val = __raw_readl(PRM_CLKSRC_CTRL);
- /* If SYS_CLK is being divided by 2, remove for now */
- val = (val & (~BIT7)) | BIT6;
- __raw_writel(val, PRM_CLKSRC_CTRL);
-
- /* enable timer2 */
- val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
- __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
-
- /* Enable I and F Clocks for GPT1 */
- val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
- __raw_writel(val, CM_ICLKEN_WKUP);
- val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
- __raw_writel(val, CM_FCLKEN_WKUP);
-
- __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
- __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
- /* enable 32kHz source *//* enabled out of reset */
- /* determine sys_clk via gauging */
-
- start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
- while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
- cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
- while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
- cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
- cdiff = cend - cstart; /* get elapsed ticks */
-
- /* based on number of ticks assign speed */
- if (cdiff > 19000)
- return (S38_4M);
- else if (cdiff > 15200)
- return (S26M);
- else if (cdiff > 13000)
- return (S24M);
- else if (cdiff > 9000)
- return (S19_2M);
- else if (cdiff > 7600)
- return (S13M);
- else
- return (S12M);
-}
-
-/******************************************************************************
- * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
- * -- input oscillator clock frequency.
- *
- *****************************************************************************/
-void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
-{
- if(osc_clk == S38_4M)
- *sys_clkin_sel= 4;
- else if(osc_clk == S26M)
- *sys_clkin_sel = 3;
- else if(osc_clk == S19_2M)
- *sys_clkin_sel = 2;
- else if(osc_clk == S13M)
- *sys_clkin_sel = 1;
- else if(osc_clk == S12M)
- *sys_clkin_sel = 0;
-}
-
-/******************************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h
- * -- called from SRAM, or Flash (using temp SRAM stack).
- *****************************************************************************/
-void prcm_init(void)
-{
- u32 osc_clk=0, sys_clkin_sel;
- dpll_param *dpll_param_p;
- u32 clk_index, sil_index;
-
- /* Gauge the input clock speed and find out the sys_clkin_sel
- * value corresponding to the input clock.
- */
- osc_clk = get_osc_clk_speed();
- get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
-
- sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
-
- /* If the input clock is greater than 19.2M always divide/2 */
- if(sys_clkin_sel > 2) {
- sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
- clk_index = sys_clkin_sel/2;
- } else {
- sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
- clk_index = sys_clkin_sel;
- }
-
- /* The DPLL tables are defined according to sysclk value and
- * silicon revision. The clk_index value will be used to get
- * the values for that input sysclk from the DPLL param table
- * and sil_index will get the values for that SysClk for the
- * appropriate silicon rev.
- */
- if(cpu_is_3410())
- sil_index = 2;
- else {
- if(get_cpu_rev() == CPU_3430_ES1)
- sil_index = 0;
- else if(get_cpu_rev() == CPU_3430_ES2)
- sil_index = 1;
- }
-
- /* Unlock MPU DPLL (slows things down, and needed later) */
- sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
- wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
-
- /* Getting the base address of Core DPLL param table*/
- dpll_param_p = (dpll_param *)get_core_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
- /* CORE DPLL */
- /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
- sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
- wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
- sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
- sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
- sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
- sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
- sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
- sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
- sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
- sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
- sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
- sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
- sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
- sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
-
- /* Getting the base address to PER DPLL param table*/
- dpll_param_p = (dpll_param *)get_per_dpll_param();
- /* Moving it to the right sysclk base */
- dpll_param_p = dpll_param_p + clk_index;
- /* PER DPLL */
- sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
- wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
- sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
- sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
- sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
- sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
- sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
- sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
- sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
- sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */
- sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
-
- /* Getting the base address to MPU DPLL param table*/
- dpll_param_p = (dpll_param *)get_mpu_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
- /* MPU DPLL (unlocked already) */
- sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
- sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
- sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
- sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
-
- /* Getting the base address to IVA DPLL param table*/
- dpll_param_p = (dpll_param *)get_iva_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
- /* IVA DPLL (set to 12*20=240MHz) */
- sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
- wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
- sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
- sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
- sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
- sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
-
- /* Set up GPTimers to sys_clk source only */
- sr32(CM_CLKSEL_PER, 0, 8, 0xff);
- sr32(CM_CLKSEL_WKUP, 0, 1, 1);
-
- delay(5000);
-}
-
-/*****************************************
- * Routine: secure_unlock
- * Description: Setup security registers for access
- * (GP Device only)
- *****************************************/
-void secure_unlock(void)
-{
- /* Permission values for registers -Full fledged permissions to all */
- #define UNLOCK_1 0xFFFFFFFF
- #define UNLOCK_2 0x00000000
- #define UNLOCK_3 0x0000FFFF
- /* Protection Module Register Target APE (PM_RT)*/
- __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
- __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
- __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
- __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
-
- __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
- __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
- __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
-
- __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
- __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
- __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
- __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
-
- /* IVA Changes */
- __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
- __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
- __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
-
- __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
-}
-
-/**********************************************************
- * Routine: try_unlock_sram()
- * Description: If chip is GP type, unlock the SRAM for
- * general use.
- ***********************************************************/
-void try_unlock_memory(void)
-{
- int mode;
-
- /* if GP device unlock device SRAM for general use */
- /* secure code breaks for Secure/Emulation device - HS/E/T*/
- mode = get_device_type();
- if (mode == GP_DEVICE) {
- secure_unlock();
- }
- return;
-}
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called at time when only stack is available.
- **********************************************************/
-
-void s_init(void)
-{
- watchdog_init();
-#ifdef CONFIG_3430_AS_3410
- /* setup the scalability control register for
- * 3430 to work in 3410 mode
- */
- __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP);
-#endif
- try_unlock_memory();
- set_muxconf_regs();
- delay(100);
- prcm_init();
- per_clocks_enable();
- config_3430sdram_ddr();
-}
-
-/*******************************************************
- * Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
- ********************************************************/
-int misc_init_r (void)
-{
- return(0);
-}
-
-/******************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- ******************************************************/
-void wait_for_command_complete(unsigned int wd_base)
-{
- int pending = 1;
- do {
- pending = __raw_readl(wd_base + WWPS);
- } while (pending);
-}
-
-/****************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************/
-void watchdog_init(void)
-{
- /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
- * either taken care of by ROM (HS/EMU) or not accessible (GP).
- * We need to take care of WD2-MPU or take a PRCM reset. WD3
- * should not be running and does not generate a PRCM reset.
- */
- sr32(CM_FCLKEN_WKUP, 5, 1, 1);
- sr32(CM_ICLKEN_WKUP, 5, 1, 1);
- wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
-
- __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
- wait_for_command_complete(WD2_BASE);
- __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
-}
-
-/**********************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- **********************************************/
-int dram_init (void)
-{
- return 0;
-}
-
-/*****************************************************************
- * Routine: peripheral_enable
- * Description: Enable the clks & power for perifs (GPT2, UART1,...)
- ******************************************************************/
-void per_clocks_enable(void)
-{
- /* Enable GP2 timer. */
- sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
- sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
- sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
-
-#ifdef CFG_NS16550
- /* Enable UART1 clocks */
- sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
- sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
-#endif
- delay(1000);
-}
-
-/* Set MUX for UART, GPMC, SDRC, GPIO */
-
-#define MUX_VAL(OFFSET,VALUE)\
- __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
-
-#define CP(x) (CONTROL_PADCONF_##x)
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_DEFAULT()\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\
- MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\
- MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\
- MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
- MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
- MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
- MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
- MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
- MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
- MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
- MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
- MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
- MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
- MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
- MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
- MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
- MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
- MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/
-
-/**********************************************************
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers
- * specific to the hardware. Many pins need
- * to be moved from protect to primary mode.
- *********************************************************/
-void set_muxconf_regs(void)
-{
- MUX_DEFAULT();
-}
-
-/**********************************************************
- * Routine: nand+_init
- * Description: Set up nand for nand and jffs2 commands
- *********************************************************/
-int nand_init(void)
-{
- /* global settings */
- __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
- __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
- __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
-#ifdef CFG_NAND
- __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
-#endif
-
- /* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0
- * , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0.
- * We configure only GPMC CS0 with required values. Configiring other devices
- * at other CS in done in u-boot anyway. So we don't have to bother doing it here.
- */
- __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
- delay(1000);
-
-#ifdef CFG_NAND
- __raw_writel( SMNAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
- __raw_writel( SMNAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
- __raw_writel( SMNAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
- __raw_writel( SMNAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
- __raw_writel( SMNAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
- __raw_writel( SMNAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
-
-#else /* CFG_ONENAND */
- __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
-#endif
-
- /* Enable the GPMC Mapping */
- __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
- ((OMAP34XX_GPMC_CS0_MAP>>24) & 0x3F) |
- (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
- delay(2000);
-#if defined(CFG_NAND)
- if (nand_chip()){
-#ifdef CFG_PRINTF
- printf("Unsupported Chip!\n");
-#endif
- return 1;
- }
-#elif defined(CFG_ONENAND)
- if (onenand_chip()){
-#ifdef CFG_PRINTF
- printf("OneNAND Unsupported !\n");
-#endif
- return 1;
- }
-#endif
- return 0;
-}
-
-#ifdef CFG_CMD_FAT
-typedef int (mmc_boot_addr) (void);
-int mmc_boot(void)
-{
- long size, i;
- unsigned long offset = CFG_LOADADDR;
- unsigned long count;
- char buf[12];
- block_dev_desc_t *dev_desc = NULL;
- int dev = 0;
- int part = 1;
- char *ep;
- unsigned char ret = 0;
-
- printf("Starting X-loader on MMC \n");
-
- ret = mmc_init(1);
- if(ret == 0){
- printf("\n MMC init failed \n");
- return 0;
- }
-
- dev_desc = mmc_get_dev(0);
- fat_register_device(dev_desc, 1);
- size = file_fat_read("u-boot.bin", (unsigned char *)offset, 0);
- if (size == -1) {
- return 0;
- }
- printf("\n%ld Bytes Read from MMC \n", size);
-
- printf("Starting OS Bootloader from MMC...\n");
-
- ((mmc_boot_addr *) CFG_LOADADDR) ();
-
- return 0;
-}
-#endif
-
-/* optionally do something like blinking LED */
-void board_hang (void)
-{ while (0) {};}
diff --git a/board/omap3430sdp/platform.S b/board/omap3430sdp/platform.S
deleted file mode 100644
index 5869270..0000000
--- a/board/omap3430sdp/platform.S
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004-2006
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-
-_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
-
-#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
- /* Copy DPLL code into SRAM */
- adr r0, go_to_speed /* get addr of clock setting code */
- mov r2, #384 /* r2 size to copy (div by 32 bytes) */
- mov r1, r1 /* r1 <- dest address (passed in) */
- add r2, r2, r0 /* r2 <- source end address */
-next2:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- bne next2
- mov pc, lr /* back to caller */
-
-/* ****************************************************************************
- * NOTE: 3430 X-loader currently does not use this code.
-* It could be removed its is kept for compatabily with u-boot.
- *
- * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- * -executed from SRAM.
- * R0 = CM_CLKEN_PLL-bypass value
- * R1 = CM_CLKSEL1_PLL-m, n, and divider values
- * R2 = CM_CLKSEL_CORE-divider values
- * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- *
- * Note: If core unlocks/relocks and SDRAM is running fast already it gets
- * confused. A reset of the controller gets it back. Taking away its
- * L3 when its not in self refresh seems bad for it. Normally, this code
- * runs from flash before SDR is init so that should be ok.
- ******************************************************************************/
-.global go_to_speed
- go_to_speed:
- stmfd sp!, {r4-r6}
-
- /* move into fast relock bypass */
- ldr r4, pll_ctl_add
- str r0, [r4]
-wait1:
- ldr r5, [r3] /* get status */
- and r5, r5, #0x1 /* isolate core status */
- cmp r5, #0x1 /* still locked? */
- beq wait1 /* if lock, loop */
-
- /* set new dpll dividers _after_ in bypass */
- ldr r5, pll_div_add1
- str r1, [r5] /* set m, n, m2 */
- ldr r5, pll_div_add2
- str r2, [r5] /* set l3/l4/.. dividers*/
- ldr r5, pll_div_add3 /* wkup */
- ldr r2, pll_div_val3 /* rsm val */
- str r2, [r5]
- ldr r5, pll_div_add4 /* gfx */
- ldr r2, pll_div_val4
- str r2, [r5]
- ldr r5, pll_div_add5 /* emu */
- ldr r2, pll_div_val5
- str r2, [r5]
-
- /* now prepare GPMC (flash) for new dpll speed */
- /* flash needs to be stable when we jump back to it */
- ldr r5, flash_cfg3_addr
- ldr r2, flash_cfg3_val
- str r2, [r5]
- ldr r5, flash_cfg4_addr
- ldr r2, flash_cfg4_val
- str r2, [r5]
- ldr r5, flash_cfg5_addr
- ldr r2, flash_cfg5_val
- str r2, [r5]
- ldr r5, flash_cfg1_addr
- ldr r2, [r5]
- orr r2, r2, #0x3 /* up gpmc divider */
- str r2, [r5]
-
- /* lock DPLL3 and wait a bit */
- orr r0, r0, #0x7 /* set up for lock mode */
- str r0, [r4] /* lock */
- nop /* ARM slow at this point working at sys_clk */
- nop
- nop
- nop
-wait2:
- ldr r5, [r3] /* get status */
- and r5, r5, #0x1 /* isolate core status */
- cmp r5, #0x1 /* still locked? */
- bne wait2 /* if lock, loop */
- nop
- nop
- nop
- nop
- ldmfd sp!, {r4-r6}
- mov pc, lr /* back to caller, locked */
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-/* The Nor has to be in the Flash Base CS0 for this condition to happen */
-flash_cfg1_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
-flash_cfg3_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
-flash_cfg3_val:
- .word STNOR_GPMC_CONFIG3
-flash_cfg4_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
-flash_cfg4_val:
- .word STNOR_GPMC_CONFIG4
-flash_cfg5_val:
- .word STNOR_GPMC_CONFIG5
-flash_cfg5_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
-pll_ctl_add:
- .word CM_CLKEN_PLL
-pll_div_add1:
- .word CM_CLKSEL1_PLL
-pll_div_add2:
- .word CM_CLKSEL_CORE
-pll_div_add3:
- .word CM_CLKSEL_WKUP
-pll_div_val3:
- .word (WKUP_RSM << 1)
-pll_div_add4:
- .word CM_CLKSEL_GFX
-pll_div_val4:
- .word (GFX_DIV << 0)
-pll_div_add5:
- .word CM_CLKSEL1_EMU
-pll_div_val5:
- .word CLSEL1_EMU_VAL
-
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
- mov ip, lr /* save link reg across call */
- bl s_init /* go setup pll,mux,memory */
- ldr ip, [sp] /* restore save ip */
- mov lr, ip /* restore link reg */
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-REG_CONTROL_STATUS:
- .word CONTROL_STATUS
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
-
-/* DPLL(1-4) PARAM TABLES */
-/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
- * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
- * The values are defined for all possible sysclk and for ES1 and ES2.
- */
-
-mpu_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word 0x0FE,0x07,0x05,0x01
-/* ES2 */
-.word 0x0FA,0x05,0x07,0x01
-/* 3410 */
-.word 0x085,0x05,0x07,0x01
-
-/* 13MHz */
-/* ES1 */
-.word 0x17D,0x0C,0x03,0x01
-/* ES2 */
-.word 0x1F4,0x0C,0x03,0x01
-/* 3410 */
-.word 0x10A,0x0C,0x03,0x01
-
-/* 19.2MHz */
-/* ES1 */
-.word 0x179,0x12,0x04,0x01
-/* ES2 */
-.word 0x271,0x17,0x03,0x01
-/* 3410 */
-.word 0x14C,0x17,0x03,0x01
-
-/* 26MHz */
-/* ES1 */
-.word 0x17D,0x19,0x03,0x01
-/* ES2 */
-.word 0x0FA,0x0C,0x07,0x01
-/* 3410 */
-.word 0x085,0x0C,0x07,0x01
-
-/* 38.4MHz */
-/* ES1 */
-.word 0x1FA,0x32,0x03,0x01
-/* ES2 */
-.word 0x271,0x2F,0x03,0x01
-/* 3410 */
-.word 0x14C,0x2F,0x03,0x01
-
-
-.globl get_mpu_dpll_param
-get_mpu_dpll_param:
- adr r0, mpu_dpll_param
- mov pc, lr
-
-iva_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word 0x07D,0x05,0x07,0x01
-/* ES2 */
-.word 0x0B4,0x05,0x07,0x01
-/* 3410 */
-.word 0x085,0x05,0x07,0x01
-
-/* 13MHz */
-/* ES1 */
-.word 0x0FA,0x0C,0x03,0x01
-/* ES2 */
-.word 0x168,0x0C,0x03,0x01
-/* 3410 */
-.word 0x10A,0x0C,0x03,0x01
-
-/* 19.2MHz */
-/* ES1 */
-.word 0x082,0x09,0x07,0x01
-/* ES2 */
-.word 0x0E1,0x0B,0x06,0x01
-/* 3410 */
-.word 0x14C,0x17,0x03,0x01
-
-/* 26MHz */
-/* ES1 */
-.word 0x07D,0x0C,0x07,0x01
-/* ES2 */
-.word 0x0B4,0x0C,0x07,0x01
-/* 3410 */
-.word 0x085,0x0C,0x07,0x01
-
-/* 38.4MHz */
-/* ES1 */
-.word 0x13F,0x30,0x03,0x01
-/* ES2 */
-.word 0x0E1,0x17,0x06,0x01
-/* 3410 */
-.word 0x14C,0x2F,0x03,0x01
-
-
-.globl get_iva_dpll_param
-get_iva_dpll_param:
- adr r0, iva_dpll_param
- mov pc, lr
-
-/* Core DPLL targets for L3 at 166 & L133 */
-core_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1
-/* ES2 */
-.word M_12,N_12,FSEL_12,M2_12
-/* 3410 */
-.word M_12,N_12,FSEL_12,M2_12
-
-/* 13MHz */
-/* ES1 */
-.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1
-/* ES2 */
-.word M_13,N_13,FSEL_13,M2_13
-/* 3410 */
-.word M_13,N_13,FSEL_13,M2_13
-
-/* 19.2MHz */
-/* ES1 */
-.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1
-/* ES2 */
-.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
-/* 3410 */
-.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
-
-/* 26MHz */
-/* ES1 */
-.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1
-/* ES2 */
-.word M_26,N_26,FSEL_26,M2_26
-/* 3410 */
-.word M_26,N_26,FSEL_26,M2_26
-
-/* 38.4MHz */
-/* ES1 */
-.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1
-/* ES2 */
-.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
-/* 3410 */
-.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
-
-.globl get_core_dpll_param
-get_core_dpll_param:
- adr r0, core_dpll_param
- mov pc, lr
-
-/* PER DPLL values are same for both ES1 and ES2 */
-per_dpll_param:
-/* 12MHz */
-.word 0xD8,0x05,0x07,0x09
-
-/* 13MHz */
-.word 0x1B0,0x0C,0x03,0x09
-
-/* 19.2MHz */
-.word 0xE1,0x09,0x07,0x09
-
-/* 26MHz */
-.word 0xD8,0x0C,0x07,0x09
-
-/* 38.4MHz */
-.word 0xE1,0x13,0x07,0x09
-
-.globl get_per_dpll_param
-get_per_dpll_param:
- adr r0, per_dpll_param
- mov pc, lr
-
diff --git a/board/omap3430sdp/x-load.lds b/board/omap3430sdp/x-load.lds
deleted file mode 100644
index 9402f74..0000000
--- a/board/omap3430sdp/x-load.lds
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * November 2006 - Changed to support 3430sdp device
- * Copyright (c) 2004-2006 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- cpu/omap3/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
diff --git a/board/omap3530gta04/config.mk b/board/omap3530gta04/config.mk
index 0122e2f..01eafc1 100644
--- a/board/omap3530gta04/config.mk
+++ b/board/omap3530gta04/config.mk
@@ -20,4 +20,4 @@
# initial stack at 0x4020fffc used in s_init (below xloader).
# The run time stack is (above xloader, 2k below)
# If any globals exist there needs to be room for them also
-TEXT_BASE = 0x40200800
+TEXT_BASE = 0x40208800
diff --git a/board/omap3evm/Makefile b/board/omap3evm/Makefile
deleted file mode 100644
index d83f45e..0000000
--- a/board/omap3evm/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := omap3evm.o
-SOBJS := platform.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/omap3evm/config.mk b/board/omap3evm/config.mk
deleted file mode 100644
index a45ec22..0000000
--- a/board/omap3evm/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-# (C) Copyright 2006
-# Texas Instruments, <www.ti.com>
-#
-# OMAP3EVM board uses OMAP3430 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments#
-#
-# OMAP3EVM has 1 bank of 128MB mPOP-SDRAM on CS0
-# Physical Address:
-# 8000'0000 (bank0)
-
-# For use if you want X-Loader to relocate from SRAM to DDR
-#TEXT_BASE = 0x80e80000
-
-# For XIP in 64K of SRAM or debug (GP device has it all availabe)
-# SRAM 40200000-4020FFFF base
-# initial stack at 0x4020fffc used in s_init (below xloader).
-# The run time stack is (above xloader, 2k below)
-# If any globals exist there needs to be room for them also
-TEXT_BASE = 0x40200800
diff --git a/board/omap3evm/omap3evm.c b/board/omap3evm/omap3evm.c
deleted file mode 100644
index 16c1f70..0000000
--- a/board/omap3evm/omap3evm.c
+++ /dev/null
@@ -1,814 +0,0 @@
-/*
- * (C) Copyright 2006
- * Texas Instruments, <www.ti.com>
- * Jian Zhang <jzhang@ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <command.h>
-#include <part.h>
-#include <fat.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/mem.h>
-
-/* Used to index into DPLL parameter tables */
-struct dpll_param {
- unsigned int m;
- unsigned int n;
- unsigned int fsel;
- unsigned int m2;
-};
-
-typedef struct dpll_param dpll_param;
-
-/* Following functions are exported from lowlevel_init.S */
-extern dpll_param * get_mpu_dpll_param();
-extern dpll_param * get_iva_dpll_param();
-extern dpll_param * get_core_dpll_param();
-extern dpll_param * get_per_dpll_param();
-
-#define __raw_readl(a) (*(volatile unsigned int *)(a))
-#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
-#define __raw_readw(a) (*(volatile unsigned short *)(a))
-#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
-
-/*******************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- ******************************************************/
-static inline void delay(unsigned long loops)
-{
- __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0"(loops));
-}
-
-void udelay (unsigned long usecs) {
- delay(usecs);
-}
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init (void)
-{
- return 0;
-}
-
-/*************************************************************
- * get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
- int mode;
- mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
- return(mode >>= 8);
-}
-
-/************************************************
- * get_sysboot_value(void) - return SYS_BOOT[4:0]
- ************************************************/
-u32 get_sysboot_value(void)
-{
- int mode;
- mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
- return mode;
-}
-/*************************************************************
- * Routine: get_mem_type(void) - returns the kind of memory connected
- * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
- *************************************************************/
-u32 get_mem_type(void)
-{
- u32 mem_type = get_sysboot_value();
- switch (mem_type){
- case 0:
- case 2:
- case 4:
- case 16:
- case 22: return GPMC_ONENAND;
-
- case 1:
- case 12:
- case 15:
- case 21:
- case 27: return GPMC_NAND;
-
- case 3:
- case 6: return MMC_ONENAND;
-
- case 8:
- case 11:
- case 14:
- case 20:
- case 26: return GPMC_MDOC;
-
- case 17:
- case 18:
- case 24: return MMC_NAND;
-
- case 7:
- case 10:
- case 13:
- case 19:
- case 25:
- default: return GPMC_NOR;
- }
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
- u32 cpuid=0;
- /* On ES1.0 the IDCODE register is not exposed on L4
- * so using CPU ID to differentiate
- * between ES2.0 and ES1.0.
- */
- __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
- if((cpuid & 0xf) == 0x0)
- return CPU_3430_ES1;
- else
- return CPU_3430_ES2;
-
-}
-
-/******************************************
- * cpu_is_3410(void) - returns true for 3410
- ******************************************/
-u32 cpu_is_3410(void)
-{
- int status;
- if(get_cpu_rev() < CPU_3430_ES2) {
- return 0;
- } else {
- /* read scalability status and return 1 for 3410*/
- status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
- /* Check whether MPU frequency is set to 266 MHz which
- * is nominal for 3410. If yes return true else false
- */
- if (((status >> 8) & 0x3) == 0x2)
- return 1;
- else
- return 0;
- }
-}
-
-/*****************************************************************
- * sr32 - clear & set a value in a bit range for a 32 bit address
- *****************************************************************/
-void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
-{
- u32 tmp, msk = 0;
- msk = 1 << num_bits;
- --msk;
- tmp = __raw_readl(addr) & ~(msk << start_bit);
- tmp |= value << start_bit;
- __raw_writel(tmp, addr);
-}
-
-/*********************************************************************
- * wait_on_value() - common routine to allow waiting for changes in
- * volatile regs.
- *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
-{
- u32 i = 0, val;
- do {
- ++i;
- val = __raw_readl(read_addr) & read_bit_mask;
- if (val == match_value)
- return (1);
- if (i == bound)
- return (0);
- } while (1);
-}
-
-#ifdef CFG_3430SDRAM_DDR
-/*********************************************************************
- * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
- *********************************************************************/
-void config_3430sdram_ddr(void)
-{
- /* reset sdrc controller */
- __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
- wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
- __raw_writel(0, SDRC_SYSCONFIG);
-
- /* setup sdrc to ball mux */
- __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
-
- /* set mdcfg */
- __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
-
- /* set timing */
- if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){
- __raw_writel(INFINEON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
- __raw_writel(INFINEON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
- }
- if ((get_mem_type() == GPMC_NAND) ||(get_mem_type() == MMC_NAND)){
- __raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
- __raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
- }
-
- __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
- __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
-
- /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- delay(5000);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
-
- /* set mr0 */
- __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
-
- /* set up dll */
- __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
- delay(0x2000); /* give time to lock */
-
-}
-#endif // CFG_3430SDRAM_DDR
-
-/*************************************************************
- * get_sys_clk_speed - determine reference oscillator speed
- * based on known 32kHz clock and gptimer.
- *************************************************************/
-u32 get_osc_clk_speed(void)
-{
- u32 start, cstart, cend, cdiff, val;
-
- val = __raw_readl(PRM_CLKSRC_CTRL);
- /* If SYS_CLK is being divided by 2, remove for now */
- val = (val & (~BIT7)) | BIT6;
- __raw_writel(val, PRM_CLKSRC_CTRL);
-
- /* enable timer2 */
- val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
- __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
-
- /* Enable I and F Clocks for GPT1 */
- val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
- __raw_writel(val, CM_ICLKEN_WKUP);
- val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
- __raw_writel(val, CM_FCLKEN_WKUP);
-
- __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
- __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
- /* enable 32kHz source *//* enabled out of reset */
- /* determine sys_clk via gauging */
-
- start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
- while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
- cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
- while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
- cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
- cdiff = cend - cstart; /* get elapsed ticks */
-
- /* based on number of ticks assign speed */
- if (cdiff > 19000)
- return (S38_4M);
- else if (cdiff > 15200)
- return (S26M);
- else if (cdiff > 13000)
- return (S24M);
- else if (cdiff > 9000)
- return (S19_2M);
- else if (cdiff > 7600)
- return (S13M);
- else
- return (S12M);
-}
-
-/******************************************************************************
- * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
- * -- input oscillator clock frequency.
- *
- *****************************************************************************/
-void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
-{
- if(osc_clk == S38_4M)
- *sys_clkin_sel= 4;
- else if(osc_clk == S26M)
- *sys_clkin_sel = 3;
- else if(osc_clk == S19_2M)
- *sys_clkin_sel = 2;
- else if(osc_clk == S13M)
- *sys_clkin_sel = 1;
- else if(osc_clk == S12M)
- *sys_clkin_sel = 0;
-}
-
-/******************************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h
- * -- called from SRAM, or Flash (using temp SRAM stack).
- *****************************************************************************/
-void prcm_init(void)
-{
- u32 osc_clk=0, sys_clkin_sel;
- dpll_param *dpll_param_p;
- u32 clk_index, sil_index;
-
- /* Gauge the input clock speed and find out the sys_clkin_sel
- * value corresponding to the input clock.
- */
- osc_clk = get_osc_clk_speed();
- get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
-
- sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
-
- /* If the input clock is greater than 19.2M always divide/2 */
- if(sys_clkin_sel > 2) {
- sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
- clk_index = sys_clkin_sel/2;
- } else {
- sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
- clk_index = sys_clkin_sel;
- }
-
- /* The DPLL tables are defined according to sysclk value and
- * silicon revision. The clk_index value will be used to get
- * the values for that input sysclk from the DPLL param table
- * and sil_index will get the values for that SysClk for the
- * appropriate silicon rev.
- */
- sil_index = get_cpu_rev() - 1;
-
- /* Unlock MPU DPLL (slows things down, and needed later) */
- sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
- wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
-
- /* Getting the base address of Core DPLL param table*/
- dpll_param_p = (dpll_param *)get_core_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
- /* CORE DPLL */
- /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
- sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
- wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
- sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
- sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
- sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
- sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
- sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
- sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
- sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
- sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
- sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
- sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
- sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
- sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
-
- /* Getting the base address to PER DPLL param table*/
- dpll_param_p = (dpll_param *)get_per_dpll_param();
- /* Moving it to the right sysclk base */
- dpll_param_p = dpll_param_p + clk_index;
- /* PER DPLL */
- sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
- wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
- sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
- sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
- sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
- sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
- sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
- sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
- sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
- sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */
- sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
-
- /* Getting the base address to MPU DPLL param table*/
- dpll_param_p = (dpll_param *)get_mpu_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
- /* MPU DPLL (unlocked already) */
- sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
- sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
- sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
- sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
-
- /* Getting the base address to IVA DPLL param table*/
- dpll_param_p = (dpll_param *)get_iva_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
- /* IVA DPLL (set to 12*20=240MHz) */
- sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
- wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
- sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
- sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
- sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
- sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
-
- /* Set up GPTimers to sys_clk source only */
- sr32(CM_CLKSEL_PER, 0, 8, 0xff);
- sr32(CM_CLKSEL_WKUP, 0, 1, 1);
-
- delay(5000);
-}
-
-/*****************************************
- * Routine: secure_unlock
- * Description: Setup security registers for access
- * (GP Device only)
- *****************************************/
-void secure_unlock(void)
-{
- /* Permission values for registers -Full fledged permissions to all */
- #define UNLOCK_1 0xFFFFFFFF
- #define UNLOCK_2 0x00000000
- #define UNLOCK_3 0x0000FFFF
- /* Protection Module Register Target APE (PM_RT)*/
- __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
- __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
- __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
- __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
-
- __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
- __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
- __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
-
- __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
- __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
- __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
- __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
-
- /* IVA Changes */
- __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
- __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
- __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
-
- __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
-}
-
-/**********************************************************
- * Routine: try_unlock_sram()
- * Description: If chip is GP type, unlock the SRAM for
- * general use.
- ***********************************************************/
-void try_unlock_memory(void)
-{
- int mode;
-
- /* if GP device unlock device SRAM for general use */
- /* secure code breaks for Secure/Emulation device - HS/E/T*/
- mode = get_device_type();
- if (mode == GP_DEVICE) {
- secure_unlock();
- }
- return;
-}
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called at time when only stack is available.
- **********************************************************/
-
-void s_init(void)
-{
- watchdog_init();
-#ifdef CONFIG_3430_AS_3410
- /* setup the scalability control register for
- * 3430 to work in 3410 mode
- */
- __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP);
-#endif
- try_unlock_memory();
- set_muxconf_regs();
- delay(100);
- prcm_init();
- per_clocks_enable();
- config_3430sdram_ddr();
-}
-
-/*******************************************************
- * Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
- ********************************************************/
-int misc_init_r (void)
-{
- return(0);
-}
-
-/******************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- ******************************************************/
-void wait_for_command_complete(unsigned int wd_base)
-{
- int pending = 1;
- do {
- pending = __raw_readl(wd_base + WWPS);
- } while (pending);
-}
-
-/****************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************/
-void watchdog_init(void)
-{
- /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
- * either taken care of by ROM (HS/EMU) or not accessible (GP).
- * We need to take care of WD2-MPU or take a PRCM reset. WD3
- * should not be running and does not generate a PRCM reset.
- */
- sr32(CM_FCLKEN_WKUP, 5, 1, 1);
- sr32(CM_ICLKEN_WKUP, 5, 1, 1);
- wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
-
- __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
- wait_for_command_complete(WD2_BASE);
- __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
-}
-
-/**********************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- **********************************************/
-int dram_init (void)
-{
- return 0;
-}
-
-/*****************************************************************
- * Routine: peripheral_enable
- * Description: Enable the clks & power for perifs (GPT2, UART1,...)
- ******************************************************************/
-void per_clocks_enable(void)
-{
- /* Enable GP2 timer. */
- sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
- sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
- sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
-
-#ifdef CFG_NS16550
- /* Enable UART1 clocks */
- sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
- sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
-#endif
- delay(1000);
-}
-
-/* Set MUX for UART, GPMC, SDRC, GPIO */
-
-#define MUX_VAL(OFFSET,VALUE)\
- __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
-
-#define CP(x) (CONTROL_PADCONF_##x)
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_DEFAULT()\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\
- MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\
- MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\
- MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
- MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
- MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
- MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
- MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
- MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
- MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
- MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
- MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
- MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
- MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
- MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
- MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
- MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
- MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/
-
-/**********************************************************
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers
- * specific to the hardware. Many pins need
- * to be moved from protect to primary mode.
- *********************************************************/
-void set_muxconf_regs(void)
-{
- MUX_DEFAULT();
-}
-
-/**********************************************************
- * Routine: nand+_init
- * Description: Set up nand for nand and jffs2 commands
- *********************************************************/
-
-int nand_init(void)
-{
- /* global settings */
- __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
- __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
- __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
-
- /* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0
- * , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0.
- * We configure only GPMC CS0 with required values. Configiring other devices
- * at other CS in done in u-boot anyway. So we don't have to bother doing it here.
- */
- __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
- delay(1000);
-
- if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)){
- __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
- __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
- __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
- __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
- __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
- __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
-
- /* Enable the GPMC Mapping */
- __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
- ((NAND_BASE_ADR>>24) & 0x3F) |
- (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
- delay(2000);
-
- if (nand_chip()){
-#ifdef CFG_PRINTF
- printf("Unsupported Chip!\n");
-#endif
- return 1;
- }
-
- }
-
- if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){
- __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
- __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
-
- /* Enable the GPMC Mapping */
- __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
- ((ONENAND_BASE>>24) & 0x3F) |
- (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
- delay(2000);
-
- if (onenand_chip()){
-#ifdef CFG_PRINTF
- printf("OneNAND Unsupported !\n");
-#endif
- return 1;
- }
- }
- return 0;
-}
-
-/* optionally do something like blinking LED */
-void board_hang (void)
-{ while (0) {};}
-
-/******************************************************************************
- * Dummy function to handle errors for EABI incompatibility
- *****************************************************************************/
-void raise(void)
-{
-}
-
-/******************************************************************************
- * Dummy function to handle errors for EABI incompatibility
- *****************************************************************************/
-void abort(void)
-{
-}
diff --git a/board/omap3evm/platform.S b/board/omap3evm/platform.S
deleted file mode 100644
index 8368487..0000000
--- a/board/omap3evm/platform.S
+++ /dev/null
@@ -1,435 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004-2006
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-
-_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
-
-#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
- /* Copy DPLL code into SRAM */
- adr r0, go_to_speed /* get addr of clock setting code */
- mov r2, #384 /* r2 size to copy (div by 32 bytes) */
- mov r1, r1 /* r1 <- dest address (passed in) */
- add r2, r2, r0 /* r2 <- source end address */
-next2:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- bne next2
- mov pc, lr /* back to caller */
-
-/* ****************************************************************************
- * NOTE: 3430 X-loader currently does not use this code.
-* It could be removed its is kept for compatabily with u-boot.
- *
- * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- * -executed from SRAM.
- * R0 = CM_CLKEN_PLL-bypass value
- * R1 = CM_CLKSEL1_PLL-m, n, and divider values
- * R2 = CM_CLKSEL_CORE-divider values
- * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- *
- * Note: If core unlocks/relocks and SDRAM is running fast already it gets
- * confused. A reset of the controller gets it back. Taking away its
- * L3 when its not in self refresh seems bad for it. Normally, this code
- * runs from flash before SDR is init so that should be ok.
- ******************************************************************************/
-.global go_to_speed
- go_to_speed:
- stmfd sp!, {r4-r6}
-
- /* move into fast relock bypass */
- ldr r4, pll_ctl_add
- str r0, [r4]
-wait1:
- ldr r5, [r3] /* get status */
- and r5, r5, #0x1 /* isolate core status */
- cmp r5, #0x1 /* still locked? */
- beq wait1 /* if lock, loop */
-
- /* set new dpll dividers _after_ in bypass */
- ldr r5, pll_div_add1
- str r1, [r5] /* set m, n, m2 */
- ldr r5, pll_div_add2
- str r2, [r5] /* set l3/l4/.. dividers*/
- ldr r5, pll_div_add3 /* wkup */
- ldr r2, pll_div_val3 /* rsm val */
- str r2, [r5]
- ldr r5, pll_div_add4 /* gfx */
- ldr r2, pll_div_val4
- str r2, [r5]
- ldr r5, pll_div_add5 /* emu */
- ldr r2, pll_div_val5
- str r2, [r5]
-
- /* now prepare GPMC (flash) for new dpll speed */
- /* flash needs to be stable when we jump back to it */
- ldr r5, flash_cfg3_addr
- ldr r2, flash_cfg3_val
- str r2, [r5]
- ldr r5, flash_cfg4_addr
- ldr r2, flash_cfg4_val
- str r2, [r5]
- ldr r5, flash_cfg5_addr
- ldr r2, flash_cfg5_val
- str r2, [r5]
- ldr r5, flash_cfg1_addr
- ldr r2, [r5]
- orr r2, r2, #0x3 /* up gpmc divider */
- str r2, [r5]
-
- /* lock DPLL3 and wait a bit */
- orr r0, r0, #0x7 /* set up for lock mode */
- str r0, [r4] /* lock */
- nop /* ARM slow at this point working at sys_clk */
- nop
- nop
- nop
-wait2:
- ldr r5, [r3] /* get status */
- and r5, r5, #0x1 /* isolate core status */
- cmp r5, #0x1 /* still locked? */
- bne wait2 /* if lock, loop */
- nop
- nop
- nop
- nop
- ldmfd sp!, {r4-r6}
- mov pc, lr /* back to caller, locked */
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-/* The Nor has to be in the Flash Base CS0 for this condition to happen */
-flash_cfg1_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
-flash_cfg3_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
-flash_cfg3_val:
- .word STNOR_GPMC_CONFIG3
-flash_cfg4_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
-flash_cfg4_val:
- .word STNOR_GPMC_CONFIG4
-flash_cfg5_val:
- .word STNOR_GPMC_CONFIG5
-flash_cfg5_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
-pll_ctl_add:
- .word CM_CLKEN_PLL
-pll_div_add1:
- .word CM_CLKSEL1_PLL
-pll_div_add2:
- .word CM_CLKSEL_CORE
-pll_div_add3:
- .word CM_CLKSEL_WKUP
-pll_div_val3:
- .word (WKUP_RSM << 1)
-pll_div_add4:
- .word CM_CLKSEL_GFX
-pll_div_val4:
- .word (GFX_DIV << 0)
-pll_div_add5:
- .word CM_CLKSEL1_EMU
-pll_div_val5:
- .word CLSEL1_EMU_VAL
-
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
- mov ip, lr /* save link reg across call */
- bl s_init /* go setup pll,mux,memory */
- ldr ip, [sp] /* restore save ip */
- mov lr, ip /* restore link reg */
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-REG_CONTROL_STATUS:
- .word CONTROL_STATUS
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
-
-
-/* DPLL(1-4) PARAM TABLES */
-/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
- * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
- * The values are defined for all possible sysclk and for ES1 and ES2.
- */
-
-mpu_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word 0x0FE
-.word 0x07
-.word 0x05
-.word 0x01
-/* ES2 */
-.word 0x0FA
-.word 0x05
-.word 0x07
-.word 0x01
-
-/* 13MHz */
-/* ES1 */
-.word 0x17D
-.word 0x0C
-.word 0x03
-.word 0x01
-/* ES2 */
-.word 0x1F4
-.word 0x0C
-.word 0x03
-.word 0x01
-
-/* 19.2MHz */
-/* ES1 */
-.word 0x179
-.word 0x12
-.word 0x04
-.word 0x01
-/* ES2 */
-.word 0x271
-.word 0x17
-.word 0x03
-.word 0x01
-
-/* 26MHz */
-/* ES1 */
-.word 0x17D
-.word 0x19
-.word 0x03
-.word 0x01
-/* ES2 */
-.word 0x0FA
-.word 0x0C
-.word 0x07
-.word 0x01
-
-/* 38.4MHz */
-/* ES1 */
-.word 0x1FA
-.word 0x32
-.word 0x03
-.word 0x01
-/* ES2 */
-.word 0x271
-.word 0x2F
-.word 0x03
-.word 0x01
-
-
-.globl get_mpu_dpll_param
-get_mpu_dpll_param:
- adr r0, mpu_dpll_param
- mov pc, lr
-
-iva_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word 0x07D
-.word 0x05
-.word 0x07
-.word 0x01
-/* ES2 */
-.word 0x0B4
-.word 0x05
-.word 0x07
-.word 0x01
-
-/* 13MHz */
-/* ES1 */
-.word 0x0FA
-.word 0x0C
-.word 0x03
-.word 0x01
-/* ES2 */
-.word 0x168
-.word 0x0C
-.word 0x03
-.word 0x01
-
-/* 19.2MHz */
-/* ES1 */
-.word 0x082
-.word 0x09
-.word 0x07
-.word 0x01
-/* ES2 */
-.word 0x0E1
-.word 0x0B
-.word 0x06
-.word 0x01
-
-/* 26MHz */
-/* ES1 */
-.word 0x07D
-.word 0x0C
-.word 0x07
-.word 0x01
-/* ES2 */
-.word 0x0B4
-.word 0x0C
-.word 0x07
-.word 0x01
-
-/* 38.4MHz */
-/* ES1 */
-.word 0x13F
-.word 0x30
-.word 0x03
-.word 0x01
-/* ES2 */
-.word 0x0E1
-.word 0x17
-.word 0x06
-.word 0x01
-
-
-.globl get_iva_dpll_param
-get_iva_dpll_param:
- adr r0, iva_dpll_param
- mov pc, lr
-
-core_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word 0x19F
-.word 0x0E
-.word 0x03
-.word 0x01
-/* ES2 */
-.word 0x0A6
-.word 0x05
-.word 0x07
-.word 0x01
-
-/* 13MHz */
-/* ES1 */
-.word 0x1B2
-.word 0x10
-.word 0x03
-.word 0x01
-/* ES2 */
-.word 0x14C
-.word 0x0C
-.word 0x03
-.word 0x01
-
-/* 19.2MHz */
-/* ES1 */
-.word 0x19F
-.word 0x17
-.word 0x03
-.word 0x01
-/* ES2 */
-.word 0x19F
-.word 0x17
-.word 0x03
-.word 0x01
-
-/* 26MHz */
-/* ES1 */
-.word 0x1B2
-.word 0x21
-.word 0x03
-.word 0x01
-/* ES2 */
-.word 0x0A6
-.word 0x0C
-.word 0x07
-.word 0x01
-
-/* 38.4MHz */
-/* ES1 */
-.word 0x19F
-.word 0x2F
-.word 0x03
-.word 0x01
-/* ES2 */
-.word 0x19F
-.word 0x2F
-.word 0x03
-.word 0x01
-
-.globl get_core_dpll_param
-get_core_dpll_param:
- adr r0, core_dpll_param
- mov pc, lr
-
-/* PER DPLL values are same for both ES1 and ES2 */
-per_dpll_param:
-/* 12MHz */
-.word 0xD8
-.word 0x05
-.word 0x07
-.word 0x09
-
-/* 13MHz */
-.word 0x1B0
-.word 0x0C
-.word 0x03
-.word 0x09
-
-/* 19.2MHz */
-.word 0xE1
-.word 0x09
-.word 0x07
-.word 0x09
-
-/* 26MHz */
-.word 0xD8
-.word 0x0C
-.word 0x07
-.word 0x09
-
-/* 38.4MHz */
-.word 0xE1
-.word 0x13
-.word 0x07
-.word 0x09
-
-.globl get_per_dpll_param
-get_per_dpll_param:
- adr r0, per_dpll_param
- mov pc, lr
-
diff --git a/board/omap3evm/x-load.lds b/board/omap3evm/x-load.lds
deleted file mode 100644
index 5f352d3..0000000
--- a/board/omap3evm/x-load.lds
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * November 2006 - Changed to support 3430sdp device
- * Copyright (c) 2004-2006 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- cpu/omap3/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
diff --git a/board/overo/Makefile b/board/overo/Makefile
deleted file mode 100644
index 32f9bf1..0000000
--- a/board/overo/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).a
-
-COBJS := overo.o
-SOBJS := platform.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS) $(SOBJS)
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/overo/config.mk b/board/overo/config.mk
deleted file mode 100644
index 7ee3014..0000000
--- a/board/overo/config.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# (C) Copyright 2006
-# Texas Instruments, <www.ti.com>
-#
-# Overo board uses TI OMAP35xx (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Overo has 1 bank of 128MB mPOP-SDRAM on CS0
-# Physical Address:
-# 8000'0000 (bank0)
-
-# For use if you want X-Loader to relocate from SRAM to DDR
-#TEXT_BASE = 0x80e80000
-
-# For XIP in 64K of SRAM or debug (GP device has it all availabe)
-# SRAM 40200000-4020FFFF base
-# initial stack at 0x4020fffc used in s_init (below xloader).
-# The run time stack is (above xloader, 2k below)
-# If any globals exist there needs to be room for them also
-TEXT_BASE = 0x40200800
diff --git a/board/overo/overo.c b/board/overo/overo.c
deleted file mode 100644
index 8df53e5..0000000
--- a/board/overo/overo.c
+++ /dev/null
@@ -1,1148 +0,0 @@
-/*
- * (C) Copyright 2006
- * Texas Instruments, <www.ti.com>
- * Jian Zhang <jzhang@ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * Modified for overo
- * Steve Sakoman <steve@sakoman.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <part.h>
-#include <fat.h>
-#include <i2c.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/sys_info.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/mem.h>
-
-/* params for 37XX */
-#define CORE_DPLL_PARAM_M2 0x09
-#define CORE_DPLL_PARAM_M 0x360
-#define CORE_DPLL_PARAM_N 0xC
-
-/* Used to index into DPLL parameter tables */
-struct dpll_param {
- unsigned int m;
- unsigned int n;
- unsigned int fsel;
- unsigned int m2;
-};
-
-typedef struct dpll_param dpll_param;
-
-/* Following functions are exported from lowlevel_init.S */
-extern dpll_param *get_mpu_dpll_param();
-extern dpll_param *get_iva_dpll_param();
-extern dpll_param *get_core_dpll_param();
-extern dpll_param *get_per_dpll_param();
-
-#define __raw_readl(a) (*(volatile unsigned int *)(a))
-#define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v))
-#define __raw_readw(a) (*(volatile unsigned short *)(a))
-#define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v))
-
-static char *rev_s[CPU_3XX_MAX_REV] = {
- "1.0",
- "2.0",
- "2.1",
- "3.0",
- "3.1",
- "UNKNOWN",
- "UNKNOWN",
- "3.1.2"};
-
-/*******************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- ******************************************************/
-static inline void delay(unsigned long loops)
-{
- __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0"(loops));
-}
-
-void udelay (unsigned long usecs) {
- delay(usecs);
-}
-
-/*****************************************
- * Routine: board_init
- * Description: Early hardware init.
- *****************************************/
-int board_init(void)
-{
- return 0;
-}
-
-/*************************************************************
- * get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
- int mode;
- mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
- return mode >>= 8;
-}
-
-/************************************************
- * get_sysboot_value(void) - return SYS_BOOT[4:0]
- ************************************************/
-u32 get_sysboot_value(void)
-{
- int mode;
- mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
- return mode;
-}
-
-/*************************************************************
- * Routine: get_mem_type(void) - returns the kind of memory connected
- * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
- *************************************************************/
-u32 get_mem_type(void)
-{
- u32 mem_type = get_sysboot_value();
-
- switch (mem_type) {
- case 0:
- case 2:
- case 4:
- case 16:
- case 22:
- return GPMC_ONENAND;
-
- case 1:
- case 12:
- case 15:
- case 21:
- case 27:
- return GPMC_NAND;
-
- case 3:
- case 6:
- return MMC_ONENAND;
-
- case 8:
- case 11:
- case 14:
- case 20:
- case 26:
- return GPMC_MDOC;
-
- case 17:
- case 18:
- case 24:
- return MMC_NAND;
-
- case 7:
- case 10:
- case 13:
- case 19:
- case 25:
- default:
- return GPMC_NOR;
- }
-}
-
-/******************************************
- * get_cpu_type(void) - extract cpu info
- ******************************************/
-u32 get_cpu_type(void)
-{
- return __raw_readl(CONTROL_OMAP_STATUS);
-}
-
-/******************************************
- * get_cpu_id(void) - extract cpu id
- * returns 0 for ES1.0, cpuid otherwise
- ******************************************/
-u32 get_cpu_id(void)
-{
- u32 cpuid = 0;
-
- /*
- * On ES1.0 the IDCODE register is not exposed on L4
- * so using CPU ID to differentiate between ES1.0 and > ES1.0.
- */
- __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
- if ((cpuid & 0xf) == 0x0) {
- return 0;
- } else {
- /* Decode the IDs on > ES1.0 */
- cpuid = __raw_readl(CONTROL_IDCODE);
- }
-
- return cpuid;
-}
-
-/******************************************
- * get_cpu_family(void) - extract cpu info
- ******************************************/
-u32 get_cpu_family(void)
-{
- u16 hawkeye;
- u32 cpu_family;
- u32 cpuid = get_cpu_id();
-
- if (cpuid == 0)
- return CPU_OMAP34XX;
-
- hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
- switch (hawkeye) {
- case HAWKEYE_OMAP34XX:
- cpu_family = CPU_OMAP34XX;
- break;
- case HAWKEYE_AM35XX:
- cpu_family = CPU_AM35XX;
- break;
- case HAWKEYE_OMAP36XX:
- cpu_family = CPU_OMAP36XX;
- break;
- default:
- cpu_family = CPU_OMAP34XX;
- }
-
- return cpu_family;
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
- u32 cpuid = get_cpu_id();
-
- if (cpuid == 0)
- return CPU_3XX_ES10;
- else
- return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
-}
-
-/******************************************
- * Print CPU information
- ******************************************/
-int print_cpuinfo (void)
-{
- char *cpu_family_s, *cpu_s, *sec_s;
-
- switch (get_cpu_family()) {
- case CPU_OMAP34XX:
- cpu_family_s = "OMAP";
- switch (get_cpu_type()) {
- case OMAP3503:
- cpu_s = "3503";
- break;
- case OMAP3515:
- cpu_s = "3515";
- break;
- case OMAP3525:
- cpu_s = "3525";
- break;
- case OMAP3530:
- cpu_s = "3530";
- break;
- default:
- cpu_s = "35XX";
- break;
- }
- break;
- case CPU_AM35XX:
- cpu_family_s = "AM";
- switch (get_cpu_type()) {
- case AM3505:
- cpu_s = "3505";
- break;
- case AM3517:
- cpu_s = "3517";
- break;
- default:
- cpu_s = "35XX";
- break;
- }
- break;
- case CPU_OMAP36XX:
- cpu_family_s = "OMAP";
- switch (get_cpu_type()) {
- case OMAP3730:
- cpu_s = "3630/3730";
- break;
- default:
- cpu_s = "36XX/37XX";
- break;
- }
- break;
- default:
- cpu_family_s = "OMAP";
- cpu_s = "35XX";
- }
-
- switch (get_device_type()) {
- case TST_DEVICE:
- sec_s = "TST";
- break;
- case EMU_DEVICE:
- sec_s = "EMU";
- break;
- case HS_DEVICE:
- sec_s = "HS";
- break;
- case GP_DEVICE:
- sec_s = "GP";
- break;
- default:
- sec_s = "?";
- }
-
- printf("%s%s-%s ES%s\n",
- cpu_family_s, cpu_s, sec_s, rev_s[get_cpu_rev()]);
-
- return 0;
-}
-
-/******************************************
- * cpu_is_3410(void) - returns true for 3410
- ******************************************/
-u32 cpu_is_3410(void)
-{
- int status;
- if (get_cpu_rev() < CPU_3430_ES2) {
- return 0;
- } else {
- /* read scalability status and return 1 for 3410*/
- status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
- /* Check whether MPU frequency is set to 266 MHz which
- * is nominal for 3410. If yes return true else false
- */
- if (((status >> 8) & 0x3) == 0x2)
- return 1;
- else
- return 0;
- }
-}
-
-/*****************************************************************
- * Routine: get_board_revision
- * Description: Returns the board revision
- *****************************************************************/
-int get_board_revision(void)
-{
- int revision;
- unsigned char data;
-
- /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
- /* these boards should return a revision number of 0 */
- /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
- data = 0x01;
- i2c_write(0x4B, 0x29, 1, &data, 1);
- data = 0x0c;
- i2c_write(0x4B, 0x2b, 1, &data, 1);
- i2c_read(0x4B, 0x2a, 1, &data, 1);
-
- if (!omap_request_gpio(112) &&
- !omap_request_gpio(113) &&
- !omap_request_gpio(115)) {
-
- omap_set_gpio_direction(112, 1);
- omap_set_gpio_direction(113, 1);
- omap_set_gpio_direction(115, 1);
-
- revision = omap_get_gpio_datain(115) << 2 |
- omap_get_gpio_datain(113) << 1 |
- omap_get_gpio_datain(112);
-
- omap_free_gpio(112);
- omap_free_gpio(113);
- omap_free_gpio(115);
- } else {
- printf("Error: unable to acquire board revision GPIOs\n");
- revision = -1;
- }
-
- return revision;
-}
-
-/*****************************************************************
- * sr32 - clear & set a value in a bit range for a 32 bit address
- *****************************************************************/
-void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
-{
- u32 tmp, msk = 0;
- msk = 1 << num_bits;
- --msk;
- tmp = __raw_readl(addr) & ~(msk << start_bit);
- tmp |= value << start_bit;
- __raw_writel(tmp, addr);
-}
-
-/*********************************************************************
- * wait_on_value() - common routine to allow waiting for changes in
- * volatile regs.
- *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
-{
- u32 i = 0, val;
- do {
- ++i;
- val = __raw_readl(read_addr) & read_bit_mask;
- if (val == match_value)
- return 1;
- if (i == bound)
- return 0;
- } while (1);
-}
-
-#ifdef CFG_3430SDRAM_DDR
-/*********************************************************************
- * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
- *********************************************************************/
-void config_3430sdram_ddr(void)
-{
- /* reset sdrc controller */
- __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
- wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
- __raw_writel(0, SDRC_SYSCONFIG);
-
- /* setup sdrc to ball mux */
- __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
-
- switch (get_board_revision()) {
- case 0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
- __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
- __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
- __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
- __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
- __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
- __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
- __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
- __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
- break;
- case 1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
- __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
- __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
- __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
- __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
- __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
- __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
- __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
- __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
- __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
- break;
- case 2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
- __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
- __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_0);
- __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_1);
- __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
- __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
- __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
- __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
- __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
- __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
- break;
- default:
- __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
- __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
- __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
- __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
- __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
- __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
- __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
- __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
- __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
- }
-
- __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
-
- /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
- __raw_writel(CMD_NOP, SDRC_MANUAL_0);
- __raw_writel(CMD_NOP, SDRC_MANUAL_1);
-
- delay(5000);
-
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
- __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
-
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
-
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
- __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
-
- /* set mr0 */
- __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
- __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1);
-
- /* set up dll */
- __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
- delay(0x2000); /* give time to lock */
-}
-#endif /* CFG_3430SDRAM_DDR */
-
-/*************************************************************
- * get_sys_clk_speed - determine reference oscillator speed
- * based on known 32kHz clock and gptimer.
- *************************************************************/
-u32 get_osc_clk_speed(void)
-{
- u32 start, cstart, cend, cdiff, cdiv, val;
-
- val = __raw_readl(PRM_CLKSRC_CTRL);
-
- if (val & SYSCLKDIV_2)
- cdiv = 2;
- else
- cdiv = 1;
-
- /* enable timer2 */
- val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
- __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
-
- /* Enable I and F Clocks for GPT1 */
- val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
- __raw_writel(val, CM_ICLKEN_WKUP);
- val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
- __raw_writel(val, CM_FCLKEN_WKUP);
-
- __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
- __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
- /* enable 32kHz source */
- /* enabled out of reset */
- /* determine sys_clk via gauging */
-
- start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
- while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
- cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
- while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
- cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
- cdiff = cend - cstart; /* get elapsed ticks */
- cdiff *= cdiv;
-
- /* based on number of ticks assign speed */
- if (cdiff > 19000)
- return S38_4M;
- else if (cdiff > 15200)
- return S26M;
- else if (cdiff > 13000)
- return S24M;
- else if (cdiff > 9000)
- return S19_2M;
- else if (cdiff > 7600)
- return S13M;
- else
- return S12M;
-}
-
-/******************************************************************************
- * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
- * -- input oscillator clock frequency.
- *
- *****************************************************************************/
-void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
-{
- if (osc_clk == S38_4M)
- *sys_clkin_sel = 4;
- else if (osc_clk == S26M)
- *sys_clkin_sel = 3;
- else if (osc_clk == S19_2M)
- *sys_clkin_sel = 2;
- else if (osc_clk == S13M)
- *sys_clkin_sel = 1;
- else if (osc_clk == S12M)
- *sys_clkin_sel = 0;
-}
-
-/******************************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h
- * -- called from SRAM, or Flash (using temp SRAM stack).
- *****************************************************************************/
-void prcm_init(void)
-{
- u32 osc_clk = 0, sys_clkin_sel;
- dpll_param *dpll_param_p;
- u32 clk_index, sil_index;
-
- /* Gauge the input clock speed and find out the sys_clkin_sel
- * value corresponding to the input clock.
- */
- osc_clk = get_osc_clk_speed();
- get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
-
- sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
-
- /* If the input clock is greater than 19.2M always divide/2 */
- if (sys_clkin_sel > 2) {
- sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */
- clk_index = sys_clkin_sel / 2;
- } else {
- sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */
- clk_index = sys_clkin_sel;
- }
-
- sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
-
- /* The DPLL tables are defined according to sysclk value and
- * silicon revision. The clk_index value will be used to get
- * the values for that input sysclk from the DPLL param table
- * and sil_index will get the values for that SysClk for the
- * appropriate silicon rev.
- */
- sil_index = get_cpu_rev() - 1;
-
- /* Unlock MPU DPLL (slows things down, and needed later) */
- sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
- wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
-
- /* Getting the base address of Core DPLL param table */
- dpll_param_p = (dpll_param *) get_core_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
- /* CORE DPLL */
- /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
- sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
- wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
-
- /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
- work. write another value and then default value. */
- sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
- sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
- sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
- sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
- sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
- sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
- sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
- sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
- sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
- sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
- sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
- sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
- sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
-
- /* Getting the base address to PER DPLL param table */
- dpll_param_p = (dpll_param *) get_per_dpll_param();
- /* Moving it to the right sysclk base */
- dpll_param_p = dpll_param_p + clk_index;
- /* PER DPLL */
- sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
- wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
- sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
- sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
- sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
- sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
-
- if (get_cpu_family() == CPU_OMAP36XX) {
- sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */
- sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */
- sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */
- } else {
- sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
- sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
- sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
- }
-
- sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
-
- /* Getting the base address to MPU DPLL param table */
- dpll_param_p = (dpll_param *) get_mpu_dpll_param();
-
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
-
- /* MPU DPLL (unlocked already) */
- sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
- sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
- sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
- sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
-
- /* Getting the base address to IVA DPLL param table */
- dpll_param_p = (dpll_param *) get_iva_dpll_param();
- /* Moving it to the right sysclk and ES rev base */
- dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
- /* IVA DPLL (set to 12*20=240MHz) */
- sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
- wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
- sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
- sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
- sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
- sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
- sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
-
- /* Set up GPTimers to sys_clk source only */
- sr32(CM_CLKSEL_PER, 0, 8, 0xff);
- sr32(CM_CLKSEL_WKUP, 0, 1, 1);
-
- delay(5000);
-}
-
-/*****************************************
- * Routine: secure_unlock
- * Description: Setup security registers for access
- * (GP Device only)
- *****************************************/
-void secure_unlock(void)
-{
- /* Permission values for registers -Full fledged permissions to all */
- #define UNLOCK_1 0xFFFFFFFF
- #define UNLOCK_2 0x00000000
- #define UNLOCK_3 0x0000FFFF
- /* Protection Module Register Target APE (PM_RT)*/
- __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
- __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
- __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
- __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
-
- __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
- __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
- __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
-
- __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
- __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
- __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
- __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
-
- /* IVA Changes */
- __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
- __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
- __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
-
- __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
-}
-
-/**********************************************************
- * Routine: try_unlock_sram()
- * Description: If chip is GP type, unlock the SRAM for
- * general use.
- ***********************************************************/
-void try_unlock_memory(void)
-{
- int mode;
-
- /* if GP device unlock device SRAM for general use */
- /* secure code breaks for Secure/Emulation device - HS/E/T*/
- mode = get_device_type();
- if (mode == GP_DEVICE)
- secure_unlock();
- return;
-}
-
-/**********************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called at time when only stack is available.
- **********************************************************/
-
-void s_init(void)
-{
- watchdog_init();
-#ifdef CONFIG_3430_AS_3410
- /* setup the scalability control register for
- * 3430 to work in 3410 mode
- */
- __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP);
-#endif
- try_unlock_memory();
- set_muxconf_regs();
- delay(100);
- prcm_init();
- per_clocks_enable();
- config_3430sdram_ddr();
-}
-
-/*******************************************************
- * Routine: misc_init_r
- ********************************************************/
-int misc_init_r(void)
-{
- print_cpuinfo();
- printf("Board revision: %d\n", get_board_revision());
- return 0;
-}
-
-/******************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- ******************************************************/
-void wait_for_command_complete(unsigned int wd_base)
-{
- int pending = 1;
- do {
- pending = __raw_readl(wd_base + WWPS);
- } while (pending);
-}
-
-/****************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************/
-void watchdog_init(void)
-{
- /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
- * either taken care of by ROM (HS/EMU) or not accessible (GP).
- * We need to take care of WD2-MPU or take a PRCM reset. WD3
- * should not be running and does not generate a PRCM reset.
- */
- sr32(CM_FCLKEN_WKUP, 5, 1, 1);
- sr32(CM_ICLKEN_WKUP, 5, 1, 1);
- wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
-
- __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
- wait_for_command_complete(WD2_BASE);
- __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
-}
-
-/**********************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- **********************************************/
-int dram_init(void)
-{
- return 0;
-}
-
-/*****************************************************************
- * Routine: peripheral_enable
- * Description: Enable the clks & power for perifs (GPT2, UART1,...)
- ******************************************************************/
-void per_clocks_enable(void)
-{
- /* Enable GP2 timer. */
- sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
- sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
- sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
-
-#ifdef CFG_NS16550
- /* UART1 clocks */
- sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
- sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
-
- /* UART 3 Clocks */
- sr32(CM_FCLKEN_PER, 11, 1, 0x1);
- sr32(CM_ICLKEN_PER, 11, 1, 0x1);
-
-#endif
-
- /* Enable GPIO 4, 5, & 6 clocks */
- sr32(CM_FCLKEN_PER, 17, 3, 0x7);
- sr32(CM_ICLKEN_PER, 17, 3, 0x7);
-
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
- /* Turn on all 3 I2C clocks */
- sr32(CM_FCLKEN1_CORE, 15, 3, 0x7);
- sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */
-#endif
-
- /* Enable the ICLK for 32K Sync Timer as its used in udelay */
- sr32(CM_ICLKEN_WKUP, 2, 1, 0x1);
-
- sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON);
- sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON);
- sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON);
- sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON);
- sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON);
- sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON);
- sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);
- sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);
- sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON);
- sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON);
- sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON);
- sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON);
-
- delay(1000);
-}
-
-/* Set MUX for UART, GPMC, SDRC, GPIO */
-
-#define MUX_VAL(OFFSET,VALUE)\
- __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
-
-#define CP(x) (CONTROL_PADCONF_##x)
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_DEFAULT()\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\
- MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\
- MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\
- MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
- MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
- MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
- MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
- /* - PEN_DOWN*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M4)) /*GPIO_127*/\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M4)) /*GPIO_128*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M4)) /*GPIO_129*/\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
- MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
- MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
- MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
- MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
- MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
- MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
- MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
- MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
- MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
- MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
- MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
- MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/
-
-/**********************************************************
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers
- * specific to the hardware. Many pins need
- * to be moved from protect to primary mode.
- *********************************************************/
-void set_muxconf_regs(void)
-{
- MUX_DEFAULT();
-}
-
-/**********************************************************
- * Routine: nand+_init
- * Description: Set up nand for nand and jffs2 commands
- *********************************************************/
-
-int nand_init(void)
-{
- /* global settings */
- __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
- __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
- __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
-
- /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
- * We configure only GPMC CS0 with required values. Configiring other devices
- * at other CS is done in u-boot. So we don't have to bother doing it here.
- */
- __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
- delay(1000);
-
-#ifdef CFG_NAND_K9F1G08R0A
- if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
- __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
- __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
- __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
- __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
- __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
- __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
-
- /* Enable the GPMC Mapping */
- __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
- ((NAND_BASE_ADR>>24) & 0x3F) |
- (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
- delay(2000);
-
- if (nand_chip()) {
-#ifdef CFG_PRINTF
- printf("Unsupported Chip!\n");
-#endif
- return 1;
- }
- }
-#endif
-
-#ifdef CFG_ONENAND
- if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
- __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
- __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
- __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
- __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
- __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
- __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
-
- /* Enable the GPMC Mapping */
- __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
- ((ONENAND_BASE>>24) & 0x3F) |
- (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
- delay(2000);
-
- if (onenand_chip()) {
-#ifdef CFG_PRINTF
- printf("OneNAND Unsupported !\n");
-#endif
- return 1;
- }
- }
-#endif
-
- return 0;
-}
-
-/* optionally do something like blinking LED */
-void board_hang(void)
-{
- while (0)
- ;
-}
-
-/******************************************************************************
- * Dummy function to handle errors for EABI incompatibility
- *****************************************************************************/
-void raise(void)
-{
-}
-
-/******************************************************************************
- * Dummy function to handle errors for EABI incompatibility
- *****************************************************************************/
-void abort(void)
-{
-}
diff --git a/board/overo/platform.S b/board/overo/platform.S
deleted file mode 100644
index 5869270..0000000
--- a/board/overo/platform.S
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004-2006
- * Texas Instruments, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks.h>
-
-_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
-
-#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
- /* Copy DPLL code into SRAM */
- adr r0, go_to_speed /* get addr of clock setting code */
- mov r2, #384 /* r2 size to copy (div by 32 bytes) */
- mov r1, r1 /* r1 <- dest address (passed in) */
- add r2, r2, r0 /* r2 <- source end address */
-next2:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- bne next2
- mov pc, lr /* back to caller */
-
-/* ****************************************************************************
- * NOTE: 3430 X-loader currently does not use this code.
-* It could be removed its is kept for compatabily with u-boot.
- *
- * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- * -executed from SRAM.
- * R0 = CM_CLKEN_PLL-bypass value
- * R1 = CM_CLKSEL1_PLL-m, n, and divider values
- * R2 = CM_CLKSEL_CORE-divider values
- * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- *
- * Note: If core unlocks/relocks and SDRAM is running fast already it gets
- * confused. A reset of the controller gets it back. Taking away its
- * L3 when its not in self refresh seems bad for it. Normally, this code
- * runs from flash before SDR is init so that should be ok.
- ******************************************************************************/
-.global go_to_speed
- go_to_speed:
- stmfd sp!, {r4-r6}
-
- /* move into fast relock bypass */
- ldr r4, pll_ctl_add
- str r0, [r4]
-wait1:
- ldr r5, [r3] /* get status */
- and r5, r5, #0x1 /* isolate core status */
- cmp r5, #0x1 /* still locked? */
- beq wait1 /* if lock, loop */
-
- /* set new dpll dividers _after_ in bypass */
- ldr r5, pll_div_add1
- str r1, [r5] /* set m, n, m2 */
- ldr r5, pll_div_add2
- str r2, [r5] /* set l3/l4/.. dividers*/
- ldr r5, pll_div_add3 /* wkup */
- ldr r2, pll_div_val3 /* rsm val */
- str r2, [r5]
- ldr r5, pll_div_add4 /* gfx */
- ldr r2, pll_div_val4
- str r2, [r5]
- ldr r5, pll_div_add5 /* emu */
- ldr r2, pll_div_val5
- str r2, [r5]
-
- /* now prepare GPMC (flash) for new dpll speed */
- /* flash needs to be stable when we jump back to it */
- ldr r5, flash_cfg3_addr
- ldr r2, flash_cfg3_val
- str r2, [r5]
- ldr r5, flash_cfg4_addr
- ldr r2, flash_cfg4_val
- str r2, [r5]
- ldr r5, flash_cfg5_addr
- ldr r2, flash_cfg5_val
- str r2, [r5]
- ldr r5, flash_cfg1_addr
- ldr r2, [r5]
- orr r2, r2, #0x3 /* up gpmc divider */
- str r2, [r5]
-
- /* lock DPLL3 and wait a bit */
- orr r0, r0, #0x7 /* set up for lock mode */
- str r0, [r4] /* lock */
- nop /* ARM slow at this point working at sys_clk */
- nop
- nop
- nop
-wait2:
- ldr r5, [r3] /* get status */
- and r5, r5, #0x1 /* isolate core status */
- cmp r5, #0x1 /* still locked? */
- bne wait2 /* if lock, loop */
- nop
- nop
- nop
- nop
- ldmfd sp!, {r4-r6}
- mov pc, lr /* back to caller, locked */
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-/* The Nor has to be in the Flash Base CS0 for this condition to happen */
-flash_cfg1_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
-flash_cfg3_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
-flash_cfg3_val:
- .word STNOR_GPMC_CONFIG3
-flash_cfg4_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
-flash_cfg4_val:
- .word STNOR_GPMC_CONFIG4
-flash_cfg5_val:
- .word STNOR_GPMC_CONFIG5
-flash_cfg5_addr:
- .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
-pll_ctl_add:
- .word CM_CLKEN_PLL
-pll_div_add1:
- .word CM_CLKSEL1_PLL
-pll_div_add2:
- .word CM_CLKSEL_CORE
-pll_div_add3:
- .word CM_CLKSEL_WKUP
-pll_div_val3:
- .word (WKUP_RSM << 1)
-pll_div_add4:
- .word CM_CLKSEL_GFX
-pll_div_val4:
- .word (GFX_DIV << 0)
-pll_div_add5:
- .word CM_CLKSEL1_EMU
-pll_div_val5:
- .word CLSEL1_EMU_VAL
-
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash old link register */
- mov ip, lr /* save link reg across call */
- bl s_init /* go setup pll,mux,memory */
- ldr ip, [sp] /* restore save ip */
- mov lr, ip /* restore link reg */
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-REG_CONTROL_STATUS:
- .word CONTROL_STATUS
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
-
-/* DPLL(1-4) PARAM TABLES */
-/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
- * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
- * The values are defined for all possible sysclk and for ES1 and ES2.
- */
-
-mpu_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word 0x0FE,0x07,0x05,0x01
-/* ES2 */
-.word 0x0FA,0x05,0x07,0x01
-/* 3410 */
-.word 0x085,0x05,0x07,0x01
-
-/* 13MHz */
-/* ES1 */
-.word 0x17D,0x0C,0x03,0x01
-/* ES2 */
-.word 0x1F4,0x0C,0x03,0x01
-/* 3410 */
-.word 0x10A,0x0C,0x03,0x01
-
-/* 19.2MHz */
-/* ES1 */
-.word 0x179,0x12,0x04,0x01
-/* ES2 */
-.word 0x271,0x17,0x03,0x01
-/* 3410 */
-.word 0x14C,0x17,0x03,0x01
-
-/* 26MHz */
-/* ES1 */
-.word 0x17D,0x19,0x03,0x01
-/* ES2 */
-.word 0x0FA,0x0C,0x07,0x01
-/* 3410 */
-.word 0x085,0x0C,0x07,0x01
-
-/* 38.4MHz */
-/* ES1 */
-.word 0x1FA,0x32,0x03,0x01
-/* ES2 */
-.word 0x271,0x2F,0x03,0x01
-/* 3410 */
-.word 0x14C,0x2F,0x03,0x01
-
-
-.globl get_mpu_dpll_param
-get_mpu_dpll_param:
- adr r0, mpu_dpll_param
- mov pc, lr
-
-iva_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word 0x07D,0x05,0x07,0x01
-/* ES2 */
-.word 0x0B4,0x05,0x07,0x01
-/* 3410 */
-.word 0x085,0x05,0x07,0x01
-
-/* 13MHz */
-/* ES1 */
-.word 0x0FA,0x0C,0x03,0x01
-/* ES2 */
-.word 0x168,0x0C,0x03,0x01
-/* 3410 */
-.word 0x10A,0x0C,0x03,0x01
-
-/* 19.2MHz */
-/* ES1 */
-.word 0x082,0x09,0x07,0x01
-/* ES2 */
-.word 0x0E1,0x0B,0x06,0x01
-/* 3410 */
-.word 0x14C,0x17,0x03,0x01
-
-/* 26MHz */
-/* ES1 */
-.word 0x07D,0x0C,0x07,0x01
-/* ES2 */
-.word 0x0B4,0x0C,0x07,0x01
-/* 3410 */
-.word 0x085,0x0C,0x07,0x01
-
-/* 38.4MHz */
-/* ES1 */
-.word 0x13F,0x30,0x03,0x01
-/* ES2 */
-.word 0x0E1,0x17,0x06,0x01
-/* 3410 */
-.word 0x14C,0x2F,0x03,0x01
-
-
-.globl get_iva_dpll_param
-get_iva_dpll_param:
- adr r0, iva_dpll_param
- mov pc, lr
-
-/* Core DPLL targets for L3 at 166 & L133 */
-core_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1
-/* ES2 */
-.word M_12,N_12,FSEL_12,M2_12
-/* 3410 */
-.word M_12,N_12,FSEL_12,M2_12
-
-/* 13MHz */
-/* ES1 */
-.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1
-/* ES2 */
-.word M_13,N_13,FSEL_13,M2_13
-/* 3410 */
-.word M_13,N_13,FSEL_13,M2_13
-
-/* 19.2MHz */
-/* ES1 */
-.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1
-/* ES2 */
-.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
-/* 3410 */
-.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
-
-/* 26MHz */
-/* ES1 */
-.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1
-/* ES2 */
-.word M_26,N_26,FSEL_26,M2_26
-/* 3410 */
-.word M_26,N_26,FSEL_26,M2_26
-
-/* 38.4MHz */
-/* ES1 */
-.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1
-/* ES2 */
-.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
-/* 3410 */
-.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
-
-.globl get_core_dpll_param
-get_core_dpll_param:
- adr r0, core_dpll_param
- mov pc, lr
-
-/* PER DPLL values are same for both ES1 and ES2 */
-per_dpll_param:
-/* 12MHz */
-.word 0xD8,0x05,0x07,0x09
-
-/* 13MHz */
-.word 0x1B0,0x0C,0x03,0x09
-
-/* 19.2MHz */
-.word 0xE1,0x09,0x07,0x09
-
-/* 26MHz */
-.word 0xD8,0x0C,0x07,0x09
-
-/* 38.4MHz */
-.word 0xE1,0x13,0x07,0x09
-
-.globl get_per_dpll_param
-get_per_dpll_param:
- adr r0, per_dpll_param
- mov pc, lr
-
diff --git a/board/overo/x-load.lds b/board/overo/x-load.lds
deleted file mode 100644
index 5f352d3..0000000
--- a/board/overo/x-load.lds
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * November 2006 - Changed to support 3430sdp device
- * Copyright (c) 2004-2006 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- cpu/omap3/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
diff --git a/common/cmd_monitor.c b/common/cmd_monitor.c
index 69be750..4e9c29b 100644
--- a/common/cmd_monitor.c
+++ b/common/cmd_monitor.c
@@ -261,14 +261,14 @@ int lowlevel_monitor (void)
else if(strcmp(argv[0], "rt") == 0) { // rt
unsigned char val;
printf("filling\n");
- for(addr=(char *) CFG_LOADADDR; addr < 512*1024*1024+(char *) 0x80000000; addr++) {
+ for(addr=(char *) CFG_LOADADDR; addr < 256*1024*1024+(char *) 0x80000000; addr++) {
val=(unsigned int) addr + (((unsigned int) addr) >> 8) + (((unsigned int) addr) >> 16) + (((unsigned int) addr) >> 24); // build from address
if((((unsigned int)addr) & 0xfffff) == 0) // approx. 1 MByte per second
printf("%08x: %02x\n", addr, val);
*addr=val; // fill ram with prime pattern
}
printf("\nchecking\n");
- for(addr=(char *) CFG_LOADADDR; addr < 512*1024*1024+(char *) 0x80000000; addr++) {
+ for(addr=(char *) CFG_LOADADDR; addr < 256*1024*1024+(char *) 0x80000000; addr++) {
unsigned char r=*addr; // read back
val=(unsigned int) addr + (((unsigned int) addr) >> 8) + (((unsigned int) addr) >> 16) + (((unsigned int) addr) >> 24);
if((((unsigned int)addr) & 0xfffff) == 0)
diff --git a/include/configs/omap3530gta04.h b/include/configs/omap3530gta04.h
index 645f48f..3e6ef21 100644
--- a/include/configs/omap3530gta04.h
+++ b/include/configs/omap3530gta04.h
@@ -47,7 +47,7 @@
#define CONFIG_BEAGLE_REV2 1
/* Enable the below macro if MMC boot support is required */
-#define CONFIG_MMC 1
+//#define CONFIG_MMC 1
#if defined(CONFIG_MMC)
#define CFG_CMD_MMC 1
#define CFG_CMD_FAT 1
@@ -86,7 +86,7 @@
#define SDRC_R_B_C 1
/* Enable the below macro if NAND boot support is required */
-#define CONFIG_NAND 1
+//#define CONFIG_NAND 1
#define NAND_BASE_ADR NAND_BASE
#define ONENAND_BASE ONENAND_MAP