From 819e36b8ceadb1d67db1ffe91b99c5282bfc6159 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Fri, 20 Apr 2012 14:10:36 +0200 Subject: tree moved to a better location --- Makefile | 271 +++++ README | 142 +++ README-GTA04 | 46 + arm_config.mk | 24 + board/omap2420h4/Makefile | 51 + board/omap2420h4/config.mk | 26 + board/omap2420h4/omap2420h4.c | 598 ++++++++++ board/omap2420h4/platform.S | 218 ++++ board/omap2420h4/x-load.lds | 54 + board/omap2430sdp/Makefile | 51 + board/omap2430sdp/config.mk | 28 + board/omap2430sdp/omap2430sdp.c | 746 +++++++++++++ board/omap2430sdp/platform.S | 198 ++++ board/omap2430sdp/x-load.lds | 54 + board/omap3430labrador/Makefile | 51 + board/omap3430labrador/config.mk | 22 + board/omap3430labrador/omap3430sdp.c | 753 +++++++++++++ board/omap3430labrador/platform.S | 360 ++++++ board/omap3430labrador/x-load.lds | 54 + board/omap3430sdp/Makefile | 51 + board/omap3430sdp/config.mk | 22 + board/omap3430sdp/omap3430sdp.c | 779 +++++++++++++ board/omap3430sdp/platform.S | 360 ++++++ board/omap3430sdp/x-load.lds | 54 + board/omap3530beagle/Makefile | 51 + board/omap3530beagle/config.mk | 20 + board/omap3530beagle/omap3530beagle.c | 1081 ++++++++++++++++++ board/omap3530beagle/platform.S | 360 ++++++ board/omap3530beagle/platform.S_old | 435 ++++++++ board/omap3530beagle/x-load.lds | 54 + board/omap3530gta04/Makefile | 51 + board/omap3530gta04/config.mk | 23 + board/omap3530gta04/omap3530gta04.c | 1279 ++++++++++++++++++++++ board/omap3530gta04/platform.S | 360 ++++++ board/omap3evm/Makefile | 51 + board/omap3evm/config.mk | 19 + board/omap3evm/omap3evm.c | 814 ++++++++++++++ board/omap3evm/platform.S | 435 ++++++++ board/omap3evm/x-load.lds | 54 + board/omap4430panda/Makefile | 53 + board/omap4430panda/clock.c | 804 ++++++++++++++ board/omap4430panda/config.mk | 21 + board/omap4430panda/omap4430panda.c | 1235 +++++++++++++++++++++ board/omap4430panda/platform.S | 51 + board/omap4430panda/syslib.c | 73 ++ board/overo/Makefile | 51 + board/overo/config.mk | 20 + board/overo/overo.c | 1148 +++++++++++++++++++ board/overo/platform.S | 360 ++++++ board/overo/x-load.lds | 54 + common/Makefile | 49 + common/cmd_load.c | 555 ++++++++++ common/cmd_monitor.c | 361 ++++++ config.mk | 208 ++++ cpu/arm1136/Makefile | 47 + cpu/arm1136/config.mk | 33 + cpu/arm1136/cpu.c | 65 ++ cpu/arm1136/start.S | 218 ++++ cpu/omap3/Makefile | 47 + cpu/omap3/config.mk | 32 + cpu/omap3/cpu.c | 51 + cpu/omap3/gpio.c | 185 ++++ cpu/omap3/mmc.c | 565 ++++++++++ cpu/omap3/start.S | 224 ++++ cpu/omap4/Makefile | 48 + cpu/omap4/config.mk | 32 + cpu/omap4/cpu.c | 79 ++ cpu/omap4/mmc.c | 547 +++++++++ cpu/omap4/sys_info.c | 35 + disk/Makefile | 47 + disk/part.c | 273 +++++ drivers/Makefile | 84 ++ drivers/k9f1g08r0a.c | 350 ++++++ drivers/k9k1216.c | 258 +++++ drivers/ns16550.c | 69 ++ drivers/omap24xx_i2c.c | 354 ++++++ drivers/onenand.c | 238 ++++ drivers/onenand_regs.h | 167 +++ drivers/serial.c | 104 ++ fs/Makefile | 29 + fs/fat/Makefile | 45 + fs/fat/fat.c | 960 ++++++++++++++++ fs/fat/file.c | 209 ++++ include/asm/arch-arm1136/bits.h | 49 + include/asm/arch-arm1136/clocks.h | 51 + include/asm/arch-arm1136/clocks242x.h | 147 +++ include/asm/arch-arm1136/clocks243x.h | 223 ++++ include/asm/arch-arm1136/mem.h | 383 +++++++ include/asm/arch-arm1136/omap2420.h | 223 ++++ include/asm/arch-arm1136/omap2430.h | 255 +++++ include/asm/arch-arm1136/sizes.h | 50 + include/asm/arch-arm1136/sys_info.h | 139 +++ include/asm/arch-arm926ejs/sizes.h | 51 + include/asm/arch-omap3/bits.h | 48 + include/asm/arch-omap3/clocks.h | 48 + include/asm/arch-omap3/clocks343x.h | 155 +++ include/asm/arch-omap3/cpu.h | 257 +++++ include/asm/arch-omap3/gpio.h | 86 ++ include/asm/arch-omap3/i2c.h | 128 +++ include/asm/arch-omap3/mem.h | 589 ++++++++++ include/asm/arch-omap3/mmc.h | 235 ++++ include/asm/arch-omap3/mmc_host_def.h | 164 +++ include/asm/arch-omap3/mux.h | 437 ++++++++ include/asm/arch-omap3/omap3430.h | 197 ++++ include/asm/arch-omap3/rev.h | 43 + include/asm/arch-omap3/sizes.h | 49 + include/asm/arch-omap3/sys_info.h | 77 ++ include/asm/arch-omap3/sys_proto.h | 59 + include/asm/arch-omap4/bits.h | 48 + include/asm/arch-omap4/clocks.h | 36 + include/asm/arch-omap4/clocks443x.h | 154 +++ include/asm/arch-omap4/cpu.h | 464 ++++++++ include/asm/arch-omap4/mem.h | 285 +++++ include/asm/arch-omap4/mmc.h | 235 ++++ include/asm/arch-omap4/mmc_host_def.h | 168 +++ include/asm/arch-omap4/mux.h | 392 +++++++ include/asm/arch-omap4/omap4430.h | 137 +++ include/asm/arch-omap4/rev.h | 41 + include/asm/arch-omap4/sizes.h | 48 + include/asm/arch-omap4/sys_info.h | 75 ++ include/asm/arch-omap4/sys_proto.h | 60 + include/asm/atomic.h | 113 ++ include/asm/byteorder.h | 32 + include/asm/errno.h | 155 +++ include/asm/io.h | 335 ++++++ include/asm/memory.h | 137 +++ include/asm/posix_types.h | 79 ++ include/asm/setup.h | 269 +++++ include/asm/sizes.h | 52 + include/asm/string.h | 47 + include/asm/types.h | 51 + include/asm/x-load-arm.h | 40 + include/command.h | 107 ++ include/common.h | 110 ++ include/configs/omap2420h4.h | 140 +++ include/configs/omap2430sdp.h | 178 +++ include/configs/omap3430labrador.h | 211 ++++ include/configs/omap3430sdp.h | 213 ++++ include/configs/omap3530beagle.h | 205 ++++ include/configs/omap3530gta04.h | 216 ++++ include/configs/omap3evm.h | 207 ++++ include/configs/omap4430panda.h | 106 ++ include/configs/overo.h | 205 ++++ include/fat.h | 215 ++++ include/i2c.h | 151 +++ include/ide.h | 55 + include/linux/byteorder/big_endian.h | 69 ++ include/linux/byteorder/generic.h | 180 +++ include/linux/byteorder/little_endian.h | 69 ++ include/linux/byteorder/swab.h | 158 +++ include/linux/config.h | 6 + include/linux/posix_types.h | 48 + include/linux/stat.h | 132 +++ include/linux/stddef.h | 18 + include/linux/time.h | 158 +++ include/linux/types.h | 130 +++ include/malloc.h | 942 ++++++++++++++++ include/mmc.h | 57 + include/ns16550.h | 130 +++ include/part.h | 121 ++ lib/Makefile | 47 + lib/_udivsi3.S | 77 ++ lib/_umodsi3.S | 88 ++ lib/board.c | 164 +++ lib/div0.c | 30 + lib/ecc.c | 250 +++++ lib/printf.c | 304 +++++ mkconfig | 63 ++ rules.mk | 35 + scripts/mkoneboot.sh | 16 + scripts/signGP.c | 300 +++++ x-loader/Makefile | 271 ----- x-loader/README | 142 --- x-loader/README-GTA04 | 46 - x-loader/arm_config.mk | 24 - x-loader/board/omap2420h4/Makefile | 51 - x-loader/board/omap2420h4/config.mk | 26 - x-loader/board/omap2420h4/omap2420h4.c | 598 ---------- x-loader/board/omap2420h4/platform.S | 218 ---- x-loader/board/omap2420h4/x-load.lds | 54 - x-loader/board/omap2430sdp/Makefile | 51 - x-loader/board/omap2430sdp/config.mk | 28 - x-loader/board/omap2430sdp/omap2430sdp.c | 746 ------------- x-loader/board/omap2430sdp/platform.S | 198 ---- x-loader/board/omap2430sdp/x-load.lds | 54 - x-loader/board/omap3430labrador/Makefile | 51 - x-loader/board/omap3430labrador/config.mk | 22 - x-loader/board/omap3430labrador/omap3430sdp.c | 753 ------------- x-loader/board/omap3430labrador/platform.S | 360 ------ x-loader/board/omap3430labrador/x-load.lds | 54 - x-loader/board/omap3430sdp/Makefile | 51 - x-loader/board/omap3430sdp/config.mk | 22 - x-loader/board/omap3430sdp/omap3430sdp.c | 779 ------------- x-loader/board/omap3430sdp/platform.S | 360 ------ x-loader/board/omap3430sdp/x-load.lds | 54 - x-loader/board/omap3530beagle/Makefile | 51 - x-loader/board/omap3530beagle/config.mk | 20 - x-loader/board/omap3530beagle/omap3530beagle.c | 1081 ------------------ x-loader/board/omap3530beagle/platform.S | 360 ------ x-loader/board/omap3530beagle/platform.S_old | 435 -------- x-loader/board/omap3530beagle/x-load.lds | 54 - x-loader/board/omap3530gta04/Makefile | 51 - x-loader/board/omap3530gta04/config.mk | 23 - x-loader/board/omap3530gta04/omap3530gta04.c | 1279 ---------------------- x-loader/board/omap3530gta04/platform.S | 360 ------ x-loader/board/omap3evm/Makefile | 51 - x-loader/board/omap3evm/config.mk | 19 - x-loader/board/omap3evm/omap3evm.c | 814 -------------- x-loader/board/omap3evm/platform.S | 435 -------- x-loader/board/omap3evm/x-load.lds | 54 - x-loader/board/omap4430panda/Makefile | 53 - x-loader/board/omap4430panda/clock.c | 804 -------------- x-loader/board/omap4430panda/config.mk | 21 - x-loader/board/omap4430panda/omap4430panda.c | 1235 --------------------- x-loader/board/omap4430panda/syslib.c | 73 -- x-loader/board/overo/Makefile | 51 - x-loader/board/overo/config.mk | 20 - x-loader/board/overo/overo.c | 1148 ------------------- x-loader/board/overo/platform.S | 360 ------ x-loader/board/overo/x-load.lds | 54 - x-loader/common/Makefile | 49 - x-loader/common/cmd_load.c | 555 ---------- x-loader/common/cmd_monitor.c | 361 ------ x-loader/config.mk | 208 ---- x-loader/cpu/arm1136/Makefile | 47 - x-loader/cpu/arm1136/config.mk | 33 - x-loader/cpu/arm1136/cpu.c | 65 -- x-loader/cpu/arm1136/start.S | 218 ---- x-loader/cpu/omap3/Makefile | 47 - x-loader/cpu/omap3/config.mk | 32 - x-loader/cpu/omap3/cpu.c | 51 - x-loader/cpu/omap3/gpio.c | 185 ---- x-loader/cpu/omap3/mmc.c | 565 ---------- x-loader/cpu/omap3/start.S | 224 ---- x-loader/cpu/omap4/Makefile | 48 - x-loader/cpu/omap4/config.mk | 32 - x-loader/cpu/omap4/cpu.c | 79 -- x-loader/cpu/omap4/mmc.c | 547 --------- x-loader/cpu/omap4/sys_info.c | 35 - x-loader/disk/Makefile | 47 - x-loader/disk/part.c | 273 ----- x-loader/drivers/Makefile | 84 -- x-loader/drivers/k9f1g08r0a.c | 350 ------ x-loader/drivers/k9k1216.c | 258 ----- x-loader/drivers/ns16550.c | 69 -- x-loader/drivers/omap24xx_i2c.c | 354 ------ x-loader/drivers/onenand.c | 238 ---- x-loader/drivers/onenand_regs.h | 167 --- x-loader/drivers/serial.c | 104 -- x-loader/fs/Makefile | 29 - x-loader/fs/fat/Makefile | 45 - x-loader/fs/fat/fat.c | 960 ---------------- x-loader/fs/fat/file.c | 209 ---- x-loader/include/asm/arch-arm1136/bits.h | 49 - x-loader/include/asm/arch-arm1136/clocks.h | 51 - x-loader/include/asm/arch-arm1136/clocks242x.h | 147 --- x-loader/include/asm/arch-arm1136/clocks243x.h | 223 ---- x-loader/include/asm/arch-arm1136/mem.h | 383 ------- x-loader/include/asm/arch-arm1136/omap2420.h | 223 ---- x-loader/include/asm/arch-arm1136/omap2430.h | 255 ----- x-loader/include/asm/arch-arm1136/sizes.h | 50 - x-loader/include/asm/arch-arm1136/sys_info.h | 139 --- x-loader/include/asm/arch-arm926ejs/sizes.h | 51 - x-loader/include/asm/arch-omap3/bits.h | 48 - x-loader/include/asm/arch-omap3/clocks.h | 48 - x-loader/include/asm/arch-omap3/clocks343x.h | 155 --- x-loader/include/asm/arch-omap3/cpu.h | 257 ----- x-loader/include/asm/arch-omap3/gpio.h | 86 -- x-loader/include/asm/arch-omap3/i2c.h | 128 --- x-loader/include/asm/arch-omap3/mem.h | 589 ---------- x-loader/include/asm/arch-omap3/mmc.h | 235 ---- x-loader/include/asm/arch-omap3/mmc_host_def.h | 164 --- x-loader/include/asm/arch-omap3/mux.h | 437 -------- x-loader/include/asm/arch-omap3/omap3430.h | 197 ---- x-loader/include/asm/arch-omap3/rev.h | 43 - x-loader/include/asm/arch-omap3/sizes.h | 49 - x-loader/include/asm/arch-omap3/sys_info.h | 77 -- x-loader/include/asm/arch-omap3/sys_proto.h | 59 - x-loader/include/asm/arch-omap4/bits.h | 48 - x-loader/include/asm/arch-omap4/clocks.h | 36 - x-loader/include/asm/arch-omap4/clocks443x.h | 154 --- x-loader/include/asm/arch-omap4/cpu.h | 464 -------- x-loader/include/asm/arch-omap4/mem.h | 285 ----- x-loader/include/asm/arch-omap4/mmc.h | 235 ---- x-loader/include/asm/arch-omap4/mmc_host_def.h | 168 --- x-loader/include/asm/arch-omap4/mux.h | 392 ------- x-loader/include/asm/arch-omap4/omap4430.h | 137 --- x-loader/include/asm/arch-omap4/rev.h | 41 - x-loader/include/asm/arch-omap4/sizes.h | 48 - x-loader/include/asm/arch-omap4/sys_info.h | 75 -- x-loader/include/asm/arch-omap4/sys_proto.h | 60 - x-loader/include/asm/atomic.h | 113 -- x-loader/include/asm/byteorder.h | 32 - x-loader/include/asm/errno.h | 155 --- x-loader/include/asm/io.h | 335 ------ x-loader/include/asm/memory.h | 137 --- x-loader/include/asm/posix_types.h | 79 -- x-loader/include/asm/setup.h | 269 ----- x-loader/include/asm/sizes.h | 52 - x-loader/include/asm/string.h | 47 - x-loader/include/asm/types.h | 51 - x-loader/include/asm/x-load-arm.h | 40 - x-loader/include/command.h | 107 -- x-loader/include/common.h | 110 -- x-loader/include/configs/omap2420h4.h | 140 --- x-loader/include/configs/omap2430sdp.h | 178 --- x-loader/include/configs/omap3430labrador.h | 211 ---- x-loader/include/configs/omap3430sdp.h | 213 ---- x-loader/include/configs/omap3530beagle.h | 205 ---- x-loader/include/configs/omap3530gta04.h | 216 ---- x-loader/include/configs/omap3evm.h | 207 ---- x-loader/include/configs/omap4430panda.h | 106 -- x-loader/include/configs/overo.h | 205 ---- x-loader/include/fat.h | 215 ---- x-loader/include/i2c.h | 151 --- x-loader/include/ide.h | 55 - x-loader/include/linux/byteorder/big_endian.h | 69 -- x-loader/include/linux/byteorder/generic.h | 180 --- x-loader/include/linux/byteorder/little_endian.h | 69 -- x-loader/include/linux/byteorder/swab.h | 158 --- x-loader/include/linux/config.h | 6 - x-loader/include/linux/posix_types.h | 48 - x-loader/include/linux/stat.h | 132 --- x-loader/include/linux/stddef.h | 18 - x-loader/include/linux/time.h | 158 --- x-loader/include/linux/types.h | 130 --- x-loader/include/malloc.h | 942 ---------------- x-loader/include/mmc.h | 57 - x-loader/include/ns16550.h | 130 --- x-loader/include/part.h | 121 -- x-loader/lib/Makefile | 47 - x-loader/lib/_udivsi3.S | 77 -- x-loader/lib/_umodsi3.S | 88 -- x-loader/lib/board.c | 164 --- x-loader/lib/div0.c | 30 - x-loader/lib/ecc.c | 250 ----- x-loader/lib/printf.c | 304 ----- x-loader/mkconfig | 63 -- x-loader/rules.mk | 35 - x-loader/scripts/mkoneboot.sh | 16 - x-loader/scripts/signGP.c | 300 ----- 341 files changed, 34045 insertions(+), 33994 deletions(-) create mode 100644 Makefile create mode 100644 README create mode 100644 README-GTA04 create mode 100644 arm_config.mk create mode 100644 board/omap2420h4/Makefile create mode 100644 board/omap2420h4/config.mk create mode 100644 board/omap2420h4/omap2420h4.c create mode 100644 board/omap2420h4/platform.S create mode 100644 board/omap2420h4/x-load.lds create mode 100644 board/omap2430sdp/Makefile create mode 100644 board/omap2430sdp/config.mk create mode 100644 board/omap2430sdp/omap2430sdp.c create mode 100644 board/omap2430sdp/platform.S create mode 100644 board/omap2430sdp/x-load.lds create mode 100644 board/omap3430labrador/Makefile create mode 100644 board/omap3430labrador/config.mk create mode 100644 board/omap3430labrador/omap3430sdp.c create mode 100644 board/omap3430labrador/platform.S create mode 100644 board/omap3430labrador/x-load.lds create mode 100644 board/omap3430sdp/Makefile create mode 100644 board/omap3430sdp/config.mk create mode 100644 board/omap3430sdp/omap3430sdp.c create mode 100644 board/omap3430sdp/platform.S create mode 100644 board/omap3430sdp/x-load.lds create mode 100644 board/omap3530beagle/Makefile create mode 100644 board/omap3530beagle/config.mk create mode 100644 board/omap3530beagle/omap3530beagle.c create mode 100644 board/omap3530beagle/platform.S create mode 100644 board/omap3530beagle/platform.S_old create mode 100644 board/omap3530beagle/x-load.lds create mode 100644 board/omap3530gta04/Makefile create mode 100644 board/omap3530gta04/config.mk create mode 100644 board/omap3530gta04/omap3530gta04.c create mode 100644 board/omap3530gta04/platform.S create mode 100644 board/omap3evm/Makefile create mode 100644 board/omap3evm/config.mk create mode 100644 board/omap3evm/omap3evm.c create mode 100644 board/omap3evm/platform.S create mode 100644 board/omap3evm/x-load.lds create mode 100644 board/omap4430panda/Makefile create mode 100644 board/omap4430panda/clock.c create mode 100644 board/omap4430panda/config.mk create mode 100644 board/omap4430panda/omap4430panda.c create mode 100644 board/omap4430panda/platform.S create mode 100644 board/omap4430panda/syslib.c create mode 100644 board/overo/Makefile create mode 100644 board/overo/config.mk create mode 100644 board/overo/overo.c create mode 100644 board/overo/platform.S create mode 100644 board/overo/x-load.lds create mode 100644 common/Makefile create mode 100644 common/cmd_load.c create mode 100644 common/cmd_monitor.c create mode 100644 config.mk create mode 100644 cpu/arm1136/Makefile create mode 100644 cpu/arm1136/config.mk create mode 100644 cpu/arm1136/cpu.c create mode 100644 cpu/arm1136/start.S create mode 100644 cpu/omap3/Makefile create mode 100644 cpu/omap3/config.mk create mode 100644 cpu/omap3/cpu.c create mode 100644 cpu/omap3/gpio.c create mode 100644 cpu/omap3/mmc.c create mode 100644 cpu/omap3/start.S create mode 100644 cpu/omap4/Makefile create mode 100644 cpu/omap4/config.mk create mode 100644 cpu/omap4/cpu.c create mode 100644 cpu/omap4/mmc.c create mode 100644 cpu/omap4/sys_info.c create mode 100644 disk/Makefile create mode 100644 disk/part.c create mode 100644 drivers/Makefile create mode 100644 drivers/k9f1g08r0a.c create mode 100644 drivers/k9k1216.c create mode 100644 drivers/ns16550.c create mode 100644 drivers/omap24xx_i2c.c create mode 100644 drivers/onenand.c create mode 100644 drivers/onenand_regs.h create mode 100644 drivers/serial.c create mode 100644 fs/Makefile create mode 100644 fs/fat/Makefile create mode 100644 fs/fat/fat.c create mode 100644 fs/fat/file.c create mode 100644 include/asm/arch-arm1136/bits.h create mode 100644 include/asm/arch-arm1136/clocks.h create mode 100644 include/asm/arch-arm1136/clocks242x.h create mode 100644 include/asm/arch-arm1136/clocks243x.h create mode 100644 include/asm/arch-arm1136/mem.h create mode 100644 include/asm/arch-arm1136/omap2420.h create mode 100644 include/asm/arch-arm1136/omap2430.h create mode 100644 include/asm/arch-arm1136/sizes.h create mode 100644 include/asm/arch-arm1136/sys_info.h create mode 100644 include/asm/arch-arm926ejs/sizes.h create mode 100644 include/asm/arch-omap3/bits.h create mode 100644 include/asm/arch-omap3/clocks.h create mode 100644 include/asm/arch-omap3/clocks343x.h create mode 100644 include/asm/arch-omap3/cpu.h create mode 100644 include/asm/arch-omap3/gpio.h create mode 100644 include/asm/arch-omap3/i2c.h create mode 100644 include/asm/arch-omap3/mem.h create mode 100644 include/asm/arch-omap3/mmc.h create mode 100644 include/asm/arch-omap3/mmc_host_def.h create mode 100644 include/asm/arch-omap3/mux.h create mode 100644 include/asm/arch-omap3/omap3430.h create mode 100755 include/asm/arch-omap3/rev.h create mode 100644 include/asm/arch-omap3/sizes.h create mode 100644 include/asm/arch-omap3/sys_info.h create mode 100644 include/asm/arch-omap3/sys_proto.h create mode 100644 include/asm/arch-omap4/bits.h create mode 100644 include/asm/arch-omap4/clocks.h create mode 100644 include/asm/arch-omap4/clocks443x.h create mode 100644 include/asm/arch-omap4/cpu.h create mode 100644 include/asm/arch-omap4/mem.h create mode 100644 include/asm/arch-omap4/mmc.h create mode 100644 include/asm/arch-omap4/mmc_host_def.h create mode 100644 include/asm/arch-omap4/mux.h create mode 100644 include/asm/arch-omap4/omap4430.h create mode 100644 include/asm/arch-omap4/rev.h create mode 100644 include/asm/arch-omap4/sizes.h create mode 100644 include/asm/arch-omap4/sys_info.h create mode 100644 include/asm/arch-omap4/sys_proto.h create mode 100644 include/asm/atomic.h create mode 100755 include/asm/byteorder.h create mode 100644 include/asm/errno.h create mode 100644 include/asm/io.h create mode 100644 include/asm/memory.h create mode 100644 include/asm/posix_types.h create mode 100644 include/asm/setup.h create mode 100644 include/asm/sizes.h create mode 100644 include/asm/string.h create mode 100644 include/asm/types.h create mode 100644 include/asm/x-load-arm.h create mode 100644 include/command.h create mode 100644 include/common.h create mode 100644 include/configs/omap2420h4.h create mode 100644 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mode 100644 x-loader/include/ns16550.h delete mode 100644 x-loader/include/part.h delete mode 100644 x-loader/lib/Makefile delete mode 100644 x-loader/lib/_udivsi3.S delete mode 100644 x-loader/lib/_umodsi3.S delete mode 100644 x-loader/lib/board.c delete mode 100644 x-loader/lib/div0.c delete mode 100644 x-loader/lib/ecc.c delete mode 100644 x-loader/lib/printf.c delete mode 100755 x-loader/mkconfig delete mode 100644 x-loader/rules.mk delete mode 100644 x-loader/scripts/mkoneboot.sh delete mode 100644 x-loader/scripts/signGP.c diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..27fe4b5 --- /dev/null +++ b/Makefile @@ -0,0 +1,271 @@ +# +# (C) Copyright 2004-2006, Texas Instruments, +# Jian Zhang +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +HOSTARCH := $(shell uname -m | \ + sed -e s/i.86/i386/ \ + -e s/sun4u/sparc64/ \ + -e s/arm.*/arm/ \ + -e s/sa110/arm/ \ + -e s/powerpc/ppc/ \ + -e s/macppc/ppc/) + +HOSTOS := $(shell uname -s | tr A-Z a-z | \ + sed -e 's/\(cygwin\).*/cygwin/') + +export HOSTARCH + +# Deal with colliding definitions from tcsh etc. +VENDOR= + +######################################################################### +# +# X-loader build supports producing a object files to the separate external +# directory. Two use cases are supported: +# +# 1) Add O= to the make command line +# 'make O=/tmp/build all' +# +# 2) Set environement variable BUILD_DIR to point to the desired location +# 'export BUILD_DIR=/tmp/build' +# 'make' +# +# Command line 'O=' setting overrides BUILD_DIR environent variable. +# +# When none of the above methods is used the local build is performed and +# the object files are placed in the source directory. +# + +ifdef O +ifeq ("$(origin O)", "command line") +BUILD_DIR := $(O) +endif +endif + +ifneq ($(BUILD_DIR),) +saved-output := $(BUILD_DIR) + +# Attempt to create a output directory. +$(shell [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR}) + +# Verify if it was successful. +BUILD_DIR := $(shell cd $(BUILD_DIR) && /bin/pwd) +$(if $(BUILD_DIR),,$(error output directory "$(saved-output)" does not exist)) +endif # ifneq ($(BUILD_DIR),) + +OBJTREE := $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR)) +SRCTREE := $(CURDIR) +TOPDIR := $(SRCTREE) +LNDIR := $(OBJTREE) +export TOPDIR SRCTREE OBJTREE + +MKCONFIG := $(SRCTREE)/mkconfig +export MKCONFIG + +ifneq ($(OBJTREE),$(SRCTREE)) +REMOTE_BUILD := 1 +export REMOTE_BUILD +endif + +# $(obj) and (src) are defined in config.mk but here in main Makefile +# we also need them before config.mk is included which is the case for +# some targets like unconfig, clean, clobber, distclean, etc. +ifneq ($(OBJTREE),$(SRCTREE)) +obj := $(OBJTREE)/ +src := $(SRCTREE)/ +else +obj := +src := +endif +export obj src + +# Make sure CDPATH settings don't interfere +unexport CDPATH + +######################################################################### + +ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk)) +# load ARCH, BOARD, and CPU configuration +include $(obj)include/config.mk +export ARCH CPU BOARD VENDOR +# load other configuration +include $(TOPDIR)/config.mk + +ifndef CROSS_COMPILE +CROSS_COMPILE = arm-none-linux-gnueabi- +#CROSS_COMPILE = arm-linux- +export CROSS_COMPILE +endif + +######################################################################### +# X-LOAD objects....order is important (i.e. start must be first) + +OBJS = cpu/$(CPU)/start.o + +OBJS := $(addprefix $(obj),$(OBJS)) + +LIBS += board/$(BOARDDIR)/lib$(BOARD).a +LIBS += cpu/$(CPU)/lib$(CPU).a +LIBS += lib/lib$(ARCH).a +LIBS += fs/fat/libfat.a +LIBS += disk/libdisk.a +LIBS += drivers/libdrivers.a +LIBS += common/libcommon.a + +LIBS := $(addprefix $(obj),$(sort $(LIBS))) +.PHONY : $(LIBS) + +# Add GCC lib +PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc + +SUBDIRS = + +__OBJS := $(subst $(obj),,$(OBJS)) +__LIBS := $(subst $(obj),,$(LIBS)) + +######################################################################### +######################################################################### + +ALL = $(obj)x-load.bin $(obj)System.map + +all: $(ALL) + +ift: $(ALL) $(obj)x-load.bin.ift + +$(obj)x-load.bin.ift: $(obj)signGP $(obj)System.map $(obj)x-load.bin + TEXT_BASE=`grep -w _start $(obj)System.map|cut -d ' ' -f1` + $(obj)./signGP $(obj)x-load.bin $(TEXT_BASE) + cp $(obj)x-load.bin.ift $(obj)MLO + +$(obj)x-load.bin: $(obj)x-load + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(obj)x-load: $(OBJS) $(LIBS) $(LDSCRIPT) + UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ + -Map x-load.map -o x-load + +$(OBJS): + $(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@)) + +$(LIBS): + $(MAKE) -C $(dir $(subst $(obj),,$@)) + +$(obj)System.map: $(obj)x-load + @$(NM) $< | \ + grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > $(obj)System.map + +oneboot: $(obj)x-load.bin + scripts/mkoneboot.sh + +$(obj)signGP: scripts/signGP.c + gcc -Wall -g -O3 -o $(obj)signGP $< + +######################################################################### +else +all $(obj)x-load $(obj)x-load.bin oneboot depend dep $(obj)System.map: + @echo "System not configured - see README" >&2 + @ exit 1 +endif + +######################################################################### + +unconfig: + rm -f $(obj)include/config.h $(obj)include/config.mk + +#======================================================================== +# ARM +#======================================================================== +######################################################################### +## OMAP2 (ARM1136) Systems +######################################################################### + +omap2420h4_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 + +omap2430sdp_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm1136 omap2430sdp + +######################################################################### +## OMAP3 (ARM-CortexA8) Systems +######################################################################### +omap3430sdp_config : unconfig + @$(MKCONFIG) $(@:_config=) arm omap3 omap3430sdp + +omap3430labrador_config : unconfig + @$(MKCONFIG) $(@:_config=) arm omap3 omap3430labrador + +omap3evm_config : unconfig + @$(MKCONFIG) $(@:_config=) arm omap3 omap3evm + +overo_config : unconfig + @$(MKCONFIG) $(@:_config=) arm omap3 overo + +omap3530beagle_config : unconfig + @$(MKCONFIG) $(@:_config=) arm omap3 omap3530beagle + +omap3530gta04_config : unconfig + @$(MKCONFIG) $(@:_config=) arm omap3 omap3530gta04 + +######################################################################### +## OMAP4 (ARM-CortexA9) Systems +######################################################################### +omap4430panda_config : unconfig + @./mkconfig $(@:_config=) arm omap4 omap4430panda + +######################################################################### + +clean: + find $(OBJTREE) -type f \ + \( -name 'core' -o -name '*.bak' -o -name '*~' \ + -o -name '*.o' -o -name '*.a' \) -print \ + | xargs rm -f + +clobber: clean + find $(OBJTREE) -type f \ + \( -name .depend -o -name '*.srec' -o -name '*.bin' \) \ + -print \ + | xargs rm -f + rm -f $(OBJS) $(obj)*.bak $(obj)tags $(obj)TAGS + rm -fr $(obj)*.*~ + rm -f $(obj)x-load $(obj)x-load.map $(ALL) $(obj)x-load.bin.ift $(obj)signGP $(obj)MLO + rm -f $(obj)include/asm/proc $(obj)include/asm/arch + +ifeq ($(OBJTREE),$(SRCTREE)) +mrproper \ +distclean: clobber unconfig +else +mrproper \ +distclean: clobber unconfig + rm -rf $(obj)* +endif + +backup: + F=`basename $(TOPDIR)` ; cd .. ; \ + gtar --force-local -zcvf `date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F + +######################################################################### diff --git a/README b/README new file mode 100644 index 0000000..d7b16dd --- /dev/null +++ b/README @@ -0,0 +1,142 @@ +# +# (C) Copyright 2004-2006 Texas Instruments +# +# Some cut/paste from U-Boot README +# (C) Copyright 2000 - 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +Summary: +======== + +This directory contains the source code for X-Loader, an initial program +loader for Embedded boards based on OMAP processors. X-Loader can be +signed by Texas Instruments IFT and installed to Nand flash to achieve +Nand booting. + + +Status: +======= + +The support for Texas Instruments H4 board (OMAP2420) has been implemented +and tested. (Nov 2004) +The support for Texas Instruments 2430SDP board (OMAP2430) has been implemented +and tested. (Jul 2006) +The support for Texas Instruments 3430SDP board (OMAP3430) has been implemented +and tested. (Dec 2006) + + +Support for other OMAP boards can be added. + + +Directory Hierarchy: +==================== + +- board Board dependent files +- cpu CPU specific files +- drivers Commonly used device drivers +- lib Libraries + +- cpu/arm926ejs Files specific to ARM 926 CPUs +- cpu/arm1136 Files specific to ARM 1136 CPUs +- cpu/omap3 Files specific to ARM CortexA8 CPU + + +- board/omap2420h4 + Files specific to OMAP 2420 H4 boards +- board/omap2430sdp + Files specific to OMAP 2430 2430sdp boards +- board/omap3430sdp + Files specific to OMAP 3420sdp boards + + +Software Configuration: +======================= + +Configuration is usually done using C preprocessor defines. Configuration +depends on the combination of board and CPU type; all such information is +kept in a configuration file "include/configs/.h". + +Example: For a OMAP4 PandaBoard, all configuration settings are in +"include/configs/omap4430panda.h" + +For all supported boards there are ready-to-use default +configurations available; just type "make _config". + +Example: For a OMAP4 PandaBoard, type: + + cd x-load + make omap4430panda_config + +After a board has been configured, type "make" to build it supposing the +needed cross tools are in your path. + + +Image Format: +============= + +X-Loader expects OS boot loader (e.g. U-Boot) in Nand flash using +JFFS2 style ECC. + + +Prepare Booting Nand Flash: +=========================== + +After you have built x-load.bin for your board, you need to do the +followings to get it into Nand flash: + +1. Use Texas Instruments IFT to sign x-load.bin. This results in a +signed image called x-load.bin.ift. +2. Use Texas Instruments FlashPrep to generate a .out file using +FlashWriterNand and specifying 0 as nand target address. +3. Use Texas instrumnets Code Composer Studio to run the .out file +which flashes x-load.bin.ift to Nand flash. + +Next you need to get your OS boot loader to Nand at the address your +X-Loader expects. For the H3 example, you can use U-Boot to flash U-Boot. +You can't use FlashWriterNand because it uses ROM code ECC style. + +Implemenation notes: +==================== +H4 support NAND flash booting +2430sdp & 3430sdp support OneNAND booting + + + + + + + + + + + + + + + + + + + + + + diff --git a/README-GTA04 b/README-GTA04 new file mode 100644 index 0000000..db2431c --- /dev/null +++ b/README-GTA04 @@ -0,0 +1,46 @@ +This X-loader has been modified for the http://www.GTA04.org board: + +* added Micron MCP detection +* added board revision detection +* added GTA04 notice to greeting +* added memory write check when loading u-boot.bin + from SD card to detect SDRAM failures +* added more Macros to compile either x-loader, MLO and + serial loader from the same sources + +For compiling the different variants, modify these files + +1. X-Loader +a) include/configs/omap3530gta04.h +//#define CONFIG_MMC 1 +#define CONFIG_NAND 1 + +b) board/omap3530gta04/config.mk +TEXT_BASE = 0x40200800 + +2. MLO +a) include/configs/omap3530gta04.h +#define CONFIG_MMC 1 +#define CONFIG_NAND 1 + +b) board/omap3530gta04/config.mk +TEXT_BASE = 0x40200800 + +3. Serial Loader +a) include/configs/omap3530gta04.h +//#define CONFIG_MMC 1 +//#define CONFIG_NAND 1 + +b) board/omap3530gta04/config.mk +TEXT_BASE = 0x40200800 + + +Compile: +make omap3530gta04_config + + +Result file: +X-Loader: x-load.bin.ift +MLO: rename x-load.bin.ift to MLO +Serial Loader: send x-load.bin through pserial tool + diff --git a/arm_config.mk b/arm_config.mk new file mode 100644 index 0000000..73d9625 --- /dev/null +++ b/arm_config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ diff --git a/board/omap2420h4/Makefile b/board/omap2420h4/Makefile new file mode 100644 index 0000000..e6f7629 --- /dev/null +++ b/board/omap2420h4/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := omap2420h4.o +SOBJS := platform.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/omap2420h4/config.mk b/board/omap2420h4/config.mk new file mode 100644 index 0000000..1c770f3 --- /dev/null +++ b/board/omap2420h4/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2004 +# Texas Instruments, +# +# TI H4 board with OMAP2420 (ARM1136) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 +# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) ES2 will be configurable +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +# CONFIG_PARTIAL_SRAM must be defined to use this. +TEXT_BASE = 0x80e80000 + +# Used with full SRAM boot. +# This is either with a GP system or a signed boot image. +# easiest, and safest way to go if you can. +# Comment out //CONFIG_PARTIAL_SRAM for this one. +# +#TEXT_BASE = 0x40280000 + diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c new file mode 100644 index 0000000..ef81b49 --- /dev/null +++ b/board/omap2420h4/omap2420h4.c @@ -0,0 +1,598 @@ +/* + * Copyright (C) 2005 Texas Instruments. + * Jian Zhang + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include + +#include +#include +#include + +static void wait_for_command_complete(unsigned int wd_base); +static void watchdog_init(void); +static void peripheral_enable(void); +static void muxSetupUART1(void); +static u32 get_cpu_rev(void); + + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init (void) +{ + return 0; +} + +#ifdef CFG_SDRAM_DDR +void +config_sdram_ddr(u32 rev) +{ + /* ball D11, mode 0 */ + __raw_writeb(0x08, 0x48000032); + + /* SDRC_CS0 Configuration */ + if (rev == CPU_2420_2422_ES1) { + __raw_writel(H4_2422_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); + __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING); + } else { + __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); + __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); + } + + __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); + __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0); + __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0); + + /* Manual Command sequence */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + + + /* + * CS0 SDRC Mode Register + * Burst length = 4 - DDR memory + * Serial mode + * CAS latency = 3 + */ + __raw_writel(0x00000032, SDRC_MR_0); + + /* SDRC DLLA control register */ + /* Delay is 90 degrees */ + if (rev == CPU_2420_2422_ES1) { + /* Enable DLL, Load counter with 115 (middle of range) */ + __raw_writel(0x00000002, SDRC_DLLA_CTRL); + /* Enable DLL, Load counter with 128 (middle of range) */ + __raw_writel(0x00000002, SDRC_DLLB_CTRL); + } else { + /* Enable DLL, Load counter with 115 (middle of range) */ + __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x + /* Enable DLL, Load counter with 128 (middle of range) */ + __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x + } + +} +#endif // CFG_SDRAM_DDR + + +#ifdef CFG_SDRAM_COMBO +void +config_sdram_combo(u32 rev) +{ + + u32 dllctrl=0; + + /* ball C12, mode 0 */ + __raw_writeb(0x00, 0x480000a1); + /* ball D11, mode 0 */ + __raw_writeb(0x00, 0x48000032); + /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */ + __raw_writeb(0x00, 0x480000a3); + + /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */ + __raw_writel(0x00000012, SDRC_SYSCONFIG); + delay(200000); + __raw_writel(0x00000010, SDRC_SYSCONFIG); + + /* SDRCTriState: no Tris */ + /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ + __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); + + + /* CS0 SDRC Memory Configuration, */ + /* DDR-SDRAM, External SDRAM is x32bit, */ + /* Configure to MUX9: 1x8Mbx32 */ + __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0); + __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); + __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); + __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); + + /* Manual Command sequence */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + + /* CS0 SDRC Mode Register */ + /* Burst length = 4 - DDR memory */ + /* Serial mode */ + /* CAS latency = 3 */ + __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0); + + /* CS1 SDRC Memory Configuration, */ + /* DDR-SDRAM, External SDRAM is x32bit, */ + /* Configure to MUX9: 1x8Mbx32 */ + __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1); + __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1); + __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1); + __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4); + + /* Manual Command sequence */ + __raw_writel(CMD_NOP, SDRC_MANUAL_1); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); + + /* CS1 SDRC Mode Register */ + /* Burst length = 4 - DDR memory */ + /* Serial mode */ + /* CAS latency = 3 */ + __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_1); + + /* SDRC DLLA control register */ + /* Delay is 90 degrees */ + if (rev == CPU_242X_ES1) + dllctrl = (BIT0|BIT3); + else + dllctrl = BIT0; + + if (rev == CPU_2420_2422_ES1) { + /* Enable DLL, Load counter with 115 (middle of range) */ + __raw_writel(0x00007306, SDRC_DLLA_CTRL); + __raw_writel(0x00007302, SDRC_DLLA_CTRL); + /* Enable DLL, Load counter with 128 (middle of range) */ + __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */ + __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */ + } + else { + /* Enable DLL, Load counter with 115 (middle of range) */ + __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x + __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x + __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ? + __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x + } +} + +#endif // CFG_SDRAM_COMBO + +#ifdef CFG_SDRAM_SDR +void +config_sdram_sdr(u32 rev) +{ + u32 dllctrl=0; + + /* ball D11, mode 0 */ + __raw_writeb(0x00, 0x48000032); + + __raw_writel(0x00000012, SDRC_SYSCONFIG); + delay(200000); + __raw_writel(0x00000010, SDRC_SYSCONFIG); + + /* Chip-level shared interface management */ + /* SDRCTriState: no Tris */ + /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ + /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */ + if (rev == CPU_2420_2422_ES1) + __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING); + else + __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); + + /* CS0 SDRC Memory Configuration, */ + /* DDR-SDRAM, External SDRAM is x32bit, */ + /* Configure to MUX14: 32Mbx32 */ + __raw_writel(H4_2420_SDRC_MDCFG_0_SDR, SDRC_MCFG_0); /* diff from combo case */ + __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); + __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); + __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); + + /* Manual Command sequence */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + + /* CS0 SDRC Mode Register */ + /* Burst length = 2 - SDR memory */ + /* Serial mode */ + /* CAS latency = 3 */ + __raw_writel(H4_2420_SDRC_MR_0_SDR, SDRC_MR_0); /* diff from combo case */ + + /* SDRC DLLA control register */ + /* Enable DLL, Load counter with 115 (middle of range) */ + /* Delay is 90 degrees */ + + if (rev == CPU_242X_ES1) + dllctrl = (BIT0|BIT3); + else + dllctrl = BIT0; + + if (rev == CPU_2420_2422_ES1) { + __raw_writel(0x00007306, SDRC_DLLA_CTRL); + __raw_writel(0x00007302, SDRC_DLLA_CTRL); + /* Enable DLL, Load counter with 128 (middle of range) */ + __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */ + __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */ + } + else { + __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x + __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x + /* Enable DLL, Load counter with 128 (middle of range) */ + __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x + __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x + } + +} +#endif // CFG_SDRAM_SDR + +#ifdef CFG_SDRAM_STACKED +void +config_sdram_stacked(u32 rev) +{ + + /* Pin Muxing for SDRC */ + __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */ + __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */ + __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */ + __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */ + + /* configure sdrc 32 bit for COMBO ddr sdram */ + __raw_writel(0x00000010, SDRC_SYSCONFIG); /* no idle ack and RESET enable */ + delay(200000); + __raw_writel(0x00000010, SDRC_SYSCONFIG); /* smart idle mode */ + + /* SDRC_SHARING */ + /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */ + //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); + + __raw_writel(0x00004900, SDRC_SHARING); + + /* SDRC_CS0 Configuration */ + /* None for ES2.1 */ + + /* SDRC_CS1 Configuration */ + __raw_writel(0x00000000, SDRC_CS_CFG); /* Remap CS1 to 0x80000000 */ + + /* Disable power down of CKE */ + __raw_writel(0x00000085, SDRC_POWER); + + __raw_writel(0x01A02019, SDRC_MCFG_1); /* SDRC_MCFG1 */ + __raw_writel(0x0003DD03, SDRC_RFR_CTRL1); /* SDRC_RFR_CTRL1 */ + __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1); /* SDRC_ACTIM_CTRLA0 */ + __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1); /* SDRC_ACTIM_CTRLB0 */ + + /*Manual Command sequence */ + __raw_writel(CMD_NOP, SDRC_MANUAL_1); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); + + /* CS0 SDRC Mode Register */ + /* Burst length = 4 - DDR memory */ + /* Serial mode */ + /* CAS latency = 3 */ + __raw_writel(0x00000032, SDRC_MR_1); + __raw_writel(0x00000020, SDRC_EMR2_1); /* weak-strength driver */ + + /* SDRC DLLA control register */ + /* Delay is 90 degrees */ + if (rev == CPU_2420_2422_ES1) { + /* Enable DLL, Load counter with 115 (middle of range) */ + __raw_writel(0x00007302, SDRC_DLLA_CTRL); + /* Enable DLL, Load counter with 128 (middle of range) */ + __raw_writel(0x00007302, SDRC_DLLB_CTRL); + } + else { + /* Enable DLL, Load counter with 115 (middle of range) */ + __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x + /* Enable DLL, Load counter with 128 (middle of range) */ + __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x + } +} +#endif // CFG_SDRAM_STACKED + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called at time when only stack is available. + **********************************************************/ +int s_init(int skip) +{ + u32 rev; + + rev = get_cpu_rev(); + + watchdog_init(); + muxSetupUART1(); + delay(100); + + /*DPLL out = 2x DPLL --> core clock */ + __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); + + /*DPLL into low power bypass (others off) */ + __raw_writel(0x00000001, CM_CLKEN_PLL); + + /*MPU core clock = Core /2 = 300 */ + __raw_writel(MPU_DIV, CM_CLKSEL_MPU); + + /*DSPif=200, DSPif=100, IVA=200 */ + __raw_writel(DSP_DIV, CM_CLKSEL_DSP); + + /*GFX clock (L3/2) 50MHz */ + __raw_writel(GFX_DIV, CM_CLKSEL_GFX); + + /*L3=100, L4=100, DisplaySS=50 Vlync=96Mhz,ssi=100, usb=50 */ + __raw_writel(BUS_DIV, CM_CLKSEL1_CORE); + + /*12MHz apll src, 12/(1+1)*50=300 */ + __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); + + /*Valid the configuration */ + __raw_writel(0x00000001, PRCM_CLKCFG_CTRL); + delay(1000); + + /*Enable DPLL=300, 96MHz APLL locked. */ + __raw_writel(0x0000000F, CM_CLKEN_PLL); + delay(200000); + +#ifdef CFG_SDRAM_DDR + config_sdram_ddr(rev); +#elif defined(CFG_SDRAM_COMBO) + config_sdram_combo(rev); +#elif defined(CFG_SDRAM_SDR) + config_sdram_sdr(rev); +#elif defined(CFG_SDRAM_STACKED) + config_sdram_stacked(rev); +#else +#error SDRAM type not supported +#endif + + delay(20000); + peripheral_enable(); + return(0); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r (void) +{ + return(0); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +static void watchdog_init(void) +{ +#define GP (BIT8|BIT9) + + /* There are 4 watch dogs. 1 secure, and 3 general purpose. + * I would expect that the ROM takes care of the secure one, + * but we will try also. Of the 3 GP ones, 1 can reset us + * directly, the other 2 only generate MPU interrupts. + */ + __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR); + +#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/ + __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR); + wait_for_command_complete(WD3_BASE); + __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR); + + __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR); + wait_for_command_complete(WD4_BASE); + __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR); +#endif + +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +static void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base+WWPS); + } while (pending); +} + + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init (void) +{ + return 0; +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +static void peripheral_enable(void) +{ + unsigned int v, if_clks=0, func_clks=0; + + /* Enable GP2 timer.*/ + if_clks |= BIT4; + func_clks |= BIT4; + v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */ + __raw_writel(v, CM_CLKSEL2_CORE); + __raw_writel(0x1, CM_CLKSEL_WKUP); + +#ifdef CFG_NS16550 + /* Enable UART1 clock */ + func_clks |= BIT21; + if_clks |= BIT21; +#endif + v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ + __raw_writel(v,CM_ICLKEN1_CORE ); + v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ + __raw_writel(v, CM_FCLKEN1_CORE); + delay(1000); + +#ifndef KERNEL_UPDATED + { +#define V1 0xffffffff +#define V2 0x00000007 + + __raw_writel(V1, CM_FCLKEN1_CORE); + __raw_writel(V2, CM_FCLKEN2_CORE); + __raw_writel(V1, CM_ICLKEN1_CORE); + __raw_writel(V1, CM_ICLKEN2_CORE); + } +#endif + +} + +/* Pin Muxing registers used for UART1 */ +#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5) +#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6) +#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7) +#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8) +/**************************************** + * Routine: muxSetupUART1 (ostboot) + * Description: Set up uart1 muxing + *****************************************/ +static void muxSetupUART1(void) +{ + volatile unsigned char *MuxConfigReg; + + /* UART1_CTS pin configuration, PIN = D21 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* UART1_RTS pin configuration, PIN = H21 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* UART1_TX pin configuration, PIN = L20 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ + + /* UART1_RX pin configuration, PIN = T21 */ + MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX; + *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ +} + +int nand_init(void) +{ + u32 rev; + + rev = get_cpu_rev(); + + + /* GPMC pin muxing */ + (*(volatile int*)0x48000070) &= 0x000000FF; + (*(volatile int*)0x48000074) &= 0x00000000; + (*(volatile int*)0x48000078) &= 0x00000000; + (*(volatile int*)0x4800007C) &= 0x00000000; + (*(volatile int*)0x48000080) &= 0xFF000000; + + /* GPMC_IO_DIR */ + (*(volatile int*)0x4800008C) = 0x19000000; + + /* GPMC Configuration */ + (*(volatile int*)0x6800A010) = 0x0000000A; + while (((*(volatile int *)0x6800A014) & 0x00000001) == 0); + + (*(volatile int*)0x6800A050) = 0x00000001; + (*(volatile int*)0x6800A060) = 0x00001800; + (*(volatile int*)0x6800A064) = 0x00141400; + (*(volatile int*)0x6800A068) = 0x00141400; + (*(volatile int*)0x6800A06C) = 0x0F010F01; + (*(volatile int*)0x6800A070) = 0x010C1414; + (*(volatile int*)0x6800A074) = 0x00000A80; + (*(volatile int*)0x6800A078) = 0x00000C44; //base 0x04000000 + + (*(volatile int*)0x6800A0A8) = 0x00000000; + delay(1000); +#ifdef CFG_SDRAM_STACKED + (*(volatile int*)0x6800A090) = 0x00011000; +#else + (*(volatile int*)0x6800A090) = 0x00011200; +#endif + (*(volatile int*)0x6800A094) = 0x001f1f00; + (*(volatile int*)0x6800A098) = 0x00080802; + (*(volatile int*)0x6800A09C) = 0x1C091C09; + (*(volatile int*)0x6800A0A0) = 0x031A1F1F; + (*(volatile int*)0x6800A0A4) = 0x000003C2; + (*(volatile int*)0x6800A0A8) = 0x00000F48; + + if (rev != CPU_2420_2422_ES1) + (*(volatile int*)0x6800A040) = 0x1FF0; // es2.x + + if (nand_chip()){ + printf("Unsupported Chip!\n"); + return 1; + } + return 0; +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 v; + v = __raw_readl(TAP_IDCODE_REG); + v = v >> 28; + return(v+1); /* currently 2422 and 2420 match up */ +} + +/* optionally do something like blinking LED */ +void board_hang (void) +{} + + + diff --git a/board/omap2420h4/platform.S b/board/omap2420h4/platform.S new file mode 100644 index 0000000..5cc37e5 --- /dev/null +++ b/board/omap2420h4/platform.S @@ -0,0 +1,218 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#ifdef CONFIG_PARTIAL_SRAM + +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = PRCM_CLKCFG_CTRL - addr of valid reg + * R1 = CM_CLKEN_PLL - addr dpll ctlr reg + * R2 = dpll value + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + ******************************************************************************/ +.global go_to_speed + go_to_speed: + sub sp, sp, #0x4 /* get some stack space */ + str r4, [sp] /* save r4's value */ + + /* move into fast relock bypass */ + ldr r8, pll_ctl_add + mov r4, #0x2 + str r4, [r8] + ldr r4, pll_stat +block: + ldr r8, [r4] /* wait for bypass to take effect */ + and r8, r8, #0x3 + cmp r8, #0x1 + bne block + + /* set new dpll dividers _after_ in bypass */ + ldr r4, pll_div_add + ldr r8, pll_div_val + str r8, [r4] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r4, cfg3_0_addr + ldr r8, cfg3_0_val + str r8, [r4] + ldr r4, cfg4_0_addr + ldr r8, cfg4_0_val + str r8, [r4] + ldr r4, cfg1_0_addr + ldr r8, [r4] + orr r8, r8, #0x3 /* up gpmc divider */ + str r8, [r4] + + /* setup to 2x loop though code. The first loop pre-loads the + * icache, the 2nd commits the prcm config, and locks the dpll + */ + mov r4, #0x1000 /* spin spin spin */ + mov r8, #0x4 /* first pass condition & set registers */ + cmp r8, #0x4 +2: + ldrne r8, [r3] /* DPLL lock check */ + and r8, r8, #0x7 + cmp r8, #0x2 + beq 4f +3: + subeq r8, r8, #0x1 + streq r8, [r0] /* commit dividers (2nd time) */ + nop +lloop1: + sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ + nop + cmp r4, #0x0 + bne lloop1 + mov r4, #0x40000 + cmp r8, #0x1 + nop + streq r2, [r1] /* lock dpll (2nd time) */ + nop +lloop2: + sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ + nop + cmp r4, #0x0 + bne lloop2 + mov r4, #0x40000 + cmp r8, #0x1 + nop + ldreq r8, [r3] /* get lock condition for dpll */ + cmp r8, #0x4 /* first time though? */ + bne 2b + moveq r8, #0x2 /* set to dpll check condition. */ + beq 3b /* if condition not true branch */ +4: + ldr r4, [sp] + add sp, sp, #0x4 /* return stack space */ + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +cfg3_0_addr: + .word GPMC_CONFIG3_0 +cfg3_0_val: + .word SMNAND_GPMC_CONFIG3 +cfg4_0_addr: + .word GPMC_CONFIG4_0 +cfg4_0_val: + .word SMNAND_GPMC_CONFIG4 +cfg1_0_addr: + .word GPMC_CONFIG1_0 +pll_ctl_add: + .word CM_CLKEN_PLL +pll_stat: + .word CM_IDLEST_CKGEN +pll_div_add: + .word CM_CLKSEL1_PLL +pll_div_val: + .word DPLL_VAL /* DPLL setting (300MHz default) */ +#endif + +.globl platformsetup +platformsetup: + mov r3, r0 /* save skip information */ +#ifdef CONFIG_APTIX + ldr r0, REG_SDRC_MCFG_0 + ldr r1, VAL_SDRC_MCFG_0 + str r1, [r0] + ldr r0, REG_SDRC_MR_0 + ldr r1, VAL_SDRC_MR_0 + str r1, [r0] + /* a ddr needs emr1 set here */ + ldr r0, REG_SDRC_SHARING + ldr r1, VAL_SDRC_SHARING + str r1, [r0] + ldr r0, REG_SDRC_RFR_CTRL_0 + ldr r1, VAL_SDRC_RFR_CTRL_0 + str r1, [r0] + + /* little delay after init */ + mov r2, #0x1800 +1: + subs r2, r2, #0x1 + bne 1b +#endif +#ifdef CONFIG_PARTIAL_SRAM + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + mov r0, r3 /* pass skip info to s_init */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ +#endif + + /* map interrupt controller */ + ldr r0, VAL_INTH_SETUP + mcr p15, 0, r0, c15, c2, 4 + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +VAL_INTH_SETUP: + .word PERIFERAL_PORT_BASE +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + + + + + + diff --git a/board/omap2420h4/x-load.lds b/board/omap2420h4/x-load.lds new file mode 100644 index 0000000..f664ca7 --- /dev/null +++ b/board/omap2420h4/x-load.lds @@ -0,0 +1,54 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap2430sdp/Makefile b/board/omap2430sdp/Makefile new file mode 100644 index 0000000..b6c984c --- /dev/null +++ b/board/omap2430sdp/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := omap2430sdp.o +SOBJS := platform.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/omap2430sdp/config.mk b/board/omap2430sdp/config.mk new file mode 100644 index 0000000..7bc5078 --- /dev/null +++ b/board/omap2430sdp/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2004 +# Texas Instruments, +# +# TI H4 board with OMAP2420 (ARM1136) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 +# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) ES2 will be configurable +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# 2430 h4 has same mem configuration as h4. + +# For use with external or internal boots. +# CONFIG_PARTIAL_SRAM must be defined to use this. +TEXT_BASE = 0x80e80000 + +# Used with full SRAM boot. +# This is either with a GP system or a signed boot image. +# easiest, and safest way to go if you can. +# Comment out //CONFIG_PARTIAL_SRAM for this one. +# +#TEXT_BASE = 0x40280000 + diff --git a/board/omap2430sdp/omap2430sdp.c b/board/omap2430sdp/omap2430sdp.c new file mode 100644 index 0000000..f2a7b42 --- /dev/null +++ b/board/omap2430sdp/omap2430sdp.c @@ -0,0 +1,746 @@ +/* + * (C) Copyright 2004-2005 + * Texas Instruments, + * Jian Zhang + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +static void wait_for_command_complete(unsigned int wd_base); +static void watchdog_init(void); +static void peripheral_enable(void); +static void muxSetupAll(void); +static u32 get_cpu_rev(void); +static u32 get_device_type(void); +static void prcm_init(void); + + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init (void) +{ + return 0; +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 v; + v = __raw_readl(TAP_IDCODE_REG); + v = v >> 28; + return(v+1); /* currently 2422 and 2420 match up */ +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return(mode >>= 8); +} + +/************************************************************* + * Helper function to wait for the status of a register + *************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return(1); + if (i==bound) + return(0); + } while (1); +} + +/************************************************************* + * Support for multiple type of memory types + *************************************************************/ +#ifdef CFG_SDRAM_DDR +void +config_sdram_ddr(u32 rev) +{ + /* ball D11, mode 0 */ + __raw_writeb(0x08, 0x48000032); + + /* SDRC_CS0 Configuration */ + __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); + __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); + + __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); + __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0); + __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0); + + /* Manual Command sequence */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + + + /* + * CS0 SDRC Mode Register + * Burst length = 4 - DDR memory + * Serial mode + * CAS latency = 3 + */ + __raw_writel(0x00000032, SDRC_MR_0); + + /* SDRC DLLA control register */ + /* Delay is 90 degrees */ + /* Enable DLL, Load counter with 115 (middle of range) */ + __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x + /* Enable DLL, Load counter with 128 (middle of range) */ + __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x + +} +#endif // CFG_SDRAM_DDR + +#ifdef CFG_SDRAM_COMBO +void +config_sdram_combo(u32 rev) +{ + + u32 dllctrl=0; + + /* ball C12, mode 0 */ + __raw_writeb(0x00, 0x480000a1); + /* ball D11, mode 0 */ + __raw_writeb(0x00, 0x48000032); + /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */ + __raw_writeb(0x00, 0x480000a3); + + /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */ + __raw_writel(0x00000012, SDRC_SYSCONFIG); + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */ + __raw_writel(0x00000000, SDRC_SYSCONFIG); + + /* SDRCTriState: no Tris */ + /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ + if (rev == CPU_2420_2422_ES1) + __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING); + else + __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); + + + /* CS0 SDRC Memory Configuration, */ + /* DDR-SDRAM, External SDRAM is x32bit, */ + /* Configure to MUX9: 1x8Mbx32 */ + __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0); + __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); + __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); + + /* This is reqd only for ES1 */ + if (rev == CPU_242X_ES1) + __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); + + /* Manual Command sequence */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0); + delay(5000); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + + /* CS0 SDRC Mode Register */ + /* Burst length = 4 - DDR memory */ + /* Serial mode */ + /* CAS latency = 3 */ + __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0); + + /* CS1 SDRC Memory Configuration, */ + /* DDR-SDRAM, External SDRAM is x32bit, */ + /* Configure to MUX9: 1x8Mbx32 */ + __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1); + __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1); + __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1); + /* This is reqd only for ES1 */ + if (rev == CPU_242X_ES1) + __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4); + + /* Manual Command sequence */ + __raw_writel(CMD_NOP, 0x680090d8); + __raw_writel(CMD_PRECHARGE, 0x680090d8); + __raw_writel(CMD_AUTOREFRESH, 0x680090d8); + __raw_writel(CMD_AUTOREFRESH, 0x680090d8); + + /* CS1 SDRC Mode Register */ + /* Burst length = 4 - DDR memory */ + /* Serial mode */ + /* CAS latency = 3 */ + __raw_writel(H4_2422_SDRC_MR_0_DDR, 0x680090b4); + + /* SDRC DLLA control register */ + /* Delay is 90 degrees */ + + if (rev == CPU_242X_ES1) + dllctrl = (BIT0|BIT3); + else + dllctrl = BIT0; + + if (rev == CPU_2420_2422_ES1) { + /* Enable DLL, Load counter with 115 (middle of range) */ + __raw_writel(0x00007306, SDRC_DLLA_CTRL); + __raw_writel(0x00007302, SDRC_DLLA_CTRL); + /* Enable DLL, Load counter with 128 (middle of range) */ + __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */ + __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */ + } + else { + /* Enable DLL, Load counter with 115 (middle of range) */ + __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x + __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x + // __raw_writel(0x00009808, SDRC_DLLA_CTRL); // ES2.x + /* Enable DLL, Load counter with 128 (middle of range) */ + __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ? + __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x + //__raw_writel(0x00009808, SDRC_DLLB_CTRL); // ES2.x + } +} + +#endif // CFG_SDRAM_COMBO + +#ifdef CFG_2430SDRAM_DDR +void +config_2430sdram_ddr(u32 rev) +{ + u32 dllstat, dllctrl; + + __raw_writel(0x00000012, SDRC_SYSCONFIG); + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */ + __raw_writel(0x00000000, SDRC_SYSCONFIG); + + /* Chip-level shared interface management */ + /* SDRCTriState: no Tris */ + /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ + /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */ + __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); + + /* CS0 SDRC Memory Configuration, */ + /* DDR-SDRAM, External SDRAM is x32bit, */ + /* Configure to MUX14: 32Mbx32 */ + __raw_writel(SDP_2430_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); + __raw_writel(SDP_2430_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); + __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); + + __raw_writel(H4_2420_SDRC_RFR_CTRL, SDRC_RFR_CTRL); + + /* Manual Command sequence */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0); + delay(5000); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + + /* CS0 SDRC Mode Register */ + /* Burst length = 2 - SDR memory */ + /* Serial mode */ + /* CAS latency = 3 */ + __raw_writel(H4_2420_SDRC_MR_0_DDR, SDRC_MR_0); + + /* Set up SDRC DLL values for 2430 DDR */ + dllctrl = (SDP_2430_SDRC_DLLAB_CTRL & ~BIT2); /* set target ctrl val */ + __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set lock mode */ + __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set lock mode */ + delay(0x1000); /* time to track to center */ + dllstat = __raw_readl(SDRC_DLLA_STATUS) & 0xFF00; /* get status */ + dllctrl = (dllctrl & 0x00FF) | dllstat | BIT2; /* build unlock value */ + __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set unlock mode */ + __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set unlock mode */ +} +#endif // CFG_2430SDRAM_DDR + +#ifdef CFG_SDRAM_STACKED +void +config_sdram_stacked(u32 rev) +{ + + /* Pin Muxing for SDRC */ + __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */ + __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */ + __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */ + __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */ + + /* configure sdrc 32 bit for COMBO ddr sdram */ + __raw_writel(0x00000010, SDRC_SYSCONFIG); /* no idle ack and RESET enable */ + delay(200000); + __raw_writel(0x00000010, SDRC_SYSCONFIG); /* smart idle mode */ + + /* SDRC_SHARING */ + /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */ + //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); + + __raw_writel(0x00004900, SDRC_SHARING); + + /* SDRC_CS0 Configuration */ + /* None for ES2.1 */ + + /* SDRC_CS1 Configuration */ + __raw_writel(0x00000000, SDRC_CS_CFG); /* Remap CS1 to 0x80000000 */ + + /* Disable power down of CKE */ + __raw_writel(0x00000085, SDRC_POWER); + + __raw_writel(0x01A02019, SDRC_MCFG_1); /* SDRC_MCFG1 */ + __raw_writel(0x0003DD03, SDRC_RFR_CTRL1); /* SDRC_RFR_CTRL1 */ + __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1); /* SDRC_ACTIM_CTRLA0 */ + __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1); /* SDRC_ACTIM_CTRLB0 */ + + /*Manual Command sequence */ + __raw_writel(0x00000000, 0x680090D8); + __raw_writel(0x00000001, 0x680090D8); + __raw_writel(0x00000002, 0x680090D8); + __raw_writel(0x00000002, 0x680090D8); + + /* CS0 SDRC Mode Register */ + /* Burst length = 4 - DDR memory */ + /* Serial mode */ + /* CAS latency = 3 */ + __raw_writel(0x00000032, 0x680090B4); + __raw_writel(0x00000020, 0x680090BC); /* weak-strength driver */ + + /* SDRC DLLA control register */ + /* Delay is 90 degrees */ + if (rev == CPU_2420_2422_ES1) { + /* Enable DLL, Load counter with 115 (middle of range) */ + __raw_writel(0x00007302, SDRC_DLLA_CTRL); + /* Enable DLL, Load counter with 128 (middle of range) */ + __raw_writel(0x00007302, SDRC_DLLB_CTRL); + } + else { + /* Enable DLL, Load counter with 115 (middle of range) */ + __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x + /* Enable DLL, Load counter with 128 (middle of range) */ + __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x + } +} +#endif // CFG_SDRAM_STACKED + +/************************************************************* + * get_sys_clk_speed - determine reference oscillator speed + * based on known 32kHz clock and gptimer. + *************************************************************/ +u32 get_osc_clk_speed(u32 *shift) +{ +#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ +#define GPT_CTR OMAP24XX_GPT2+TCRR /* read counter address */ + u32 start, cstart, cend, cdiff, val; + unsigned int v, if_clks=0, func_clks=0 ; + + + + if(__raw_readl(PRCM_CLKSRC_CTRL) & BIT7){ /* if currently /2 */ + *shift = 1; + }else{ + *shift = 0; + } + + /* enable timer2 */ + val = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* mask for sys_clk use */ + __raw_writel(val, CM_CLKSEL2_CORE); /* timer2 source to sys_clk */ + __raw_writel(BIT4, CM_ICLKEN1_CORE); /* timer2 interface clock on */ + __raw_writel(BIT4, CM_FCLKEN1_CORE); /* timer2 function clock on */ + /* Enable GP2 timer.*/ + if_clks |= BIT4; + func_clks |= BIT4; + v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ + __raw_writel(v,CM_ICLKEN1_CORE ); + v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ + __raw_writel(v, CM_FCLKEN1_CORE); + __raw_writel(0, OMAP24XX_GPT2+TLDR); /* start counting at 0 */ + __raw_writel(GPT_EN, OMAP24XX_GPT2+TCLR); /* enable clock */ + /* enable 32kHz source */ /* enabled out of reset */ + /* determine sys_clk via gauging */ + start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles*/ + while(__raw_readl(S32K_CR) < start); /* dead loop till start time */ + cstart = __raw_readl(GPT_CTR); /* get start sys_clk count */ + while(__raw_readl(S32K_CR) < (start+20)); /* wait for 40 cycles */ + cend = __raw_readl(GPT_CTR); /* get end sys_clk count */ + cdiff = cend - cstart; /* get elapsed ticks */ + /* based on number of ticks assign speed */ + if(cdiff > (19000 >> *shift)) + return(S38_4M); + else if (cdiff > (15200 >> *shift)) + return(S26M); + else if (cdiff > (13000 >> *shift)) + return(S24M); + else if (cdiff > (9000 >> *shift)) + return(S19_2M); + else if (cdiff > (7600 >> *shift)) + return(S13M); + else + return(S12M); +} + +/********************************************************************************* + * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default). + * -- called from SRAM + *********************************************************************************/ +void +prcm_init() +{ + u32 div, speed, val, div_by_2; + + val = __raw_readl(PRCM_CLKSRC_CTRL) & ~(BIT1 | BIT0); +#if defined(OMAP2430_SQUARE_CLOCK_INPUT) + __raw_writel(val, PRCM_CLKSRC_CTRL); +#else + __raw_writel((val | BIT0), PRCM_CLKSRC_CTRL); +#endif + speed = get_osc_clk_speed(&div_by_2); + if((speed > S19_2M) && (!div_by_2)){ /* if fast && /2 off, enable it */ + val = ~(BIT6|BIT7) & __raw_readl(PRCM_CLKSRC_CTRL); + val |= (0x2 << 6); /* divide by 2 if (24,26,38.4) -> (12/13/19.2) */ + __raw_writel(val, PRCM_CLKSRC_CTRL); + } + + __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */ + __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */ + __raw_writel(0, CM_ICLKEN1_CORE); + __raw_writel(0, CM_ICLKEN2_CORE); + + /*DPLL into low power bypass (others off) */ + __raw_writel(0x00000001, CM_CLKEN_PLL); + + __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */ + __raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */ + __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */ + __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */ + __raw_writel(MDM_DIV, CM_CLKSEL_MDM); /* set mdm dividers */ + + div = BUS_DIV; + __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/SSi dividers */ + delay(1000); + + /*13MHz apll src, PRCM 'x' DPLL rate */ + __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); + + /*Valid the configuration */ + __raw_writel(0x00000001, PRCM_CLKCFG_CTRL); + delay(1000); + + /* set up APLLS_CLKIN per crystal */ + if (speed > S19_2M) + speed >>= 1; /* if fast shift to /2 range */ + val = (0x2 << 23); /* default to 13Mhz for 2430c */ + if (speed == S12M) + val = (0x3 << 23); + else if (speed == S19_2M) + val = (0x0 << 23); + val |= (~(BIT23|BIT24|BIT25) & __raw_readl(CM_CLKSEL1_PLL)); + __raw_writel(val, CM_CLKSEL1_PLL); + + __raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */ + wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);/* wait for apll lock */ + + delay(200000); +} + +void SEC_generic(void) +{ +/* Permission values for registers -Full fledged permissions to all */ +#define UNLOCK_1 0xFFFFFFFF +#define UNLOCK_2 0x00000000 +#define UNLOCK_3 0x0000FFFF + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x68); /* REQ_INFO_PERMISSION_1 L*/ + __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ + __raw_writel(UNLOCK_2, PM_RT_APE_BASE_ADDR_ARM + 0x60); /* ADDR_MATCH_1 L*/ + + + __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ + + __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ + __raw_writel(UNLOCK_2, PM_OCM_RAM_BASE_ADDR_ARM + 0x80); /* ADDR_MATCH_2 L*/ + + /* IVA Changes */ + __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP type, unlock the SRAM for general use. + ***********************************************************/ +void try_unlock_sram(void) +{ + int mode; + + /* if GP device unlock device SRAM for general use */ + mode = get_device_type(); + + if ((mode == GP_DEVICE) || (mode == HS_DEVICE) || (mode == EMU_DEVICE) + || (mode == TST_DEVICE)) { + /* Secure or Emulation device - HS/E/T */ + SEC_generic(); + } + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called at time when only stack is available. + **********************************************************/ + +int s_init(int skip) +{ + u32 rev; + + rev = get_cpu_rev(); + + watchdog_init(); + try_unlock_sram(); + muxSetupAll(); + delay(100); + prcm_init(); + +#ifdef CFG_SDRAM_DDR + config_sdram_ddr(rev); +#elif defined(CFG_SDRAM_COMBO) + config_sdram_combo(rev); +#elif defined(CFG_2430SDRAM_DDR) + config_2430sdram_ddr(rev); +#elif defined(CFG_SDRAM_STACKED) + config_sdram_stacked(rev); +#else +#error SDRAM type not supported +#endif + + delay(20000); + peripheral_enable(); + return(0); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r (void) +{ + return(0); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +static void watchdog_init(void) +{ +#define GP (BIT8|BIT9) + + /* There are 4 watch dogs. 1 secure, and 3 general purpose. + * I would expect that the ROM takes care of the secure one, + * but we will try also. Of the 3 GP ones, 1 can reset us + * directly, the other 2 only generate MPU interrupts. + */ + __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR); + +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +static void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base+WWPS); + } while (pending); +} + + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init (void) +{ + return 0; +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +static void peripheral_enable(void) +{ + unsigned int v, if_clks=0, if_clks2 = 0, func_clks=0, func_clks2 = 0; + + /* Enable GP2 timer.*/ + if_clks |= BIT4; + func_clks |= BIT4; + v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP24XX_GPT2 */ + __raw_writel(v, CM_CLKSEL2_CORE); + __raw_writel(0x1, CM_CLKSEL_WKUP); + +#ifdef CFG_NS16550 + /* Enable UART1 clock */ + func_clks |= BIT21; + if_clks |= BIT21; +#endif + v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ + __raw_writel(v,CM_ICLKEN1_CORE ); + v = __raw_readl(CM_ICLKEN2_CORE) | if_clks2; /* Interface clocks on */ + __raw_writel(v, CM_ICLKEN2_CORE); + v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ + __raw_writel(v, CM_FCLKEN1_CORE); + v = __raw_readl(CM_FCLKEN2_CORE) | func_clks2; /* Functional Clocks on */ + __raw_writel(v, CM_FCLKEN2_CORE); + delay(1000); + +} + +/* Do pin muxing for all the devices used in X-Loader */ +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writeb(VALUE, OMAP24XX_CTRL_BASE + OFFSET); +static void muxSetupAll(void) +{ + /* UART 1*/ + MUX_VAL(0x00B1, 0x1B) /* uart1_cts- EN, HI, 3, ->gpio_32 */ + MUX_VAL(0x00B2, 0x1B) /* uart1_rts- EN, HI, 3, ->gpio_8 */ + MUX_VAL(0x00B3, 0x1B) /* uart1_tx- EN, HI, 3, ->gpio_9 */ + MUX_VAL(0x00B4, 0x1B) /* uart1_rx- EN, HI, 3, ->gpio_10 */ + MUX_VAL(0x0107, 0x01) /* ssi1_dat_tx- Dis, 1, ->uart1_tx */ + MUX_VAL(0x0108, 0x01) /* ssi1_flag_tx- Dis, 1, ->uart1_rts */ + MUX_VAL(0x0109, 0x01) /* ssi1_rdy_tx- Dis, 1, ->uart1_cts */ + MUX_VAL(0x010A, 0x01) /* ssi1_dat_rx- Dis, 1, ->uart1_rx */ + + /* Mux settings for SDRC */ + MUX_VAL(0x0054, 0x1B) /* sdrc_a14 - EN, HI, 3, ->gpio_0 */ + MUX_VAL(0x0055, 0x1B) /* sdrc_a13 - EN, HI, 3, ->gpio_1 */ + MUX_VAL(0x0056, 0x00) /* sdrc_a12 - Dis, 0 */ + MUX_VAL(0x0046, 0x00) /* sdrc_ncs1 - Dis, 0 */ + MUX_VAL(0x0048, 0x00) /* sdrc_cke1 - Dis, 0 */ + /* GPMC */ + MUX_VAL(0x0030, 0x00) /* gpmc_clk - Dis, 0 */ + MUX_VAL(0x0032, 0x00) /* gpmc_ncs1- Dis, 0 */ + MUX_VAL(0x0033, 0x00) /* gpmc_ncs2- Dis, 0 */ + MUX_VAL(0x0034, 0x03) /* gpmc_ncs3- Dis, 3, ->gpio_24 */ + MUX_VAL(0x0035, 0x03) /* gpmc_ncs4- Dis, 3, ->gpio_25 */ + MUX_VAL(0x0036, 0x00) /* gpmc_ncs5- Dis, 0 */ + MUX_VAL(0x0037, 0x03) /* gpmc_ncs6- Dis, 3, ->gpio_27 */ + MUX_VAL(0x0038, 0x00) /* gpmc_ncs7- Dis, 0 */ + MUX_VAL(0x0040, 0x18) /* gpmc_wait1- Dis, 0 */ + MUX_VAL(0x0041, 0x18) /* gpmc_wait2- Dis, 0 */ + MUX_VAL(0x0042, 0x1B) /* gpmc_wait3- EN, HI, 3, ->gpio_35 */ + MUX_VAL(0x0085, 0x1B) /* gpmc_a10- EN, HI, 3, ->gpio_3 */ +} + +int nand_init(void) +{ + u32 rev; + + /* GPMC Configuration */ + rev = get_cpu_rev(); + + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ +#ifdef CFG_NAND + __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ +#endif + + /* Set the GPMC Vals . For NAND boot on 2430SDP, NAND is mapped at CS0 + * , NOR at CS1 and MPDB at CS5. And oneNAND boot, we map oneNAND at CS0. + * We configure only GPMC CS0 with required values. Configiring other devices + * at other CS in done in u-boot anyway. So we don't have to bother doing it here. + */ + __raw_writel(0, GPMC_CONFIG7_0); + sdelay(1000); + +#ifdef CFG_NAND + __raw_writel( SMNAND_GPMC_CONFIG1, GPMC_CONFIG1_0); + __raw_writel( SMNAND_GPMC_CONFIG2, GPMC_CONFIG2_0); + __raw_writel( SMNAND_GPMC_CONFIG3, GPMC_CONFIG3_0); + __raw_writel( SMNAND_GPMC_CONFIG4, GPMC_CONFIG4_0); + __raw_writel( SMNAND_GPMC_CONFIG5, GPMC_CONFIG5_0); + __raw_writel( SMNAND_GPMC_CONFIG6, GPMC_CONFIG6_0); + +#else /* CFG_ONENAND */ + __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1_0); + __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2_0); + __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3_0); + __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4_0); + __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5_0); + __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6_0); +#endif + + /* Enable the GPMC Mapping */ + __raw_writel(( ((OMAP24XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((OMAP24XX_GPMC_CS0_MAP>>24) & 0x3F) | + (1<<6) ), GPMC_CONFIG7_0); + sdelay(2000); +#ifdef CFG_NAND + if (nand_chip()){ +#ifdef CFG_PRINTF + printf("Unsupported Chip!\n"); +#endif + return 1; + } +#else + if (onenand_chip()){ +#ifdef CFG_PRINTF + printf("OneNAND Unsupported !\n"); +#endif + return 1; + } + +#endif + return 0; +} + +/* optionally do something like blinking LED */ +void board_hang (void) +{ while (0) {};} diff --git a/board/omap2430sdp/platform.S b/board/omap2430sdp/platform.S new file mode 100644 index 0000000..f221d7e --- /dev/null +++ b/board/omap2430sdp/platform.S @@ -0,0 +1,198 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2005 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = PRCM_CLKCFG_CTRL - addr of valid reg + * R1 = CM_CLKEN_PLL - addr dpll ctlr reg + * R2 = dpll value + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + ******************************************************************************/ +.global go_to_speed + go_to_speed: + sub sp, sp, #0x4 /* get some stack space */ + str r4, [sp] /* save r4's value */ + + /* move into fast relock bypass */ + ldr r8, pll_ctl_add + mov r4, #0x2 + str r4, [r8] + ldr r4, pll_stat +block: + ldr r8, [r4] /* wait for bypass to take effect */ + and r8, r8, #0x3 + cmp r8, #0x1 + bne block + + /* set new dpll dividers _after_ in bypass */ + ldr r4, pll_div_add + ldr r8, pll_div_val + str r8, [r4] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r4, flash_cfg3_addr + ldr r8, flash_cfg3_val + str r8, [r4] + ldr r4, flash_cfg4_addr + ldr r8, flash_cfg4_val + str r8, [r4] + ldr r4, flash_cfg1_addr + ldr r8, [r4] + orr r8, r8, #0x3 /* up gpmc divider */ + str r8, [r4] + + /* setup to 2x loop though code. The first loop pre-loads the + * icache, the 2nd commits the prcm config, and locks the dpll + */ + mov r4, #0x1000 /* spin spin spin */ + mov r8, #0x4 /* first pass condition & set registers */ + cmp r8, #0x4 +2: + ldrne r8, [r3] /* DPLL lock check */ + and r8, r8, #0x7 + cmp r8, #0x2 + beq 4f +3: + subeq r8, r8, #0x1 + streq r8, [r0] /* commit dividers (2nd time) */ + nop +lloop1: + sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ + nop + cmp r4, #0x0 + bne lloop1 + mov r4, #0x40000 + cmp r8, #0x1 + nop + streq r2, [r1] /* lock dpll (2nd time) */ + nop +lloop2: + sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ + nop + cmp r4, #0x0 + bne lloop2 + mov r4, #0x40000 + cmp r8, #0x1 + nop + ldreq r8, [r3] /* get lock condition for dpll */ + cmp r8, #0x4 /* first time though? */ + bne 2b + moveq r8, #0x2 /* set to dpll check condition. */ + beq 3b /* if condition not true branch */ +4: + ldr r4, [sp] + add sp, sp, #0x4 /* return stack space */ + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +#ifdef CFG_ONENAND +flash_cfg3_addr: + .word GPMC_CONFIG3_0 +flash_cfg3_val: + .word ONENAND_GPMC_CONFIG3 +flash_cfg4_addr: + .word GPMC_CONFIG4_0 +flash_cfg4_val: + .word ONENAND_GPMC_CONFIG4 +flash_cfg1_addr: + .word GPMC_CONFIG1_0 +#else +flash_cfg3_addr: + .word GPMC_CONFIG3_0 +flash_cfg3_val: + .word SMNAND_GPMC_CONFIG3 +flash_cfg4_addr: + .word GPMC_CONFIG4_0 +flash_cfg4_val: + .word SMNAND_GPMC_CONFIG4 +flash_cfg1_addr: + .word GPMC_CONFIG1_0 +#endif +pll_ctl_add: + .word CM_CLKEN_PLL +pll_stat: + .word CM_IDLEST_CKGEN +pll_div_add: + .word CM_CLKSEL1_PLL +pll_div_val: + .word DPLL_VAL /* DPLL setting (300MHz default) */ + +.globl platformsetup +platformsetup: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* map interrupt controller */ + ldr r0, VAL_INTH_SETUP + mcr p15, 0, r0, c15, c2, 4 + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +VAL_INTH_SETUP: + .word PERIFERAL_PORT_BASE +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + diff --git a/board/omap2430sdp/x-load.lds b/board/omap2430sdp/x-load.lds new file mode 100644 index 0000000..f12e8f8 --- /dev/null +++ b/board/omap2430sdp/x-load.lds @@ -0,0 +1,54 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2005 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap3430labrador/Makefile b/board/omap3430labrador/Makefile new file mode 100644 index 0000000..d54b666 --- /dev/null +++ b/board/omap3430labrador/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := omap3430sdp.o +SOBJS := platform.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/omap3430labrador/config.mk b/board/omap3430labrador/config.mk new file mode 100644 index 0000000..d6ad6c5 --- /dev/null +++ b/board/omap3430labrador/config.mk @@ -0,0 +1,22 @@ +# +# (C) Copyright 2006 +# Texas Instruments, +# +# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# SDP3430 has 1 bank of 32MB or 128MB mDDR-SDRAM on CS0 +# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000'0000 (bank1) - re-mappable below CS1 + +# For use if you want X-Loader to relocate from SRAM to DDR +#TEXT_BASE = 0x80e80000 + +# For XIP in 64K of SRAM or debug (GP device has it all availabe) +# SRAM 40200000-4020FFFF base +# initial stack at 0x4020fffc used in s_init (below xloader). +# The run time stack is (above xloader, 2k below) +# If any globals exist there needs to be room for them also +TEXT_BASE = 0x40208800 diff --git a/board/omap3430labrador/omap3430sdp.c b/board/omap3430labrador/omap3430sdp.c new file mode 100644 index 0000000..89d9ff1 --- /dev/null +++ b/board/omap3430labrador/omap3430sdp.c @@ -0,0 +1,753 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, + * Jian Zhang + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Used to index into DPLL parameter tables */ +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +}; + +typedef struct dpll_param dpll_param; + +#define MAX_SIL_INDEX 3 + +/* Following functions are exported from lowlevel_init.S */ +extern dpll_param * get_mpu_dpll_param(void); +extern dpll_param * get_iva_dpll_param(void); +extern dpll_param * get_core_dpll_param(void); +extern dpll_param * get_per_dpll_param(void); + +#define __raw_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init (void) +{ + return 0; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return(mode >>= 8); +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 cpuid=0; + /* On ES1.0 the IDCODE register is not exposed on L4 + * so using CPU ID to differentiate + * between ES2.0 and ES1.0. + */ + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); + if((cpuid & 0xf) == 0x0) + return CPU_3430_ES1; + else + return CPU_3430_ES2; + +} + +/****************************************** + * cpu_is_3410(void) - returns true for 3410 + ******************************************/ +u32 cpu_is_3410(void) +{ + int status; + if(get_cpu_rev() < CPU_3430_ES2) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = __raw_readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + __raw_writel(tmp, addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return (1); + if (i == bound) + return (0); + } while (1); +} + +#ifdef CFG_3430SDRAM_DDR +/********************************************************************* + * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. + *********************************************************************/ +void config_3430sdram_ddr(void) +{ + /* reset sdrc controller */ + __raw_writel(SOFTRESET, SDRC_SYSCONFIG); + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); + __raw_writel(0, SDRC_SYSCONFIG); + + /* setup sdrc to ball mux */ + __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); + + /* set mdcfg */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); + + /* set timing */ + __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); + __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); + __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL); + + /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0); + delay(5000); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + + /* set mr0 */ + __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); + + /* set up dll */ + __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); + delay(0x2000); /* give time to lock */ + +} +#endif // CFG_3430SDRAM_DDR + +/************************************************************* + * get_sys_clk_speed - determine reference oscillator speed + * based on known 32kHz clock and gptimer. + *************************************************************/ +u32 get_osc_clk_speed(void) +{ + u32 start, cstart, cend, cdiff, val; + + val = __raw_readl(PRM_CLKSRC_CTRL); + /* If SYS_CLK is being divided by 2, remove for now */ + val = (val & (~BIT7)) | BIT6; + __raw_writel(val, PRM_CLKSRC_CTRL); + + /* enable timer2 */ + val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; + __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ + + /* Enable I and F Clocks for GPT1 */ + val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; + __raw_writel(val, CM_ICLKEN_WKUP); + val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; + __raw_writel(val, CM_FCLKEN_WKUP); + + __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ + __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ + /* enable 32kHz source *//* enabled out of reset */ + /* determine sys_clk via gauging */ + + start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ + while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ + cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ + while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ + cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ + cdiff = cend - cstart; /* get elapsed ticks */ + + /* based on number of ticks assign speed */ + if (cdiff > 19000) + return (S38_4M); + else if (cdiff > 15200) + return (S26M); + else if (cdiff > 13000) + return (S24M); + else if (cdiff > 9000) + return (S19_2M); + else if (cdiff > 7600) + return (S13M); + else + return (S12M); +} + +/****************************************************************************** + * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on + * -- input oscillator clock frequency. + * + *****************************************************************************/ +void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) +{ + if(osc_clk == S38_4M) + *sys_clkin_sel= 4; + else if(osc_clk == S26M) + *sys_clkin_sel = 3; + else if(osc_clk == S19_2M) + *sys_clkin_sel = 2; + else if(osc_clk == S13M) + *sys_clkin_sel = 1; + else if(osc_clk == S12M) + *sys_clkin_sel = 0; +} + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * -- called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + u32 osc_clk=0, sys_clkin_sel; + dpll_param *dpll_param_p; + u32 clk_index, sil_index; + + /* Gauge the input clock speed and find out the sys_clkin_sel + * value corresponding to the input clock. + */ + osc_clk = get_osc_clk_speed(); + get_sys_clkin_sel(osc_clk, &sys_clkin_sel); + + sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ + + /* If the input clock is greater than 19.2M always divide/2 */ + if(sys_clkin_sel > 2) { + sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */ + clk_index = sys_clkin_sel/2; + } else { + sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */ + clk_index = sys_clkin_sel; + } + + sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ + + /* The DPLL tables are defined according to sysclk value and + * silicon revision. The clk_index value will be used to get + * the values for that input sysclk from the DPLL param table + * and sil_index will get the values for that SysClk for the + * appropriate silicon rev. + */ + if(cpu_is_3410()) + sil_index = 2; + else { + if(get_cpu_rev() == CPU_3430_ES1) + sil_index = 0; + else if(get_cpu_rev() == CPU_3430_ES2) + sil_index = 1; + } + + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address of Core DPLL param table*/ + dpll_param_p = (dpll_param *)get_core_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + /* CORE DPLL */ + /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); + /* For 3430 ES1.0 Errata 1.50, default value directly doesnt + work. write another value and then default value. */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ + sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ + sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ + sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb ES1 only */ + sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ + sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ + sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ + sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ + sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to PER DPLL param table*/ + dpll_param_p = (dpll_param *)get_per_dpll_param(); + /* Moving it to the right sysclk base */ + dpll_param_p = dpll_param_p + clk_index; + /* PER DPLL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); + wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ + sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ + sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to MPU DPLL param table*/ + dpll_param_p = (dpll_param *)get_mpu_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + /* MPU DPLL (unlocked already) */ + sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address to IVA DPLL param table*/ + dpll_param_p = (dpll_param *)get_iva_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + /* IVA DPLL (set to 12*20=240MHz) */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); + sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ + sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ + sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); + + /* Set up GPTimers to sys_clk source only */ + sr32(CM_CLKSEL_PER, 0, 8, 0xff); + sr32(CM_CLKSEL_WKUP, 0, 1, 1); + + delay(5000); +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) { + secure_unlock(); + } + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called at time when only stack is available. + **********************************************************/ + +void s_init(void) +{ + watchdog_init(); +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP); +#endif + try_unlock_memory(); + set_muxconf_regs(); + delay(100); + prcm_init(); + per_clocks_enable(); + config_3430sdram_ddr(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r (void) +{ + return(0); +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init (void) +{ + return 0; +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +void per_clocks_enable(void) +{ + /* Enable GP2 timer. */ + sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ + sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ + sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ + +#ifdef CFG_NS16550 +////#ifdef CONFIG_SERIAL3 + sr32(CM_FCLKEN_PER, 11, 1, 0x1); + sr32(CM_ICLKEN_PER, 11, 1, 0x1); +////#else + /* Enable UART1 clocks */ + sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); + sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); +////#endif +#endif + delay(1000); +} + +/* Set MUX for UART, GPMC, SDRC, GPIO */ + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4 lab*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5 lab*/\ + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*sys_ndmareq1 lab*/\ + MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_IO_DIR lab*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1 lab*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ + MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ + MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ + MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ + MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ + MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ + MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ + MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ + MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ + MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ + MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ + MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/ +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT(); +} + +/********************************************************** + * Routine: nand+_init + * Description: Set up nand for nand and jffs2 commands + *********************************************************/ +int nand_init(void) +{ + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ +#ifdef CFG_NAND + __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ +#endif + + /* setup CS0 for Micron NAND, leave other CS's to u-boot */ + __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); + delay(1000); + +#ifdef CFG_NAND + __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); + +#else /* CFG_ONENAND */ + __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); +#endif + + /* Enable the GPMC Mapping */ + __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((OMAP34XX_GPMC_CS0_MAP>>24) & 0x3F) | + (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); + delay(2000); + +#ifdef CFG_NAND + if (nand_chip()){ +#ifdef CFG_PRINTF + printf("Unsupported Chip!\n"); +#endif + return 1; + } +#else + if (onenand_chip()){ +#ifdef CFG_PRINTF + printf("OneNAND Unsupported !\n"); +#endif + return 1; + } +#endif + return 0; +} + +/* optionally do something like blinking LED */ +void board_hang (void) +{ while (0) {};} diff --git a/board/omap3430labrador/platform.S b/board/omap3430labrador/platform.S new file mode 100644 index 0000000..5869270 --- /dev/null +++ b/board/omap3430labrador/platform.S @@ -0,0 +1,360 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * NOTE: 3430 X-loader currently does not use this code. +* It could be removed its is kept for compatabily with u-boot. + * + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = CM_CLKEN_PLL-bypass value + * R1 = CM_CLKSEL1_PLL-m, n, and divider values + * R2 = CM_CLKSEL_CORE-divider values + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + * + * Note: If core unlocks/relocks and SDRAM is running fast already it gets + * confused. A reset of the controller gets it back. Taking away its + * L3 when its not in self refresh seems bad for it. Normally, this code + * runs from flash before SDR is init so that should be ok. + ******************************************************************************/ +.global go_to_speed + go_to_speed: + stmfd sp!, {r4-r6} + + /* move into fast relock bypass */ + ldr r4, pll_ctl_add + str r0, [r4] +wait1: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + beq wait1 /* if lock, loop */ + + /* set new dpll dividers _after_ in bypass */ + ldr r5, pll_div_add1 + str r1, [r5] /* set m, n, m2 */ + ldr r5, pll_div_add2 + str r2, [r5] /* set l3/l4/.. dividers*/ + ldr r5, pll_div_add3 /* wkup */ + ldr r2, pll_div_val3 /* rsm val */ + str r2, [r5] + ldr r5, pll_div_add4 /* gfx */ + ldr r2, pll_div_val4 + str r2, [r5] + ldr r5, pll_div_add5 /* emu */ + ldr r2, pll_div_val5 + str r2, [r5] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r5, flash_cfg3_addr + ldr r2, flash_cfg3_val + str r2, [r5] + ldr r5, flash_cfg4_addr + ldr r2, flash_cfg4_val + str r2, [r5] + ldr r5, flash_cfg5_addr + ldr r2, flash_cfg5_val + str r2, [r5] + ldr r5, flash_cfg1_addr + ldr r2, [r5] + orr r2, r2, #0x3 /* up gpmc divider */ + str r2, [r5] + + /* lock DPLL3 and wait a bit */ + orr r0, r0, #0x7 /* set up for lock mode */ + str r0, [r4] /* lock */ + nop /* ARM slow at this point working at sys_clk */ + nop + nop + nop +wait2: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + bne wait2 /* if lock, loop */ + nop + nop + nop + nop + ldmfd sp!, {r4-r6} + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_div_add1: + .word CM_CLKSEL1_PLL +pll_div_add2: + .word CM_CLKSEL_CORE +pll_div_add3: + .word CM_CLKSEL_WKUP +pll_div_val3: + .word (WKUP_RSM << 1) +pll_div_add4: + .word CM_CLKSEL_GFX +pll_div_val4: + .word (GFX_DIV << 0) +pll_div_add5: + .word CM_CLKSEL1_EMU +pll_div_val5: + .word CLSEL1_EMU_VAL + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + +/* DPLL(1-4) PARAM TABLES */ +/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal + * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). + * The values are defined for all possible sysclk and for ES1 and ES2. + */ + +mpu_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x0FE,0x07,0x05,0x01 +/* ES2 */ +.word 0x0FA,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x17D,0x0C,0x03,0x01 +/* ES2 */ +.word 0x1F4,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x179,0x12,0x04,0x01 +/* ES2 */ +.word 0x271,0x17,0x03,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x17D,0x19,0x03,0x01 +/* ES2 */ +.word 0x0FA,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x1FA,0x32,0x03,0x01 +/* ES2 */ +.word 0x271,0x2F,0x03,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +.globl get_mpu_dpll_param +get_mpu_dpll_param: + adr r0, mpu_dpll_param + mov pc, lr + +iva_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x07D,0x05,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x0FA,0x0C,0x03,0x01 +/* ES2 */ +.word 0x168,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x082,0x09,0x07,0x01 +/* ES2 */ +.word 0x0E1,0x0B,0x06,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x07D,0x0C,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x13F,0x30,0x03,0x01 +/* ES2 */ +.word 0x0E1,0x17,0x06,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +.globl get_iva_dpll_param +get_iva_dpll_param: + adr r0, iva_dpll_param + mov pc, lr + +/* Core DPLL targets for L3 at 166 & L133 */ +core_dpll_param: +/* 12MHz */ +/* ES1 */ +.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 +/* ES2 */ +.word M_12,N_12,FSEL_12,M2_12 +/* 3410 */ +.word M_12,N_12,FSEL_12,M2_12 + +/* 13MHz */ +/* ES1 */ +.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 +/* ES2 */ +.word M_13,N_13,FSEL_13,M2_13 +/* 3410 */ +.word M_13,N_13,FSEL_13,M2_13 + +/* 19.2MHz */ +/* ES1 */ +.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 +/* ES2 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 +/* 3410 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 + +/* 26MHz */ +/* ES1 */ +.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 +/* ES2 */ +.word M_26,N_26,FSEL_26,M2_26 +/* 3410 */ +.word M_26,N_26,FSEL_26,M2_26 + +/* 38.4MHz */ +/* ES1 */ +.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 +/* ES2 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 +/* 3410 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 + +.globl get_core_dpll_param +get_core_dpll_param: + adr r0, core_dpll_param + mov pc, lr + +/* PER DPLL values are same for both ES1 and ES2 */ +per_dpll_param: +/* 12MHz */ +.word 0xD8,0x05,0x07,0x09 + +/* 13MHz */ +.word 0x1B0,0x0C,0x03,0x09 + +/* 19.2MHz */ +.word 0xE1,0x09,0x07,0x09 + +/* 26MHz */ +.word 0xD8,0x0C,0x07,0x09 + +/* 38.4MHz */ +.word 0xE1,0x13,0x07,0x09 + +.globl get_per_dpll_param +get_per_dpll_param: + adr r0, per_dpll_param + mov pc, lr + diff --git a/board/omap3430labrador/x-load.lds b/board/omap3430labrador/x-load.lds new file mode 100644 index 0000000..9402f74 --- /dev/null +++ b/board/omap3430labrador/x-load.lds @@ -0,0 +1,54 @@ +/* + * November 2006 - Changed to support 3430sdp device + * Copyright (c) 2004-2006 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap3430sdp/Makefile b/board/omap3430sdp/Makefile new file mode 100644 index 0000000..d54b666 --- /dev/null +++ b/board/omap3430sdp/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := omap3430sdp.o +SOBJS := platform.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/omap3430sdp/config.mk b/board/omap3430sdp/config.mk new file mode 100644 index 0000000..d6ad6c5 --- /dev/null +++ b/board/omap3430sdp/config.mk @@ -0,0 +1,22 @@ +# +# (C) Copyright 2006 +# Texas Instruments, +# +# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# SDP3430 has 1 bank of 32MB or 128MB mDDR-SDRAM on CS0 +# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000'0000 (bank1) - re-mappable below CS1 + +# For use if you want X-Loader to relocate from SRAM to DDR +#TEXT_BASE = 0x80e80000 + +# For XIP in 64K of SRAM or debug (GP device has it all availabe) +# SRAM 40200000-4020FFFF base +# initial stack at 0x4020fffc used in s_init (below xloader). +# The run time stack is (above xloader, 2k below) +# If any globals exist there needs to be room for them also +TEXT_BASE = 0x40208800 diff --git a/board/omap3430sdp/omap3430sdp.c b/board/omap3430sdp/omap3430sdp.c new file mode 100644 index 0000000..6ed62bc --- /dev/null +++ b/board/omap3430sdp/omap3430sdp.c @@ -0,0 +1,779 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Jian Zhang + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Used to index into DPLL parameter tables */ +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +}; + +typedef struct dpll_param dpll_param; + +#define MAX_SIL_INDEX 3 + +/* Following functions are exported from lowlevel_init.S */ +extern dpll_param * get_mpu_dpll_param(); +extern dpll_param * get_iva_dpll_param(); +extern dpll_param * get_core_dpll_param(); +extern dpll_param * get_per_dpll_param(); + +#define __raw_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init (void) +{ + return 0; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return(mode >>= 8); +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 cpuid=0; + /* On ES1.0 the IDCODE register is not exposed on L4 + * so using CPU ID to differentiate + * between ES2.0 and ES1.0. + */ + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); + if((cpuid & 0xf) == 0x0) + return CPU_3430_ES1; + else + return CPU_3430_ES2; + +} + +/****************************************** + * cpu_is_3410(void) - returns true for 3410 + ******************************************/ +u32 cpu_is_3410(void) +{ + int status; + if(get_cpu_rev() < CPU_3430_ES2) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = __raw_readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + __raw_writel(tmp, addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return (1); + if (i == bound) + return (0); + } while (1); +} + +#ifdef CFG_3430SDRAM_DDR +/********************************************************************* + * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. + *********************************************************************/ +void config_3430sdram_ddr(void) +{ + /* reset sdrc controller */ + __raw_writel(SOFTRESET, SDRC_SYSCONFIG); + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); + __raw_writel(0, SDRC_SYSCONFIG); + + /* setup sdrc to ball mux */ + __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); + + /* set mdcfg */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); + + /* set timing */ + __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); + __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); + __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL); + + /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0); + delay(5000); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + + /* set mr0 */ + __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); + + /* set up dll */ + __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); + delay(0x2000); /* give time to lock */ + +} +#endif // CFG_3430SDRAM_DDR + +/************************************************************* + * get_sys_clk_speed - determine reference oscillator speed + * based on known 32kHz clock and gptimer. + *************************************************************/ +u32 get_osc_clk_speed(void) +{ + u32 start, cstart, cend, cdiff, val; + + val = __raw_readl(PRM_CLKSRC_CTRL); + /* If SYS_CLK is being divided by 2, remove for now */ + val = (val & (~BIT7)) | BIT6; + __raw_writel(val, PRM_CLKSRC_CTRL); + + /* enable timer2 */ + val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; + __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ + + /* Enable I and F Clocks for GPT1 */ + val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; + __raw_writel(val, CM_ICLKEN_WKUP); + val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; + __raw_writel(val, CM_FCLKEN_WKUP); + + __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ + __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ + /* enable 32kHz source *//* enabled out of reset */ + /* determine sys_clk via gauging */ + + start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ + while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ + cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ + while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ + cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ + cdiff = cend - cstart; /* get elapsed ticks */ + + /* based on number of ticks assign speed */ + if (cdiff > 19000) + return (S38_4M); + else if (cdiff > 15200) + return (S26M); + else if (cdiff > 13000) + return (S24M); + else if (cdiff > 9000) + return (S19_2M); + else if (cdiff > 7600) + return (S13M); + else + return (S12M); +} + +/****************************************************************************** + * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on + * -- input oscillator clock frequency. + * + *****************************************************************************/ +void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) +{ + if(osc_clk == S38_4M) + *sys_clkin_sel= 4; + else if(osc_clk == S26M) + *sys_clkin_sel = 3; + else if(osc_clk == S19_2M) + *sys_clkin_sel = 2; + else if(osc_clk == S13M) + *sys_clkin_sel = 1; + else if(osc_clk == S12M) + *sys_clkin_sel = 0; +} + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * -- called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + u32 osc_clk=0, sys_clkin_sel; + dpll_param *dpll_param_p; + u32 clk_index, sil_index; + + /* Gauge the input clock speed and find out the sys_clkin_sel + * value corresponding to the input clock. + */ + osc_clk = get_osc_clk_speed(); + get_sys_clkin_sel(osc_clk, &sys_clkin_sel); + + sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ + + /* If the input clock is greater than 19.2M always divide/2 */ + if(sys_clkin_sel > 2) { + sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */ + clk_index = sys_clkin_sel/2; + } else { + sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */ + clk_index = sys_clkin_sel; + } + + /* The DPLL tables are defined according to sysclk value and + * silicon revision. The clk_index value will be used to get + * the values for that input sysclk from the DPLL param table + * and sil_index will get the values for that SysClk for the + * appropriate silicon rev. + */ + if(cpu_is_3410()) + sil_index = 2; + else { + if(get_cpu_rev() == CPU_3430_ES1) + sil_index = 0; + else if(get_cpu_rev() == CPU_3430_ES2) + sil_index = 1; + } + + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address of Core DPLL param table*/ + dpll_param_p = (dpll_param *)get_core_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + /* CORE DPLL */ + /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ + sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ + sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ + sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ + sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ + sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ + sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ + sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ + sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to PER DPLL param table*/ + dpll_param_p = (dpll_param *)get_per_dpll_param(); + /* Moving it to the right sysclk base */ + dpll_param_p = dpll_param_p + clk_index; + /* PER DPLL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); + wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ + sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ + sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to MPU DPLL param table*/ + dpll_param_p = (dpll_param *)get_mpu_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + /* MPU DPLL (unlocked already) */ + sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address to IVA DPLL param table*/ + dpll_param_p = (dpll_param *)get_iva_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + /* IVA DPLL (set to 12*20=240MHz) */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); + sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ + sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ + sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); + + /* Set up GPTimers to sys_clk source only */ + sr32(CM_CLKSEL_PER, 0, 8, 0xff); + sr32(CM_CLKSEL_WKUP, 0, 1, 1); + + delay(5000); +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) { + secure_unlock(); + } + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called at time when only stack is available. + **********************************************************/ + +void s_init(void) +{ + watchdog_init(); +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP); +#endif + try_unlock_memory(); + set_muxconf_regs(); + delay(100); + prcm_init(); + per_clocks_enable(); + config_3430sdram_ddr(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r (void) +{ + return(0); +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init (void) +{ + return 0; +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +void per_clocks_enable(void) +{ + /* Enable GP2 timer. */ + sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ + sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ + sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ + +#ifdef CFG_NS16550 + /* Enable UART1 clocks */ + sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); + sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); +#endif + delay(1000); +} + +/* Set MUX for UART, GPMC, SDRC, GPIO */ + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT()\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\ + MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\ + MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ + MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ + MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ + MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ + MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ + MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ + MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ + MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ + MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ + MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ + MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ + MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ + MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ + MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ + MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT(); +} + +/********************************************************** + * Routine: nand+_init + * Description: Set up nand for nand and jffs2 commands + *********************************************************/ +int nand_init(void) +{ + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ +#ifdef CFG_NAND + __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ +#endif + + /* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0 + * , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0. + * We configure only GPMC CS0 with required values. Configiring other devices + * at other CS in done in u-boot anyway. So we don't have to bother doing it here. + */ + __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); + delay(1000); + +#ifdef CFG_NAND + __raw_writel( SMNAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel( SMNAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel( SMNAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel( SMNAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel( SMNAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel( SMNAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); + +#else /* CFG_ONENAND */ + __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); +#endif + + /* Enable the GPMC Mapping */ + __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((OMAP34XX_GPMC_CS0_MAP>>24) & 0x3F) | + (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); + delay(2000); +#if defined(CFG_NAND) + if (nand_chip()){ +#ifdef CFG_PRINTF + printf("Unsupported Chip!\n"); +#endif + return 1; + } +#elif defined(CFG_ONENAND) + if (onenand_chip()){ +#ifdef CFG_PRINTF + printf("OneNAND Unsupported !\n"); +#endif + return 1; + } +#endif + return 0; +} + +#ifdef CFG_CMD_FAT +typedef int (mmc_boot_addr) (void); +int mmc_boot(void) +{ + long size, i; + unsigned long offset = CFG_LOADADDR; + unsigned long count; + char buf[12]; + block_dev_desc_t *dev_desc = NULL; + int dev = 0; + int part = 1; + char *ep; + unsigned char ret = 0; + + printf("Starting X-loader on MMC \n"); + + ret = mmc_init(1); + if(ret == 0){ + printf("\n MMC init failed \n"); + return 0; + } + + dev_desc = mmc_get_dev(0); + fat_register_device(dev_desc, 1); + size = file_fat_read("u-boot.bin", (unsigned char *)offset, 0); + if (size == -1) { + return 0; + } + printf("\n%ld Bytes Read from MMC \n", size); + + printf("Starting OS Bootloader from MMC...\n"); + + ((mmc_boot_addr *) CFG_LOADADDR) (); + + return 0; +} +#endif + +/* optionally do something like blinking LED */ +void board_hang (void) +{ while (0) {};} diff --git a/board/omap3430sdp/platform.S b/board/omap3430sdp/platform.S new file mode 100644 index 0000000..5869270 --- /dev/null +++ b/board/omap3430sdp/platform.S @@ -0,0 +1,360 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * NOTE: 3430 X-loader currently does not use this code. +* It could be removed its is kept for compatabily with u-boot. + * + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = CM_CLKEN_PLL-bypass value + * R1 = CM_CLKSEL1_PLL-m, n, and divider values + * R2 = CM_CLKSEL_CORE-divider values + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + * + * Note: If core unlocks/relocks and SDRAM is running fast already it gets + * confused. A reset of the controller gets it back. Taking away its + * L3 when its not in self refresh seems bad for it. Normally, this code + * runs from flash before SDR is init so that should be ok. + ******************************************************************************/ +.global go_to_speed + go_to_speed: + stmfd sp!, {r4-r6} + + /* move into fast relock bypass */ + ldr r4, pll_ctl_add + str r0, [r4] +wait1: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + beq wait1 /* if lock, loop */ + + /* set new dpll dividers _after_ in bypass */ + ldr r5, pll_div_add1 + str r1, [r5] /* set m, n, m2 */ + ldr r5, pll_div_add2 + str r2, [r5] /* set l3/l4/.. dividers*/ + ldr r5, pll_div_add3 /* wkup */ + ldr r2, pll_div_val3 /* rsm val */ + str r2, [r5] + ldr r5, pll_div_add4 /* gfx */ + ldr r2, pll_div_val4 + str r2, [r5] + ldr r5, pll_div_add5 /* emu */ + ldr r2, pll_div_val5 + str r2, [r5] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r5, flash_cfg3_addr + ldr r2, flash_cfg3_val + str r2, [r5] + ldr r5, flash_cfg4_addr + ldr r2, flash_cfg4_val + str r2, [r5] + ldr r5, flash_cfg5_addr + ldr r2, flash_cfg5_val + str r2, [r5] + ldr r5, flash_cfg1_addr + ldr r2, [r5] + orr r2, r2, #0x3 /* up gpmc divider */ + str r2, [r5] + + /* lock DPLL3 and wait a bit */ + orr r0, r0, #0x7 /* set up for lock mode */ + str r0, [r4] /* lock */ + nop /* ARM slow at this point working at sys_clk */ + nop + nop + nop +wait2: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + bne wait2 /* if lock, loop */ + nop + nop + nop + nop + ldmfd sp!, {r4-r6} + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_div_add1: + .word CM_CLKSEL1_PLL +pll_div_add2: + .word CM_CLKSEL_CORE +pll_div_add3: + .word CM_CLKSEL_WKUP +pll_div_val3: + .word (WKUP_RSM << 1) +pll_div_add4: + .word CM_CLKSEL_GFX +pll_div_val4: + .word (GFX_DIV << 0) +pll_div_add5: + .word CM_CLKSEL1_EMU +pll_div_val5: + .word CLSEL1_EMU_VAL + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + +/* DPLL(1-4) PARAM TABLES */ +/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal + * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). + * The values are defined for all possible sysclk and for ES1 and ES2. + */ + +mpu_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x0FE,0x07,0x05,0x01 +/* ES2 */ +.word 0x0FA,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x17D,0x0C,0x03,0x01 +/* ES2 */ +.word 0x1F4,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x179,0x12,0x04,0x01 +/* ES2 */ +.word 0x271,0x17,0x03,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x17D,0x19,0x03,0x01 +/* ES2 */ +.word 0x0FA,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x1FA,0x32,0x03,0x01 +/* ES2 */ +.word 0x271,0x2F,0x03,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +.globl get_mpu_dpll_param +get_mpu_dpll_param: + adr r0, mpu_dpll_param + mov pc, lr + +iva_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x07D,0x05,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x0FA,0x0C,0x03,0x01 +/* ES2 */ +.word 0x168,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x082,0x09,0x07,0x01 +/* ES2 */ +.word 0x0E1,0x0B,0x06,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x07D,0x0C,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x13F,0x30,0x03,0x01 +/* ES2 */ +.word 0x0E1,0x17,0x06,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +.globl get_iva_dpll_param +get_iva_dpll_param: + adr r0, iva_dpll_param + mov pc, lr + +/* Core DPLL targets for L3 at 166 & L133 */ +core_dpll_param: +/* 12MHz */ +/* ES1 */ +.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 +/* ES2 */ +.word M_12,N_12,FSEL_12,M2_12 +/* 3410 */ +.word M_12,N_12,FSEL_12,M2_12 + +/* 13MHz */ +/* ES1 */ +.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 +/* ES2 */ +.word M_13,N_13,FSEL_13,M2_13 +/* 3410 */ +.word M_13,N_13,FSEL_13,M2_13 + +/* 19.2MHz */ +/* ES1 */ +.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 +/* ES2 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 +/* 3410 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 + +/* 26MHz */ +/* ES1 */ +.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 +/* ES2 */ +.word M_26,N_26,FSEL_26,M2_26 +/* 3410 */ +.word M_26,N_26,FSEL_26,M2_26 + +/* 38.4MHz */ +/* ES1 */ +.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 +/* ES2 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 +/* 3410 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 + +.globl get_core_dpll_param +get_core_dpll_param: + adr r0, core_dpll_param + mov pc, lr + +/* PER DPLL values are same for both ES1 and ES2 */ +per_dpll_param: +/* 12MHz */ +.word 0xD8,0x05,0x07,0x09 + +/* 13MHz */ +.word 0x1B0,0x0C,0x03,0x09 + +/* 19.2MHz */ +.word 0xE1,0x09,0x07,0x09 + +/* 26MHz */ +.word 0xD8,0x0C,0x07,0x09 + +/* 38.4MHz */ +.word 0xE1,0x13,0x07,0x09 + +.globl get_per_dpll_param +get_per_dpll_param: + adr r0, per_dpll_param + mov pc, lr + diff --git a/board/omap3430sdp/x-load.lds b/board/omap3430sdp/x-load.lds new file mode 100644 index 0000000..9402f74 --- /dev/null +++ b/board/omap3430sdp/x-load.lds @@ -0,0 +1,54 @@ +/* + * November 2006 - Changed to support 3430sdp device + * Copyright (c) 2004-2006 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap3530beagle/Makefile b/board/omap3530beagle/Makefile new file mode 100644 index 0000000..b7b51ce --- /dev/null +++ b/board/omap3530beagle/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := omap3530beagle.o +SOBJS := platform.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/omap3530beagle/config.mk b/board/omap3530beagle/config.mk new file mode 100644 index 0000000..f271b14 --- /dev/null +++ b/board/omap3530beagle/config.mk @@ -0,0 +1,20 @@ +# +# (C) Copyright 2006 +# Texas Instruments, +# +# Beagle board uses TI OMAP3530 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Beagle has 1 bank of 128MB mPOP-SDRAM on CS0 +# Physical Address: +# 8000'0000 (bank0) + +# For use if you want X-Loader to relocate from SRAM to DDR +#TEXT_BASE = 0x80e80000 + +# For XIP in 64K of SRAM or debug (GP device has it all availabe) +# SRAM 40200000-4020FFFF base +# initial stack at 0x4020fffc used in s_init (below xloader). +# The run time stack is (above xloader, 2k below) +# If any globals exist there needs to be room for them also +TEXT_BASE = 0x40200800 diff --git a/board/omap3530beagle/omap3530beagle.c b/board/omap3530beagle/omap3530beagle.c new file mode 100644 index 0000000..073e35a --- /dev/null +++ b/board/omap3530beagle/omap3530beagle.c @@ -0,0 +1,1081 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Jian Zhang + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* params for XM */ +#define CORE_DPLL_PARAM_M2 0x09 +#define CORE_DPLL_PARAM_M 0x360 +#define CORE_DPLL_PARAM_N 0xC + +/* BeagleBoard revisions */ +#define REVISION_AXBX 0x7 +#define REVISION_CX 0x6 +#define REVISION_C4 0x5 +#define REVISION_XM 0x0 + +/* Used to index into DPLL parameter tables */ +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +}; + +typedef struct dpll_param dpll_param; + +/* Following functions are exported from lowlevel_init.S */ +extern dpll_param *get_mpu_dpll_param(); +extern dpll_param *get_iva_dpll_param(); +extern dpll_param *get_core_dpll_param(); +extern dpll_param *get_per_dpll_param(); + +#define __raw_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v)) + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +void udelay (unsigned long usecs) { + delay(usecs); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + return 0; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return mode >>= 8; +} + +/************************************************ + * get_sysboot_value(void) - return SYS_BOOT[4:0] + ************************************************/ +u32 get_sysboot_value(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK); + return mode; +} + +/************************************************************* + * Routine: get_mem_type(void) - returns the kind of memory connected + * to GPMC that we are trying to boot form. Uses SYS BOOT settings. + *************************************************************/ +u32 get_mem_type(void) +{ + + if (beagle_revision() == REVISION_XM) + return GPMC_NONE; + + u32 mem_type = get_sysboot_value(); + switch (mem_type) { + case 0: + case 2: + case 4: + case 16: + case 22: + return GPMC_ONENAND; + + case 1: + case 12: + case 15: + case 21: + case 27: + return GPMC_NAND; + + case 3: + case 6: + return MMC_ONENAND; + + case 8: + case 11: + case 14: + case 20: + case 26: + return GPMC_MDOC; + + case 17: + case 18: + case 24: + return MMC_NAND; + + case 7: + case 10: + case 13: + case 19: + case 25: + default: + return GPMC_NOR; + } +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 cpuid = 0; + /* On ES1.0 the IDCODE register is not exposed on L4 + * so using CPU ID to differentiate + * between ES2.0 and ES1.0. + */ + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); + if ((cpuid & 0xf) == 0x0) + return CPU_3430_ES1; + else + return CPU_3430_ES2; + +} + +/****************************************** + * cpu_is_3410(void) - returns true for 3410 + ******************************************/ +u32 cpu_is_3410(void) +{ + int status; + if (get_cpu_rev() < CPU_3430_ES2) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/****************************************** + * beagle_identify + * Description: Detect if we are running on a Beagle revision Ax/Bx, + * C1/2/3, C4 or D. This can be done by reading + * the level of GPIO173, GPIO172 and GPIO171. This should + * result in + * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx + * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3 + * GPIO173, GPIO172, GPIO171: 1 0 1 => C4 + * GPIO173, GPIO172, GPIO171: 0 0 0 => XM + ******************************************/ +int beagle_revision(void) +{ + int rev; + + omap_request_gpio(171); + omap_request_gpio(172); + omap_request_gpio(173); + omap_set_gpio_direction(171, 1); + omap_set_gpio_direction(172, 1); + omap_set_gpio_direction(173, 1); + + rev = omap_get_gpio_datain(173) << 2 | + omap_get_gpio_datain(172) << 1 | + omap_get_gpio_datain(171); + omap_free_gpio(171); + omap_free_gpio(172); + omap_free_gpio(173); + + return rev; +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = __raw_readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + __raw_writel(tmp, addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return 1; + if (i == bound) + return 0; + } while (1); +} + +#ifdef CFG_3430SDRAM_DDR + +#define MICRON_DDR 0 +#define NUMONYX_MCP 1 +int identify_xm_ddr() +{ + int mfr, id; + + __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); + + /* Enable the GPMC Mapping */ + __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((NAND_BASE_ADR>>24) & 0x3F) | + (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); + delay(2000); + + nand_readid(&mfr, &id); + if (mfr == 0) + return MICRON_DDR; + if ((mfr == 0x20) && (id == 0xba)) + return NUMONYX_MCP; +} +/********************************************************************* + * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. + *********************************************************************/ +void config_3430sdram_ddr(void) +{ + /* reset sdrc controller */ + __raw_writel(SOFTRESET, SDRC_SYSCONFIG); + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); + __raw_writel(0, SDRC_SYSCONFIG); + + /* setup sdrc to ball mux */ + __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); + + switch(beagle_revision()) { + case REVISION_C4: + if (identify_xm_ddr() == NUMONYX_MCP) { + __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0); + __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1); + __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); + __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); + __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); + __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); + } else { + __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); + __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); + __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); + __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); + __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); + } + break; + case REVISION_XM: + if (identify_xm_ddr() == MICRON_DDR) { + __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0); + __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1); + __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0); + __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0); + __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1); + __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1); + } else { + __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0); + __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1); + __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); + __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); + __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); + __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); + } + break; + default: + __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); + __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); + __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); + __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); + __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); + } + + __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER); + + /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0); + __raw_writel(CMD_NOP, SDRC_MANUAL_1); + + delay(5000); + + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); + + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); + + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); + + /* set mr0 */ + __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); + __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1); + + /* set up dll */ + __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); + delay(0x2000); /* give time to lock */ + +} +#endif /* CFG_3430SDRAM_DDR */ + +/************************************************************* + * get_sys_clk_speed - determine reference oscillator speed + * based on known 32kHz clock and gptimer. + *************************************************************/ +u32 get_osc_clk_speed(void) +{ + u32 start, cstart, cend, cdiff, cdiv, val; + + val = __raw_readl(PRM_CLKSRC_CTRL); + + if (val & SYSCLKDIV_2) + cdiv = 2; + else + cdiv = 1; + + /* enable timer2 */ + val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; + __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ + + /* Enable I and F Clocks for GPT1 */ + val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; + __raw_writel(val, CM_ICLKEN_WKUP); + val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; + __raw_writel(val, CM_FCLKEN_WKUP); + + __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ + __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ + /* enable 32kHz source */ + /* enabled out of reset */ + /* determine sys_clk via gauging */ + + start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ + while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */ + cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ + while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */ + cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ + cdiff = cend - cstart; /* get elapsed ticks */ + cdiff *= cdiv; + + /* based on number of ticks assign speed */ + if (cdiff > 19000) + return S38_4M; + else if (cdiff > 15200) + return S26M; + else if (cdiff > 13000) + return S24M; + else if (cdiff > 9000) + return S19_2M; + else if (cdiff > 7600) + return S13M; + else + return S12M; +} + +/****************************************************************************** + * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on + * -- input oscillator clock frequency. + * + *****************************************************************************/ +void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) +{ + if (osc_clk == S38_4M) + *sys_clkin_sel = 4; + else if (osc_clk == S26M) + *sys_clkin_sel = 3; + else if (osc_clk == S19_2M) + *sys_clkin_sel = 2; + else if (osc_clk == S13M) + *sys_clkin_sel = 1; + else if (osc_clk == S12M) + *sys_clkin_sel = 0; +} + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * -- called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + u32 osc_clk = 0, sys_clkin_sel; + dpll_param *dpll_param_p; + u32 clk_index, sil_index; + + /* Gauge the input clock speed and find out the sys_clkin_sel + * value corresponding to the input clock. + */ + osc_clk = get_osc_clk_speed(); + get_sys_clkin_sel(osc_clk, &sys_clkin_sel); + + sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ + + /* If the input clock is greater than 19.2M always divide/2 */ + if (sys_clkin_sel > 2) { + sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */ + clk_index = sys_clkin_sel / 2; + } else { + sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */ + clk_index = sys_clkin_sel; + } + + sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ + + /* The DPLL tables are defined according to sysclk value and + * silicon revision. The clk_index value will be used to get + * the values for that input sysclk from the DPLL param table + * and sil_index will get the values for that SysClk for the + * appropriate silicon rev. + */ + sil_index = get_cpu_rev() - 1; + + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address of Core DPLL param table */ + dpll_param_p = (dpll_param *) get_core_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; + /* CORE DPLL */ + /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); + + /* For 3430 ES1.0 Errata 1.50, default value directly doesnt + work. write another value and then default value. */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ + sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ + sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ + sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ + sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ + sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ + sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ + sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ + sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to PER DPLL param table */ + dpll_param_p = (dpll_param *) get_per_dpll_param(); + /* Moving it to the right sysclk base */ + dpll_param_p = dpll_param_p + clk_index; + /* PER DPLL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); + wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ + + if (beagle_revision() == REVISION_XM) { + sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */ + sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */ + sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */ + } else { + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ + sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ + } + + sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to MPU DPLL param table */ + dpll_param_p = (dpll_param *) get_mpu_dpll_param(); + + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; + + /* MPU DPLL (unlocked already) */ + sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address to IVA DPLL param table */ + dpll_param_p = (dpll_param *) get_iva_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; + /* IVA DPLL (set to 12*20=240MHz) */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); + sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ + sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ + sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); + + /* Set up GPTimers to sys_clk source only */ + sr32(CM_CLKSEL_PER, 0, 8, 0xff); + sr32(CM_CLKSEL_WKUP, 0, 1, 1); + + delay(5000); +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock(void) +{ + /* Permission values for registers -Full fledged permissions to all */ +#define UNLOCK_1 0xFFFFFFFF +#define UNLOCK_2 0x00000000 +#define UNLOCK_3 0x0000FFFF + /* Protection Module Register Target APE (PM_RT) */ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T */ + mode = get_device_type(); + if (mode == GP_DEVICE) + secure_unlock(); + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called at time when only stack is available. + **********************************************************/ + +void s_init(void) +{ + watchdog_init(); +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP); +#endif + try_unlock_memory(); + set_muxconf_regs(); + delay(100); + per_clocks_enable(); + prcm_init(); + config_3430sdram_ddr(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ + int rev; + + rev = beagle_revision(); + switch (rev) { + case REVISION_AXBX: + printf("Beagle Rev Ax/Bx\n"); + break; + case REVISION_CX: + printf("Beagle Rev C1/C2/C3\n"); + break; + case REVISION_C4: + if (identify_xm_ddr() == NUMONYX_MCP) + printf("Beagle Rev C4 from Special Computing\n"); + else + printf("Beagle Rev C4\n"); + break; + case REVISION_XM: + printf("Beagle xM Rev A\n"); + break; + default: + printf("Beagle unknown 0x%02x\n", rev); + } + + return 0; +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + return 0; +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +void per_clocks_enable(void) +{ + /* Enable GP2 timer. */ + sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ + sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ + sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ + +#ifdef CFG_NS16550 + /* UART1 clocks */ + sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); + sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); + + /* UART 3 Clocks */ + sr32(CM_FCLKEN_PER, 11, 1, 0x1); + sr32(CM_ICLKEN_PER, 11, 1, 0x1); + +#endif + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + /* Turn on all 3 I2C clocks */ + sr32(CM_FCLKEN1_CORE, 15, 3, 0x7); + sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */ +#endif + + /* Enable the ICLK for 32K Sync Timer as its used in udelay */ + sr32(CM_ICLKEN_WKUP, 2, 1, 0x1); + + sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON); + sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON); + sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON); + sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON); + sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON); + sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON); + sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON); + sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON); + sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON); + sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON); + sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON); + sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON); + + /* Enable GPIO 5 & GPIO 6 clocks */ + sr32(CM_FCLKEN_PER, 17, 2, 0x3); + sr32(CM_ICLKEN_PER, 17, 2, 0x3); + + delay(1000); +} + +/* Set MUX for UART, GPMC, SDRC, GPIO */ + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT()\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*GPMC_nCS6*/\ + MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPIO_61*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPIO_64*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPIO_65*/\ + MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ + MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ + MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ + MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\ + MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(McSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\ + MUX_VAL(CP(McSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\ + MUX_VAL(CP(McSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ + MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ + MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ + MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ + MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ + MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ + MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ + MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ + MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ + MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ + MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29 */\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT(); +} + +/********************************************************** + * Routine: nand+_init + * Description: Set up nand for nand and jffs2 commands + *********************************************************/ + +int nand_init(void) +{ + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ + + /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0. + * We configure only GPMC CS0 with required values. Configiring other devices + * at other CS is done in u-boot. So we don't have to bother doing it here. + */ + __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); + delay(1000); + +#ifdef CFG_NAND_K9F1G08R0A + if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) { + __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); + + /* Enable the GPMC Mapping */ + __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((NAND_BASE_ADR>>24) & 0x3F) | + (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); + delay(2000); + + if (nand_chip()) { +#ifdef CFG_PRINTF + printf("Unsupported Chip!\n"); +#endif + return 1; + } + } +#endif + +#ifdef CFG_ONENAND + if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) { + __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); + + /* Enable the GPMC Mapping */ + __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((ONENAND_BASE>>24) & 0x3F) | + (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); + delay(2000); + + if (onenand_chip()) { +#ifdef CFG_PRINTF + printf("OneNAND Unsupported !\n"); +#endif + return 1; + } + } +#endif + return 0; +} + +#define DEBUG_LED1 149 /* gpio */ +#define DEBUG_LED2 150 /* gpio */ + +void blinkLEDs() +{ + void *p; + + /* Alternately turn the LEDs on and off */ + p = (unsigned long *)OMAP34XX_GPIO5_BASE; + while (1) { + /* turn LED1 on and LED2 off */ + *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED1 % 32); + *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED2 % 32); + + /* delay for a while */ + delay(1000); + + /* turn LED1 off and LED2 on */ + *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED1 % 32); + *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED2 % 32); + + /* delay for a while */ + delay(1000); + } +} + +/* optionally do something like blinking LED */ +void board_hang(void) +{ + while (1) + blinkLEDs(); +} + +/****************************************************************************** + * Dummy function to handle errors for EABI incompatibility + *****************************************************************************/ +void raise(void) +{ +} + +/****************************************************************************** + * Dummy function to handle errors for EABI incompatibility + *****************************************************************************/ +void abort(void) +{ +} diff --git a/board/omap3530beagle/platform.S b/board/omap3530beagle/platform.S new file mode 100644 index 0000000..5869270 --- /dev/null +++ b/board/omap3530beagle/platform.S @@ -0,0 +1,360 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * NOTE: 3430 X-loader currently does not use this code. +* It could be removed its is kept for compatabily with u-boot. + * + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = CM_CLKEN_PLL-bypass value + * R1 = CM_CLKSEL1_PLL-m, n, and divider values + * R2 = CM_CLKSEL_CORE-divider values + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + * + * Note: If core unlocks/relocks and SDRAM is running fast already it gets + * confused. A reset of the controller gets it back. Taking away its + * L3 when its not in self refresh seems bad for it. Normally, this code + * runs from flash before SDR is init so that should be ok. + ******************************************************************************/ +.global go_to_speed + go_to_speed: + stmfd sp!, {r4-r6} + + /* move into fast relock bypass */ + ldr r4, pll_ctl_add + str r0, [r4] +wait1: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + beq wait1 /* if lock, loop */ + + /* set new dpll dividers _after_ in bypass */ + ldr r5, pll_div_add1 + str r1, [r5] /* set m, n, m2 */ + ldr r5, pll_div_add2 + str r2, [r5] /* set l3/l4/.. dividers*/ + ldr r5, pll_div_add3 /* wkup */ + ldr r2, pll_div_val3 /* rsm val */ + str r2, [r5] + ldr r5, pll_div_add4 /* gfx */ + ldr r2, pll_div_val4 + str r2, [r5] + ldr r5, pll_div_add5 /* emu */ + ldr r2, pll_div_val5 + str r2, [r5] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r5, flash_cfg3_addr + ldr r2, flash_cfg3_val + str r2, [r5] + ldr r5, flash_cfg4_addr + ldr r2, flash_cfg4_val + str r2, [r5] + ldr r5, flash_cfg5_addr + ldr r2, flash_cfg5_val + str r2, [r5] + ldr r5, flash_cfg1_addr + ldr r2, [r5] + orr r2, r2, #0x3 /* up gpmc divider */ + str r2, [r5] + + /* lock DPLL3 and wait a bit */ + orr r0, r0, #0x7 /* set up for lock mode */ + str r0, [r4] /* lock */ + nop /* ARM slow at this point working at sys_clk */ + nop + nop + nop +wait2: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + bne wait2 /* if lock, loop */ + nop + nop + nop + nop + ldmfd sp!, {r4-r6} + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_div_add1: + .word CM_CLKSEL1_PLL +pll_div_add2: + .word CM_CLKSEL_CORE +pll_div_add3: + .word CM_CLKSEL_WKUP +pll_div_val3: + .word (WKUP_RSM << 1) +pll_div_add4: + .word CM_CLKSEL_GFX +pll_div_val4: + .word (GFX_DIV << 0) +pll_div_add5: + .word CM_CLKSEL1_EMU +pll_div_val5: + .word CLSEL1_EMU_VAL + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + +/* DPLL(1-4) PARAM TABLES */ +/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal + * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). + * The values are defined for all possible sysclk and for ES1 and ES2. + */ + +mpu_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x0FE,0x07,0x05,0x01 +/* ES2 */ +.word 0x0FA,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x17D,0x0C,0x03,0x01 +/* ES2 */ +.word 0x1F4,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x179,0x12,0x04,0x01 +/* ES2 */ +.word 0x271,0x17,0x03,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x17D,0x19,0x03,0x01 +/* ES2 */ +.word 0x0FA,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x1FA,0x32,0x03,0x01 +/* ES2 */ +.word 0x271,0x2F,0x03,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +.globl get_mpu_dpll_param +get_mpu_dpll_param: + adr r0, mpu_dpll_param + mov pc, lr + +iva_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x07D,0x05,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x0FA,0x0C,0x03,0x01 +/* ES2 */ +.word 0x168,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x082,0x09,0x07,0x01 +/* ES2 */ +.word 0x0E1,0x0B,0x06,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x07D,0x0C,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x13F,0x30,0x03,0x01 +/* ES2 */ +.word 0x0E1,0x17,0x06,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +.globl get_iva_dpll_param +get_iva_dpll_param: + adr r0, iva_dpll_param + mov pc, lr + +/* Core DPLL targets for L3 at 166 & L133 */ +core_dpll_param: +/* 12MHz */ +/* ES1 */ +.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 +/* ES2 */ +.word M_12,N_12,FSEL_12,M2_12 +/* 3410 */ +.word M_12,N_12,FSEL_12,M2_12 + +/* 13MHz */ +/* ES1 */ +.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 +/* ES2 */ +.word M_13,N_13,FSEL_13,M2_13 +/* 3410 */ +.word M_13,N_13,FSEL_13,M2_13 + +/* 19.2MHz */ +/* ES1 */ +.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 +/* ES2 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 +/* 3410 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 + +/* 26MHz */ +/* ES1 */ +.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 +/* ES2 */ +.word M_26,N_26,FSEL_26,M2_26 +/* 3410 */ +.word M_26,N_26,FSEL_26,M2_26 + +/* 38.4MHz */ +/* ES1 */ +.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 +/* ES2 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 +/* 3410 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 + +.globl get_core_dpll_param +get_core_dpll_param: + adr r0, core_dpll_param + mov pc, lr + +/* PER DPLL values are same for both ES1 and ES2 */ +per_dpll_param: +/* 12MHz */ +.word 0xD8,0x05,0x07,0x09 + +/* 13MHz */ +.word 0x1B0,0x0C,0x03,0x09 + +/* 19.2MHz */ +.word 0xE1,0x09,0x07,0x09 + +/* 26MHz */ +.word 0xD8,0x0C,0x07,0x09 + +/* 38.4MHz */ +.word 0xE1,0x13,0x07,0x09 + +.globl get_per_dpll_param +get_per_dpll_param: + adr r0, per_dpll_param + mov pc, lr + diff --git a/board/omap3530beagle/platform.S_old b/board/omap3530beagle/platform.S_old new file mode 100644 index 0000000..8368487 --- /dev/null +++ b/board/omap3530beagle/platform.S_old @@ -0,0 +1,435 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * NOTE: 3430 X-loader currently does not use this code. +* It could be removed its is kept for compatabily with u-boot. + * + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = CM_CLKEN_PLL-bypass value + * R1 = CM_CLKSEL1_PLL-m, n, and divider values + * R2 = CM_CLKSEL_CORE-divider values + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + * + * Note: If core unlocks/relocks and SDRAM is running fast already it gets + * confused. A reset of the controller gets it back. Taking away its + * L3 when its not in self refresh seems bad for it. Normally, this code + * runs from flash before SDR is init so that should be ok. + ******************************************************************************/ +.global go_to_speed + go_to_speed: + stmfd sp!, {r4-r6} + + /* move into fast relock bypass */ + ldr r4, pll_ctl_add + str r0, [r4] +wait1: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + beq wait1 /* if lock, loop */ + + /* set new dpll dividers _after_ in bypass */ + ldr r5, pll_div_add1 + str r1, [r5] /* set m, n, m2 */ + ldr r5, pll_div_add2 + str r2, [r5] /* set l3/l4/.. dividers*/ + ldr r5, pll_div_add3 /* wkup */ + ldr r2, pll_div_val3 /* rsm val */ + str r2, [r5] + ldr r5, pll_div_add4 /* gfx */ + ldr r2, pll_div_val4 + str r2, [r5] + ldr r5, pll_div_add5 /* emu */ + ldr r2, pll_div_val5 + str r2, [r5] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r5, flash_cfg3_addr + ldr r2, flash_cfg3_val + str r2, [r5] + ldr r5, flash_cfg4_addr + ldr r2, flash_cfg4_val + str r2, [r5] + ldr r5, flash_cfg5_addr + ldr r2, flash_cfg5_val + str r2, [r5] + ldr r5, flash_cfg1_addr + ldr r2, [r5] + orr r2, r2, #0x3 /* up gpmc divider */ + str r2, [r5] + + /* lock DPLL3 and wait a bit */ + orr r0, r0, #0x7 /* set up for lock mode */ + str r0, [r4] /* lock */ + nop /* ARM slow at this point working at sys_clk */ + nop + nop + nop +wait2: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + bne wait2 /* if lock, loop */ + nop + nop + nop + nop + ldmfd sp!, {r4-r6} + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_div_add1: + .word CM_CLKSEL1_PLL +pll_div_add2: + .word CM_CLKSEL_CORE +pll_div_add3: + .word CM_CLKSEL_WKUP +pll_div_val3: + .word (WKUP_RSM << 1) +pll_div_add4: + .word CM_CLKSEL_GFX +pll_div_val4: + .word (GFX_DIV << 0) +pll_div_add5: + .word CM_CLKSEL1_EMU +pll_div_val5: + .word CLSEL1_EMU_VAL + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + + +/* DPLL(1-4) PARAM TABLES */ +/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal + * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). + * The values are defined for all possible sysclk and for ES1 and ES2. + */ + +mpu_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x0FE +.word 0x07 +.word 0x05 +.word 0x01 +/* ES2 */ +.word 0x0FA +.word 0x05 +.word 0x07 +.word 0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x17D +.word 0x0C +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x1F4 +.word 0x0C +.word 0x03 +.word 0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x179 +.word 0x12 +.word 0x04 +.word 0x01 +/* ES2 */ +.word 0x271 +.word 0x17 +.word 0x03 +.word 0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x17D +.word 0x19 +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x0FA +.word 0x0C +.word 0x07 +.word 0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x1FA +.word 0x32 +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x271 +.word 0x2F +.word 0x03 +.word 0x01 + + +.globl get_mpu_dpll_param +get_mpu_dpll_param: + adr r0, mpu_dpll_param + mov pc, lr + +iva_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x07D +.word 0x05 +.word 0x07 +.word 0x01 +/* ES2 */ +.word 0x0B4 +.word 0x05 +.word 0x07 +.word 0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x0FA +.word 0x0C +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x168 +.word 0x0C +.word 0x03 +.word 0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x082 +.word 0x09 +.word 0x07 +.word 0x01 +/* ES2 */ +.word 0x0E1 +.word 0x0B +.word 0x06 +.word 0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x07D +.word 0x0C +.word 0x07 +.word 0x01 +/* ES2 */ +.word 0x0B4 +.word 0x0C +.word 0x07 +.word 0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x13F +.word 0x30 +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x0E1 +.word 0x17 +.word 0x06 +.word 0x01 + + +.globl get_iva_dpll_param +get_iva_dpll_param: + adr r0, iva_dpll_param + mov pc, lr + +core_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x19F +.word 0x0E +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x0A6 +.word 0x05 +.word 0x07 +.word 0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x1B2 +.word 0x10 +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x14C +.word 0x0C +.word 0x03 +.word 0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x19F +.word 0x17 +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x19F +.word 0x17 +.word 0x03 +.word 0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x1B2 +.word 0x21 +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x0A6 +.word 0x0C +.word 0x07 +.word 0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x19F +.word 0x2F +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x19F +.word 0x2F +.word 0x03 +.word 0x01 + +.globl get_core_dpll_param +get_core_dpll_param: + adr r0, core_dpll_param + mov pc, lr + +/* PER DPLL values are same for both ES1 and ES2 */ +per_dpll_param: +/* 12MHz */ +.word 0xD8 +.word 0x05 +.word 0x07 +.word 0x09 + +/* 13MHz */ +.word 0x1B0 +.word 0x0C +.word 0x03 +.word 0x09 + +/* 19.2MHz */ +.word 0xE1 +.word 0x09 +.word 0x07 +.word 0x09 + +/* 26MHz */ +.word 0xD8 +.word 0x0C +.word 0x07 +.word 0x09 + +/* 38.4MHz */ +.word 0xE1 +.word 0x13 +.word 0x07 +.word 0x09 + +.globl get_per_dpll_param +get_per_dpll_param: + adr r0, per_dpll_param + mov pc, lr + diff --git a/board/omap3530beagle/x-load.lds b/board/omap3530beagle/x-load.lds new file mode 100644 index 0000000..9402f74 --- /dev/null +++ b/board/omap3530beagle/x-load.lds @@ -0,0 +1,54 @@ +/* + * November 2006 - Changed to support 3430sdp device + * Copyright (c) 2004-2006 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap3530gta04/Makefile b/board/omap3530gta04/Makefile new file mode 100644 index 0000000..436d974 --- /dev/null +++ b/board/omap3530gta04/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := omap3530gta04.o +SOBJS := platform.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/omap3530gta04/config.mk b/board/omap3530gta04/config.mk new file mode 100644 index 0000000..01eafc1 --- /dev/null +++ b/board/omap3530gta04/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2006 +# Texas Instruments, +# +# Beagle board uses TI OMAP3530 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Beagle has 1 bank of 128MB mPOP-SDRAM on CS0 +# Physical Address: +# 8000'0000 (bank0) + +# For use if you want X-Loader to relocate from SRAM to DDR +#TEXT_BASE = 0x80e80000 + +# if you want X-Loader to load to RAM through peripheral boot +#TEXT_BASE = 0x40200000 # for serial loader + +# For XIP in 64K of SRAM or debug (GP device has it all availabe) +# SRAM 40200000-4020FFFF base +# initial stack at 0x4020fffc used in s_init (below xloader). +# The run time stack is (above xloader, 2k below) +# If any globals exist there needs to be room for them also +TEXT_BASE = 0x40208800 diff --git a/board/omap3530gta04/omap3530gta04.c b/board/omap3530gta04/omap3530gta04.c new file mode 100644 index 0000000..04f310d --- /dev/null +++ b/board/omap3530gta04/omap3530gta04.c @@ -0,0 +1,1279 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Jian Zhang + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* params for 37XX */ +#define CORE_DPLL_PARAM_M2 0x09 +#define CORE_DPLL_PARAM_M 0x360 +#define CORE_DPLL_PARAM_N 0xC + +/* Used to index into DPLL parameter tables */ +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +}; + +typedef struct dpll_param dpll_param; + +/* Following functions are exported from lowlevel_init.S */ +extern dpll_param *get_mpu_dpll_param(void); +extern dpll_param *get_iva_dpll_param(void); +extern dpll_param *get_core_dpll_param(void); +extern dpll_param *get_per_dpll_param(void); + +#define __raw_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v)) + +static char *rev_s[CPU_3XX_MAX_REV] = { + "1.0", + "2.0", + "2.1", + "3.0", + "3.1", + "UNKNOWN", + "UNKNOWN", + "3.1.2"}; + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +void udelay (unsigned long usecs) { + delay(usecs); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + /* + use code like this to early enable USB charging! + so that the board boots with no battery but USB power + + if i2c does not work at this position, + try to move this code to gta04_revision() + + I2C_SET_BUS(0); + data = 0x01; + i2c_write(0x4B, 0x29, 1, &data, 1); + data = 0x0c; + i2c_write(0x4B, 0x2b, 1, &data, 1); + i2c_read(0x4B, 0x2a, 1, &data, 1); + +*/ + +#if 0 /* no - does not work as expected */ + + /* + For charging using USB, the software must enable the USB automatic + charge by forcing the BOOT_BCI[1] BCIAUTOUSB bit to 1. When the USB + charger is plugged in, the software detects the type of device + (USB charger or carkit charger). The software must set the POWER_CTRL[5] + OTG_EN bit to 1 at least 50 ms before forcing the BCIMFSTS4[2] USBFASTMCHG + bit to 1. + */ + + u8 data; + int i; + + I2C_SET_BUS(0); + + /* enable access to BCIIREF1 */ + data = 0xE7; + i2c_write(0x4A, 0x85, 1, &data, 1); // write BCIMFKEY + + /* set charging current = 852mA */ + data = 0xFF; + i2c_write(0x4A, 0x9B, 1, &data, 1); // write BCIIREF1 + + /* forcing the field BCIAUTOUSB (BOOT_BCI[1]) to 1 */ + i2c_read(0x4B, 0x3D, 1, &data, 1); // read BOOT_BCI + data |= 0x33; // CONFIG_DONE | BCIAUTOWEN | BCIAUTOUSB | BCIAUTOAC + i2c_write(0x4B, 0x3D, 1, &data, 1); // write BOOT_BCI + + /* Enabling interfacing with usb through OCP */ + i2c_read(0x48, 0xFE, 1, &data, 1); // read BOOT_BCI + data |= 0x01; // PHY_DPLL_CLK + i2c_write(0x48, 0xFE, 1, &data, 1); // write BOOT_BCI + + do { + udelay(10); + i2c_read(0x48, 0xFE, 1, &data, 1); // read PHY_CLK_CTRL_STS + } while (!(data & 0x01)); /* loop until PHY DPLL is locked */ + + /* OTG_EN (POWER_CTRL[5]) to 1 */ + data = 0x20; + i2c_write(0x48, 0xAD, 1, &data, 1); // write POWER_CTRL_SET + + for(i=0; i<50; i++) + udelay(1000); + + /* forcing USBFASTMCHG(BCIMFSTS4[2]) to 1 */ + i2c_read(0x4A, 0x84, 1, &data, 1); // read BCIMFSTS4 + data |= 0x04; // USBFASTMCHG + i2c_write(0x4A, 0x84, 1, &data, 1); // write BCIMFSTS4 + +#endif + return 0; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return mode >>= 8; +} + +/************************************************ + * get_sysboot_value(void) - return SYS_BOOT[4:0] + ************************************************/ +u32 get_sysboot_value(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK); + return mode; +} + +/************************************************************* + * Routine: get_mem_type(void) - returns the kind of memory connected + * to GPMC that we are trying to boot form. Uses SYS BOOT settings. + *************************************************************/ +u32 get_mem_type(void) +{ + u32 mem_type = get_sysboot_value(); + switch (mem_type) { + case 0: + case 2: + case 4: + case 16: + case 22: + return GPMC_ONENAND; + + case 1: + case 12: + case 15: + case 21: + case 27: + return GPMC_NAND; + + case 3: + case 6: + return MMC_ONENAND; + + case 8: + case 11: + case 14: + case 20: + case 26: + return GPMC_MDOC; + + case 17: + case 18: + case 24: + return MMC_NAND; + + case 7: + case 10: + case 13: + case 19: + case 25: + default: + return GPMC_NOR; + } +} + +/****************************************** + * get_cpu_type(void) - extract cpu info + ******************************************/ +u32 get_cpu_type(void) +{ + return __raw_readl(CONTROL_OMAP_STATUS); +} + +/****************************************** + * get_cpu_id(void) - extract cpu id + * returns 0 for ES1.0, cpuid otherwise + ******************************************/ +u32 get_cpu_id(void) +{ + u32 cpuid = 0; + + /* + * On ES1.0 the IDCODE register is not exposed on L4 + * so using CPU ID to differentiate between ES1.0 and > ES1.0. + */ + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid)); + if ((cpuid & 0xf) == 0x0) { + return 0; + } else { + /* Decode the IDs on > ES1.0 */ + cpuid = __raw_readl(CONTROL_IDCODE); + } + + return cpuid; +} + +/****************************************** + * get_cpu_family(void) - extract cpu info + ******************************************/ +u32 get_cpu_family(void) +{ + u16 hawkeye; + u32 cpu_family; + u32 cpuid = get_cpu_id(); + + if (cpuid == 0) + return CPU_OMAP34XX; + + hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff; + switch (hawkeye) { + case HAWKEYE_OMAP34XX: + cpu_family = CPU_OMAP34XX; + break; + case HAWKEYE_AM35XX: + cpu_family = CPU_AM35XX; + break; + case HAWKEYE_OMAP36XX: + cpu_family = CPU_OMAP36XX; + break; + default: + cpu_family = CPU_OMAP34XX; + } + + return cpu_family; +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 cpuid = 0; + /* On ES1.0 the IDCODE register is not exposed on L4 + * so using CPU ID to differentiate + * between ES2.0 and ES1.0. + */ + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); + if ((cpuid & 0xf) == 0x0) + return CPU_3430_ES1; + else + return CPU_3430_ES2; + +} + +/****************************************** + * Print CPU information + ******************************************/ +int print_cpuinfo (void) +{ + char *cpu_family_s, *cpu_s, *sec_s; + + switch (get_cpu_family()) { + case CPU_OMAP34XX: + cpu_family_s = "OMAP"; + switch (get_cpu_type()) { + case OMAP3503: + cpu_s = "3503"; + break; + case OMAP3515: + cpu_s = "3515"; + break; + case OMAP3525: + cpu_s = "3525"; + break; + case OMAP3530: + cpu_s = "3530"; + break; + default: + cpu_s = "35XX"; + break; + } + break; + case CPU_AM35XX: + cpu_family_s = "AM"; + switch (get_cpu_type()) { + case AM3505: + cpu_s = "3505"; + break; + case AM3517: + cpu_s = "3517"; + break; + default: + cpu_s = "35XX"; + break; + } + break; + case CPU_OMAP36XX: + cpu_family_s = "OMAP"; + switch (get_cpu_type()) { + case OMAP3730: + cpu_s = "3630/3730"; + break; + default: + cpu_s = "36XX/37XX"; + break; + } + break; + default: + cpu_family_s = "OMAP"; + cpu_s = "35XX"; + } + + switch (get_device_type()) { + case TST_DEVICE: + sec_s = "TST"; + break; + case EMU_DEVICE: + sec_s = "EMU"; + break; + case HS_DEVICE: + sec_s = "HS"; + break; + case GP_DEVICE: + sec_s = "GP"; + break; + default: + sec_s = "?"; + } + + printf("%s%s-%s ES%s\n", + cpu_family_s, cpu_s, sec_s, rev_s[get_cpu_rev()]); + + return 0; +} + +/****************************************** + * cpu_is_3410(void) - returns true for 3410 + ******************************************/ +u32 cpu_is_3410(void) +{ + int status; + if (get_cpu_rev() < CPU_3430_ES2) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +int gta04_revision(void) +{ + int rev; + static char revision[8] = { /* revision table defined by pull-down R305, R306, R307 */ + 9, + 6, + 7, + 3, + 8, + 4, + 5, + 2 + }; + omap_request_gpio(171); + omap_request_gpio(172); + omap_request_gpio(173); + omap_set_gpio_direction(171, 1); + omap_set_gpio_direction(172, 1); + omap_set_gpio_direction(173, 1); + + rev = omap_get_gpio_datain(173) << 2 | + omap_get_gpio_datain(172) << 1 | + omap_get_gpio_datain(171) << 0; + omap_free_gpio(171); + omap_free_gpio(172); + omap_free_gpio(173); + + return revision[rev]; /* 000 means GTA04A2 */ +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = __raw_readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + __raw_writel(tmp, addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return 1; + if (i == bound) + return 0; + } while (1); +} + +#ifdef CFG_3430SDRAM_DDR + +#define MICRON_DDR 0 +#define NUMONYX_MCP 1 +#define MICRON_MCP 2 + +int identify_xm_ddr(void) +{ +#ifdef CONFIG_NAND + + int mfr, id; + extern int nand_readid(int *mfr, int *id); + + __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); + + /* Enable the GPMC Mapping */ + __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((NAND_BASE_ADR>>24) & 0x3F) | + (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); + delay(2000); + + nand_readid(&mfr, &id); + if (mfr == 0) + return MICRON_DDR; + if ((mfr == 0x20) && (id == 0xba)) + return NUMONYX_MCP; + if ((mfr == 0x2c) && (id == 0xbc)) + return MICRON_MCP; +#endif + return 0; +} + +/********************************************************************* + * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. + *********************************************************************/ +void config_3430sdram_ddr(void) +{ + /* reset sdrc controller */ + __raw_writel(SOFTRESET, SDRC_SYSCONFIG); + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); + __raw_writel(0, SDRC_SYSCONFIG); + + /* setup sdrc to ball mux */ + __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); + + // FIXME: can we not only read the chip maker but also bus clock speed and bank size??? + + switch (identify_xm_ddr()) { + case NUMONYX_MCP: + // should not be used on GTA04 + __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0); + __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1); + __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); + __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); + __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); + __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); + break; + case MICRON_MCP: + // big Micron + __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0); + __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1); + __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0); + __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0); + __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1); + __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1); + break; + case MICRON_DDR: + default: + // small micron + __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); + __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); + __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); + __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); + __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); + break; + } + + __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER); + + /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0); + __raw_writel(CMD_NOP, SDRC_MANUAL_1); + + delay(5000); + + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); + + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); + + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); + + /* set mr0 */ + __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); + __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1); + + /* set up dll */ + __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); + delay(0x2000); /* give time to lock */ + +} +#endif /* CFG_3430SDRAM_DDR */ + +/************************************************************* + * get_sys_clk_speed - determine reference oscillator speed + * based on known 32kHz clock and gptimer. + *************************************************************/ +u32 get_osc_clk_speed(void) +{ + u32 start, cstart, cend, cdiff, cdiv, val; + + val = __raw_readl(PRM_CLKSRC_CTRL); + + if (val & SYSCLKDIV_2) + cdiv = 2; + else + cdiv = 1; + + /* enable timer2 */ + val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; + __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ + + /* Enable I and F Clocks for GPT1 */ + val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; + __raw_writel(val, CM_ICLKEN_WKUP); + val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; + __raw_writel(val, CM_FCLKEN_WKUP); + + __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ + __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ + /* enable 32kHz source */ + /* enabled out of reset */ + /* determine sys_clk via gauging */ + + start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ + while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */ + cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ + while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */ + cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ + cdiff = cend - cstart; /* get elapsed ticks */ + cdiff *= cdiv; + + /* based on number of ticks assign speed */ + if (cdiff > 19000) + return S38_4M; + else if (cdiff > 15200) + return S26M; + else if (cdiff > 13000) + return S24M; + else if (cdiff > 9000) + return S19_2M; + else if (cdiff > 7600) + return S13M; + else + return S12M; +} + +/****************************************************************************** + * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on + * -- input oscillator clock frequency. + * + *****************************************************************************/ +void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) +{ + if (osc_clk == S38_4M) + *sys_clkin_sel = 4; + else if (osc_clk == S26M) + *sys_clkin_sel = 3; + else if (osc_clk == S19_2M) + *sys_clkin_sel = 2; + else if (osc_clk == S13M) + *sys_clkin_sel = 1; + else if (osc_clk == S12M) + *sys_clkin_sel = 0; +} + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * -- called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + u32 osc_clk = 0, sys_clkin_sel; + dpll_param *dpll_param_p; + u32 clk_index, sil_index; + + /* Gauge the input clock speed and find out the sys_clkin_sel + * value corresponding to the input clock. + */ + osc_clk = get_osc_clk_speed(); + get_sys_clkin_sel(osc_clk, &sys_clkin_sel); + + sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ + + /* If the input clock is greater than 19.2M always divide/2 */ + if (sys_clkin_sel > 2) { + sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */ + clk_index = sys_clkin_sel / 2; + } else { + sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */ + clk_index = sys_clkin_sel; + } + + sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ + + /* The DPLL tables are defined according to sysclk value and + * silicon revision. The clk_index value will be used to get + * the values for that input sysclk from the DPLL param table + * and sil_index will get the values for that SysClk for the + * appropriate silicon rev. + */ + sil_index = get_cpu_rev() - 1; + + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address of Core DPLL param table */ + dpll_param_p = (dpll_param *) get_core_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; + /* CORE DPLL */ + /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); + + /* For 3430 ES1.0 Errata 1.50, default value directly doesnt + work. write another value and then default value. */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ + sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ + sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ + sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ + sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ + sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ + sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ + sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ + sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to PER DPLL param table */ + dpll_param_p = (dpll_param *) get_per_dpll_param(); + /* Moving it to the right sysclk base */ + dpll_param_p = dpll_param_p + clk_index; + /* PER DPLL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); + wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ + + if (get_cpu_family() == CPU_OMAP36XX) { + sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */ + sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */ + sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */ + } else { + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ + sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ + } + + sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to MPU DPLL param table */ + dpll_param_p = (dpll_param *) get_mpu_dpll_param(); + + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; + + /* MPU DPLL (unlocked already) */ + sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address to IVA DPLL param table */ + dpll_param_p = (dpll_param *) get_iva_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; + /* IVA DPLL (set to 12*20=240MHz) */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); + sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ + sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ + sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); + + /* Set up GPTimers to sys_clk source only */ + sr32(CM_CLKSEL_PER, 0, 8, 0xff); + sr32(CM_CLKSEL_WKUP, 0, 1, 1); + + delay(5000); +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock(void) +{ + /* Permission values for registers -Full fledged permissions to all */ +#define UNLOCK_1 0xFFFFFFFF +#define UNLOCK_2 0x00000000 +#define UNLOCK_3 0x0000FFFF + /* Protection Module Register Target APE (PM_RT) */ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T */ + mode = get_device_type(); + if (mode == GP_DEVICE) + secure_unlock(); + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called at time when only stack is available. + **********************************************************/ + +void s_init(void) +{ + watchdog_init(); +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP); +#endif + try_unlock_memory(); + set_muxconf_regs(); + delay(100); + per_clocks_enable(); + prcm_init(); + config_3430sdram_ddr(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ + int rev; + print_cpuinfo(); + rev = gta04_revision(); + printf("Board detected: GTA04A%d\n", rev); + switch (identify_xm_ddr()) { + case NUMONYX_MCP: printf("Memory: Numonyx MCP 512MB/bank\n"); break; + case MICRON_MCP: printf("Memory: Micron MCP 256MB/bank\n"); break; + case MICRON_DDR: printf("Memory: Micron DDR 128MB/bank\n"); break; + default: printf("Memory: unknown 128MB/bank\n"); break; + } + return 0; +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + return 0; +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +void per_clocks_enable(void) +{ + /* Enable GP2 timer. */ + sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ + sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ + sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ + +#ifdef CFG_NS16550 + /* UART1 clocks */ + sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); + sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); + + /* UART 3 Clocks */ + sr32(CM_FCLKEN_PER, 11, 1, 0x1); + sr32(CM_ICLKEN_PER, 11, 1, 0x1); + +#endif + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + /* Turn on all 3 I2C clocks */ + sr32(CM_FCLKEN1_CORE, 15, 3, 0x7); + sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */ +#endif + + /* Enable the ICLK for 32K Sync Timer as its used in udelay */ + sr32(CM_ICLKEN_WKUP, 2, 1, 0x1); + + sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON); + sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON); + sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON); + sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON); + sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON); + sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON); + sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON); + sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON); + sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON); + sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON); + sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON); + sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON); + + /* Enable GPIO 5 & GPIO 6 clocks */ + sr32(CM_FCLKEN_PER, 17, 2, 0x3); + sr32(CM_ICLKEN_PER, 17, 2, 0x3); + + delay(1000); +} + +/* Set MUX for UART, GPMC, SDRC, GPIO */ + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT()\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ +MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M4)) /*GPMC_nCS6=gpio_57=gpt11_pwm*/\ + MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPIO_61*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPIO_64*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPIO_65*/\ + MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ + MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ + MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ + MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\ + MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ +MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M4)) /*UART3_CTS_RCTX */\ +MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M4)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(McSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\ + MUX_VAL(CP(McSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\ + MUX_VAL(CP(McSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M4)) /*GPIO_186*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ + MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ +MUX_VAL(CP(ETK_CTL), (IEN | PTU | DIS | M4)) /*GPIO_13*/\ + MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ + MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ + MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ + MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ + MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ + MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ + MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ + MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29 */\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT(); +#if 1 // enable backlight as first boot indication + MUX_VAL(CP(GPMC_nCS6), (IEN | PTU | EN | M4)); /*GPMC_nCS6=gpio_57=gpt11_pwm*/ +#endif +} + +/********************************************************** + * Routine: nand+_init + * Description: Set up nand for nand and jffs2 commands + *********************************************************/ + +int nand_init(void) +{ +#ifdef CONFIG_NAND + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ + + /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0. + * We configure only GPMC CS0 with required values. Configiring other devices + * at other CS is done in u-boot. So we don't have to bother doing it here. + */ + __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); + delay(1000); + +#ifdef CFG_NAND_K9F1G08R0A + if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) { + __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); + + /* Enable the GPMC Mapping */ + __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((NAND_BASE_ADR>>24) & 0x3F) | + (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); + delay(2000); + + if (nand_chip()) { +#ifdef CFG_PRINTF + printf("Unsupported Chip!\n"); +#endif + return 1; + } + } +#endif + +#ifdef CFG_ONENAND + if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) { + __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); + + /* Enable the GPMC Mapping */ + __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((ONENAND_BASE>>24) & 0x3F) | + (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); + delay(2000); + + if (onenand_chip()) { +#ifdef CFG_PRINTF + printf("OneNAND Unsupported !\n"); +#endif + return 1; + } + } +#endif +#endif + return 0; +} + +// 57 for backlight + +#define DEBUG_LED1 149 /* gpio */ +// #define DEBUG_LED2 150 /* gpio */ + +void blinkLEDs(void) +{ + void *p; + + /* Alternately turn the LEDs on and off */ + p = (unsigned long *)OMAP34XX_GPIO5_BASE; + while (1) { + /* turn LED1 on and LED2 off */ + *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED1 % 32); +#ifdef DEBUG_LED2 + *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED2 % 32); +#endif + /* delay for a while */ + delay(1000); + + /* turn LED1 off and LED2 on */ + *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED1 % 32); +#ifdef DEBUG_LED2 + *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED2 % 32); +#endif + /* delay for a while */ + delay(1000); + } +} + +/* optionally do something like blinking LED */ +void board_hang(void) +{ + while (1) + blinkLEDs(); +} + +/****************************************************************************** + * Dummy function to handle errors for EABI incompatibility + *****************************************************************************/ +void raise(void) +{ +} + +/****************************************************************************** + * Dummy function to handle errors for EABI incompatibility + *****************************************************************************/ +void abort(void) +{ +} diff --git a/board/omap3530gta04/platform.S b/board/omap3530gta04/platform.S new file mode 100644 index 0000000..5869270 --- /dev/null +++ b/board/omap3530gta04/platform.S @@ -0,0 +1,360 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * NOTE: 3430 X-loader currently does not use this code. +* It could be removed its is kept for compatabily with u-boot. + * + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = CM_CLKEN_PLL-bypass value + * R1 = CM_CLKSEL1_PLL-m, n, and divider values + * R2 = CM_CLKSEL_CORE-divider values + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + * + * Note: If core unlocks/relocks and SDRAM is running fast already it gets + * confused. A reset of the controller gets it back. Taking away its + * L3 when its not in self refresh seems bad for it. Normally, this code + * runs from flash before SDR is init so that should be ok. + ******************************************************************************/ +.global go_to_speed + go_to_speed: + stmfd sp!, {r4-r6} + + /* move into fast relock bypass */ + ldr r4, pll_ctl_add + str r0, [r4] +wait1: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + beq wait1 /* if lock, loop */ + + /* set new dpll dividers _after_ in bypass */ + ldr r5, pll_div_add1 + str r1, [r5] /* set m, n, m2 */ + ldr r5, pll_div_add2 + str r2, [r5] /* set l3/l4/.. dividers*/ + ldr r5, pll_div_add3 /* wkup */ + ldr r2, pll_div_val3 /* rsm val */ + str r2, [r5] + ldr r5, pll_div_add4 /* gfx */ + ldr r2, pll_div_val4 + str r2, [r5] + ldr r5, pll_div_add5 /* emu */ + ldr r2, pll_div_val5 + str r2, [r5] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r5, flash_cfg3_addr + ldr r2, flash_cfg3_val + str r2, [r5] + ldr r5, flash_cfg4_addr + ldr r2, flash_cfg4_val + str r2, [r5] + ldr r5, flash_cfg5_addr + ldr r2, flash_cfg5_val + str r2, [r5] + ldr r5, flash_cfg1_addr + ldr r2, [r5] + orr r2, r2, #0x3 /* up gpmc divider */ + str r2, [r5] + + /* lock DPLL3 and wait a bit */ + orr r0, r0, #0x7 /* set up for lock mode */ + str r0, [r4] /* lock */ + nop /* ARM slow at this point working at sys_clk */ + nop + nop + nop +wait2: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + bne wait2 /* if lock, loop */ + nop + nop + nop + nop + ldmfd sp!, {r4-r6} + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_div_add1: + .word CM_CLKSEL1_PLL +pll_div_add2: + .word CM_CLKSEL_CORE +pll_div_add3: + .word CM_CLKSEL_WKUP +pll_div_val3: + .word (WKUP_RSM << 1) +pll_div_add4: + .word CM_CLKSEL_GFX +pll_div_val4: + .word (GFX_DIV << 0) +pll_div_add5: + .word CM_CLKSEL1_EMU +pll_div_val5: + .word CLSEL1_EMU_VAL + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + +/* DPLL(1-4) PARAM TABLES */ +/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal + * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). + * The values are defined for all possible sysclk and for ES1 and ES2. + */ + +mpu_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x0FE,0x07,0x05,0x01 +/* ES2 */ +.word 0x0FA,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x17D,0x0C,0x03,0x01 +/* ES2 */ +.word 0x1F4,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x179,0x12,0x04,0x01 +/* ES2 */ +.word 0x271,0x17,0x03,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x17D,0x19,0x03,0x01 +/* ES2 */ +.word 0x0FA,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x1FA,0x32,0x03,0x01 +/* ES2 */ +.word 0x271,0x2F,0x03,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +.globl get_mpu_dpll_param +get_mpu_dpll_param: + adr r0, mpu_dpll_param + mov pc, lr + +iva_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x07D,0x05,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x0FA,0x0C,0x03,0x01 +/* ES2 */ +.word 0x168,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x082,0x09,0x07,0x01 +/* ES2 */ +.word 0x0E1,0x0B,0x06,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x07D,0x0C,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x13F,0x30,0x03,0x01 +/* ES2 */ +.word 0x0E1,0x17,0x06,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +.globl get_iva_dpll_param +get_iva_dpll_param: + adr r0, iva_dpll_param + mov pc, lr + +/* Core DPLL targets for L3 at 166 & L133 */ +core_dpll_param: +/* 12MHz */ +/* ES1 */ +.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 +/* ES2 */ +.word M_12,N_12,FSEL_12,M2_12 +/* 3410 */ +.word M_12,N_12,FSEL_12,M2_12 + +/* 13MHz */ +/* ES1 */ +.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 +/* ES2 */ +.word M_13,N_13,FSEL_13,M2_13 +/* 3410 */ +.word M_13,N_13,FSEL_13,M2_13 + +/* 19.2MHz */ +/* ES1 */ +.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 +/* ES2 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 +/* 3410 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 + +/* 26MHz */ +/* ES1 */ +.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 +/* ES2 */ +.word M_26,N_26,FSEL_26,M2_26 +/* 3410 */ +.word M_26,N_26,FSEL_26,M2_26 + +/* 38.4MHz */ +/* ES1 */ +.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 +/* ES2 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 +/* 3410 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 + +.globl get_core_dpll_param +get_core_dpll_param: + adr r0, core_dpll_param + mov pc, lr + +/* PER DPLL values are same for both ES1 and ES2 */ +per_dpll_param: +/* 12MHz */ +.word 0xD8,0x05,0x07,0x09 + +/* 13MHz */ +.word 0x1B0,0x0C,0x03,0x09 + +/* 19.2MHz */ +.word 0xE1,0x09,0x07,0x09 + +/* 26MHz */ +.word 0xD8,0x0C,0x07,0x09 + +/* 38.4MHz */ +.word 0xE1,0x13,0x07,0x09 + +.globl get_per_dpll_param +get_per_dpll_param: + adr r0, per_dpll_param + mov pc, lr + diff --git a/board/omap3evm/Makefile b/board/omap3evm/Makefile new file mode 100644 index 0000000..d83f45e --- /dev/null +++ b/board/omap3evm/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := omap3evm.o +SOBJS := platform.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/omap3evm/config.mk b/board/omap3evm/config.mk new file mode 100644 index 0000000..a45ec22 --- /dev/null +++ b/board/omap3evm/config.mk @@ -0,0 +1,19 @@ +# (C) Copyright 2006 +# Texas Instruments, +# +# OMAP3EVM board uses OMAP3430 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments# +# +# OMAP3EVM has 1 bank of 128MB mPOP-SDRAM on CS0 +# Physical Address: +# 8000'0000 (bank0) + +# For use if you want X-Loader to relocate from SRAM to DDR +#TEXT_BASE = 0x80e80000 + +# For XIP in 64K of SRAM or debug (GP device has it all availabe) +# SRAM 40200000-4020FFFF base +# initial stack at 0x4020fffc used in s_init (below xloader). +# The run time stack is (above xloader, 2k below) +# If any globals exist there needs to be room for them also +TEXT_BASE = 0x40200800 diff --git a/board/omap3evm/omap3evm.c b/board/omap3evm/omap3evm.c new file mode 100644 index 0000000..16c1f70 --- /dev/null +++ b/board/omap3evm/omap3evm.c @@ -0,0 +1,814 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Jian Zhang + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Used to index into DPLL parameter tables */ +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +}; + +typedef struct dpll_param dpll_param; + +/* Following functions are exported from lowlevel_init.S */ +extern dpll_param * get_mpu_dpll_param(); +extern dpll_param * get_iva_dpll_param(); +extern dpll_param * get_core_dpll_param(); +extern dpll_param * get_per_dpll_param(); + +#define __raw_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +void udelay (unsigned long usecs) { + delay(usecs); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init (void) +{ + return 0; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return(mode >>= 8); +} + +/************************************************ + * get_sysboot_value(void) - return SYS_BOOT[4:0] + ************************************************/ +u32 get_sysboot_value(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK); + return mode; +} +/************************************************************* + * Routine: get_mem_type(void) - returns the kind of memory connected + * to GPMC that we are trying to boot form. Uses SYS BOOT settings. + *************************************************************/ +u32 get_mem_type(void) +{ + u32 mem_type = get_sysboot_value(); + switch (mem_type){ + case 0: + case 2: + case 4: + case 16: + case 22: return GPMC_ONENAND; + + case 1: + case 12: + case 15: + case 21: + case 27: return GPMC_NAND; + + case 3: + case 6: return MMC_ONENAND; + + case 8: + case 11: + case 14: + case 20: + case 26: return GPMC_MDOC; + + case 17: + case 18: + case 24: return MMC_NAND; + + case 7: + case 10: + case 13: + case 19: + case 25: + default: return GPMC_NOR; + } +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 cpuid=0; + /* On ES1.0 the IDCODE register is not exposed on L4 + * so using CPU ID to differentiate + * between ES2.0 and ES1.0. + */ + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); + if((cpuid & 0xf) == 0x0) + return CPU_3430_ES1; + else + return CPU_3430_ES2; + +} + +/****************************************** + * cpu_is_3410(void) - returns true for 3410 + ******************************************/ +u32 cpu_is_3410(void) +{ + int status; + if(get_cpu_rev() < CPU_3430_ES2) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = __raw_readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + __raw_writel(tmp, addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return (1); + if (i == bound) + return (0); + } while (1); +} + +#ifdef CFG_3430SDRAM_DDR +/********************************************************************* + * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. + *********************************************************************/ +void config_3430sdram_ddr(void) +{ + /* reset sdrc controller */ + __raw_writel(SOFTRESET, SDRC_SYSCONFIG); + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); + __raw_writel(0, SDRC_SYSCONFIG); + + /* setup sdrc to ball mux */ + __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); + + /* set mdcfg */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); + + /* set timing */ + if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){ + __raw_writel(INFINEON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); + __raw_writel(INFINEON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); + } + if ((get_mem_type() == GPMC_NAND) ||(get_mem_type() == MMC_NAND)){ + __raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); + __raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); + } + + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); + __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER); + + /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0); + delay(5000); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + + /* set mr0 */ + __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); + + /* set up dll */ + __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); + delay(0x2000); /* give time to lock */ + +} +#endif // CFG_3430SDRAM_DDR + +/************************************************************* + * get_sys_clk_speed - determine reference oscillator speed + * based on known 32kHz clock and gptimer. + *************************************************************/ +u32 get_osc_clk_speed(void) +{ + u32 start, cstart, cend, cdiff, val; + + val = __raw_readl(PRM_CLKSRC_CTRL); + /* If SYS_CLK is being divided by 2, remove for now */ + val = (val & (~BIT7)) | BIT6; + __raw_writel(val, PRM_CLKSRC_CTRL); + + /* enable timer2 */ + val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; + __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ + + /* Enable I and F Clocks for GPT1 */ + val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; + __raw_writel(val, CM_ICLKEN_WKUP); + val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; + __raw_writel(val, CM_FCLKEN_WKUP); + + __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ + __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ + /* enable 32kHz source *//* enabled out of reset */ + /* determine sys_clk via gauging */ + + start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ + while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ + cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ + while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ + cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ + cdiff = cend - cstart; /* get elapsed ticks */ + + /* based on number of ticks assign speed */ + if (cdiff > 19000) + return (S38_4M); + else if (cdiff > 15200) + return (S26M); + else if (cdiff > 13000) + return (S24M); + else if (cdiff > 9000) + return (S19_2M); + else if (cdiff > 7600) + return (S13M); + else + return (S12M); +} + +/****************************************************************************** + * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on + * -- input oscillator clock frequency. + * + *****************************************************************************/ +void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) +{ + if(osc_clk == S38_4M) + *sys_clkin_sel= 4; + else if(osc_clk == S26M) + *sys_clkin_sel = 3; + else if(osc_clk == S19_2M) + *sys_clkin_sel = 2; + else if(osc_clk == S13M) + *sys_clkin_sel = 1; + else if(osc_clk == S12M) + *sys_clkin_sel = 0; +} + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * -- called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + u32 osc_clk=0, sys_clkin_sel; + dpll_param *dpll_param_p; + u32 clk_index, sil_index; + + /* Gauge the input clock speed and find out the sys_clkin_sel + * value corresponding to the input clock. + */ + osc_clk = get_osc_clk_speed(); + get_sys_clkin_sel(osc_clk, &sys_clkin_sel); + + sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ + + /* If the input clock is greater than 19.2M always divide/2 */ + if(sys_clkin_sel > 2) { + sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */ + clk_index = sys_clkin_sel/2; + } else { + sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */ + clk_index = sys_clkin_sel; + } + + /* The DPLL tables are defined according to sysclk value and + * silicon revision. The clk_index value will be used to get + * the values for that input sysclk from the DPLL param table + * and sil_index will get the values for that SysClk for the + * appropriate silicon rev. + */ + sil_index = get_cpu_rev() - 1; + + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address of Core DPLL param table*/ + dpll_param_p = (dpll_param *)get_core_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + 2*clk_index + sil_index; + /* CORE DPLL */ + /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ + sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ + sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ + sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ + sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ + sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ + sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ + sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ + sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to PER DPLL param table*/ + dpll_param_p = (dpll_param *)get_per_dpll_param(); + /* Moving it to the right sysclk base */ + dpll_param_p = dpll_param_p + clk_index; + /* PER DPLL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); + wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ + sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ + sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to MPU DPLL param table*/ + dpll_param_p = (dpll_param *)get_mpu_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + 2*clk_index + sil_index; + /* MPU DPLL (unlocked already) */ + sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address to IVA DPLL param table*/ + dpll_param_p = (dpll_param *)get_iva_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + 2*clk_index + sil_index; + /* IVA DPLL (set to 12*20=240MHz) */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); + sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ + sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ + sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); + + /* Set up GPTimers to sys_clk source only */ + sr32(CM_CLKSEL_PER, 0, 8, 0xff); + sr32(CM_CLKSEL_WKUP, 0, 1, 1); + + delay(5000); +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) { + secure_unlock(); + } + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called at time when only stack is available. + **********************************************************/ + +void s_init(void) +{ + watchdog_init(); +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP); +#endif + try_unlock_memory(); + set_muxconf_regs(); + delay(100); + prcm_init(); + per_clocks_enable(); + config_3430sdram_ddr(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r (void) +{ + return(0); +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init (void) +{ + return 0; +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +void per_clocks_enable(void) +{ + /* Enable GP2 timer. */ + sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ + sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ + sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ + +#ifdef CFG_NS16550 + /* Enable UART1 clocks */ + sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); + sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); +#endif + delay(1000); +} + +/* Set MUX for UART, GPMC, SDRC, GPIO */ + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT()\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\ + MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\ + MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ + MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ + MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ + MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ + MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ + MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ + MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ + MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ + MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ + MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ + MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ + MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ + MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ + MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ + MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT(); +} + +/********************************************************** + * Routine: nand+_init + * Description: Set up nand for nand and jffs2 commands + *********************************************************/ + +int nand_init(void) +{ + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ + + /* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0 + * , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0. + * We configure only GPMC CS0 with required values. Configiring other devices + * at other CS in done in u-boot anyway. So we don't have to bother doing it here. + */ + __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); + delay(1000); + + if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)){ + __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); + + /* Enable the GPMC Mapping */ + __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((NAND_BASE_ADR>>24) & 0x3F) | + (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); + delay(2000); + + if (nand_chip()){ +#ifdef CFG_PRINTF + printf("Unsupported Chip!\n"); +#endif + return 1; + } + + } + + if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){ + __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); + + /* Enable the GPMC Mapping */ + __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((ONENAND_BASE>>24) & 0x3F) | + (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); + delay(2000); + + if (onenand_chip()){ +#ifdef CFG_PRINTF + printf("OneNAND Unsupported !\n"); +#endif + return 1; + } + } + return 0; +} + +/* optionally do something like blinking LED */ +void board_hang (void) +{ while (0) {};} + +/****************************************************************************** + * Dummy function to handle errors for EABI incompatibility + *****************************************************************************/ +void raise(void) +{ +} + +/****************************************************************************** + * Dummy function to handle errors for EABI incompatibility + *****************************************************************************/ +void abort(void) +{ +} diff --git a/board/omap3evm/platform.S b/board/omap3evm/platform.S new file mode 100644 index 0000000..8368487 --- /dev/null +++ b/board/omap3evm/platform.S @@ -0,0 +1,435 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * NOTE: 3430 X-loader currently does not use this code. +* It could be removed its is kept for compatabily with u-boot. + * + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = CM_CLKEN_PLL-bypass value + * R1 = CM_CLKSEL1_PLL-m, n, and divider values + * R2 = CM_CLKSEL_CORE-divider values + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + * + * Note: If core unlocks/relocks and SDRAM is running fast already it gets + * confused. A reset of the controller gets it back. Taking away its + * L3 when its not in self refresh seems bad for it. Normally, this code + * runs from flash before SDR is init so that should be ok. + ******************************************************************************/ +.global go_to_speed + go_to_speed: + stmfd sp!, {r4-r6} + + /* move into fast relock bypass */ + ldr r4, pll_ctl_add + str r0, [r4] +wait1: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + beq wait1 /* if lock, loop */ + + /* set new dpll dividers _after_ in bypass */ + ldr r5, pll_div_add1 + str r1, [r5] /* set m, n, m2 */ + ldr r5, pll_div_add2 + str r2, [r5] /* set l3/l4/.. dividers*/ + ldr r5, pll_div_add3 /* wkup */ + ldr r2, pll_div_val3 /* rsm val */ + str r2, [r5] + ldr r5, pll_div_add4 /* gfx */ + ldr r2, pll_div_val4 + str r2, [r5] + ldr r5, pll_div_add5 /* emu */ + ldr r2, pll_div_val5 + str r2, [r5] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r5, flash_cfg3_addr + ldr r2, flash_cfg3_val + str r2, [r5] + ldr r5, flash_cfg4_addr + ldr r2, flash_cfg4_val + str r2, [r5] + ldr r5, flash_cfg5_addr + ldr r2, flash_cfg5_val + str r2, [r5] + ldr r5, flash_cfg1_addr + ldr r2, [r5] + orr r2, r2, #0x3 /* up gpmc divider */ + str r2, [r5] + + /* lock DPLL3 and wait a bit */ + orr r0, r0, #0x7 /* set up for lock mode */ + str r0, [r4] /* lock */ + nop /* ARM slow at this point working at sys_clk */ + nop + nop + nop +wait2: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + bne wait2 /* if lock, loop */ + nop + nop + nop + nop + ldmfd sp!, {r4-r6} + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_div_add1: + .word CM_CLKSEL1_PLL +pll_div_add2: + .word CM_CLKSEL_CORE +pll_div_add3: + .word CM_CLKSEL_WKUP +pll_div_val3: + .word (WKUP_RSM << 1) +pll_div_add4: + .word CM_CLKSEL_GFX +pll_div_val4: + .word (GFX_DIV << 0) +pll_div_add5: + .word CM_CLKSEL1_EMU +pll_div_val5: + .word CLSEL1_EMU_VAL + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + + +/* DPLL(1-4) PARAM TABLES */ +/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal + * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). + * The values are defined for all possible sysclk and for ES1 and ES2. + */ + +mpu_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x0FE +.word 0x07 +.word 0x05 +.word 0x01 +/* ES2 */ +.word 0x0FA +.word 0x05 +.word 0x07 +.word 0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x17D +.word 0x0C +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x1F4 +.word 0x0C +.word 0x03 +.word 0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x179 +.word 0x12 +.word 0x04 +.word 0x01 +/* ES2 */ +.word 0x271 +.word 0x17 +.word 0x03 +.word 0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x17D +.word 0x19 +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x0FA +.word 0x0C +.word 0x07 +.word 0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x1FA +.word 0x32 +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x271 +.word 0x2F +.word 0x03 +.word 0x01 + + +.globl get_mpu_dpll_param +get_mpu_dpll_param: + adr r0, mpu_dpll_param + mov pc, lr + +iva_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x07D +.word 0x05 +.word 0x07 +.word 0x01 +/* ES2 */ +.word 0x0B4 +.word 0x05 +.word 0x07 +.word 0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x0FA +.word 0x0C +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x168 +.word 0x0C +.word 0x03 +.word 0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x082 +.word 0x09 +.word 0x07 +.word 0x01 +/* ES2 */ +.word 0x0E1 +.word 0x0B +.word 0x06 +.word 0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x07D +.word 0x0C +.word 0x07 +.word 0x01 +/* ES2 */ +.word 0x0B4 +.word 0x0C +.word 0x07 +.word 0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x13F +.word 0x30 +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x0E1 +.word 0x17 +.word 0x06 +.word 0x01 + + +.globl get_iva_dpll_param +get_iva_dpll_param: + adr r0, iva_dpll_param + mov pc, lr + +core_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x19F +.word 0x0E +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x0A6 +.word 0x05 +.word 0x07 +.word 0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x1B2 +.word 0x10 +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x14C +.word 0x0C +.word 0x03 +.word 0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x19F +.word 0x17 +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x19F +.word 0x17 +.word 0x03 +.word 0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x1B2 +.word 0x21 +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x0A6 +.word 0x0C +.word 0x07 +.word 0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x19F +.word 0x2F +.word 0x03 +.word 0x01 +/* ES2 */ +.word 0x19F +.word 0x2F +.word 0x03 +.word 0x01 + +.globl get_core_dpll_param +get_core_dpll_param: + adr r0, core_dpll_param + mov pc, lr + +/* PER DPLL values are same for both ES1 and ES2 */ +per_dpll_param: +/* 12MHz */ +.word 0xD8 +.word 0x05 +.word 0x07 +.word 0x09 + +/* 13MHz */ +.word 0x1B0 +.word 0x0C +.word 0x03 +.word 0x09 + +/* 19.2MHz */ +.word 0xE1 +.word 0x09 +.word 0x07 +.word 0x09 + +/* 26MHz */ +.word 0xD8 +.word 0x0C +.word 0x07 +.word 0x09 + +/* 38.4MHz */ +.word 0xE1 +.word 0x13 +.word 0x07 +.word 0x09 + +.globl get_per_dpll_param +get_per_dpll_param: + adr r0, per_dpll_param + mov pc, lr + diff --git a/board/omap3evm/x-load.lds b/board/omap3evm/x-load.lds new file mode 100644 index 0000000..5f352d3 --- /dev/null +++ b/board/omap3evm/x-load.lds @@ -0,0 +1,54 @@ +/* + * November 2006 - Changed to support 3430sdp device + * Copyright (c) 2004-2006 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap4430panda/Makefile b/board/omap4430panda/Makefile new file mode 100644 index 0000000..6b6f9be --- /dev/null +++ b/board/omap4430panda/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2009 +# Texas Instruments, +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# version 2 as published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := omap4430panda.o clock.o syslib.o +SOBJS := platform.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c new file mode 100644 index 0000000..792e5d6 --- /dev/null +++ b/board/omap4430panda/clock.c @@ -0,0 +1,804 @@ +/* + * (C) Copyright 2009 + * Texas Instruments, + * Richard Woodruff + * Rajendra Nayak + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CONFIG_OMAP4_SDC 1 + +/* Used to index into DPLL parameter tables */ +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int m2; + unsigned int m3; + unsigned int m4; + unsigned int m5; + unsigned int m6; + unsigned int m7; +}; + +/* Tables having M,N,M2 et al values for different sys_clk speeds + * This table is generated only for OPP100 + * The tables are organized as follows: + * Rows : 1 - 12M, 2 - 13M, 3 - 16.8M, 4 - 19.2M, 5 - 26M, 6 - 27M, 7 - 38.4M + */ + +/* MPU parameters */ +struct dpll_param mpu_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values */ +#ifdef CONFIG_MPU_600 + /* RUN MPU @ 600 MHz */ + {0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, +#elif CONFIG_MPU_1000 + {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, +#else + {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, +#endif +}; + +/* IVA parameters */ +struct dpll_param iva_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values */ +#ifdef CONFIG_OMAP4_SDC + {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}, +#else + {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}, +#endif +}; + +/* CORE parameters */ +struct dpll_param core_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values - DDR@200MHz*/ + {0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05}, +}; + +/* CORE parameters - ES2.1 */ +struct dpll_param core_dpll_param_ddr400[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values - DDR@400MHz*/ + {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}, +}; + +/* CORE parameters for L3 at 190 MHz - For ES1 only*/ +struct dpll_param core_dpll_param_l3_190[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values */ +#ifdef CONFIG_OMAP4_SDC +#ifdef CORE_190MHZ + {0x1f0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}, +#else /* Default CORE @166MHz */ + {0x1b0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}, +#endif +#else + {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x08}, +#endif +}; + +/* PER parameters */ +struct dpll_param per_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values */ +#if 0 + /* SDC settings */ + {0x0a, 0x00, 0x04, 0x03, 0x06, 0x05, 0x02, 0x03}, +#endif + {0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05}, +}; + +/* ABE parameters */ +struct dpll_param abe_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values */ +#ifdef CONFIG_OMAP4_SDC + {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0}, +#else + {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0}, +#endif +}; + +/* USB parameters */ +struct dpll_param usb_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values */ +#ifdef CONFIG_OMAP4_SDC + {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, +#else + {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, +#endif +}; + +typedef struct dpll_param dpll_param; + +static void configure_mpu_dpll(u32 clk_index) +{ + dpll_param *dpll_param_p; + + /* Unlock the MPU dpll */ + sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY); + + /* Program MPU DPLL */ + dpll_param_p = &mpu_dpll_param[clk_index]; + + sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */ + + /* Set M,N,M2 values */ + sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param_p->n); + sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param_p->m2); + sr32(CM_DIV_M2_DPLL_MPU, 8, 1, 0x1); + + /* Lock the mpu dpll */ + sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_LOCK | 0x10); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_MPU, LDELAY); + + return; +} + +static void configure_iva_dpll(u32 clk_index) +{ + dpll_param *dpll_param_p; + + /* Unlock the IVA dpll */ + sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_IVA, LDELAY); + + /* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */ + sr32(CM_BYPCLK_DPLL_IVA, 0, 2, 0x1); + + /* Program IVA DPLL */ + dpll_param_p = &iva_dpll_param[clk_index]; + + sr32(CM_AUTOIDLE_DPLL_IVA, 0, 3, 0x0); /* Disable DPLL autoidle */ + + /* Set M,N,M4,M5 */ + sr32(CM_CLKSEL_DPLL_IVA, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_IVA, 0, 7, dpll_param_p->n); + sr32(CM_DIV_M4_DPLL_IVA, 0, 5, dpll_param_p->m4); + sr32(CM_DIV_M4_DPLL_IVA, 8, 1, 0x1); + sr32(CM_DIV_M5_DPLL_IVA, 0, 5, dpll_param_p->m5); + sr32(CM_DIV_M5_DPLL_IVA, 8, 1, 0x1); + + /* Lock the iva dpll */ + sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_LOCK); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_IVA, LDELAY); + + return; +} + +static void configure_per_dpll(u32 clk_index) +{ + dpll_param *dpll_param_p; + + /* Unlock the PER dpll */ + sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_PER, LDELAY); + + /* Program PER DPLL */ + dpll_param_p = &per_dpll_param[clk_index]; + + /* Disable autoidle */ + sr32(CM_AUTOIDLE_DPLL_PER, 0, 3, 0x0); + + sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param_p->n); + sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param_p->m2); + sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param_p->m3); + sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param_p->m4); + sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param_p->m5); + sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6); + sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7); + +// if(omap_revision() == OMAP4430_ES1_0) +// { + /* Do this only on ES1.0 */ + sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1); +// } + + /* Lock the per dpll */ + sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_PER, LDELAY); + + return; +} + +static void configure_abe_dpll(u32 clk_index) +{ + dpll_param *dpll_param_p; + + /* Select sys_clk as ref clk for ABE dpll */ + sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0); + + /* Enable slimbus and pad clocks */ + sr32(CM_CLKSEL_ABE, 0, 32, 0x500); + + /* Unlock the ABE dpll */ + sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY); + + /* Program ABE DPLL */ + dpll_param_p = &abe_dpll_param[clk_index]; + + /* Disable autoidle */ + sr32(CM_AUTOIDLE_DPLL_ABE, 0, 3, 0x0); + + sr32(CM_CLKSEL_DPLL_ABE, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_ABE, 0, 6, dpll_param_p->n); + + /* Force DPLL CLKOUTHIF to stay enabled */ + sr32(CM_DIV_M2_DPLL_ABE, 0, 32, 0x500); + sr32(CM_DIV_M2_DPLL_ABE, 0, 5, dpll_param_p->m2); + sr32(CM_DIV_M2_DPLL_ABE, 8, 1, 0x1); + /* Force DPLL CLKOUTHIF to stay enabled */ + sr32(CM_DIV_M3_DPLL_ABE, 0, 32, 0x100); + sr32(CM_DIV_M3_DPLL_ABE, 0, 5, dpll_param_p->m3); + sr32(CM_DIV_M3_DPLL_ABE, 8, 1, 0x1); + + /* Lock the abe dpll */ + sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_LOCK); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_ABE, LDELAY); + + return; +} + +static void configure_usb_dpll(u32 clk_index) +{ + dpll_param *dpll_param_p; + + /* Select the 60Mhz clock 480/8 = 60*/ + sr32(CM_CLKSEL_USB_60MHz, 0, 32, 0x1); + + /* Unlock the USB dpll */ + sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_USB, LDELAY); + + /* Program USB DPLL */ + dpll_param_p = &usb_dpll_param[clk_index]; + + /* Disable autoidle */ + sr32(CM_AUTOIDLE_DPLL_USB, 0, 3, 0x0); + + sr32(CM_CLKSEL_DPLL_USB, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_USB, 0, 6, dpll_param_p->n); + + /* Force DPLL CLKOUT to stay active */ + sr32(CM_DIV_M2_DPLL_USB, 0, 32, 0x100); + sr32(CM_DIV_M2_DPLL_USB, 0, 5, dpll_param_p->m2); + sr32(CM_DIV_M2_DPLL_USB, 8, 1, 0x1); + sr32(CM_CLKDCOLDO_DPLL_USB, 8, 1, 0x1); + + /* Lock the usb dpll */ + sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_LOCK); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_USB, LDELAY); + + /* force enable the CLKDCOLDO clock */ + sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100); + + return; +} + +static void configure_core_dpll(clk_index) +{ + dpll_param *dpll_param_p; + + /* Get the sysclk speed from cm_sys_clksel + * Set it to 38.4 MHz, in case ROM code is bypassed + */ + if (!clk_index) + return; + + /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */ + sr32(CM_CLKSEL_CORE, 0, 32, 0x110); + + /* Unlock the CORE dpll */ + sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY); + + /* Program Core DPLL */ + if(omap_revision() == OMAP4430_ES1_0) + dpll_param_p = &core_dpll_param_l3_190[clk_index]; + else if(omap_revision() == OMAP4430_ES2_0) + dpll_param_p = &core_dpll_param[clk_index]; + else if(omap_revision() == OMAP4430_ES2_1) + dpll_param_p = &core_dpll_param_ddr400[clk_index]; + + /* Disable autoidle */ + sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0); + + sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n); + sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2); + sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3); + sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4); + sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5); + sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6); + sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7); + + if(omap_revision() == OMAP4430_ES1_0) + { + /* Do this only on ES1.0 */ + sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); + } + + + /* Lock the core dpll */ + sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); + + return; +} + + +void configure_core_dpll_no_lock(void) +{ + dpll_param *dpll_param_p; + u32 clk_index; + + /* Get the sysclk speed from cm_sys_clksel + * Set it to 38.4 MHz, in case ROM code is bypassed + */ + __raw_writel(0x7,CM_SYS_CLKSEL); + clk_index = 7; + + clk_index = clk_index - 1; + /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */ + sr32(CM_CLKSEL_CORE, 0, 32, 0x110); + + /* Unlock the CORE dpll */ + sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY); + + /* Program Core DPLL */ + if(omap_revision() == OMAP4430_ES1_0) + dpll_param_p = &core_dpll_param_l3_190[clk_index]; + else if(omap_revision() == OMAP4430_ES2_0) + dpll_param_p = &core_dpll_param[clk_index]; + else if(omap_revision() == OMAP4430_ES2_1) + dpll_param_p = &core_dpll_param_ddr400[clk_index]; + + /* Disable autoidle */ + sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0); + + sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n); + sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2); + sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3); + sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4); + sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5); + sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6); + sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7); + +// if(omap_revision() == OMAP4430_ES1_0) +// { + /* Do this only on ES1.0 */ + sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); +// } + + return; +} + +void lock_core_dpll(void) +{ + /* Lock the core dpll */ + sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); + + return; +} + +void lock_core_dpll_shadow(void) +{ + dpll_param *dpll_param_p; + /* Lock the core dpll using freq update method */ + *(volatile int*)0x4A004120 = 10; //(CM_CLKMODE_DPLL_CORE) + + if(omap_revision() == OMAP4430_ES1_0) + dpll_param_p = &core_dpll_param_l3_190[6]; + else if(omap_revision() == OMAP4430_ES2_0) + dpll_param_p = &core_dpll_param[6]; + else if(omap_revision() == OMAP4430_ES2_1) + dpll_param_p = &core_dpll_param_ddr400[6]; + + /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1, + * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1 + */ + *(volatile int*)0x4A004260 = 0x70D | (dpll_param_p->m2 << 11); + + /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */ + while( ( (*(volatile int*)0x4A004260) & 0x1) == 0x1 ); + + /* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */ + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); + //lock_core_dpll(); + + return; +} + +static void enable_all_clocks(void) +{ + volatile int regvalue = 0; + + /* Enable Ducati clocks */ + sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1); + sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2); + + wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY); + + /* Enable ivahd and sl2 clocks */ + sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1); + sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1); + sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2); + + wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY); + + /* wait for ivahd to become accessible */ + //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY); + /* wait for sl2 to become accessible */ + //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY); + + /* Enable Tesla clocks */ + sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1); + sr32(DSP_CLKSTCTRL, 0, 32, 0x2); + + wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY); + + /* wait for tesla to become accessible */ + //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY); + + /* TODO: Some hack needed by MM: Clean this */ + #if 0 /* Doesn't work on some Zebu */ + *(volatile int*)0x4a306910 = 0x00000003; + *(volatile int*)0x550809a0 = 0x00000001; + *(volatile int*)0x55080a20 = 0x00000007; + #endif + + /* ABE clocks */ + sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3); + sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY); + sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY); + sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY); + sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY); + sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY); + sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY); + sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY); + sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY); + sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY); + sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY); + sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY); + sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY); + sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY); + /* Disable sleep transitions */ + sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0); + + /* L4PER clocks */ + sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2); + sr32(CM_L4PER_DMTIMER10_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER10_CLKCTRL, LDELAY); + sr32(CM_L4PER_DMTIMER11_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER11_CLKCTRL, LDELAY); + sr32(CM_L4PER_DMTIMER2_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER2_CLKCTRL, LDELAY); + sr32(CM_L4PER_DMTIMER3_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER3_CLKCTRL, LDELAY); + sr32(CM_L4PER_DMTIMER4_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER4_CLKCTRL, LDELAY); + sr32(CM_L4PER_DMTIMER9_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY); + + /* GPIO clocks */ + sr32(CM_L4PER_GPIO2_CLKCTRL, 0 ,32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY); + + sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2); + + /* I2C clocks */ + sr32(CM_L4PER_I2C1_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C1_CLKCTRL, LDELAY); + sr32(CM_L4PER_I2C2_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C2_CLKCTRL, LDELAY); + sr32(CM_L4PER_I2C3_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C3_CLKCTRL, LDELAY); + sr32(CM_L4PER_I2C4_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C4_CLKCTRL, LDELAY); + + sr32(CM_L4PER_MCBSP4_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCBSP4_CLKCTRL, LDELAY); + + /* MCSPI clocks */ + sr32(CM_L4PER_MCSPI1_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI1_CLKCTRL, LDELAY); + sr32(CM_L4PER_MCSPI2_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI2_CLKCTRL, LDELAY); + sr32(CM_L4PER_MCSPI3_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI3_CLKCTRL, LDELAY); + sr32(CM_L4PER_MCSPI4_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI4_CLKCTRL, LDELAY); + + /* MMC clocks */ + sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2); + sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC1_CLKCTRL, LDELAY); + sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2); + sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC2_CLKCTRL, LDELAY); + sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY); + sr32(CM_L4PER_MMCSD4_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD4_CLKCTRL, LDELAY); + sr32(CM_L4PER_MMCSD5_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_MMCSD5_CLKCTRL, LDELAY); + + /* UART clocks */ + sr32(CM_L4PER_UART1_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART1_CLKCTRL, LDELAY); + sr32(CM_L4PER_UART2_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART2_CLKCTRL, LDELAY); + sr32(CM_L4PER_UART3_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART3_CLKCTRL, LDELAY); + sr32(CM_L4PER_UART4_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART4_CLKCTRL, LDELAY); + + /* WKUP clocks */ + sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY); + sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002); + wait_on_value(BIT17|BIT16, 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY); + + sr32(CM_WKUP_KEYBOARD_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_WKUP_KEYBOARD_CLKCTRL, LDELAY); + + sr32(CM_SDMA_CLKSTCTRL, 0, 32, 0x0); + sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x3); + sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_1_CLKCTRL, LDELAY); + sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_2_CLKCTRL, LDELAY); + sr32(CM_D2D_CLKSTCTRL, 0, 32, 0x3); + sr32(CM_L3_2_GPMC_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L3_2_GPMC_CLKCTRL, LDELAY); + sr32(CM_L3INSTR_L3_3_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_3_CLKCTRL, LDELAY); + sr32(CM_L3INSTR_L3_INSTR_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_INSTR_CLKCTRL, LDELAY); + sr32(CM_L3INSTR_OCP_WP1_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_OCP_WP1_CLKCTRL, LDELAY); + + /* WDT clocks */ + sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY); + + /* Enable Camera clocks */ + sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3); + sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY); + sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY); + sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0); + + /* Enable DSS clocks */ + /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */ + *(volatile int*)0x4A307100 = 0x7; //DSS_PRM + sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2); + sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY); + sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY); + /* Check for DSS Clocks */ + while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00) + /* Set HW_AUTO transition mode */ + sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3); + + /* Enable SGX clocks */ + sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2); + sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY); + /* Check for SGX FCLK and ICLK */ + while ( (*(volatile int*)0x4A009200) != 0x302 ); + //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0); + /* Enable hsi/unipro/usb clocks */ + sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY); + sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY); + sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY); + sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY); + sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1); + //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY); + sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY); + /* enable the 32K, 48M optional clocks and enable the module */ + sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301); + //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY); + return; +} + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * -- called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + u32 clk_index; + + /* Get the sysclk speed from cm_sys_clksel + * Set the CM_SYS_CLKSEL in case ROM code has not set + */ + __raw_writel(0x7,CM_SYS_CLKSEL); + clk_index = readl(CM_SYS_CLKSEL); + if (!clk_index) + return; /* Sys clk uninitialized */ + /* Core DPLL is locked using FREQ update method */ + /* configure_core_dpll(clk_index - 1); */ + + /* Configure all DPLL's at 100% OPP */ + configure_mpu_dpll(clk_index - 1); + configure_iva_dpll(clk_index - 1); + configure_per_dpll(clk_index - 1); + configure_abe_dpll(clk_index - 1); + configure_usb_dpll(clk_index - 1); + +#ifdef CONFIG_OMAP4_SDC + /* Enable all clocks */ + enable_all_clocks(); +#endif + + return; +} diff --git a/board/omap4430panda/config.mk b/board/omap4430panda/config.mk new file mode 100644 index 0000000..01173eb --- /dev/null +++ b/board/omap4430panda/config.mk @@ -0,0 +1,21 @@ +# +# (C) Copyright 2006-2009 +# Texas Instruments, +# +# SDP4430 board uses ARM-CortexA9 cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x40304350 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c new file mode 100644 index 0000000..5695733 --- /dev/null +++ b/board/omap4430panda/omap4430panda.c @@ -0,0 +1,1235 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#include +#endif + +/* EMIF and DMM registers */ +#define EMIF1_BASE 0x4c000000 +#define EMIF2_BASE 0x4d000000 +#define DMM_BASE 0x4e000000 +/* EMIF */ +#define EMIF_MOD_ID_REV 0x0000 +#define EMIF_STATUS 0x0004 +#define EMIF_SDRAM_CONFIG 0x0008 +#define EMIF_LPDDR2_NVM_CONFIG 0x000C +#define EMIF_SDRAM_REF_CTRL 0x0010 +#define EMIF_SDRAM_REF_CTRL_SHDW 0x0014 +#define EMIF_SDRAM_TIM_1 0x0018 +#define EMIF_SDRAM_TIM_1_SHDW 0x001C +#define EMIF_SDRAM_TIM_2 0x0020 +#define EMIF_SDRAM_TIM_2_SHDW 0x0024 +#define EMIF_SDRAM_TIM_3 0x0028 +#define EMIF_SDRAM_TIM_3_SHDW 0x002C +#define EMIF_LPDDR2_NVM_TIM 0x0030 +#define EMIF_LPDDR2_NVM_TIM_SHDW 0x0034 +#define EMIF_PWR_MGMT_CTRL 0x0038 +#define EMIF_PWR_MGMT_CTRL_SHDW 0x003C +#define EMIF_LPDDR2_MODE_REG_DATA 0x0040 +#define EMIF_LPDDR2_MODE_REG_CFG 0x0050 +#define EMIF_L3_CONFIG 0x0054 +#define EMIF_L3_CFG_VAL_1 0x0058 +#define EMIF_L3_CFG_VAL_2 0x005C +#define IODFT_TLGC 0x0060 +#define EMIF_PERF_CNT_1 0x0080 +#define EMIF_PERF_CNT_2 0x0084 +#define EMIF_PERF_CNT_CFG 0x0088 +#define EMIF_PERF_CNT_SEL 0x008C +#define EMIF_PERF_CNT_TIM 0x0090 +#define EMIF_READ_IDLE_CTRL 0x0098 +#define EMIF_READ_IDLE_CTRL_SHDW 0x009c +#define EMIF_ZQ_CONFIG 0x00C8 +#define EMIF_DDR_PHY_CTRL_1 0x00E4 +#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00E8 +#define EMIF_DDR_PHY_CTRL_2 0x00EC + +#define DMM_LISA_MAP_0 0x0040 +#define DMM_LISA_MAP_1 0x0044 +#define DMM_LISA_MAP_2 0x0048 +#define DMM_LISA_MAP_3 0x004C + +#define MR0_ADDR 0 +#define MR1_ADDR 1 +#define MR2_ADDR 2 +#define MR4_ADDR 4 +#define MR10_ADDR 10 +#define MR16_ADDR 16 +#define REF_EN 0x40000000 +/* defines for MR1 */ +#define MR1_BL4 2 +#define MR1_BL8 3 +#define MR1_BL16 4 + +#define MR1_BT_SEQ 0 +#define BT_INT 1 + +#define MR1_WC 0 +#define MR1_NWC 1 + +#define MR1_NWR3 1 +#define MR1_NWR4 2 +#define MR1_NWR5 3 +#define MR1_NWR6 4 +#define MR1_NWR7 5 +#define MR1_NWR8 6 + +#define MR1_VALUE (MR1_NWR3 << 5) | (MR1_WC << 4) | (MR1_BT_SEQ << 3) \ + | (MR1_BL8 << 0) + +/* defines for MR2 */ +#define MR2_RL3_WL1 1 +#define MR2_RL4_WL2 2 +#define MR2_RL5_WL2 3 +#define MR2_RL6_WL3 4 + +/* defines for MR10 */ +#define MR10_ZQINIT 0xFF +#define MR10_ZQRESET 0xC3 +#define MR10_ZQCL 0xAB +#define MR10_ZQCS 0x56 + + +/* TODO: FREQ update method is not working so shadow registers programming + * is just for same of completeness. This would be safer if auto + * trasnitions are working + */ +#define FREQ_UPDATE_EMIF +/* EMIF Needs to be configured@19.2 MHz and shadow registers + * should be programmed for new OPP. + */ +/* Elpida 2x2Gbit */ +#define SDRAM_CONFIG_INIT 0x80800EB1 +#define DDR_PHY_CTRL_1_INIT 0x849FFFF5 +#define READ_IDLE_CTRL 0x000501FF +#define PWR_MGMT_CTRL 0x4000000f +#define PWR_MGMT_CTRL_OPP100 0x4000000f +#define ZQ_CONFIG 0x500b3215 + +#define CS1_MR(mr) ((mr) | 0x80000000) +struct ddr_regs{ + u32 tim1; + u32 tim2; + u32 tim3; + u32 phy_ctrl_1; + u32 ref_ctrl; + u32 config_init; + u32 config_final; + u32 zq_config; + u8 mr1; + u8 mr2; +}; +const struct ddr_regs ddr_regs_380_mhz = { + .tim1 = 0x10cb061a, + .tim2 = 0x20350d52, + .tim3 = 0x00b1431f, + .phy_ctrl_1 = 0x849FF408, + .ref_ctrl = 0x000005ca, + .config_init = 0x80000eb1, + .config_final = 0x80001ab1, + .zq_config = 0x500b3215, + .mr1 = 0x83, + .mr2 = 0x4 +}; + +/* + * Unused timings - but we may need them later + * Keep them commented + */ +#if 0 +const struct ddr_regs ddr_regs_400_mhz = { + .tim1 = 0x10eb065a, + .tim2 = 0x20370dd2, + .tim3 = 0x00b1c33f, + .phy_ctrl_1 = 0x849FF408, + .ref_ctrl = 0x00000618, + .config_init = 0x80000eb1, + .config_final = 0x80001ab1, + .zq_config = 0x500b3215, + .mr1 = 0x83, + .mr2 = 0x4 +}; + +const struct ddr_regs ddr_regs_200_mhz = { + .tim1 = 0x08648309, + .tim2 = 0x101b06ca, + .tim3 = 0x0048a19f, + .phy_ctrl_1 = 0x849FF405, + .ref_ctrl = 0x0000030c, + .config_init = 0x80000eb1, + .config_final = 0x80000eb1, + .zq_config = 0x500b3215, + .mr1 = 0x23, + .mr2 = 0x1 +}; +#endif + +const struct ddr_regs ddr_regs_200_mhz_2cs = { + .tim1 = 0x08648309, + .tim2 = 0x101b06ca, + .tim3 = 0x0048a19f, + .phy_ctrl_1 = 0x849FF405, + .ref_ctrl = 0x0000030c, + .config_init = 0x80000eb9, + .config_final = 0x80000eb9, + .zq_config = 0xD00b3215, + .mr1 = 0x23, + .mr2 = 0x1 +}; + +const struct ddr_regs ddr_regs_400_mhz_2cs = { + /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/ + .tim1 = 0x10eb0662, + .tim2 = 0x20370dd2, + .tim3 = 0x00b1c33f, + .phy_ctrl_1 = 0x849FF408, + .ref_ctrl = 0x00000618, + .config_init = 0x80000eb9, + .config_final = 0x80001ab9, + .zq_config = 0xD00b3215, + .mr1 = 0x83, + .mr2 = 0x4 +}; + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0"(loops)); +} + + +void big_delay(unsigned int count) +{ + int i; + for (i=0; iconfig_init; + + /* PHY control values */ + *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = DDR_PHY_CTRL_1_INIT; + *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1_SHDW)= ddr_regs->phy_ctrl_1; + + /* + * EMIF_READ_IDLE_CTRL + */ + *(volatile int*)(base + EMIF_READ_IDLE_CTRL) = READ_IDLE_CTRL; + *(volatile int*)(base + EMIF_READ_IDLE_CTRL_SHDW) = READ_IDLE_CTRL; + + /* + * EMIF_SDRAM_TIM_1 + */ + *(volatile int*)(base + EMIF_SDRAM_TIM_1) = ddr_regs->tim1; + *(volatile int*)(base + EMIF_SDRAM_TIM_1_SHDW) = ddr_regs->tim1; + + /* + * EMIF_SDRAM_TIM_2 + */ + *(volatile int*)(base + EMIF_SDRAM_TIM_2) = ddr_regs->tim2; + *(volatile int*)(base + EMIF_SDRAM_TIM_2_SHDW) = ddr_regs->tim2; + + /* + * EMIF_SDRAM_TIM_3 + */ + *(volatile int*)(base + EMIF_SDRAM_TIM_3) = ddr_regs->tim3; + *(volatile int*)(base + EMIF_SDRAM_TIM_3_SHDW) = ddr_regs->tim3; + + *(volatile int*)(base + EMIF_ZQ_CONFIG) = ddr_regs->zq_config; + /* + * EMIF_PWR_MGMT_CTRL + */ + //*(volatile int*)(base + EMIF_PWR_MGMT_CTRL) = PWR_MGMT_CTRL; + //*(volatile int*)(base + EMIF_PWR_MGMT_CTRL_SHDW) = PWR_MGMT_CTRL_OPP100; + /* + * poll MR0 register (DAI bit) + * REG_CS[31] = 0 -- Mode register command to CS0 + * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW + * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW + */ + + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = MR0_ADDR; + do { + reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA); + } while ((reg_value & 0x1) != 0); + + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR0_ADDR); + do { + reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA); + } while ((reg_value & 0x1) != 0); + + + /* set MR10 register */ + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR10_ADDR; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR10_ADDR); + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT; + + /* wait for tZQINIT=1us */ + delay(10); + + /* set MR1 register */ + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR1_ADDR; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR1_ADDR); + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1; + + + /* set MR2 register RL=6 for OPP100 */ + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR2_ADDR; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR2_ADDR); + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2; + + /* Set SDRAM CONFIG register again here with final RL-WL value */ + *(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config_final; + *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = ddr_regs->phy_ctrl_1; + + /* + * EMIF_SDRAM_REF_CTRL + * refresh rate = DDR_CLK / reg_refresh_rate + * 3.9 uS = (400MHz) / reg_refresh_rate + */ + *(volatile int*)(base + EMIF_SDRAM_REF_CTRL) = ddr_regs->ref_ctrl; + *(volatile int*)(base + EMIF_SDRAM_REF_CTRL_SHDW) = ddr_regs->ref_ctrl; + + /* set MR16 register */ + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR16_ADDR | REF_EN; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = + CS1_MR(MR16_ADDR | REF_EN); + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0; + /* LPDDR2 init complete */ + +} +/***************************************** + * Routine: ddr_init + * Description: Configure DDR + * EMIF1 -- CS0 -- DDR1 (256 MB) + * EMIF2 -- CS0 -- DDR2 (256 MB) + *****************************************/ +static void ddr_init(void) +{ + unsigned int base_addr, rev; + rev = omap_revision(); + + if (rev == OMAP4430_ES1_0) + { + /* Configurte the Control Module DDRIO device */ + __raw_writel(0x1c1c1c1c, 0x4A100638); + __raw_writel(0x1c1c1c1c, 0x4A10063c); + __raw_writel(0x1c1c1c1c, 0x4A100640); + __raw_writel(0x1c1c1c1c, 0x4A100648); + __raw_writel(0x1c1c1c1c, 0x4A10064c); + __raw_writel(0x1c1c1c1c, 0x4A100650); + /* LPDDR2IO set to NMOS PTV */ + __raw_writel(0x00ffc000, 0x4A100704); + } else if (rev == OMAP4430_ES2_0) { + __raw_writel(0x9e9e9e9e, 0x4A100638); + __raw_writel(0x9e9e9e9e, 0x4A10063c); + __raw_writel(0x9e9e9e9e, 0x4A100640); + __raw_writel(0x9e9e9e9e, 0x4A100648); + __raw_writel(0x9e9e9e9e, 0x4A10064c); + __raw_writel(0x9e9e9e9e, 0x4A100650); + /* LPDDR2IO set to NMOS PTV */ + __raw_writel(0x00ffc000, 0x4A100704); + } + + /* + * DMM Configuration + */ + + /* Both EMIFs 128 byte interleaved*/ + if (rev == OMAP4430_ES1_0) + *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80540300; + else + *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80640300; + + /* EMIF2 only at 0x90000000 */ + //*(volatile int*)(DMM_BASE + DMM_LISA_MAP_1) = 0x90400200; + + *(volatile int*)(DMM_BASE + DMM_LISA_MAP_2) = 0x00000000; + *(volatile int*)(DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100; + + /* DDR needs to be initialised @ 19.2 MHz + * So put core DPLL in bypass mode + * Configure the Core DPLL but don't lock it + */ + configure_core_dpll_no_lock(); + + /* No IDLE: BUG in SDC */ + //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); + //while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); + *(volatile int*)(EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; + *(volatile int*)(EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; + + base_addr = EMIF1_BASE; + emif_config(base_addr); + + /* Configure EMIF24D */ + base_addr = EMIF2_BASE; + emif_config(base_addr); + /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */ + lock_core_dpll_shadow(); + /* TODO: SDC needs few hacks to get DDR freq update working */ + + /* Set DLL_OVERRIDE = 0 */ + *(volatile int*)CM_DLL_CTRL = 0x0; + + delay(200); + + /* Check for DDR PHY ready for EMIF1 & EMIF2 */ + while((((*(volatile int*)(EMIF1_BASE + EMIF_STATUS))&(0x04)) != 0x04) \ + || (((*(volatile int*)(EMIF2_BASE + EMIF_STATUS))&(0x04)) != 0x04)); + + /* Reprogram the DDR PYHY Control register */ + /* PHY control values */ + + sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1); + sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1); + + /* Put the Core Subsystem PD to ON State */ + + /* No IDLE: BUG in SDC */ + //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); + //while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); + *(volatile int*)(EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; + *(volatile int*)(EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; + + /* SYSTEM BUG: + * In n a specific situation, the OCP interface between the DMM and + * EMIF may hang. + * 1. A TILER port is used to perform 2D burst writes of + * width 1 and height 8 + * 2. ELLAn port is used to perform reads + * 3. All accesses are routed to the same EMIF controller + * + * Work around to avoid this issue REG_SYS_THRESH_MAX value should + * be kept higher than default 0x7. As per recommondation 0x0A will + * be used for better performance with REG_LL_THRESH_MAX = 0x00 + */ + if (rev == OMAP4430_ES1_0) { + *(volatile int*)(EMIF1_BASE + EMIF_L3_CONFIG) = 0x0A0000FF; + *(volatile int*)(EMIF2_BASE + EMIF_L3_CONFIG) = 0x0A0000FF; + } + + /* + * DMM : DMM_LISA_MAP_0(Section_0) + * [31:24] SYS_ADDR 0x80 + * [22:20] SYS_SIZE 0x7 - 2Gb + * [19:18] SDRC_INTLDMM 0x1 - 128 byte + * [17:16] SDRC_ADDRSPC 0x0 + * [9:8] SDRC_MAP 0x3 + * [7:0] SDRC_ADDR 0X0 + */ + reset_phy(EMIF1_BASE); + reset_phy(EMIF2_BASE); + + *((volatile int *)0x80000000) = 0; + *((volatile int *)0x80000080) = 0; + //*((volatile int *)0x90000000) = 0; +} +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + return 0; +} + +/************************************************************* + * Routine: get_mem_type(void) - returns the kind of memory connected + * to GPMC that we are trying to boot form. Uses SYS BOOT settings. + *************************************************************/ +u32 get_mem_type(void) +{ + /* no nand, so return GPMC_NONE */ + return GPMC_NONE; +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock_mem(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP/EMU(special) type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + return; +} + + +#if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000) +static scale_vcores(void) +{ + unsigned int rev = omap_revision(); + /* For VC bypass only VCOREx_CGF_FORCE is necessary and + * VCOREx_CFG_VOLTAGE changes can be discarded + */ + /* PRM_VC_CFG_I2C_MODE */ + *(volatile int*)(0x4A307BA8) = 0x0; + /* PRM_VC_CFG_I2C_CLK */ + *(volatile int*)(0x4A307BAC) = 0x6026; + + /* set VCORE1 force VSEL */ + /* PRM_VC_VAL_BYPASS) */ + if(rev == OMAP4430_ES1_0) + *(volatile int*)(0x4A307BA0) = 0x3B5512; + else + *(volatile int*)(0x4A307BA0) = 0x3A5512; + + *(volatile int*)(0x4A307BA0) |= 0x1000000; + while((*(volatile int*)(0x4A307BA0)) & 0x1000000); + + /* PRM_IRQSTATUS_MPU */ + *(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010); + + + /* FIXME: set VCORE2 force VSEL, Check the reset value */ + /* PRM_VC_VAL_BYPASS) */ + if(rev == OMAP4430_ES1_0) + *(volatile int*)(0x4A307BA0) = 0x315B12; + else + *(volatile int*)(0x4A307BA0) = 0x295B12; + *(volatile int*)(0x4A307BA0) |= 0x1000000; + while((*(volatile int*)(0x4A307BA0)) & 0x1000000); + + /* PRM_IRQSTATUS_MPU */ + *(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010); + + /*/set VCORE3 force VSEL */ + /* PRM_VC_VAL_BYPASS */ + if(rev == OMAP4430_ES1_0) + *(volatile int*)(0x4A307BA0) = 0x316112; + else if (rev == OMAP4430_ES2_0) + *(volatile int*)(0x4A307BA0) = 0x296112; + else if (rev == OMAP4430_ES2_1) + *(volatile int*)(0x4A307BA0) = 0x2A6112; + *(volatile int*)(0x4A307BA0) |= 0x1000000; + while((*(volatile int*)(0x4A307BA0)) & 0x1000000); + + /* PRM_IRQSTATUS_MPU */ + *(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010); + +} +#endif + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with SRAM stack. + **********************************************************/ + +void s_init(void) +{ + unsigned int rev = omap_revision(); + + set_muxconf_regs(); + delay(100); + + /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ + /* Currently SMI in Kernel on ES2 devices seems to have an isse + * Once that is resolved, we can postpone this config to kernel + */ + //setup_auxcr(get_device_type(), external_boot); + + ddr_init(); + +/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ +#if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000) + scale_vcores(); +#endif + prcm_init(); + + if(rev != OMAP4430_ES1_0) { + if (__raw_readl(0x4805D138) & (1<<22)) { + sr32(0x4A30a31C, 8, 1, 0x1); /* enable software ioreq */ + sr32(0x4A30a31C, 1, 2, 0x0); /* set for sys_clk (38.4MHz) */ + sr32(0x4A30a31C, 16, 4, 0x1); /* set divisor to 2 */ + sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */ + sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ + } + else { + sr32(0x4A30a314, 8, 1, 0x1); /* enable software ioreq */ + sr32(0x4A30a314, 1, 2, 0x2); /* set for PER_DPLL */ + sr32(0x4A30a314, 16, 4, 0xf); /* set divisor to 16 */ + sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */ + sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ + } + } + +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ + return 0; +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + return 0; +} + +#define OMAP44XX_WKUP_CTRL_BASE 0x4A31E000 +#if 1 +#define M0_SAFE M0 +#define M1_SAFE M1 +#define M2_SAFE M2 +#define M4_SAFE M4 +#define M7_SAFE M7 +#define M3_SAFE M3 +#define M5_SAFE M5 +#define M6_SAFE M6 +#else +#define M0_SAFE M7 +#define M1_SAFE M7 +#define M2_SAFE M7 +#define M4_SAFE M7 +#define M7_SAFE M7 +#define M3_SAFE M7 +#define M5_SAFE M7 +#define M6_SAFE M7 +#endif +#define MV(OFFSET, VALUE)\ + __raw_writew((VALUE), OMAP44XX_CTRL_BASE + (OFFSET)); +#define MV1(OFFSET, VALUE)\ + __raw_writew((VALUE), OMAP44XX_WKUP_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +#define WK(x) (CONTROL_WKUP_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ + +#define MUX_DEFAULT_OMAP4() \ + MV(CP(GPMC_AD0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \ + MV(CP(GPMC_AD1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \ + MV(CP(GPMC_AD2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat2 */ \ + MV(CP(GPMC_AD3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat3 */ \ + MV(CP(GPMC_AD4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat4 */ \ + MV(CP(GPMC_AD5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat5 */ \ + MV(CP(GPMC_AD6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat6 */ \ + MV(CP(GPMC_AD7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat7 */ \ + MV(CP(GPMC_AD8) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_32 */ \ + MV(CP(GPMC_AD9) , ( PTU | IEN | M3)) /* gpio_33 */ \ + MV(CP(GPMC_AD10) , ( PTU | IEN | M3)) /* gpio_34 */ \ + MV(CP(GPMC_AD11) , ( PTU | IEN | M3)) /* gpio_35 */ \ + MV(CP(GPMC_AD12) , ( PTU | IEN | M3)) /* gpio_36 */ \ + MV(CP(GPMC_AD13) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_37 */ \ + MV(CP(GPMC_AD14) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_38 */ \ + MV(CP(GPMC_AD15) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \ + MV(CP(GPMC_A16) , ( M3)) /* gpio_40 */ \ + MV(CP(GPMC_A17) , ( PTD | M3)) /* gpio_41 */ \ + MV(CP(GPMC_A18) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row6 */ \ + MV(CP(GPMC_A19) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \ + MV(CP(GPMC_A20) , ( IEN | M3)) /* gpio_44 */ \ + MV(CP(GPMC_A21) , ( M3)) /* gpio_45 */ \ + MV(CP(GPMC_A22) , ( M3)) /* gpio_46 */ \ + MV(CP(GPMC_A23) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \ + MV(CP(GPMC_A24) , ( PTD | M3)) /* gpio_48 */ \ + MV(CP(GPMC_A25) , ( PTD | M3)) /* gpio_49 */ \ + MV(CP(GPMC_NCS0) , ( M3)) /* gpio_50 */ \ + MV(CP(GPMC_NCS1) , ( IEN | M3)) /* gpio_51 */ \ + MV(CP(GPMC_NCS2) , ( IEN | M3)) /* gpio_52 */ \ + MV(CP(GPMC_NCS3) , ( IEN | M3)) /* gpio_53 */ \ + MV(CP(GPMC_NWP) , ( M3)) /* gpio_54 */ \ + MV(CP(GPMC_CLK) , ( PTD | M3)) /* gpio_55 */ \ + MV(CP(GPMC_NADV_ALE) , ( M3)) /* gpio_56 */ \ + MV(CP(GPMC_NOE) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)) /* sdmmc2_clk */ \ + MV(CP(GPMC_NWE) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_cmd */ \ + MV(CP(GPMC_NBE0_CLE) , ( M3)) /* gpio_59 */ \ + MV(CP(GPMC_NBE1) , ( PTD | M3)) /* gpio_60 */ \ + MV(CP(GPMC_WAIT0) , ( PTU | IEN | M3)) /* gpio_61 */ \ + MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_62 */ \ + MV(CP(C2C_DATA11) , ( PTD | M3)) /* gpio_100 */ \ + MV(CP(C2C_DATA12) , ( PTD | IEN | M3)) /* gpio_101 */ \ + MV(CP(C2C_DATA13) , ( PTD | M3)) /* gpio_102 */ \ + MV(CP(C2C_DATA14) , ( M1)) /* dsi2_te0 */ \ + MV(CP(C2C_DATA15) , ( PTD | M3)) /* gpio_104 */ \ + MV(CP(HDMI_HPD) , ( M0)) /* hdmi_hpd */ \ + MV(CP(HDMI_CEC) , ( M0)) /* hdmi_cec */ \ + MV(CP(HDMI_DDC_SCL) , ( PTU | M0)) /* hdmi_ddc_scl */ \ + MV(CP(HDMI_DDC_SDA) , ( PTU | IEN | M0)) /* hdmi_ddc_sda */ \ + MV(CP(CSI21_DX0) , ( IEN | M0)) /* csi21_dx0 */ \ + MV(CP(CSI21_DY0) , ( IEN | M0)) /* csi21_dy0 */ \ + MV(CP(CSI21_DX1) , ( IEN | M0)) /* csi21_dx1 */ \ + MV(CP(CSI21_DY1) , ( IEN | M0)) /* csi21_dy1 */ \ + MV(CP(CSI21_DX2) , ( IEN | M0)) /* csi21_dx2 */ \ + MV(CP(CSI21_DY2) , ( IEN | M0)) /* csi21_dy2 */ \ + MV(CP(CSI21_DX3) , ( PTD | M7)) /* csi21_dx3 */ \ + MV(CP(CSI21_DY3) , ( PTD | M7)) /* csi21_dy3 */ \ + MV(CP(CSI21_DX4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7)) /* csi21_dx4 */ \ + MV(CP(CSI21_DY4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7)) /* csi21_dy4 */ \ + MV(CP(CSI22_DX0) , ( IEN | M0)) /* csi22_dx0 */ \ + MV(CP(CSI22_DY0) , ( IEN | M0)) /* csi22_dy0 */ \ + MV(CP(CSI22_DX1) , ( IEN | M0)) /* csi22_dx1 */ \ + MV(CP(CSI22_DY1) , ( IEN | M0)) /* csi22_dy1 */ \ + MV(CP(CAM_SHUTTER) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \ + MV(CP(CAM_STROBE) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \ + MV(CP(CAM_GLOBALRESET) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \ + MV(CP(USBB1_ULPITLL_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \ + MV(CP(USBB1_ULPITLL_STP) , ( OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \ + MV(CP(USBB1_ULPITLL_DIR) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \ + MV(CP(USBB1_ULPITLL_NXT) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \ + MV(CP(USBB1_ULPITLL_DAT0) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \ + MV(CP(USBB1_ULPITLL_DAT1) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \ + MV(CP(USBB1_ULPITLL_DAT2) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \ + MV(CP(USBB1_ULPITLL_DAT3) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \ + MV(CP(USBB1_ULPITLL_DAT4) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \ + MV(CP(USBB1_ULPITLL_DAT5) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \ + MV(CP(USBB1_ULPITLL_DAT6) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \ + MV(CP(USBB1_ULPITLL_DAT7) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat7 */ \ + MV(CP(USBB1_HSIC_DATA) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_data */ \ + MV(CP(USBB1_HSIC_STROBE) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_strobe */ \ + MV(CP(USBC1_ICUSB_DP) , ( IEN | M0)) /* usbc1_icusb_dp */ \ + MV(CP(USBC1_ICUSB_DM) , ( IEN | M0)) /* usbc1_icusb_dm */ \ + MV(CP(SDMMC1_CLK) , ( PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc1_clk */ \ + MV(CP(SDMMC1_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_cmd */ \ + MV(CP(SDMMC1_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat0 */ \ + MV(CP(SDMMC1_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat1 */ \ + MV(CP(SDMMC1_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat2 */ \ + MV(CP(SDMMC1_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat3 */ \ + MV(CP(SDMMC1_DAT4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat4 */ \ + MV(CP(SDMMC1_DAT5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat5 */ \ + MV(CP(SDMMC1_DAT6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat6 */ \ + MV(CP(SDMMC1_DAT7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat7 */ \ + MV(CP(ABE_MCBSP2_CLKX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_clkx */ \ + MV(CP(ABE_MCBSP2_DR) , ( IEN | OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dr */ \ + MV(CP(ABE_MCBSP2_DX) , ( OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dx */ \ + MV(CP(ABE_MCBSP2_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_fsx */ \ + MV(CP(ABE_MCBSP1_CLKX) , ( IEN | M1)) /* abe_slimbus1_clock */ \ + MV(CP(ABE_MCBSP1_DR) , ( IEN | M1)) /* abe_slimbus1_data */ \ + MV(CP(ABE_MCBSP1_DX) , ( OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp1_dx */ \ + MV(CP(ABE_MCBSP1_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp1_fsx */ \ + MV(CP(ABE_PDM_UL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_ul_data */ \ + MV(CP(ABE_PDM_DL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_dl_data */ \ + MV(CP(ABE_PDM_FRAME) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_frame */ \ + MV(CP(ABE_PDM_LB_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_lb_clk */ \ + MV(CP(ABE_CLKS) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_clks */ \ + MV(CP(ABE_DMIC_CLK1) , ( M0)) /* abe_dmic_clk1 */ \ + MV(CP(ABE_DMIC_DIN1) , ( IEN | M0)) /* abe_dmic_din1 */ \ + MV(CP(ABE_DMIC_DIN2) , ( IEN | M0)) /* abe_dmic_din2 */ \ + MV(CP(ABE_DMIC_DIN3) , ( IEN | M0)) /* abe_dmic_din3 */ \ + MV(CP(UART2_CTS) , ( PTU | IEN | M0)) /* uart2_cts */ \ + MV(CP(UART2_RTS) , ( M0)) /* uart2_rts */ \ + MV(CP(UART2_RX) , ( PTU | IEN | M0)) /* uart2_rx */ \ + MV(CP(UART2_TX) , ( M0)) /* uart2_tx */ \ + MV(CP(HDQ_SIO) , ( M3)) /* gpio_127 */ \ + MV(CP(I2C1_SCL) , ( PTU | IEN | M0)) /* i2c1_scl */ \ + MV(CP(I2C1_SDA) , ( PTU | IEN | M0)) /* i2c1_sda */ \ + MV(CP(I2C2_SCL) , ( PTU | IEN | M0)) /* i2c2_scl */ \ + MV(CP(I2C2_SDA) , ( PTU | IEN | M0)) /* i2c2_sda */ \ + MV(CP(I2C3_SCL) , ( PTU | IEN | M0)) /* i2c3_scl */ \ + MV(CP(I2C3_SDA) , ( PTU | IEN | M0)) /* i2c3_sda */ \ + MV(CP(I2C4_SCL) , ( PTU | IEN | M0)) /* i2c4_scl */ \ + MV(CP(I2C4_SDA) , ( PTU | IEN | M0)) /* i2c4_sda */ \ + MV(CP(MCSPI1_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_clk */ \ + MV(CP(MCSPI1_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_somi */ \ + MV(CP(MCSPI1_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_simo */ \ + MV(CP(MCSPI1_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_cs0 */ \ + MV(CP(MCSPI1_CS1) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* mcspi1_cs1 */ \ + MV(CP(MCSPI1_CS2) , ( PTU | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_139 */ \ + MV(CP(MCSPI1_CS3) , ( PTU | IEN | M3)) /* gpio_140 */ \ + MV(CP(UART3_CTS_RCTX) , ( PTU | IEN | M0)) /* uart3_tx */ \ + MV(CP(UART3_RTS_SD) , ( M0)) /* uart3_rts_sd */ \ + MV(CP(UART3_RX_IRRX) , ( IEN | M0)) /* uart3_rx */ \ + MV(CP(UART3_TX_IRTX) , ( M0)) /* uart3_tx */ \ + MV(CP(SDMMC5_CLK) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc5_clk */ \ + MV(CP(SDMMC5_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_cmd */ \ + MV(CP(SDMMC5_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat0 */ \ + MV(CP(SDMMC5_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat1 */ \ + MV(CP(SDMMC5_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat2 */ \ + MV(CP(SDMMC5_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat3 */ \ + MV(CP(MCSPI4_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_clk */ \ + MV(CP(MCSPI4_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_simo */ \ + MV(CP(MCSPI4_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_somi */ \ + MV(CP(MCSPI4_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \ + MV(CP(UART4_RX) , ( IEN | M0)) /* uart4_rx */ \ + MV(CP(UART4_TX) , ( M0)) /* uart4_tx */ \ + MV(CP(USBB2_ULPITLL_CLK) , ( IEN | M3)) /* gpio_157 */ \ + MV(CP(USBB2_ULPITLL_STP) , ( IEN | M5)) /* dispc2_data23 */ \ + MV(CP(USBB2_ULPITLL_DIR) , ( IEN | M5)) /* dispc2_data22 */ \ + MV(CP(USBB2_ULPITLL_NXT) , ( IEN | M5)) /* dispc2_data21 */ \ + MV(CP(USBB2_ULPITLL_DAT0) , ( IEN | M5)) /* dispc2_data20 */ \ + MV(CP(USBB2_ULPITLL_DAT1) , ( IEN | M5)) /* dispc2_data19 */ \ + MV(CP(USBB2_ULPITLL_DAT2) , ( IEN | M5)) /* dispc2_data18 */ \ + MV(CP(USBB2_ULPITLL_DAT3) , ( IEN | M5)) /* dispc2_data15 */ \ + MV(CP(USBB2_ULPITLL_DAT4) , ( IEN | M5)) /* dispc2_data14 */ \ + MV(CP(USBB2_ULPITLL_DAT5) , ( IEN | M5)) /* dispc2_data13 */ \ + MV(CP(USBB2_ULPITLL_DAT6) , ( IEN | M5)) /* dispc2_data12 */ \ + MV(CP(USBB2_ULPITLL_DAT7) , ( IEN | M5)) /* dispc2_data11 */ \ + MV(CP(USBB2_HSIC_DATA) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \ + MV(CP(USBB2_HSIC_STROBE) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \ + MV(CP(UNIPRO_TX0) , ( PTD | IEN | M3)) /* gpio_171 */ \ + MV(CP(UNIPRO_TY0) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \ + MV(CP(UNIPRO_TX1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \ + MV(CP(UNIPRO_TY1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \ + MV(CP(UNIPRO_TX2) , ( PTU | IEN | M3)) /* gpio_0 */ \ + MV(CP(UNIPRO_TY2) , ( PTU | IEN | M3)) /* gpio_1 */ \ + MV(CP(UNIPRO_RX0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \ + MV(CP(UNIPRO_RY0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \ + MV(CP(UNIPRO_RX1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \ + MV(CP(UNIPRO_RY1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row3 */ \ + MV(CP(UNIPRO_RX2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row4 */ \ + MV(CP(UNIPRO_RY2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row5 */ \ + MV(CP(USBA0_OTG_CE) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* usba0_otg_ce */ \ + MV(CP(USBA0_OTG_DP) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \ + MV(CP(USBA0_OTG_DM) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \ + MV(CP(FREF_CLK1_OUT) , ( M0)) /* fref_clk1_out */ \ + MV(CP(FREF_CLK2_OUT) , ( PTD | IEN | M3)) /* gpio_182 */ \ + MV(CP(SYS_NIRQ1) , ( PTU | IEN | M0)) /* sys_nirq1 */ \ + MV(CP(SYS_NIRQ2) , ( PTU | IEN | M0)) /* sys_nirq2 */ \ + MV(CP(SYS_BOOT0) , ( PTU | IEN | M3)) /* gpio_184 */ \ + MV(CP(SYS_BOOT1) , ( M3)) /* gpio_185 */ \ + MV(CP(SYS_BOOT2) , ( PTD | IEN | M3)) /* gpio_186 */ \ + MV(CP(SYS_BOOT3) , ( M3)) /* gpio_187 */ \ + MV(CP(SYS_BOOT4) , ( M3)) /* gpio_188 */ \ + MV(CP(SYS_BOOT5) , ( PTD | IEN | M3)) /* gpio_189 */ \ + MV(CP(DPM_EMU0) , ( IEN | M0)) /* dpm_emu0 */ \ + MV(CP(DPM_EMU1) , ( IEN | M0)) /* dpm_emu1 */ \ + MV(CP(DPM_EMU2) , ( IEN | M0)) /* dpm_emu2 */ \ + MV(CP(DPM_EMU3) , ( IEN | M5)) /* dispc2_data10 */ \ + MV(CP(DPM_EMU4) , ( IEN | M5)) /* dispc2_data9 */ \ + MV(CP(DPM_EMU5) , ( IEN | M5)) /* dispc2_data16 */ \ + MV(CP(DPM_EMU6) , ( IEN | M5)) /* dispc2_data17 */ \ + MV(CP(DPM_EMU7) , ( IEN | M5)) /* dispc2_hsync */ \ + MV(CP(DPM_EMU8) , ( IEN | M5)) /* dispc2_pclk */ \ + MV(CP(DPM_EMU9) , ( IEN | M5)) /* dispc2_vsync */ \ + MV(CP(DPM_EMU10) , ( IEN | M5)) /* dispc2_de */ \ + MV(CP(DPM_EMU11) , ( IEN | M5)) /* dispc2_data8 */ \ + MV(CP(DPM_EMU12) , ( IEN | M5)) /* dispc2_data7 */ \ + MV(CP(DPM_EMU13) , ( IEN | M5)) /* dispc2_data6 */ \ + MV(CP(DPM_EMU14) , ( IEN | M5)) /* dispc2_data5 */ \ + MV(CP(DPM_EMU15) , ( IEN | M5)) /* dispc2_data4 */ \ + MV(CP(DPM_EMU16) , ( M3)) /* gpio_27 */ \ + MV(CP(DPM_EMU17) , ( IEN | M5)) /* dispc2_data2 */ \ + MV(CP(DPM_EMU18) , ( IEN | M5)) /* dispc2_data1 */ \ + MV(CP(DPM_EMU19) , ( IEN | M5)) /* dispc2_data0 */ \ + MV1(WK(PAD0_SIM_IO) , ( IEN | M0)) /* sim_io */ \ + MV1(WK(PAD1_SIM_CLK) , ( M0)) /* sim_clk */ \ + MV1(WK(PAD0_SIM_RESET) , ( M0)) /* sim_reset */ \ + MV1(WK(PAD1_SIM_CD) , ( PTU | IEN | M0)) /* sim_cd */ \ + MV1(WK(PAD0_SIM_PWRCTRL) , ( M0)) /* sim_pwrctrl */ \ + MV1(WK(PAD1_SR_SCL) , ( PTU | IEN | M0)) /* sr_scl */ \ + MV1(WK(PAD0_SR_SDA) , ( PTU | IEN | M0)) /* sr_sda */ \ + MV1(WK(PAD1_FREF_XTAL_IN) , ( M0)) /* # */ \ + MV1(WK(PAD0_FREF_SLICER_IN) , ( M0)) /* fref_slicer_in */ \ + MV1(WK(PAD1_FREF_CLK_IOREQ) , ( M0)) /* fref_clk_ioreq */ \ + MV1(WK(PAD0_FREF_CLK0_OUT) , ( M2)) /* sys_drm_msecure */ \ + MV1(WK(PAD1_FREF_CLK3_REQ) , ( PTU | IEN | M0)) /* # */ \ + MV1(WK(PAD0_FREF_CLK3_OUT) , ( M0)) /* fref_clk3_out */ \ + MV1(WK(PAD1_FREF_CLK4_REQ) , ( PTU | IEN | M0)) /* # */ \ + MV1(WK(PAD0_FREF_CLK4_OUT) , ( M0)) /* # */ \ + MV1(WK(PAD1_SYS_32K) , ( IEN | M0)) /* sys_32k */ \ + MV1(WK(PAD0_SYS_NRESPWRON) , ( M0)) /* sys_nrespwron */ \ + MV1(WK(PAD1_SYS_NRESWARM) , ( M0)) /* sys_nreswarm */ \ + MV1(WK(PAD0_SYS_PWR_REQ) , ( PTU | M0)) /* sys_pwr_req */ \ + MV1(WK(PAD1_SYS_PWRON_RESET) , ( M3)) /* gpio_wk29 */ \ + MV1(WK(PAD0_SYS_BOOT6) , ( IEN | M3)) /* gpio_wk9 */ \ + MV1(WK(PAD1_SYS_BOOT7) , ( IEN | M3)) /* gpio_wk10 */ \ + MV1(WK(PAD1_FREF_CLK3_REQ), (M3)) /* gpio_wk30 */ \ + MV1(WK(PAD1_FREF_CLK4_REQ), (M3)) /* gpio_wk7 */ \ + MV1(WK(PAD0_FREF_CLK4_OUT), (M3)) /* gpio_wk8 */ + +#define MUX_DEFAULT_OMAP4_ALL() \ + MV(CP(GPMC_AD0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \ + MV(CP(GPMC_AD1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \ + MV(CP(GPMC_AD2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat2 */ \ + MV(CP(GPMC_AD3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat3 */ \ + MV(CP(GPMC_AD4), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat4 */ \ + MV(CP(GPMC_AD5), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat5 */ \ + MV(CP(GPMC_AD6), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat6 */ \ + MV(CP(GPMC_AD7), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat7 */ \ + MV(CP(GPMC_AD8), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_32 */ \ + MV(CP(GPMC_AD9), (M3_SAFE)) /* gpio_33 */ \ + MV(CP(GPMC_AD10), (M3_SAFE)) /* gpio_34 */ \ + MV(CP(GPMC_AD11), (M3_SAFE)) /* gpio_35 */ \ + MV(CP(GPMC_AD12), (M3_SAFE)) /* gpio_36 */ \ + MV(CP(GPMC_AD13), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_37 */ \ + MV(CP(GPMC_AD14), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_38 */ \ + MV(CP(GPMC_AD15), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \ + MV(CP(GPMC_A16), (M3_SAFE)) /* gpio_40 */ \ + MV(CP(GPMC_A17), (M3_SAFE)) /* gpio_41 */ \ + MV(CP(GPMC_A18), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row6 */ \ + MV(CP(GPMC_A19), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \ + MV(CP(GPMC_A20), (M3_SAFE)) /* gpio_44 */ \ + MV(CP(GPMC_A21), (M3_SAFE)) /* gpio_45 */ \ + MV(CP(GPMC_A22), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col6 */ \ + MV(CP(GPMC_A23), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \ + MV(CP(GPMC_A24), (M3_SAFE)) /* gpio_48 */ \ + MV(CP(GPMC_A25), (M3_SAFE)) /* gpio_49 */ \ + MV(CP(GPMC_NCS0), (M0)) /* gpmc_ncs0 */ \ + MV(CP(GPMC_NCS1), (M3_SAFE)) /* gpio_51 */ \ + MV(CP(GPMC_NCS2), (M3_SAFE)) /* gpio_52 */ \ + MV(CP(GPMC_NCS3), (M3_SAFE)) /* gpio_53 */ \ + MV(CP(GPMC_NWP), (M0_SAFE)) /* gpmc_nwp */ \ + MV(CP(GPMC_CLK), (M3_SAFE)) /* gpio_55 */ \ + MV(CP(GPMC_NADV_ALE), (M0)) /* gpmc_nadv_ale */ \ + MV(CP(GPMC_NOE), (PTU | OFF_EN | OFF_OUT_PTD | M1)) /* sdmmc2_clk */ \ + MV(CP(GPMC_NWE), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_cmd */ \ + MV(CP(GPMC_NBE0_CLE), (M0)) /* gpmc_nbe0_cle*/ \ + MV(CP(GPMC_NBE1), (M3_SAFE)) /* gpio_60 */ \ + MV(CP(GPMC_WAIT0), (M0)) /* gpmc_wait */ \ + MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \ + MV(CP(C2C_DATA11), (M3_SAFE)) /* gpio_100 */ \ + MV(CP(C2C_DATA12), (M1_SAFE)) /* dsi1_te0 */ \ + MV(CP(C2C_DATA13), (M3_SAFE)) /* gpio_102 */ \ + MV(CP(C2C_DATA14), (M1_SAFE)) /* dsi2_te0 */ \ + MV(CP(C2C_DATA15), (M3_SAFE)) /* gpio_104 */ \ + MV(CP(HDMI_HPD), (M0_SAFE)) /* hdmi_hpd */ \ + MV(CP(HDMI_CEC), (M0_SAFE)) /* hdmi_cec */ \ + MV(CP(HDMI_DDC_SCL), (M0_SAFE)) /* hdmi_ddc_scl */ \ + MV(CP(HDMI_DDC_SDA), (M0_SAFE)) /* hdmi_ddc_sda */ \ + MV(CP(CSI21_DX0), (M0_SAFE)) /* csi21_dx0 */ \ + MV(CP(CSI21_DY0), (M0_SAFE)) /* csi21_dy0 */ \ + MV(CP(CSI21_DX1), (M0_SAFE)) /* csi21_dx1 */ \ + MV(CP(CSI21_DY1), (M0_SAFE)) /* csi21_dy1 */ \ + MV(CP(CSI21_DX2), (M0_SAFE)) /* csi21_dx2 */ \ + MV(CP(CSI21_DY2), (M0_SAFE)) /* csi21_dy2 */ \ + MV(CP(CSI21_DX3), (M0_SAFE)) /* csi21_dx3 */ \ + MV(CP(CSI21_DY3), (M0_SAFE)) /* csi21_dy3 */ \ + MV(CP(CSI21_DX4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_75 */ \ + MV(CP(CSI21_DY4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_76 */ \ + MV(CP(CSI22_DX0), (M0_SAFE)) /* csi22_dx0 */ \ + MV(CP(CSI22_DY0), (M0_SAFE)) /* csi22_dy0 */ \ + MV(CP(CSI22_DX1), (M0_SAFE)) /* csi22_dx1 */ \ + MV(CP(CSI22_DY1), (M0_SAFE)) /* csi22_dy1 */ \ + MV(CP(CAM_SHUTTER), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \ + MV(CP(CAM_STROBE), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \ + MV(CP(CAM_GLOBALRESET), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \ + MV(CP(USBB1_ULPITLL_CLK), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \ + MV(CP(USBB1_ULPITLL_STP), (PTU | OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \ + MV(CP(USBB1_ULPITLL_DIR), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \ + MV(CP(USBB1_ULPITLL_NXT), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \ + MV(CP(USBB1_ULPITLL_DAT0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \ + MV(CP(USBB1_ULPITLL_DAT1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \ + MV(CP(USBB1_ULPITLL_DAT2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \ + MV(CP(USBB1_ULPITLL_DAT3), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \ + MV(CP(USBB1_ULPITLL_DAT4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \ + MV(CP(USBB1_ULPITLL_DAT5), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \ + MV(CP(USBB1_ULPITLL_DAT6), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \ + MV(CP(USBB1_ULPITLL_DAT7), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat7 */ \ + MV(CP(USBB1_HSIC_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_data */ \ + MV(CP(USBB1_HSIC_STROBE), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_strobe */ \ + MV(CP(USBC1_ICUSB_DP), (M0_SAFE)) /* usbc1_icusb_dp */ \ + MV(CP(USBC1_ICUSB_DM), (M0_SAFE)) /* usbc1_icusb_dm */ \ + MV(CP(SDMMC1_CLK), (PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc1_clk */ \ + MV(CP(SDMMC1_CMD), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_cmd */ \ + MV(CP(SDMMC1_DAT0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat0 */ \ + MV(CP(SDMMC1_DAT1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat1 */ \ + MV(CP(SDMMC1_DAT2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat2 */ \ + MV(CP(SDMMC1_DAT3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat3 */ \ + MV(CP(SDMMC1_DAT4), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat4 */ \ + MV(CP(SDMMC1_DAT5), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat5 */ \ + MV(CP(SDMMC1_DAT6), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat6 */ \ + MV(CP(SDMMC1_DAT7), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat7 */ \ + MV(CP(ABE_MCBSP2_CLKX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_clkx */ \ + MV(CP(ABE_MCBSP2_DR), (IEN | OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dr */ \ + MV(CP(ABE_MCBSP2_DX), (OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dx */ \ + MV(CP(ABE_MCBSP2_FSX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_fsx */ \ + MV(CP(ABE_MCBSP1_CLKX), (M1_SAFE)) /* abe_slimbus1_clock */ \ + MV(CP(ABE_MCBSP1_DR), (M1_SAFE)) /* abe_slimbus1_data */ \ + MV(CP(ABE_MCBSP1_DX), (OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp1_dx */ \ + MV(CP(ABE_MCBSP1_FSX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp1_fsx */ \ + MV(CP(ABE_PDM_UL_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_ul_data */ \ + MV(CP(ABE_PDM_DL_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_dl_data */ \ + MV(CP(ABE_PDM_FRAME), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_frame */ \ + MV(CP(ABE_PDM_LB_CLK), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_lb_clk */ \ + MV(CP(ABE_CLKS), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_clks */ \ + MV(CP(ABE_DMIC_CLK1), (M0_SAFE)) /* abe_dmic_clk1 */ \ + MV(CP(ABE_DMIC_DIN1), (M0_SAFE)) /* abe_dmic_din1 */ \ + MV(CP(ABE_DMIC_DIN2), (M0_SAFE)) /* abe_dmic_din2 */ \ + MV(CP(ABE_DMIC_DIN3), (M0_SAFE)) /* abe_dmic_din3 */ \ + MV(CP(UART2_CTS), (PTU | IEN | M0)) /* uart2_cts */ \ + MV(CP(UART2_RTS), (M0)) /* uart2_rts */ \ + MV(CP(UART2_RX), (PTU | IEN | M0)) /* uart2_rx */ \ + MV(CP(UART2_TX), (M0)) /* uart2_tx */ \ + MV(CP(HDQ_SIO), (M3_SAFE)) /* gpio_127 */ \ + MV(CP(I2C1_SCL), (PTU | IEN | M0)) /* i2c1_scl */ \ + MV(CP(I2C1_SDA), (PTU | IEN | M0)) /* i2c1_sda */ \ + MV(CP(I2C2_SCL), (PTU | IEN | M0)) /* i2c2_scl */ \ + MV(CP(I2C2_SDA), (PTU | IEN | M0)) /* i2c2_sda */ \ + MV(CP(I2C3_SCL), (PTU | IEN | M0)) /* i2c3_scl */ \ + MV(CP(I2C3_SDA), (PTU | IEN | M0)) /* i2c3_sda */ \ + MV(CP(I2C4_SCL), (PTU | IEN | M0)) /* i2c4_scl */ \ + MV(CP(I2C4_SDA), (PTU | IEN | M0)) /* i2c4_sda */ \ + MV(CP(MCSPI1_CLK), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_clk */ \ + MV(CP(MCSPI1_SOMI), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_somi */ \ + MV(CP(MCSPI1_SIMO), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_simo */ \ + MV(CP(MCSPI1_CS0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_cs0 */ \ + MV(CP(MCSPI1_CS1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* mcspi1_cs1 */ \ + MV(CP(MCSPI1_CS2), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_139 */ \ + MV(CP(MCSPI1_CS3), (M3_SAFE)) /* gpio_140 */ \ + MV(CP(UART3_CTS_RCTX), (PTU | IEN | M0)) /* uart3_tx */ \ + MV(CP(UART3_RTS_SD), (M0)) /* uart3_rts_sd */ \ + MV(CP(UART3_RX_IRRX), (IEN | M0)) /* uart3_rx */ \ + MV(CP(UART3_TX_IRTX), (M0)) /* uart3_tx */ \ + MV(CP(SDMMC5_CLK), (PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc5_clk */ \ + MV(CP(SDMMC5_CMD), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_cmd */ \ + MV(CP(SDMMC5_DAT0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat0 */ \ + MV(CP(SDMMC5_DAT1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat1 */ \ + MV(CP(SDMMC5_DAT2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat2 */ \ + MV(CP(SDMMC5_DAT3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat3 */ \ + MV(CP(MCSPI4_CLK), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_clk */ \ + MV(CP(MCSPI4_SIMO), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_simo */ \ + MV(CP(MCSPI4_SOMI), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_somi */ \ + MV(CP(MCSPI4_CS0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \ + MV(CP(UART4_RX), (IEN | M0)) /* uart4_rx */ \ + MV(CP(UART4_TX), (M0)) /* uart4_tx */ \ + MV(CP(USBB2_ULPITLL_CLK), (M3)) /* gpio_157 */ \ + MV(CP(USBB2_ULPITLL_STP), (M5)) /* dispc2_data23 */ \ + MV(CP(USBB2_ULPITLL_DIR), (M5)) /* dispc2_data22 */ \ + MV(CP(USBB2_ULPITLL_NXT), (M5)) /* dispc2_data21 */ \ + MV(CP(USBB2_ULPITLL_DAT0), (M5)) /* dispc2_data20 */ \ + MV(CP(USBB2_ULPITLL_DAT1), (M5)) /* dispc2_data19 */ \ + MV(CP(USBB2_ULPITLL_DAT2), (M5)) /* dispc2_data18 */ \ + MV(CP(USBB2_ULPITLL_DAT3), (M5)) /* dispc2_data15 */ \ + MV(CP(USBB2_ULPITLL_DAT4), (M5)) /* dispc2_data14 */ \ + MV(CP(USBB2_ULPITLL_DAT5), (M5)) /* dispc2_data13 */ \ + MV(CP(USBB2_ULPITLL_DAT6), (M5)) /* dispc2_data12 */ \ + MV(CP(USBB2_ULPITLL_DAT7), (M5)) /* dispc2_data11 */ \ + MV(CP(USBB2_HSIC_DATA), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \ + MV(CP(USBB2_HSIC_STROBE), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \ + MV(CP(UNIPRO_TX0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col0 */ \ + MV(CP(UNIPRO_TY0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \ + MV(CP(UNIPRO_TX1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \ + MV(CP(UNIPRO_TY1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \ + MV(CP(UNIPRO_TX2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_0 */ \ + MV(CP(UNIPRO_TY2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_1 */ \ + MV(CP(UNIPRO_RX0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \ + MV(CP(UNIPRO_RY0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \ + MV(CP(UNIPRO_RX1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \ + MV(CP(UNIPRO_RY1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row3 */ \ + MV(CP(UNIPRO_RX2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row4 */ \ + MV(CP(UNIPRO_RY2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row5 */ \ + MV(CP(USBA0_OTG_CE), (PTU | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* usba0_otg_ce */ \ + MV(CP(USBA0_OTG_DP), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \ + MV(CP(USBA0_OTG_DM), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \ + MV(CP(FREF_CLK1_OUT), (M0_SAFE)) /* fref_clk1_out */ \ + MV(CP(FREF_CLK2_OUT), (M0_SAFE)) /* fref_clk2_out */ \ + MV(CP(SYS_NIRQ1), (PTU | IEN | M0)) /* sys_nirq1 */ \ + MV(CP(SYS_NIRQ2), (PTU | IEN | M0)) /* sys_nirq2 */ \ + MV(CP(SYS_BOOT0), (M3_SAFE)) /* gpio_184 */ \ + MV(CP(SYS_BOOT1), (M3_SAFE)) /* gpio_185 */ \ + MV(CP(SYS_BOOT2), (M3_SAFE)) /* gpio_186 */ \ + MV(CP(SYS_BOOT3), (M3_SAFE)) /* gpio_187 */ \ + MV(CP(SYS_BOOT4), (M3_SAFE)) /* gpio_188 */ \ + MV(CP(SYS_BOOT5), (M3_SAFE)) /* gpio_189 */ \ + MV(CP(DPM_EMU0), (M0_SAFE)) /* dpm_emu0 */ \ + MV(CP(DPM_EMU1), (M0_SAFE)) /* dpm_emu1 */ \ + MV(CP(DPM_EMU2), (M0_SAFE)) /* dpm_emu2 */ \ + MV(CP(DPM_EMU3), (M5)) /* dispc2_data10 */ \ + MV(CP(DPM_EMU4), (M5)) /* dispc2_data9 */ \ + MV(CP(DPM_EMU5), (M5)) /* dispc2_data16 */ \ + MV(CP(DPM_EMU6), (M5)) /* dispc2_data17 */ \ + MV(CP(DPM_EMU7), (M5)) /* dispc2_hsync */ \ + MV(CP(DPM_EMU8), (M5)) /* dispc2_pclk */ \ + MV(CP(DPM_EMU9), (M5)) /* dispc2_vsync */ \ + MV(CP(DPM_EMU10), (M5)) /* dispc2_de */ \ + MV(CP(DPM_EMU11), (M5)) /* dispc2_data8 */ \ + MV(CP(DPM_EMU12), (M5)) /* dispc2_data7 */ \ + MV(CP(DPM_EMU13), (M5)) /* dispc2_data6 */ \ + MV(CP(DPM_EMU14), (M5)) /* dispc2_data5 */ \ + MV(CP(DPM_EMU15), (M5)) /* dispc2_data4 */ \ + MV(CP(DPM_EMU16), (M5)) /* dispc2_data3/dmtimer8_pwm_evt */ \ + MV(CP(DPM_EMU17), (M5)) /* dispc2_data2 */ \ + MV(CP(DPM_EMU18), (M5)) /* dispc2_data1 */ \ + MV(CP(DPM_EMU19), (M5)) /* dispc2_data0 */ \ + MV1(WK(PAD0_SIM_IO), (M0_SAFE)) /* sim_io */ \ + MV1(WK(PAD1_SIM_CLK), (M0_SAFE)) /* sim_clk */ \ + MV1(WK(PAD0_SIM_RESET), (M0_SAFE)) /* sim_reset */ \ + MV1(WK(PAD1_SIM_CD), (M0_SAFE)) /* sim_cd */ \ + MV1(WK(PAD0_SIM_PWRCTRL), (M0_SAFE)) /* sim_pwrctrl */ \ + MV1(WK(PAD1_SR_SCL), (PTU | IEN | M0)) /* sr_scl */ \ + MV1(WK(PAD0_SR_SDA), (PTU | IEN | M0)) /* sr_sda */ \ + MV1(WK(PAD1_FREF_XTAL_IN), (M0_SAFE)) /* # */ \ + MV1(WK(PAD0_FREF_SLICER_IN), (M0_SAFE)) /* fref_slicer_in */ \ + MV1(WK(PAD1_FREF_CLK_IOREQ), (M0_SAFE)) /* fref_clk_ioreq */ \ + MV1(WK(PAD0_FREF_CLK0_OUT), (M0)) /* sys_drm_msecure */ \ + MV1(WK(PAD1_FREF_CLK3_REQ), (M0)) /* # */ \ + MV1(WK(PAD0_FREF_CLK3_OUT), (M0_SAFE)) /* fref_clk3_out */ \ + MV1(WK(PAD1_FREF_CLK4_REQ), (M0_SAFE)) /* # */ \ + MV1(WK(PAD0_FREF_CLK4_OUT), (M0_SAFE)) /* # */ \ + MV1(WK(PAD1_SYS_32K), (IEN | M0_SAFE)) /* sys_32k */ \ + MV1(WK(PAD0_SYS_NRESPWRON), (IEN | M0_SAFE)) /* sys_nrespwron */ \ + MV1(WK(PAD1_SYS_NRESWARM), (IEN | M0_SAFE)) /* sys_nreswarm */ \ + MV1(WK(PAD0_SYS_PWR_REQ), (M0_SAFE)) /* sys_pwr_req */ \ + MV1(WK(PAD1_SYS_PWRON_RESET), (M3_SAFE)) /* gpio_wk29 */ \ + MV1(WK(PAD0_SYS_BOOT6), (M3_SAFE)) /* gpio_wk9 */ \ + MV1(WK(PAD1_SYS_BOOT7), (M3_SAFE)) /* gpio_wk10 */ \ + MV1(WK(PAD1_JTAG_TCK), (IEN | M0)) /* jtag_tck */ \ + MV1(WK(PAD0_JTAG_RTCK), (M0)) /* jtag_rtck */ \ + MV1(WK(PAD1_JTAG_TMS_TMSC), (IEN | M0)) /* jtag_tms_tmsc */ \ + MV1(WK(PAD0_JTAG_TDI), (IEN | M0)) /* jtag_tdi */ \ + MV1(WK(PAD1_JTAG_TDO), (M0)) /* jtag_tdo */ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT_OMAP4(); + return; +} + +/****************************************************************************** + * Routine: update_mux() + * Description:Update balls which are different between boards. All should be + * updated to match functionality. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* REVISIT */ + return; + +} + +/* optionally do something like blinking LED */ +void board_hang (void) +{ while (0) {};} + +int nand_init(void) +{ + return 0; +} +void reset_phy(unsigned int base) +{ + *(volatile int*)(base + IODFT_TLGC) |= (1 << 10); +} diff --git a/board/omap4430panda/platform.S b/board/omap4430panda/platform.S new file mode 100644 index 0000000..2eff964 --- /dev/null +++ b/board/omap4430panda/platform.S @@ -0,0 +1,51 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK diff --git a/board/omap4430panda/syslib.c b/board/omap4430panda/syslib.c new file mode 100644 index 0000000..2b16cc4 --- /dev/null +++ b/board/omap4430panda/syslib.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as + * its generally used in bypass conditions only. This + * is necessary until timers are accessible. + * + * not inline to increase chances its in cache when called + *************************************************************/ +void sdelay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = __raw_readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + __raw_writel(tmp, addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return (1); + if (i == bound) + return (0); + } while (1); +} + diff --git a/board/overo/Makefile b/board/overo/Makefile new file mode 100644 index 0000000..32f9bf1 --- /dev/null +++ b/board/overo/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := overo.o +SOBJS := platform.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/overo/config.mk b/board/overo/config.mk new file mode 100644 index 0000000..7ee3014 --- /dev/null +++ b/board/overo/config.mk @@ -0,0 +1,20 @@ +# +# (C) Copyright 2006 +# Texas Instruments, +# +# Overo board uses TI OMAP35xx (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Overo has 1 bank of 128MB mPOP-SDRAM on CS0 +# Physical Address: +# 8000'0000 (bank0) + +# For use if you want X-Loader to relocate from SRAM to DDR +#TEXT_BASE = 0x80e80000 + +# For XIP in 64K of SRAM or debug (GP device has it all availabe) +# SRAM 40200000-4020FFFF base +# initial stack at 0x4020fffc used in s_init (below xloader). +# The run time stack is (above xloader, 2k below) +# If any globals exist there needs to be room for them also +TEXT_BASE = 0x40200800 diff --git a/board/overo/overo.c b/board/overo/overo.c new file mode 100644 index 0000000..8df53e5 --- /dev/null +++ b/board/overo/overo.c @@ -0,0 +1,1148 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Jian Zhang + * Richard Woodruff + * + * Modified for overo + * Steve Sakoman + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* params for 37XX */ +#define CORE_DPLL_PARAM_M2 0x09 +#define CORE_DPLL_PARAM_M 0x360 +#define CORE_DPLL_PARAM_N 0xC + +/* Used to index into DPLL parameter tables */ +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +}; + +typedef struct dpll_param dpll_param; + +/* Following functions are exported from lowlevel_init.S */ +extern dpll_param *get_mpu_dpll_param(); +extern dpll_param *get_iva_dpll_param(); +extern dpll_param *get_core_dpll_param(); +extern dpll_param *get_per_dpll_param(); + +#define __raw_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v)) + +static char *rev_s[CPU_3XX_MAX_REV] = { + "1.0", + "2.0", + "2.1", + "3.0", + "3.1", + "UNKNOWN", + "UNKNOWN", + "3.1.2"}; + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +void udelay (unsigned long usecs) { + delay(usecs); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + return 0; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return mode >>= 8; +} + +/************************************************ + * get_sysboot_value(void) - return SYS_BOOT[4:0] + ************************************************/ +u32 get_sysboot_value(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK); + return mode; +} + +/************************************************************* + * Routine: get_mem_type(void) - returns the kind of memory connected + * to GPMC that we are trying to boot form. Uses SYS BOOT settings. + *************************************************************/ +u32 get_mem_type(void) +{ + u32 mem_type = get_sysboot_value(); + + switch (mem_type) { + case 0: + case 2: + case 4: + case 16: + case 22: + return GPMC_ONENAND; + + case 1: + case 12: + case 15: + case 21: + case 27: + return GPMC_NAND; + + case 3: + case 6: + return MMC_ONENAND; + + case 8: + case 11: + case 14: + case 20: + case 26: + return GPMC_MDOC; + + case 17: + case 18: + case 24: + return MMC_NAND; + + case 7: + case 10: + case 13: + case 19: + case 25: + default: + return GPMC_NOR; + } +} + +/****************************************** + * get_cpu_type(void) - extract cpu info + ******************************************/ +u32 get_cpu_type(void) +{ + return __raw_readl(CONTROL_OMAP_STATUS); +} + +/****************************************** + * get_cpu_id(void) - extract cpu id + * returns 0 for ES1.0, cpuid otherwise + ******************************************/ +u32 get_cpu_id(void) +{ + u32 cpuid = 0; + + /* + * On ES1.0 the IDCODE register is not exposed on L4 + * so using CPU ID to differentiate between ES1.0 and > ES1.0. + */ + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid)); + if ((cpuid & 0xf) == 0x0) { + return 0; + } else { + /* Decode the IDs on > ES1.0 */ + cpuid = __raw_readl(CONTROL_IDCODE); + } + + return cpuid; +} + +/****************************************** + * get_cpu_family(void) - extract cpu info + ******************************************/ +u32 get_cpu_family(void) +{ + u16 hawkeye; + u32 cpu_family; + u32 cpuid = get_cpu_id(); + + if (cpuid == 0) + return CPU_OMAP34XX; + + hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff; + switch (hawkeye) { + case HAWKEYE_OMAP34XX: + cpu_family = CPU_OMAP34XX; + break; + case HAWKEYE_AM35XX: + cpu_family = CPU_AM35XX; + break; + case HAWKEYE_OMAP36XX: + cpu_family = CPU_OMAP36XX; + break; + default: + cpu_family = CPU_OMAP34XX; + } + + return cpu_family; +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 cpuid = get_cpu_id(); + + if (cpuid == 0) + return CPU_3XX_ES10; + else + return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf; +} + +/****************************************** + * Print CPU information + ******************************************/ +int print_cpuinfo (void) +{ + char *cpu_family_s, *cpu_s, *sec_s; + + switch (get_cpu_family()) { + case CPU_OMAP34XX: + cpu_family_s = "OMAP"; + switch (get_cpu_type()) { + case OMAP3503: + cpu_s = "3503"; + break; + case OMAP3515: + cpu_s = "3515"; + break; + case OMAP3525: + cpu_s = "3525"; + break; + case OMAP3530: + cpu_s = "3530"; + break; + default: + cpu_s = "35XX"; + break; + } + break; + case CPU_AM35XX: + cpu_family_s = "AM"; + switch (get_cpu_type()) { + case AM3505: + cpu_s = "3505"; + break; + case AM3517: + cpu_s = "3517"; + break; + default: + cpu_s = "35XX"; + break; + } + break; + case CPU_OMAP36XX: + cpu_family_s = "OMAP"; + switch (get_cpu_type()) { + case OMAP3730: + cpu_s = "3630/3730"; + break; + default: + cpu_s = "36XX/37XX"; + break; + } + break; + default: + cpu_family_s = "OMAP"; + cpu_s = "35XX"; + } + + switch (get_device_type()) { + case TST_DEVICE: + sec_s = "TST"; + break; + case EMU_DEVICE: + sec_s = "EMU"; + break; + case HS_DEVICE: + sec_s = "HS"; + break; + case GP_DEVICE: + sec_s = "GP"; + break; + default: + sec_s = "?"; + } + + printf("%s%s-%s ES%s\n", + cpu_family_s, cpu_s, sec_s, rev_s[get_cpu_rev()]); + + return 0; +} + +/****************************************** + * cpu_is_3410(void) - returns true for 3410 + ******************************************/ +u32 cpu_is_3410(void) +{ + int status; + if (get_cpu_rev() < CPU_3430_ES2) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/***************************************************************** + * Routine: get_board_revision + * Description: Returns the board revision + *****************************************************************/ +int get_board_revision(void) +{ + int revision; + unsigned char data; + + /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */ + /* these boards should return a revision number of 0 */ + /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */ + data = 0x01; + i2c_write(0x4B, 0x29, 1, &data, 1); + data = 0x0c; + i2c_write(0x4B, 0x2b, 1, &data, 1); + i2c_read(0x4B, 0x2a, 1, &data, 1); + + if (!omap_request_gpio(112) && + !omap_request_gpio(113) && + !omap_request_gpio(115)) { + + omap_set_gpio_direction(112, 1); + omap_set_gpio_direction(113, 1); + omap_set_gpio_direction(115, 1); + + revision = omap_get_gpio_datain(115) << 2 | + omap_get_gpio_datain(113) << 1 | + omap_get_gpio_datain(112); + + omap_free_gpio(112); + omap_free_gpio(113); + omap_free_gpio(115); + } else { + printf("Error: unable to acquire board revision GPIOs\n"); + revision = -1; + } + + return revision; +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = __raw_readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + __raw_writel(tmp, addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return 1; + if (i == bound) + return 0; + } while (1); +} + +#ifdef CFG_3430SDRAM_DDR +/********************************************************************* + * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. + *********************************************************************/ +void config_3430sdram_ddr(void) +{ + /* reset sdrc controller */ + __raw_writel(SOFTRESET, SDRC_SYSCONFIG); + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); + __raw_writel(0, SDRC_SYSCONFIG); + + /* setup sdrc to ball mux */ + __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); + + switch (get_board_revision()) { + case 0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ + __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); + __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); + __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); + __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); + __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); + break; + case 1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ + __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0); + __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1); + __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); + __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); + __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); + __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); + break; + case 2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ + __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_0); + __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_1); + __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); + __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); + __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); + __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); + break; + default: + __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); + __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); + __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); + __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); + __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); + __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); + } + + __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER); + + /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0); + __raw_writel(CMD_NOP, SDRC_MANUAL_1); + + delay(5000); + + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); + + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); + + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); + + /* set mr0 */ + __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); + __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1); + + /* set up dll */ + __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); + delay(0x2000); /* give time to lock */ +} +#endif /* CFG_3430SDRAM_DDR */ + +/************************************************************* + * get_sys_clk_speed - determine reference oscillator speed + * based on known 32kHz clock and gptimer. + *************************************************************/ +u32 get_osc_clk_speed(void) +{ + u32 start, cstart, cend, cdiff, cdiv, val; + + val = __raw_readl(PRM_CLKSRC_CTRL); + + if (val & SYSCLKDIV_2) + cdiv = 2; + else + cdiv = 1; + + /* enable timer2 */ + val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; + __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ + + /* Enable I and F Clocks for GPT1 */ + val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; + __raw_writel(val, CM_ICLKEN_WKUP); + val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; + __raw_writel(val, CM_FCLKEN_WKUP); + + __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ + __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ + /* enable 32kHz source */ + /* enabled out of reset */ + /* determine sys_clk via gauging */ + + start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ + while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ + cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ + while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ + cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ + cdiff = cend - cstart; /* get elapsed ticks */ + cdiff *= cdiv; + + /* based on number of ticks assign speed */ + if (cdiff > 19000) + return S38_4M; + else if (cdiff > 15200) + return S26M; + else if (cdiff > 13000) + return S24M; + else if (cdiff > 9000) + return S19_2M; + else if (cdiff > 7600) + return S13M; + else + return S12M; +} + +/****************************************************************************** + * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on + * -- input oscillator clock frequency. + * + *****************************************************************************/ +void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) +{ + if (osc_clk == S38_4M) + *sys_clkin_sel = 4; + else if (osc_clk == S26M) + *sys_clkin_sel = 3; + else if (osc_clk == S19_2M) + *sys_clkin_sel = 2; + else if (osc_clk == S13M) + *sys_clkin_sel = 1; + else if (osc_clk == S12M) + *sys_clkin_sel = 0; +} + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * -- called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + u32 osc_clk = 0, sys_clkin_sel; + dpll_param *dpll_param_p; + u32 clk_index, sil_index; + + /* Gauge the input clock speed and find out the sys_clkin_sel + * value corresponding to the input clock. + */ + osc_clk = get_osc_clk_speed(); + get_sys_clkin_sel(osc_clk, &sys_clkin_sel); + + sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ + + /* If the input clock is greater than 19.2M always divide/2 */ + if (sys_clkin_sel > 2) { + sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */ + clk_index = sys_clkin_sel / 2; + } else { + sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */ + clk_index = sys_clkin_sel; + } + + sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ + + /* The DPLL tables are defined according to sysclk value and + * silicon revision. The clk_index value will be used to get + * the values for that input sysclk from the DPLL param table + * and sil_index will get the values for that SysClk for the + * appropriate silicon rev. + */ + sil_index = get_cpu_rev() - 1; + + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address of Core DPLL param table */ + dpll_param_p = (dpll_param *) get_core_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; + /* CORE DPLL */ + /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); + + /* For 3430 ES1.0 Errata 1.50, default value directly doesnt + work. write another value and then default value. */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ + sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ + sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ + sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ + sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ + sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ + sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ + sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ + sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to PER DPLL param table */ + dpll_param_p = (dpll_param *) get_per_dpll_param(); + /* Moving it to the right sysclk base */ + dpll_param_p = dpll_param_p + clk_index; + /* PER DPLL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); + wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ + + if (get_cpu_family() == CPU_OMAP36XX) { + sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */ + sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */ + sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */ + } else { + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ + sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ + } + + sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to MPU DPLL param table */ + dpll_param_p = (dpll_param *) get_mpu_dpll_param(); + + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; + + /* MPU DPLL (unlocked already) */ + sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address to IVA DPLL param table */ + dpll_param_p = (dpll_param *) get_iva_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; + /* IVA DPLL (set to 12*20=240MHz) */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); + sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ + sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ + sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); + + /* Set up GPTimers to sys_clk source only */ + sr32(CM_CLKSEL_PER, 0, 8, 0xff); + sr32(CM_CLKSEL_WKUP, 0, 1, 1); + + delay(5000); +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) + secure_unlock(); + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called at time when only stack is available. + **********************************************************/ + +void s_init(void) +{ + watchdog_init(); +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP); +#endif + try_unlock_memory(); + set_muxconf_regs(); + delay(100); + prcm_init(); + per_clocks_enable(); + config_3430sdram_ddr(); +} + +/******************************************************* + * Routine: misc_init_r + ********************************************************/ +int misc_init_r(void) +{ + print_cpuinfo(); + printf("Board revision: %d\n", get_board_revision()); + return 0; +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + return 0; +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +void per_clocks_enable(void) +{ + /* Enable GP2 timer. */ + sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ + sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ + sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ + +#ifdef CFG_NS16550 + /* UART1 clocks */ + sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); + sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); + + /* UART 3 Clocks */ + sr32(CM_FCLKEN_PER, 11, 1, 0x1); + sr32(CM_ICLKEN_PER, 11, 1, 0x1); + +#endif + + /* Enable GPIO 4, 5, & 6 clocks */ + sr32(CM_FCLKEN_PER, 17, 3, 0x7); + sr32(CM_ICLKEN_PER, 17, 3, 0x7); + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + /* Turn on all 3 I2C clocks */ + sr32(CM_FCLKEN1_CORE, 15, 3, 0x7); + sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */ +#endif + + /* Enable the ICLK for 32K Sync Timer as its used in udelay */ + sr32(CM_ICLKEN_WKUP, 2, 1, 0x1); + + sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON); + sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON); + sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON); + sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON); + sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON); + sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON); + sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON); + sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON); + sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON); + sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON); + sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON); + sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON); + + delay(1000); +} + +/* Set MUX for UART, GPMC, SDRC, GPIO */ + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT()\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\ + MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\ + MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ + MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ + MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ + MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\ + /* - PEN_DOWN*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M4)) /*GPIO_127*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M4)) /*GPIO_128*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M4)) /*GPIO_129*/\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ + MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ + MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ + MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ + MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ + MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ + MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ + MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ + MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ + MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ + MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ + MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT(); +} + +/********************************************************** + * Routine: nand+_init + * Description: Set up nand for nand and jffs2 commands + *********************************************************/ + +int nand_init(void) +{ + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ + + /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0. + * We configure only GPMC CS0 with required values. Configiring other devices + * at other CS is done in u-boot. So we don't have to bother doing it here. + */ + __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); + delay(1000); + +#ifdef CFG_NAND_K9F1G08R0A + if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) { + __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); + + /* Enable the GPMC Mapping */ + __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((NAND_BASE_ADR>>24) & 0x3F) | + (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); + delay(2000); + + if (nand_chip()) { +#ifdef CFG_PRINTF + printf("Unsupported Chip!\n"); +#endif + return 1; + } + } +#endif + +#ifdef CFG_ONENAND + if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) { + __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); + + /* Enable the GPMC Mapping */ + __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((ONENAND_BASE>>24) & 0x3F) | + (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); + delay(2000); + + if (onenand_chip()) { +#ifdef CFG_PRINTF + printf("OneNAND Unsupported !\n"); +#endif + return 1; + } + } +#endif + + return 0; +} + +/* optionally do something like blinking LED */ +void board_hang(void) +{ + while (0) + ; +} + +/****************************************************************************** + * Dummy function to handle errors for EABI incompatibility + *****************************************************************************/ +void raise(void) +{ +} + +/****************************************************************************** + * Dummy function to handle errors for EABI incompatibility + *****************************************************************************/ +void abort(void) +{ +} diff --git a/board/overo/platform.S b/board/overo/platform.S new file mode 100644 index 0000000..5869270 --- /dev/null +++ b/board/overo/platform.S @@ -0,0 +1,360 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * NOTE: 3430 X-loader currently does not use this code. +* It could be removed its is kept for compatabily with u-boot. + * + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = CM_CLKEN_PLL-bypass value + * R1 = CM_CLKSEL1_PLL-m, n, and divider values + * R2 = CM_CLKSEL_CORE-divider values + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + * + * Note: If core unlocks/relocks and SDRAM is running fast already it gets + * confused. A reset of the controller gets it back. Taking away its + * L3 when its not in self refresh seems bad for it. Normally, this code + * runs from flash before SDR is init so that should be ok. + ******************************************************************************/ +.global go_to_speed + go_to_speed: + stmfd sp!, {r4-r6} + + /* move into fast relock bypass */ + ldr r4, pll_ctl_add + str r0, [r4] +wait1: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + beq wait1 /* if lock, loop */ + + /* set new dpll dividers _after_ in bypass */ + ldr r5, pll_div_add1 + str r1, [r5] /* set m, n, m2 */ + ldr r5, pll_div_add2 + str r2, [r5] /* set l3/l4/.. dividers*/ + ldr r5, pll_div_add3 /* wkup */ + ldr r2, pll_div_val3 /* rsm val */ + str r2, [r5] + ldr r5, pll_div_add4 /* gfx */ + ldr r2, pll_div_val4 + str r2, [r5] + ldr r5, pll_div_add5 /* emu */ + ldr r2, pll_div_val5 + str r2, [r5] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r5, flash_cfg3_addr + ldr r2, flash_cfg3_val + str r2, [r5] + ldr r5, flash_cfg4_addr + ldr r2, flash_cfg4_val + str r2, [r5] + ldr r5, flash_cfg5_addr + ldr r2, flash_cfg5_val + str r2, [r5] + ldr r5, flash_cfg1_addr + ldr r2, [r5] + orr r2, r2, #0x3 /* up gpmc divider */ + str r2, [r5] + + /* lock DPLL3 and wait a bit */ + orr r0, r0, #0x7 /* set up for lock mode */ + str r0, [r4] /* lock */ + nop /* ARM slow at this point working at sys_clk */ + nop + nop + nop +wait2: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + bne wait2 /* if lock, loop */ + nop + nop + nop + nop + ldmfd sp!, {r4-r6} + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_div_add1: + .word CM_CLKSEL1_PLL +pll_div_add2: + .word CM_CLKSEL_CORE +pll_div_add3: + .word CM_CLKSEL_WKUP +pll_div_val3: + .word (WKUP_RSM << 1) +pll_div_add4: + .word CM_CLKSEL_GFX +pll_div_val4: + .word (GFX_DIV << 0) +pll_div_add5: + .word CM_CLKSEL1_EMU +pll_div_val5: + .word CLSEL1_EMU_VAL + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + +/* DPLL(1-4) PARAM TABLES */ +/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal + * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). + * The values are defined for all possible sysclk and for ES1 and ES2. + */ + +mpu_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x0FE,0x07,0x05,0x01 +/* ES2 */ +.word 0x0FA,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x17D,0x0C,0x03,0x01 +/* ES2 */ +.word 0x1F4,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x179,0x12,0x04,0x01 +/* ES2 */ +.word 0x271,0x17,0x03,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x17D,0x19,0x03,0x01 +/* ES2 */ +.word 0x0FA,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x1FA,0x32,0x03,0x01 +/* ES2 */ +.word 0x271,0x2F,0x03,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +.globl get_mpu_dpll_param +get_mpu_dpll_param: + adr r0, mpu_dpll_param + mov pc, lr + +iva_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x07D,0x05,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x0FA,0x0C,0x03,0x01 +/* ES2 */ +.word 0x168,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x082,0x09,0x07,0x01 +/* ES2 */ +.word 0x0E1,0x0B,0x06,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x07D,0x0C,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x13F,0x30,0x03,0x01 +/* ES2 */ +.word 0x0E1,0x17,0x06,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +.globl get_iva_dpll_param +get_iva_dpll_param: + adr r0, iva_dpll_param + mov pc, lr + +/* Core DPLL targets for L3 at 166 & L133 */ +core_dpll_param: +/* 12MHz */ +/* ES1 */ +.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 +/* ES2 */ +.word M_12,N_12,FSEL_12,M2_12 +/* 3410 */ +.word M_12,N_12,FSEL_12,M2_12 + +/* 13MHz */ +/* ES1 */ +.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 +/* ES2 */ +.word M_13,N_13,FSEL_13,M2_13 +/* 3410 */ +.word M_13,N_13,FSEL_13,M2_13 + +/* 19.2MHz */ +/* ES1 */ +.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 +/* ES2 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 +/* 3410 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 + +/* 26MHz */ +/* ES1 */ +.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 +/* ES2 */ +.word M_26,N_26,FSEL_26,M2_26 +/* 3410 */ +.word M_26,N_26,FSEL_26,M2_26 + +/* 38.4MHz */ +/* ES1 */ +.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 +/* ES2 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 +/* 3410 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 + +.globl get_core_dpll_param +get_core_dpll_param: + adr r0, core_dpll_param + mov pc, lr + +/* PER DPLL values are same for both ES1 and ES2 */ +per_dpll_param: +/* 12MHz */ +.word 0xD8,0x05,0x07,0x09 + +/* 13MHz */ +.word 0x1B0,0x0C,0x03,0x09 + +/* 19.2MHz */ +.word 0xE1,0x09,0x07,0x09 + +/* 26MHz */ +.word 0xD8,0x0C,0x07,0x09 + +/* 38.4MHz */ +.word 0xE1,0x13,0x07,0x09 + +.globl get_per_dpll_param +get_per_dpll_param: + adr r0, per_dpll_param + mov pc, lr + diff --git a/board/overo/x-load.lds b/board/overo/x-load.lds new file mode 100644 index 0000000..5f352d3 --- /dev/null +++ b/board/overo/x-load.lds @@ -0,0 +1,54 @@ +/* + * November 2006 - Changed to support 3430sdp device + * Copyright (c) 2004-2006 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/common/Makefile b/common/Makefile new file mode 100644 index 0000000..beb58eb --- /dev/null +++ b/common/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)libcommon.a + +AOBJS = + +COBJS = cmd_load.o cmd_monitor.o + +SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) + +CPPFLAGS += -I.. + +all: $(LIB) $(AOBJS) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/common/cmd_load.c b/common/cmd_load.c new file mode 100644 index 0000000..122b797 --- /dev/null +++ b/common/cmd_load.c @@ -0,0 +1,555 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Serial up- and download support + */ +#include + +#define putc serial_putc +#define tstc serial_tstc + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} +static inline void udelay(unsigned long us) +{ + delay(us * 200); /* approximate */ +} + +#ifdef CFG_CMD_FAT +extern void * memcpy(void * dest,const void *src,size_t count); +#else +void * memcpy(void * dest,const void *src,size_t count) +{ + char *tmp = (char *) dest, *s = (char *) src; + + while (count--) + *tmp++ = *s++; + + return dest; +} +#endif + +/* -------------------------------------------------------------------- */ + +#define XON_CHAR 17 +#define XOFF_CHAR 19 +#define START_CHAR 0x01 +#define ETX_CHAR 0x03 +#define END_CHAR 0x0D +#define SPACE 0x20 +#define K_ESCAPE 0x23 +#define SEND_TYPE 'S' +#define DATA_TYPE 'D' +#define ACK_TYPE 'Y' +#define NACK_TYPE 'N' +#define BREAK_TYPE 'B' +#define tochar(x) ((char) (((x) + SPACE) & 0xff)) +#define untochar(x) ((int) (((x) - SPACE) & 0xff)) + +extern int os_data_count; +extern int os_data_header[8]; + +static void set_kerm_bin_mode(unsigned long *); +static int k_recv(void); +static ulong load_serial_bin (ulong offset); + +extern int lowlevel_monitor (void); + +char his_eol; /* character he needs at end of packet */ +int his_pad_count; /* number of pad chars he needs */ +char his_pad_char; /* pad chars he needs */ +char his_quote; /* quote chars he'll use */ + +int do_load_serial_bin (ulong offset, int baudrate) +{ + ulong addr; + int rcode = 0; + + printf ("## Ready for binary (kermit) download " + "to 0x%08lX at %d bps. Press 'M' to break into low level monitor.\n", + offset, + baudrate); + addr = load_serial_bin (offset); + if (addr == ~0) { + printf ("## Binary (kermit) download aborted\n"); + rcode = 1; + } else { + printf ("## Start Addr = 0x%08lX\n", addr); + } + + return rcode; +} + + +static ulong load_serial_bin (ulong offset) +{ + int size, i; + + set_kerm_bin_mode ((ulong *) offset); + size = k_recv (); + + /* + * Gather any trailing characters (for instance, the ^D which + * is sent by 'cu' after sending a file), and give the + * box some time (100 * 1 ms) + */ + for (i=0; i<100; ++i) { + if (tstc()) { + (void) getc(); + } + udelay(1000); + } + + printf("## Total Size = 0x%08x = %d Bytes\n", size, size); + + return offset; +} + +void send_pad (void) +{ + int count = his_pad_count; + + while (count-- > 0) + putc (his_pad_char); +} + +/* converts escaped kermit char to binary char */ +char ktrans (char in) +{ + if ((in & 0x60) == 0x40) { + return (char) (in & ~0x40); + } else if ((in & 0x7f) == 0x3f) { + return (char) (in | 0x40); + } else + return in; +} + +int chk1 (char *buffer) +{ + int total = 0; + + while (*buffer) { + total += *buffer++; + } + return (int) ((total + ((total >> 6) & 0x03)) & 0x3f); +} + +void s1_sendpacket (char *packet) +{ + send_pad (); + while (*packet) { + putc (*packet++); + } +} + +static char a_b[24]; +void send_ack (int n) +{ + a_b[0] = START_CHAR; + a_b[1] = tochar (3); + a_b[2] = tochar (n); + a_b[3] = ACK_TYPE; + a_b[4] = '\0'; + a_b[4] = tochar (chk1 (&a_b[1])); + a_b[5] = his_eol; + a_b[6] = '\0'; + s1_sendpacket (a_b); +} + +void send_nack (int n) +{ + a_b[0] = START_CHAR; + a_b[1] = tochar (3); + a_b[2] = tochar (n); + a_b[3] = NACK_TYPE; + a_b[4] = '\0'; + a_b[4] = tochar (chk1 (&a_b[1])); + a_b[5] = his_eol; + a_b[6] = '\0'; + s1_sendpacket (a_b); +} + + +/* os_data_* takes an OS Open image and puts it into memory, and + puts the boot header in an array named os_data_header + + if image is binary, no header is stored in os_data_header. +*/ +void (*os_data_init) (void); +void (*os_data_char) (char new_char); +static int os_data_state, os_data_state_saved; +int os_data_count; +static int os_data_count_saved; +static char *os_data_addr, *os_data_addr_saved; +static char *bin_start_address; +int os_data_header[8]; +static void bin_data_init (void) +{ + os_data_state = 0; + os_data_count = 0; + os_data_addr = bin_start_address; +} +static void os_data_save (void) +{ + os_data_state_saved = os_data_state; + os_data_count_saved = os_data_count; + os_data_addr_saved = os_data_addr; +} +static void os_data_restore (void) +{ + os_data_state = os_data_state_saved; + os_data_count = os_data_count_saved; + os_data_addr = os_data_addr_saved; +} +static void bin_data_char (char new_char) +{ + switch (os_data_state) { + case 0: /* data */ + *os_data_addr++ = new_char; + --os_data_count; + break; + } +} +static void set_kerm_bin_mode (unsigned long *addr) +{ + bin_start_address = (char *) addr; + os_data_init = bin_data_init; + os_data_char = bin_data_char; +} + + +/* k_data_* simply handles the kermit escape translations */ +static int k_data_escape, k_data_escape_saved; +void k_data_init (void) +{ + k_data_escape = 0; + os_data_init (); +} +void k_data_save (void) +{ + k_data_escape_saved = k_data_escape; + os_data_save (); +} +void k_data_restore (void) +{ + k_data_escape = k_data_escape_saved; + os_data_restore (); +} +void k_data_char (char new_char) +{ + if (k_data_escape) { + /* last char was escape - translate this character */ + os_data_char (ktrans (new_char)); + k_data_escape = 0; + } else { + if (new_char == his_quote) { + /* this char is escape - remember */ + k_data_escape = 1; + } else { + /* otherwise send this char as-is */ + os_data_char (new_char); + } + } +} + +#define SEND_DATA_SIZE 20 +char send_parms[SEND_DATA_SIZE]; +char *send_ptr; + +/* handle_send_packet interprits the protocol info and builds and + sends an appropriate ack for what we can do */ +void handle_send_packet (int n) +{ + int length = 3; + int bytes; + + /* initialize some protocol parameters */ + his_eol = END_CHAR; /* default end of line character */ + his_pad_count = 0; + his_pad_char = '\0'; + his_quote = K_ESCAPE; + + /* ignore last character if it filled the buffer */ + if (send_ptr == &send_parms[SEND_DATA_SIZE - 1]) + --send_ptr; + bytes = send_ptr - send_parms; /* how many bytes we'll process */ + do { + if (bytes-- <= 0) + break; + /* handle MAXL - max length */ + /* ignore what he says - most I'll take (here) is 94 */ + a_b[++length] = tochar (94); + if (bytes-- <= 0) + break; + /* handle TIME - time you should wait for my packets */ + /* ignore what he says - don't wait for my ack longer than 1 second */ + a_b[++length] = tochar (1); + if (bytes-- <= 0) + break; + /* handle NPAD - number of pad chars I need */ + /* remember what he says - I need none */ + his_pad_count = untochar (send_parms[2]); + a_b[++length] = tochar (0); + if (bytes-- <= 0) + break; + /* handle PADC - pad chars I need */ + /* remember what he says - I need none */ + his_pad_char = ktrans (send_parms[3]); + a_b[++length] = 0x40; /* He should ignore this */ + if (bytes-- <= 0) + break; + /* handle EOL - end of line he needs */ + /* remember what he says - I need CR */ + his_eol = untochar (send_parms[4]); + a_b[++length] = tochar (END_CHAR); + if (bytes-- <= 0) + break; + /* handle QCTL - quote control char he'll use */ + /* remember what he says - I'll use '#' */ + his_quote = send_parms[5]; + a_b[++length] = '#'; + if (bytes-- <= 0) + break; + /* handle QBIN - 8-th bit prefixing */ + /* ignore what he says - I refuse */ + a_b[++length] = 'N'; + if (bytes-- <= 0) + break; + /* handle CHKT - the clock check type */ + /* ignore what he says - I do type 1 (for now) */ + a_b[++length] = '1'; + if (bytes-- <= 0) + break; + /* handle REPT - the repeat prefix */ + /* ignore what he says - I refuse (for now) */ + a_b[++length] = 'N'; + if (bytes-- <= 0) + break; + /* handle CAPAS - the capabilities mask */ + /* ignore what he says - I only do long packets - I don't do windows */ + a_b[++length] = tochar (2); /* only long packets */ + a_b[++length] = tochar (0); /* no windows */ + a_b[++length] = tochar (94); /* large packet msb */ + a_b[++length] = tochar (94); /* large packet lsb */ + } while (0); + + a_b[0] = START_CHAR; + a_b[1] = tochar (length); + a_b[2] = tochar (n); + a_b[3] = ACK_TYPE; + a_b[++length] = '\0'; + a_b[length] = tochar (chk1 (&a_b[1])); + a_b[++length] = his_eol; + a_b[++length] = '\0'; + s1_sendpacket (a_b); +} + +/* k_recv receives a OS Open image file over kermit line */ +static int k_recv (void) +{ + char new_char; + char k_state, k_state_saved; + int sum; + int done; + int length; + int n, last_n; + int z = 0; + int len_lo, len_hi; + + /* initialize some protocol parameters */ + his_eol = END_CHAR; /* default end of line character */ + his_pad_count = 0; + his_pad_char = '\0'; + his_quote = K_ESCAPE; + + /* initialize the k_recv and k_data state machine */ + done = 0; + k_state = 0; + k_data_init (); + k_state_saved = k_state; + k_data_save (); + n = 0; /* just to get rid of a warning */ + last_n = -1; + + /* expect this "type" sequence (but don't check): + S: send initiate + F: file header + D: data (multiple) + Z: end of file + B: break transmission + */ + + /* enter main loop */ + while (!done) { + /* set the send packet pointer to begining of send packet parms */ + send_ptr = send_parms; + + /* With each packet, start summing the bytes starting with the length. + Save the current sequence number. + Note the type of the packet. + If a character less than SPACE (0x20) is received - error. + */ + +#if 0 + /* OLD CODE, Prior to checking sequence numbers */ + /* first have all state machines save current states */ + k_state_saved = k_state; + k_data_save (); +#endif + + /* get a packet */ + /* wait for the starting character or ^C */ + for (;;) { + switch (getc ()) { + case START_CHAR: /* start packet */ + goto START; + case ETX_CHAR: /* ^C waiting for packet */ + return (0); + case 'M': + lowlevel_monitor(); + break; + default: + ; + } + } +START: + /* get length of packet */ + sum = 0; + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + length = untochar (new_char); + /* get sequence number */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + n = untochar (new_char); + --length; + + /* NEW CODE - check sequence numbers for retried packets */ + /* Note - this new code assumes that the sequence number is correctly + * received. Handling an invalid sequence number adds another layer + * of complexity that may not be needed - yet! At this time, I'm hoping + * that I don't need to buffer the incoming data packets and can write + * the data into memory in real time. + */ + if (n == last_n) { + /* same sequence number, restore the previous state */ + k_state = k_state_saved; + k_data_restore (); + } else { + /* new sequence number, checkpoint the download */ + last_n = n; + k_state_saved = k_state; + k_data_save (); + } + /* END NEW CODE */ + + /* get packet type */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + k_state = new_char; + --length; + /* check for extended length */ + if (length == -2) { + /* (length byte was 0, decremented twice) */ + /* get the two length bytes */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + len_hi = untochar (new_char); + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + len_lo = untochar (new_char); + length = len_hi * 95 + len_lo; + /* check header checksum */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + if (new_char != tochar ((sum + ((sum >> 6) & 0x03)) & 0x3f)) + goto packet_error; + sum += new_char & 0xff; +/* --length; */ /* new length includes only data and block check to come */ + } + /* bring in rest of packet */ + while (length > 1) { + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + --length; + if (k_state == DATA_TYPE) { + /* pass on the data if this is a data packet */ + k_data_char (new_char); + } else if (k_state == SEND_TYPE) { + /* save send pack in buffer as is */ + *send_ptr++ = new_char; + /* if too much data, back off the pointer */ + if (send_ptr >= &send_parms[SEND_DATA_SIZE]) + --send_ptr; + } + } + /* get and validate checksum character */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + if (new_char != tochar ((sum + ((sum >> 6) & 0x03)) & 0x3f)) + goto packet_error; + /* get END_CHAR */ + new_char = getc (); + if (new_char != END_CHAR) { + packet_error: + /* restore state machines */ + k_state = k_state_saved; + k_data_restore (); + /* send a negative acknowledge packet in */ + send_nack (n); + } else if (k_state == SEND_TYPE) { + /* crack the protocol parms, build an appropriate ack packet */ + handle_send_packet (n); + } else { + /* send simple acknowledge packet in */ + send_ack (n); + /* quit if end of transmission */ + if (k_state == BREAK_TYPE) + done = 1; + } + ++z; + } + return ((ulong) os_data_addr - (ulong) bin_start_address); +} diff --git a/common/cmd_monitor.c b/common/cmd_monitor.c new file mode 100644 index 0000000..05ff5df --- /dev/null +++ b/common/cmd_monitor.c @@ -0,0 +1,361 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Simple command line monitor + * run in Kermit mode by starting with "M" + */ +#include +#include + +#define putc serial_putc +#define tstc serial_tstc + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} +static inline void udelay(unsigned long us) +{ + delay(us * 200); /* approximate */ +} + +typedef struct gpio { + unsigned char res1[0x34]; + unsigned int oe; /* 0x34 */ + unsigned int datain; /* 0x38 */ + unsigned char res2[0x54]; + unsigned int cleardataout; /* 0x90 */ + unsigned int setdataout; /* 0x94 */ +} gpio_t; + +// unclear if the functional clocks are enabled! + +static gpio_t *blocks[]={ // GPIO1 .. 6 + OMAP34XX_GPIO1_BASE, + OMAP34XX_GPIO2_BASE, + OMAP34XX_GPIO3_BASE, + OMAP34XX_GPIO4_BASE, + OMAP34XX_GPIO5_BASE, + OMAP34XX_GPIO6_BASE +}; + +static inline int gpio_get(int n) +{ + int bit=n % 32; + gpio_t *base=blocks[n/32]; + return (base->datain >> bit)&1; +} + +static inline int gpio_is_input(int n) +{ // geht nicht richtig + int bit=n % 32; + gpio_t *base=blocks[n/32]; + return (base->oe >> bit)&1; +} + +int strcmp(char *s1, char *s2) +{ + while(*s1 == *s2) { + if(*s1 == 0) + return 0; // same + s1++; + s2++; + } + return *s1 > *s2?1:-1; +} + +long xtol(char *s) +{ + long val=0; + while(1) + { + if(*s >= '0' && *s <= '9') + val=16*val+(*s++-'0'); + else if(*s >= 'A' && *s <= 'F') + val=16*val+(*s++-'A'+10); + else if(*s >= 'a' && *s <= 'f') + val=16*val+(*s++-'a'+10); + else + break; + } + return val; +} + +static char *addr=(char *) CFG_LOADADDR; +static char line[100]; +static char *argv[10]; + +#define __raw_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) + +#define MUX_VAL(OFFSET,VALUE)\ +__raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) + +void testfn(void) +{ // code can be copied to SDRAM (assuming that it is position-independent!) + int i; + for(i=0; i<10; i++) { + if(i & 1) + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | EN | M4)) /*GPT_PWM11/GPIO57*/ + else + MUX_VAL(CP(GPMC_nCS6), (IEN | PTU | EN | M4)) /*GPT_PWM11/GPIO57*/ + udelay(500*1000); + } +} + +int lowlevel_monitor (void) +{ // add testing code here + int i=0; + printf("Hello World!\n"); + while(1) { + char *c; + int argc=0; + int pos=0; + printf ("$ "); + while(1) { + line[pos]=getc(); + switch(line[pos]) { + case '\b': + case 0x7f: + if(pos > 0) { + putc('\b'); + pos--; + } + continue; + case 0: + case '\n': + continue; // ignore + case '\r': + break; // command + default: + if(pos < sizeof(line)/sizeof(line[0])) { + putc(line[pos]); + pos++; + } + continue; + } + line[pos]=0; + printf("\n"); + break; + } + c=line; + while(argc < sizeof(argv)/sizeof(argv[0])) { + while (*c == ' ' || *c == '\t') + c++; + if(*c == 0) + break; + argv[argc]=c; + while(*c != 0 && *c != '\t' && *c != ' ') + c++; + argc++; + if(*c == 0) + break; + *c=0; // substitute + c++; + } + if(argc == 0) + continue; // empty line +// printf("argc=%d argv[0]=%s\n", argc, argv[0]); + if(strcmp(argv[0], "c") == 0) { // c - copy test function to SDRAM and execute + extern void * memcpy(void * dest,const void *src,size_t count); + void (*fn)(void) = &testfn; + size_t cnt = 0x1000; + addr=(char *) CFG_LOADADDR; + printf("%08x (%d) --> %08x\n", fn, cnt, addr); + memcpy(addr, fn, cnt); + (*fn)(); + } + else if(strcmp(argv[0], "x") == 0) { // x [addr] - execute code + void (*fn)(void) = addr; + if(argc > 1) + fn = (void *) xtol(argv[1]); + (*fn)(); + } + else if(strcmp(argv[0], "l") == 0) { // l - loop + int d=1; + while(1) + printf ("Welcome to uart-monitor (%d)\n", d++), udelay(500*1000); + } + else if(strcmp(argv[0], "a") == 0) { // a [addr] + if(argc > 1) + addr=(char *) xtol(argv[1]); + printf("%08x\n", addr); + } + else if(strcmp(argv[0], "r") == 0) { // r [size] + int i; + int n=1; + if(argc > 1) + n=xtol(argv[1]); + printf("%08x:", addr); + for(i=0; i 1) + n=xtol(argv[1]); + printf("%08x:", addr); + for(i=0; i 1) + val=xtol(argv[1]); + if(argc > 2) + n=xtol(argv[2]); + for(i=0; i> 8) + (((unsigned int) addr) >> 16) + (((unsigned int) addr) >> 24); // build from address + if((((unsigned int)addr) & 0xfffff) == 0) // approx. 1 MByte per second + printf("%08x: %02x\n", addr, val); + *addr=val; // fill ram with prime pattern + } + printf("\nchecking\n"); + for(addr=(char *) CFG_LOADADDR; addr < 512*1024*1024+(char *) 0x80000000; addr++) { + unsigned char r=*addr; // read back + val=(unsigned int) addr + (((unsigned int) addr) >> 8) + (((unsigned int) addr) >> 16) + (((unsigned int) addr) >> 24); + if((((unsigned int)addr) & 0xfffff) == 0) + printf("%08x\n", addr); + if(r != val) // check RAM + printf("read error %8x: %2x %2x\n", addr, r, val); + } + printf("\ndone\n"); + addr=(char *) CFG_LOADADDR; + } +#if 0 + else if(strcmp(argv[0], "clk") == 0) { // clk + extern u32 osc_clk; + printf("clk=%d\n", osc_clk); + } +#endif + else if(strcmp(argv[0], "bl") == 0) { // blink backlight + int i; + for(i=0; i<10; i++) { + printf("blink %d\n", i+1); + // works only on GTA04A3 board since R209 is high compared to PTU + if(i & 1) + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | EN | M4)) /*GPT_PWM11/GPIO57*/ + else + MUX_VAL(CP(GPMC_nCS6), (IEN | PTU | EN | M4)) /*GPT_PWM11/GPIO57*/ + udelay(500*1000); + } + } + else if(strcmp(argv[0], "g") == 0) { // g - read GPIO + unsigned int i; + int n=32*sizeof(blocks)/sizeof(blocks[0]); + printf("GPIO1 data: %08x\n", ((gpio_t *) OMAP34XX_GPIO1_BASE) -> datain); + printf("%03d:", 0); + for(i=0; i>= 16; + } + if(addr == 0x48002264) { + addr=0x480025DC; + printf("\n%08x", addr); + cols=0; + } + else { + addr+=4; + if(++cols == 8) + printf("\n%08x", addr), cols=0; + } + } + printf("\n"); + } + else if(strcmp(argv[0], "k") == 0) { // k - back to kermit mode + printf("Going back to Kermit mode\n"); + break; + } + else + { + printf("uart-monitor unknown command: %s\n", argv[0]); + printf("a: \n"); + printf("bl: \n"); + printf("c: \n"); + printf("f: fill RAM with pattern\n"); + printf("g: read GPIO\n"); + printf("k: back to Kermit mode\n"); + printf("l: \n"); + printf("m: read Pinmux\n"); + printf("r: \n"); + printf("ram: \n"); + printf("rl: \n"); + printf("rt: RAM test\n"); + printf("x: \n"); + } + } + return 0; +} + diff --git a/config.mk b/config.mk new file mode 100644 index 0000000..f4c58e9 --- /dev/null +++ b/config.mk @@ -0,0 +1,208 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +ifneq ($(OBJTREE),$(SRCTREE)) +ifeq ($(CURDIR),$(SRCTREE)) +dir := +else +dir := $(subst $(SRCTREE)/,,$(CURDIR)) +endif + +obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/) +src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/) + +$(shell mkdir -p $(obj)) +else +obj := +src := +endif + +# clean the slate ... +PLATFORM_RELFLAGS = +PLATFORM_CPPFLAGS = +PLATFORM_LDFLAGS = + +# +# When cross-compiling on NetBSD, we have to define __PPC__ or else we +# will pick up a va_list declaration that is incompatible with the +# actual argument lists emitted by the compiler. +# +# [Tested on NetBSD/i386 1.5 + cross-powerpc-netbsd-1.3] + +ifeq ($(ARCH),ppc) +ifeq ($(CROSS_COMPILE),powerpc-netbsd-) +PLATFORM_CPPFLAGS+= -D__PPC__ +endif +ifeq ($(CROSS_COMPILE),powerpc-openbsd-) +PLATFORM_CPPFLAGS+= -D__PPC__ +endif +endif + +ifeq ($(ARCH),arm) +ifeq ($(CROSS_COMPILE),powerpc-netbsd-) +PLATFORM_CPPFLAGS+= -D__ARM__ +endif +ifeq ($(CROSS_COMPILE),powerpc-openbsd-) +PLATFORM_CPPFLAGS+= -D__ARM__ +endif +endif + +ifdef ARCH +sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules +endif +ifdef CPU +sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules +endif +ifdef VENDOR +BOARDDIR = $(VENDOR)/$(BOARD) +else +BOARDDIR = $(BOARD) +endif +ifdef BOARD +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk # include board specific rules +endif + +######################################################################### + +CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ + else if [ -x /bin/bash ]; then echo /bin/bash; \ + else echo sh; fi ; fi) + +ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +HOSTCC = cc +else +HOSTCC = gcc +endif +HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer +HOSTSTRIP = strip + +######################################################################### +# +# Option checker (courtesy linux kernel) to ensure +# only supported compiler options are used +# +cc-option = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \ + > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;) + +# +# Include the make variables (CC, etc...) +# +AS = $(CROSS_COMPILE)as +LD = $(CROSS_COMPILE)ld +CC = $(CROSS_COMPILE)gcc +CPP = $(CC) -E +AR = $(CROSS_COMPILE)ar +NM = $(CROSS_COMPILE)nm +STRIP = $(CROSS_COMPILE)strip +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump +RANLIB = $(CROSS_COMPILE)RANLIB + +RELFLAGS= $(PLATFORM_RELFLAGS) +DBGFLAGS= -g # -DDEBUG +OPTFLAGS= -Os #-fomit-frame-pointer +ifndef LDSCRIPT +#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/x-load.lds.debug +LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/x-load.lds +endif +OBJCFLAGS += --gap-fill=0xff + +gccincdir := $(shell $(CC) -print-file-name=include) + +CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ + -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) + +ifneq ($(OBJTREE),$(SRCTREE)) +CPPFLAGS += -I$(OBJTREE)/include +endif + +CPPFLAGS += -I$(TOPDIR)/include +CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ + -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) + +ifdef BUILD_TAG +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \ + -DBUILD_TAG='"$(BUILD_TAG)"' +else +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes +endif + +AFLAGS_DEBUG := -Wa,-gstabs +AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) + +LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) + +# Location of a usable BFD library, where we define "usable" as +# "built for ${HOST}, supports ${TARGET}". Sensible values are +# - When cross-compiling: the root of the cross-environment +# - Linux/ppc (native): /usr +# - NetBSD/ppc (native): you lose ... (must extract these from the +# binutils build directory, plus the native and U-Boot include +# files don't like each other) +# +# So far, this is used only by tools/gdb/Makefile. + +ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +BFD_ROOT_DIR = /usr/local/tools +else +ifeq ($(HOSTARCH),$(ARCH)) +# native +BFD_ROOT_DIR = /usr +else +#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386 +#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386 +BFD_ROOT_DIR = /opt/powerpc +endif +endif + +######################################################################### + +export CONFIG_SHELL HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \ + AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP \ + MAKE +export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS + +######################################################################### + +ifndef REMOTE_BUILD + +%.s: %.S + $(CPP) $(AFLAGS) -o $@ $< +%.o: %.S + $(CC) $(AFLAGS) -c -o $@ $< +%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< + +else + +$(obj)%.s: %.S + $(CPP) $(AFLAGS) -o $@ $< +$(obj)%.o: %.S + $(CC) $(AFLAGS) -c -o $@ $< +$(obj)%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< +endif + +######################################################################### diff --git a/cpu/arm1136/Makefile b/cpu/arm1136/Makefile new file mode 100644 index 0000000..b556419 --- /dev/null +++ b/cpu/arm1136/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = cpu.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm1136/config.mk b/cpu/arm1136/config.mk new file mode 100644 index 0000000..3106824 --- /dev/null +++ b/cpu/arm1136/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 + +PLATFORM_CPPFLAGS += -march=armv5 +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +# diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c new file mode 100644 index 0000000..1168fb9 --- /dev/null +++ b/cpu/arm1136/cpu.c @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2004 Texas Insturments + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * udelay() is CPU specific code + */ + +#include + +/* See also ARM Ref. Man. */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ +#define C1_WB (1<<3) /* merging write buffer on/off */ +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ +#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ + +int cpu_init (void) +{ + int i; + + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~(C1_DC | C1_IC); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* flush I/D-cache */ + i = 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); // invalidate both caches and flush btb + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); // mem barrier to sync things + + return 0; +} + + + + + + + + diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S new file mode 100644 index 0000000..16108d0 --- /dev/null +++ b/cpu/arm1136/start.S @@ -0,0 +1,218 @@ +/* + * armboot - Startup Code for OMP2420/ARM1136 CPU-core + * + * Copyright (c) 2004 Texas Instruments + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2003 Richard Woodruff + * Copyright (c) 2003 Kshitij + * Copyright (c) 2004 Jian Zhang + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +.globl _start +_start: + b reset + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + +_hang: + .word do_hang + + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 /* now 16*4=64 */ + +.global _end_vect +_end_vect: + + .balignl 16,0xdeadbeef +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* Copy vectors to mask ROM indirect addr */ + adr r0, _start /* r0 <- current position of code */ + add r0, r0, #4 /* skip reset vector */ + mov r2, #64 /* r2 <- size to copy */ + add r2, r0, r2 /* r2 <- source end address */ + mov r1, #0x40000000 /* build vect addr */ + mov r3, #0x00200000 + add r1, r1, r3 + mov r3, #0xf800 + add r1, r1, r3 +next: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next /* loop until equal */ + + bl cpy_clk_code /* put dpll adjust code behind vectors */ + + /* the mask ROM code should have PLL and others stable */ + bl cpu_init_crit + +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + /* beq stack_setup */ + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub sp, r0, #128 /* leave 32 words for abort-stack */ + +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ + +//clbss_l:str r2, [r0] /* clear loop... */ +// add r0, r0, #4 +// cmp r0, r1 +// bne clbss_l + + ldr pc, _start_armboot + +_start_armboot: .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align +#ifndef CONFIG_ICACHE_OFF + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache +#endif + mcr p15, 0, r0, c1, c0, 0 + + /* + * Jump to board specific initialization... The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle wake up conditions. + */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* pass on info about skipping some init portions */ + moveq r0,#0x1 /* flag to skip prcm and sdrc setup */ + movne r0,#0x0 + +//mov r0, #1 /* this skip memory init */ + + mov ip, lr /* persevere link reg across call */ + bl platformsetup /* go setup pll,mux,memory */ + + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ + + +/* + * exception handler + */ + .align 5 +do_hang: + ldr sp, _TEXT_BASE /* use 32 words abort stack */ + bl hang /* hang and never return */ + diff --git a/cpu/omap3/Makefile b/cpu/omap3/Makefile new file mode 100644 index 0000000..678619c --- /dev/null +++ b/cpu/omap3/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = cpu.o mmc.o gpio.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/omap3/config.mk b/cpu/omap3/config.mk new file mode 100644 index 0000000..bd76483 --- /dev/null +++ b/cpu/omap3/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 + +#PLATFORM_CPPFLAGS += -march=armv7-a +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/omap3/cpu.c b/cpu/omap3/cpu.c new file mode 100644 index 0000000..1cf422a --- /dev/null +++ b/cpu/omap3/cpu.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2004-2006 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ +#include + +/* See also ARM Ref. Man. */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ +#define C1_WB (1<<3) /* merging write buffer on/off */ +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ +#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ + +int cpu_init (void) +{ + return 0; +} + diff --git a/cpu/omap3/gpio.c b/cpu/omap3/gpio.c new file mode 100644 index 0000000..aeb6066 --- /dev/null +++ b/cpu/omap3/gpio.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include + +static struct gpio_bank gpio_bank_34xx[6] = { + { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX }, + { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX }, +}; + +static struct gpio_bank *gpio_bank = &gpio_bank_34xx[0]; + +static inline struct gpio_bank *get_gpio_bank(int gpio) +{ + return &gpio_bank[gpio >> 5]; +} + +static inline int get_gpio_index(int gpio) +{ + return gpio & 0x1f; +} + +static inline int gpio_valid(int gpio) +{ + if (gpio < 0) + return -1; + if (gpio < 192) + return 0; + return -1; +} + +static int check_gpio(int gpio) +{ + if (gpio_valid(gpio) < 0) { + printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); + return -1; + } + return 0; +} + +static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) +{ + void *reg = bank->base; + u32 l; + + switch (bank->method) { + case METHOD_GPIO_24XX: + reg += OMAP24XX_GPIO_OE; + break; + default: + return; + } + l = __raw_readl(reg); + if (is_input) + l |= 1 << gpio; + else + l &= ~(1 << gpio); + __raw_writel(l, reg); +} + +void omap_set_gpio_direction(int gpio, int is_input) +{ + struct gpio_bank *bank; + + if (check_gpio(gpio) < 0) + return; + bank = get_gpio_bank(gpio); + _set_gpio_direction(bank, get_gpio_index(gpio), is_input); +} + +static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) +{ + void *reg = bank->base; + u32 l = 0; + + switch (bank->method) { + case METHOD_GPIO_24XX: + if (enable) + reg += OMAP24XX_GPIO_SETDATAOUT; + else + reg += OMAP24XX_GPIO_CLEARDATAOUT; + l = 1 << gpio; + break; + default: + printf("omap3-gpio unknown bank method %s %d\n", + __FILE__, __LINE__); + return; + } + __raw_writel(l, reg); +} + +void omap_set_gpio_dataout(int gpio, int enable) +{ + struct gpio_bank *bank; + + if (check_gpio(gpio) < 0) + return; + bank = get_gpio_bank(gpio); + _set_gpio_dataout(bank, get_gpio_index(gpio), enable); +} + +int omap_get_gpio_datain(int gpio) +{ + struct gpio_bank *bank; + void *reg; + + if (check_gpio(gpio) < 0) + return -EINVAL; + bank = get_gpio_bank(gpio); + reg = bank->base; + switch (bank->method) { + case METHOD_GPIO_24XX: + reg += OMAP24XX_GPIO_DATAIN; + break; + default: + return -EINVAL; + } + return (__raw_readl(reg) + & (1 << get_gpio_index(gpio))) != 0; +} + +static void _reset_gpio(struct gpio_bank *bank, int gpio) +{ + _set_gpio_direction(bank, get_gpio_index(gpio), 1); +} + +int omap_request_gpio(int gpio) +{ + if (check_gpio(gpio) < 0) + return -EINVAL; + + return 0; +} + +void omap_free_gpio(int gpio) +{ + struct gpio_bank *bank; + + if (check_gpio(gpio) < 0) + return; + bank = get_gpio_bank(gpio); + + _reset_gpio(bank, gpio); +} diff --git a/cpu/omap3/mmc.c b/cpu/omap3/mmc.c new file mode 100644 index 0000000..e0c63b0 --- /dev/null +++ b/cpu/omap3/mmc.c @@ -0,0 +1,565 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +const unsigned short mmc_transspeed_val[15][4] = { + {CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)}, + {CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)}, + {CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)}, + {CLKD(15, 1), CLKD(15, 10), CLKD(15, 100), CLKD(15, 1000)}, + {CLKD(20, 1), CLKD(20, 10), CLKD(20, 100), CLKD(20, 1000)}, + {CLKD(26, 1), CLKD(26, 10), CLKD(26, 100), CLKD(26, 1000)}, + {CLKD(30, 1), CLKD(30, 10), CLKD(30, 100), CLKD(30, 1000)}, + {CLKD(35, 1), CLKD(35, 10), CLKD(35, 100), CLKD(35, 1000)}, + {CLKD(40, 1), CLKD(40, 10), CLKD(40, 100), CLKD(40, 1000)}, + {CLKD(45, 1), CLKD(45, 10), CLKD(45, 100), CLKD(45, 1000)}, + {CLKD(52, 1), CLKD(52, 10), CLKD(52, 100), CLKD(52, 1000)}, + {CLKD(55, 1), CLKD(55, 10), CLKD(55, 100), CLKD(55, 1000)}, + {CLKD(60, 1), CLKD(60, 10), CLKD(60, 100), CLKD(60, 1000)}, + {CLKD(70, 1), CLKD(70, 10), CLKD(70, 100), CLKD(70, 1000)}, + {CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)} +}; + +mmc_card_data cur_card_data; +static block_dev_desc_t mmc_blk_dev; + +block_dev_desc_t *mmc_get_dev(int dev) +{ + return ((block_dev_desc_t *) &mmc_blk_dev); +} + +void twl4030_mmc_config(void) +{ + unsigned char data; + + data = 0x20; + i2c_write(0x4B, 0x82, 1, &data, 1); + data = 0x2; + i2c_write(0x4B, 0x85, 1, &data, 1); +} + +unsigned char mmc_board_init(void) +{ + unsigned int value = 0; + + twl4030_mmc_config(); + + value = CONTROL_PBIAS_LITE; + CONTROL_PBIAS_LITE = value | (1 << 2) | (1 << 1) | (1 << 9); + + value = CONTROL_DEV_CONF0; + CONTROL_DEV_CONF0 = value | (1 << 24); + + return 1; +} + +void mmc_init_stream(void) +{ + volatile unsigned int mmc_stat; + + OMAP_HSMMC_CON |= INIT_INITSTREAM; + + OMAP_HSMMC_CMD = MMC_CMD0; + do { + mmc_stat = OMAP_HSMMC_STAT; + } while (!(mmc_stat & CC_MASK)); + + OMAP_HSMMC_STAT = CC_MASK; + + OMAP_HSMMC_CMD = MMC_CMD0; + do { + mmc_stat = OMAP_HSMMC_STAT; + } while (!(mmc_stat & CC_MASK)); + + OMAP_HSMMC_STAT = OMAP_HSMMC_STAT; + OMAP_HSMMC_CON &= ~INIT_INITSTREAM; +} + +unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) +{ + unsigned int val; + + mmc_reg_out(OMAP_HSMMC_SYSCTL, (ICE_MASK | DTO_MASK | CEN_MASK), + (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); + + switch (iclk) { + case CLK_INITSEQ: + val = MMC_INIT_SEQ_CLK / 2; + break; + case CLK_400KHZ: + val = MMC_400kHz_CLK; + break; + case CLK_MISC: + val = clk_div; + break; + default: + return 0; + } + mmc_reg_out(OMAP_HSMMC_SYSCTL, + ICE_MASK | CLKD_MASK, (val << CLKD_OFFSET) | ICE_OSCILLATE); + + while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY) { + } + + OMAP_HSMMC_SYSCTL |= CEN_ENABLE; + return 1; +} + +unsigned char mmc_init_setup(void) +{ + unsigned int reg_val; + + mmc_board_init(); + + OMAP_HSMMC_SYSCONFIG |= MMC_SOFTRESET; + while ((OMAP_HSMMC_SYSSTATUS & RESETDONE) == 0) ; + + OMAP_HSMMC_SYSCTL |= SOFTRESETALL; + while ((OMAP_HSMMC_SYSCTL & SOFTRESETALL) != 0x0) ; + + OMAP_HSMMC_HCTL = DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0; + OMAP_HSMMC_CAPA |= VS30_3V0SUP | VS18_1V8SUP; + + reg_val = OMAP_HSMMC_CON & RESERVED_MASK; + + OMAP_HSMMC_CON = CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | + CDP_ACTIVEHIGH | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | + STR_BLOCK | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN; + + mmc_clock_config(CLK_INITSEQ, 0); + OMAP_HSMMC_HCTL |= SDBP_PWRON; + + OMAP_HSMMC_IE = 0x307f0033; + + mmc_init_stream(); + return 1; +} + +unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, + unsigned int *response) +{ + volatile unsigned int mmc_stat; + + while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS) { + } + + OMAP_HSMMC_BLK = BLEN_512BYTESLEN | NBLK_STPCNT; + OMAP_HSMMC_STAT = 0xFFFFFFFF; + OMAP_HSMMC_ARG = arg; + OMAP_HSMMC_CMD = cmd | CMD_TYPE_NORMAL | CICE_NOCHECK | + CCCE_NOCHECK | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | + DE_DISABLE; + + while (1) { + do { + mmc_stat = OMAP_HSMMC_STAT; + } while (mmc_stat == 0); + + if ((mmc_stat & ERRI_MASK) != 0) + return (unsigned char) mmc_stat; + + if (mmc_stat & CC_MASK) { + OMAP_HSMMC_STAT = CC_MASK; + response[0] = OMAP_HSMMC_RSP10; + if ((cmd & RSP_TYPE_MASK) == RSP_TYPE_LGHT136) { + response[1] = OMAP_HSMMC_RSP32; + response[2] = OMAP_HSMMC_RSP54; + response[3] = OMAP_HSMMC_RSP76; + } + break; + } + } + return 1; +} + +unsigned char mmc_read_data(unsigned int *output_buf) +{ + volatile unsigned int mmc_stat; + unsigned int read_count = 0; + + /* + * Start Polled Read + */ + while (1) { + do { + mmc_stat = OMAP_HSMMC_STAT; + } while (mmc_stat == 0); + + if ((mmc_stat & ERRI_MASK) != 0) + return (unsigned char) mmc_stat; + + if (mmc_stat & BRR_MASK) { + unsigned int k; + + OMAP_HSMMC_STAT |= BRR_MASK; + for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) { + *output_buf = OMAP_HSMMC_DATA; + output_buf++; + read_count += 4; + } + } + + if (mmc_stat & BWR_MASK) + OMAP_HSMMC_STAT |= BWR_MASK; + + if (mmc_stat & TC_MASK) { + OMAP_HSMMC_STAT |= TC_MASK; + break; + } + } + return 1; +} + +unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) +{ + unsigned char err; + unsigned int argument = 0; + unsigned int ocr_value, ocr_recvd, ret_cmd41, hcs_val; + unsigned int resp[4]; + unsigned short retry_cnt = 2000; + + /* Set to Initialization Clock */ + err = mmc_clock_config(CLK_400KHZ, 0); + if (err != 1) + return err; + + mmc_card_cur->RCA = MMC_RELATIVE_CARD_ADDRESS; + argument = 0x00000000; + + ocr_value = (0x1FF << 15); + err = mmc_send_cmd(MMC_CMD0, argument, resp); + if (err != 1) + return err; + + argument = SD_CMD8_CHECK_PATTERN | SD_CMD8_2_7_3_6_V_RANGE; + err = mmc_send_cmd(MMC_SDCMD8, argument, resp); + hcs_val = (err == 1) ? + MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR : + MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE; + + argument = 0x0000 << 16; + err = mmc_send_cmd(MMC_CMD55, argument, resp); + if (err == 1) { + mmc_card_cur->card_type = SD_CARD; + ocr_value |= hcs_val; + ret_cmd41 = MMC_ACMD41; + } else { + mmc_card_cur->card_type = MMC_CARD; + ocr_value |= MMC_OCR_REG_ACCESS_MODE_SECTOR; + ret_cmd41 = MMC_CMD1; + OMAP_HSMMC_CON &= ~OD; + OMAP_HSMMC_CON |= OPENDRAIN; + } + + argument = ocr_value; + err = mmc_send_cmd(ret_cmd41, argument, resp); + if (err != 1) + return err; + + ocr_recvd = ((mmc_resp_r3 *) resp)->ocr; + + while (!(ocr_recvd & (0x1 << 31)) && (retry_cnt > 0)) { + retry_cnt--; + if (mmc_card_cur->card_type == SD_CARD) { + argument = 0x0000 << 16; + err = mmc_send_cmd(MMC_CMD55, argument, resp); + } + + argument = ocr_value; + err = mmc_send_cmd(ret_cmd41, argument, resp); + if (err != 1) + return err; + ocr_recvd = ((mmc_resp_r3 *) resp)->ocr; + } + + if (!(ocr_recvd & (0x1 << 31))) + return 0; + + if (mmc_card_cur->card_type == MMC_CARD) { + if ((ocr_recvd & MMC_OCR_REG_ACCESS_MODE_MASK) == + MMC_OCR_REG_ACCESS_MODE_SECTOR) { + mmc_card_cur->mode = SECTOR_MODE; + } else { + mmc_card_cur->mode = BYTE_MODE; + } + + ocr_recvd &= ~MMC_OCR_REG_ACCESS_MODE_MASK; + } else { + if ((ocr_recvd & MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK) + == MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR) { + mmc_card_cur->mode = SECTOR_MODE; + } else { + mmc_card_cur->mode = BYTE_MODE; + } + ocr_recvd &= ~MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK; + } + + ocr_recvd &= ~(0x1 << 31); + if (!(ocr_recvd & ocr_value)) + return 0; + + err = mmc_send_cmd(MMC_CMD2, argument, resp); + if (err != 1) + return err; + + if (mmc_card_cur->card_type == MMC_CARD) { + argument = mmc_card_cur->RCA << 16; + err = mmc_send_cmd(MMC_CMD3, argument, resp); + if (err != 1) + return err; + } else { + argument = 0x00000000; + err = mmc_send_cmd(MMC_SDCMD3, argument, resp); + if (err != 1) + return err; + + mmc_card_cur->RCA = ((mmc_resp_r6 *) resp)->newpublishedrca; + } + + OMAP_HSMMC_CON &= ~OD; + OMAP_HSMMC_CON |= NOOPENDRAIN; + return 1; +} + +unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, + mmc_csd_reg_t *cur_csd) +{ + mmc_extended_csd_reg_t ext_csd; + unsigned int size, count, blk_len, blk_no, card_size, argument; + unsigned char err; + unsigned int resp[4]; + + if (mmc_dev_data->mode == SECTOR_MODE) { + if (mmc_dev_data->card_type == SD_CARD) { + card_size = + (((mmc_sd2_csd_reg_t *) cur_csd)-> + c_size_lsb & MMC_SD2_CSD_C_SIZE_LSB_MASK) | + ((((mmc_sd2_csd_reg_t *) cur_csd)-> + c_size_msb & MMC_SD2_CSD_C_SIZE_MSB_MASK) + << MMC_SD2_CSD_C_SIZE_MSB_OFFSET); + mmc_dev_data->size = card_size * 1024; + if (mmc_dev_data->size == 0) + return 0; + } else { + argument = 0x00000000; + err = mmc_send_cmd(MMC_CMD8, argument, resp); + if (err != 1) + return err; + err = mmc_read_data((unsigned int *) &ext_csd); + if (err != 1) + return err; + mmc_dev_data->size = ext_csd.sectorcount; + + if (mmc_dev_data->size == 0) + mmc_dev_data->size = 8388608; + } + } else { + if (cur_csd->c_size_mult >= 8) + return 0; + + if (cur_csd->read_bl_len >= 12) + return 0; + + /* Compute size */ + count = 1 << (cur_csd->c_size_mult + 2); + card_size = (cur_csd->c_size_lsb & MMC_CSD_C_SIZE_LSB_MASK) | + ((cur_csd->c_size_msb & MMC_CSD_C_SIZE_MSB_MASK) + << MMC_CSD_C_SIZE_MSB_OFFSET); + blk_no = (card_size + 1) * count; + blk_len = 1 << cur_csd->read_bl_len; + size = blk_no * blk_len; + mmc_dev_data->size = size / MMCSD_SECTOR_SIZE; + if (mmc_dev_data->size == 0) + return 0; + } + return 1; +} + +unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes, + mmc_card_data *mmc_c, + unsigned long *output_buf) +{ + unsigned char err; + unsigned int argument; + unsigned int resp[4]; + unsigned int num_sec_val = + (num_bytes + (MMCSD_SECTOR_SIZE - 1)) / MMCSD_SECTOR_SIZE; + unsigned int sec_inc_val; + + if (num_sec_val == 0) + return 1; + + if (mmc_c->mode == SECTOR_MODE) { + argument = start_sec; + sec_inc_val = 1; + } else { + argument = start_sec * MMCSD_SECTOR_SIZE; + sec_inc_val = MMCSD_SECTOR_SIZE; + } + + while (num_sec_val) { + err = mmc_send_cmd(MMC_CMD17, argument, resp); + if (err != 1) + return err; + + err = mmc_read_data((unsigned int *) output_buf); + if (err != 1) + return err; + + output_buf += (MMCSD_SECTOR_SIZE / 4); + argument += sec_inc_val; + num_sec_val--; + } + return 1; +} + +unsigned char configure_mmc(mmc_card_data *mmc_card_cur) +{ + unsigned char ret_val; + unsigned int argument; + unsigned int resp[4]; + unsigned int trans_clk, trans_fact, trans_unit, retries = 2; + mmc_csd_reg_t Card_CSD; + unsigned char trans_speed; + + ret_val = mmc_init_setup(); + + if (ret_val != 1) + return ret_val; + + do { + ret_val = mmc_detect_card(mmc_card_cur); + retries--; + } while ((retries > 0) && (ret_val != 1)); + + argument = mmc_card_cur->RCA << 16; + ret_val = mmc_send_cmd(MMC_CMD9, argument, resp); + if (ret_val != 1) + return ret_val; + + ((unsigned int *) &Card_CSD)[3] = resp[3]; + ((unsigned int *) &Card_CSD)[2] = resp[2]; + ((unsigned int *) &Card_CSD)[1] = resp[1]; + ((unsigned int *) &Card_CSD)[0] = resp[0]; + + if (mmc_card_cur->card_type == MMC_CARD) + mmc_card_cur->version = Card_CSD.spec_vers; + + trans_speed = Card_CSD.tran_speed; + + ret_val = mmc_send_cmd(MMC_CMD4, MMC_DSR_DEFAULT << 16, resp); + if (ret_val != 1) + return ret_val; + + trans_unit = trans_speed & MMC_CSD_TRAN_SPEED_UNIT_MASK; + trans_fact = trans_speed & MMC_CSD_TRAN_SPEED_FACTOR_MASK; + + if (trans_unit > MMC_CSD_TRAN_SPEED_UNIT_100MHZ) + return 0; + + if ((trans_fact < MMC_CSD_TRAN_SPEED_FACTOR_1_0) || + (trans_fact > MMC_CSD_TRAN_SPEED_FACTOR_8_0)) + return 0; + + trans_unit >>= 0; + trans_fact >>= 3; + + trans_clk = mmc_transspeed_val[trans_fact - 1][trans_unit] * 2; + ret_val = mmc_clock_config(CLK_MISC, trans_clk); + + if (ret_val != 1) + return ret_val; + + argument = mmc_card_cur->RCA << 16; + ret_val = mmc_send_cmd(MMC_CMD7_SELECT, argument, resp); + if (ret_val != 1) + return ret_val; + + /* Configure the block length to 512 bytes */ + argument = MMCSD_SECTOR_SIZE; + ret_val = mmc_send_cmd(MMC_CMD16, argument, resp); + if (ret_val != 1) + return ret_val; + + /* get the card size in sectors */ + ret_val = mmc_read_cardsize(mmc_card_cur, &Card_CSD); + if (ret_val != 1) + return ret_val; + + return 1; +} +unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt, + void *dst) +{ + omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data, + (unsigned long *) dst); + return 1; +} + +int mmc_init(int verbose) +{ + unsigned char ret; + + ret = configure_mmc(&cur_card_data); + + if (ret == 1) { + mmc_blk_dev.if_type = IF_TYPE_MMC; + mmc_blk_dev.part_type = PART_TYPE_DOS; + mmc_blk_dev.dev = 0; + mmc_blk_dev.lun = 0; + mmc_blk_dev.type = 0; + + /* FIXME fill in the correct size (is set to 32MByte) */ + mmc_blk_dev.blksz = MMCSD_SECTOR_SIZE; + mmc_blk_dev.lba = 0x10000; + mmc_blk_dev.removable = 0; + mmc_blk_dev.block_read = mmc_bread; + + fat_register_device(&mmc_blk_dev, 1); + return 1; + } + else + return 0; +} + +int mmc_read(ulong src, uchar *dst, int size) +{ + return 0; +} + +int mmc_write(uchar *src, ulong dst, int size) +{ + return 0; +} + +int mmc2info(ulong addr) +{ + return 0; +} diff --git a/cpu/omap3/start.S b/cpu/omap3/start.S new file mode 100644 index 0000000..4cbf437 --- /dev/null +++ b/cpu/omap3/start.S @@ -0,0 +1,224 @@ +/* + * armboot - Startup Code for OMP2420/ARM1136 CPU-core + * + * Copyright (c) 2004-2006 Texas Instruments + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2003 Richard Woodruff + * Copyright (c) 2003 Kshitij + * Copyright (c) 2004 Jian Zhang + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +.globl _start +_start: + b reset + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + +_hang: + .word do_hang + + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 /* now 16*4=64 */ + +.global _end_vect +_end_vect: + + .balignl 16,0xdeadbeef +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* Copy vectors to mask ROM indirect addr */ + adr r0, _start /* r0 <- current position of code */ + add r0, r0, #4 /* skip reset vector */ + mov r2, #64 /* r2 <- size to copy */ + add r2, r0, r2 /* r2 <- source end address */ + mov r1, #SRAM_OFFSET0 /* build vect addr */ + mov r3, #SRAM_OFFSET1 + add r1, r1, r3 + mov r3, #SRAM_OFFSET2 + add r1, r1, r3 +next: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next /* loop until equal */ + + bl cpy_clk_code /* put dpll adjust code behind vectors */ + + /* the mask ROM code should have PLL and others stable */ + bl cpu_init_crit + +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* no need to relocate if XIP */ + beq stack_setup /* skip txt cpy if XIP(SRAM, SDRAM) */ + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub sp, r0, #128 /* leave 32 words for abort-stack */ + and sp, sp, #~7 /* 8 byte alinged for (ldr/str)d */ + + /* Clear BSS (if any). Is below tx (watch load addr - need space) */ +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear value */ +clbss_l: + str r2, [r0] /* clear BSS location */ + cmp r0, r1 /* are we at the end yet */ + add r0, r0, #4 /* increment clear index pointer */ + bne clbss_l /* keep clearing till at end */ + + ldr pc, _start_armboot /* jump to C code */ + +_start_armboot: .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +cpu_init_crit: + /* + * Invalidate L1 I/D + */ + mov r0, #0 /* set up for MCR */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr p15, 0, r0, c7, c5, 1 /* invalidate icache */ + + /* Invalide L2 cache (gp device call point) + * - warning, this may have issues on EMU/HS devices + * this call can corrupt r0-r5 + */ + mov r12, #0x1 @ set up to invalide L2 +smi: .word 0xE1600070 @ Call SMI monitor + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002000 @ clear bits 13 (--V-) + bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) + orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align +#ifndef CONFIG_ICACHE_OFF + orr r0, r0, #0x00001800 @ set bit 11,12 (---I Z---) BTB,I-Cache +#endif + mcr p15, 0, r0, c1, c0, 0 + + /* + * Jump to board specific initialization... The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle wake up conditions. + */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* pass on info about skipping some init portions */ + moveq r0,#0x1 /* flag to skip prcm and sdrc setup */ + movne r0,#0x0 + + mov ip, lr /* persevere link reg across call */ + bl lowlevel_init /* go setup pll,mux,memory */ + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ + +/* + * exception handler + */ + .align 5 +do_hang: + ldr sp, _TEXT_BASE /* use 32 words abort stack */ + bl hang /* hang and never return */ + diff --git a/cpu/omap4/Makefile b/cpu/omap4/Makefile new file mode 100644 index 0000000..0b39db0 --- /dev/null +++ b/cpu/omap4/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2009 +# Texas Instruments, +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# version 2 as published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = cpu.o mmc.o sys_info.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/omap4/config.mk b/cpu/omap4/config.mk new file mode 100644 index 0000000..20972b5 --- /dev/null +++ b/cpu/omap4/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# version 2 as published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +PLATFORM_CPPFLAGS += -march=armv7-a +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/omap4/cpu.c b/cpu/omap4/cpu.c new file mode 100644 index 0000000..698bbdf --- /dev/null +++ b/cpu/omap4/cpu.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2004-2009 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include + +/* See also ARM Ref. Man. */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ +#define C1_WB (1<<3) /* merging write buffer on/off */ +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ +#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ + +int cpu_init (void) +{ + return 0; +} + +unsigned int cortex_a9_rev(void) +{ + + unsigned int i; + + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (i)); + + return i; +} + +unsigned int omap_revision(void) +{ + unsigned int rev = cortex_a9_rev(); + + switch(rev) { + case 0x410FC091: + return OMAP4430_ES1_0; + case 0x411FC092: + if (__raw_readl(0x4a002204) == 0x3b95c02f) + return OMAP4430_ES2_1; + else + return OMAP4430_ES2_0; + default: + return OMAP4430_SILICON_ID_INVALID; + } +} diff --git a/cpu/omap4/mmc.c b/cpu/omap4/mmc.c new file mode 100644 index 0000000..6842402 --- /dev/null +++ b/cpu/omap4/mmc.c @@ -0,0 +1,547 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +const unsigned short mmc_transspeed_val[15][4] = { + {CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)}, + {CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)}, + {CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)}, + {CLKD(15, 1), CLKD(15, 10), CLKD(15, 100), CLKD(15, 1000)}, + {CLKD(20, 1), CLKD(20, 10), CLKD(20, 100), CLKD(20, 1000)}, + {CLKD(26, 1), CLKD(26, 10), CLKD(26, 100), CLKD(26, 1000)}, + {CLKD(30, 1), CLKD(30, 10), CLKD(30, 100), CLKD(30, 1000)}, + {CLKD(35, 1), CLKD(35, 10), CLKD(35, 100), CLKD(35, 1000)}, + {CLKD(40, 1), CLKD(40, 10), CLKD(40, 100), CLKD(40, 1000)}, + {CLKD(45, 1), CLKD(45, 10), CLKD(45, 100), CLKD(45, 1000)}, + {CLKD(52, 1), CLKD(52, 10), CLKD(52, 100), CLKD(52, 1000)}, + {CLKD(55, 1), CLKD(55, 10), CLKD(55, 100), CLKD(55, 1000)}, + {CLKD(60, 1), CLKD(60, 10), CLKD(60, 100), CLKD(60, 1000)}, + {CLKD(70, 1), CLKD(70, 10), CLKD(70, 100), CLKD(70, 1000)}, + {CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)} +}; + +mmc_card_data cur_card_data; +static block_dev_desc_t mmc_blk_dev; + +block_dev_desc_t *mmc_get_dev(int dev) +{ + return ((block_dev_desc_t *) &mmc_blk_dev); +} + +unsigned char mmc_board_init(void) +{ + unsigned int value = 0; + + return 1; +} + +void mmc_init_stream(void) +{ + volatile unsigned int mmc_stat; + + OMAP_HSMMC_CON |= INIT_INITSTREAM; + + OMAP_HSMMC_CMD = MMC_CMD0; + do { + mmc_stat = OMAP_HSMMC_STAT; + } while (!(mmc_stat & CC_MASK)); + + OMAP_HSMMC_STAT = CC_MASK; + + OMAP_HSMMC_CMD = MMC_CMD0; + do { + mmc_stat = OMAP_HSMMC_STAT; + } while (!(mmc_stat & CC_MASK)); + + OMAP_HSMMC_STAT = OMAP_HSMMC_STAT; + OMAP_HSMMC_CON &= ~INIT_INITSTREAM; +} + +unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) +{ + unsigned int val; + + mmc_reg_out(OMAP_HSMMC_SYSCTL, (ICE_MASK | DTO_MASK | CEN_MASK), + (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); + + switch (iclk) { + case CLK_INITSEQ: + val = MMC_INIT_SEQ_CLK / 2; + break; + case CLK_400KHZ: + val = MMC_400kHz_CLK; + break; + case CLK_MISC: + val = clk_div; + break; + default: + return 0; + } + mmc_reg_out(OMAP_HSMMC_SYSCTL, + ICE_MASK | CLKD_MASK, (val << CLKD_OFFSET) | ICE_OSCILLATE); + + while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY) { + } + + OMAP_HSMMC_SYSCTL |= CEN_ENABLE; + return 1; +} + +unsigned char mmc_init_setup(void) +{ + unsigned int reg_val; + + mmc_board_init(); + + OMAP_HSMMC_SYSCONFIG |= MMC_SOFTRESET; + while ((OMAP_HSMMC_SYSSTATUS & RESETDONE) == 0) ; + + OMAP_HSMMC_SYSCTL |= SOFTRESETALL; + while ((OMAP_HSMMC_SYSCTL & SOFTRESETALL) != 0x0) ; + + OMAP_HSMMC_HCTL = DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0; + OMAP_HSMMC_CAPA |= VS30_3V0SUP | VS18_1V8SUP; + + reg_val = OMAP_HSMMC_CON & RESERVED_MASK; + + OMAP_HSMMC_CON = CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | + CDP_ACTIVEHIGH | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | + STR_BLOCK | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN; + + mmc_clock_config(CLK_INITSEQ, 0); + OMAP_HSMMC_HCTL |= SDBP_PWRON; + + OMAP_HSMMC_IE = 0x307f0033; + + mmc_init_stream(); + return 1; +} + +unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, + unsigned int *response) +{ + volatile unsigned int mmc_stat; + + while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS) { + } + + OMAP_HSMMC_BLK = BLEN_512BYTESLEN | NBLK_STPCNT; + OMAP_HSMMC_STAT = 0xFFFFFFFF; + OMAP_HSMMC_ARG = arg; + OMAP_HSMMC_CMD = cmd | CMD_TYPE_NORMAL | CICE_NOCHECK | + CCCE_NOCHECK | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | + DE_DISABLE; + + while (1) { + do { + mmc_stat = OMAP_HSMMC_STAT; + } while (mmc_stat == 0); + + if ((mmc_stat & ERRI_MASK) != 0) + return (unsigned char) mmc_stat; + + if (mmc_stat & CC_MASK) { + OMAP_HSMMC_STAT = CC_MASK; + response[0] = OMAP_HSMMC_RSP10; + if ((cmd & RSP_TYPE_MASK) == RSP_TYPE_LGHT136) { + response[1] = OMAP_HSMMC_RSP32; + response[2] = OMAP_HSMMC_RSP54; + response[3] = OMAP_HSMMC_RSP76; + } + break; + } + } + return 1; +} + +unsigned char mmc_read_data(unsigned int *output_buf) +{ + volatile unsigned int mmc_stat; + unsigned int read_count = 0; + + /* + * Start Polled Read + */ + while (1) { + do { + mmc_stat = OMAP_HSMMC_STAT; + } while (mmc_stat == 0); + + if ((mmc_stat & ERRI_MASK) != 0) + return (unsigned char) mmc_stat; + + if (mmc_stat & BRR_MASK) { + unsigned int k; + + OMAP_HSMMC_STAT |= BRR_MASK; + for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) { + *output_buf = OMAP_HSMMC_DATA; + output_buf++; + read_count += 4; + } + } + + if (mmc_stat & BWR_MASK) + OMAP_HSMMC_STAT |= BWR_MASK; + + if (mmc_stat & TC_MASK) { + OMAP_HSMMC_STAT |= TC_MASK; + break; + } + } + return 1; +} + +unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) +{ + unsigned char err; + unsigned int argument = 0; + unsigned int ocr_value, ocr_recvd, ret_cmd41, hcs_val; + unsigned int resp[4]; + unsigned short retry_cnt = 2000; + + /* Set to Initialization Clock */ + err = mmc_clock_config(CLK_400KHZ, 0); + if (err != 1) + return err; + + mmc_card_cur->RCA = MMC_RELATIVE_CARD_ADDRESS; + argument = 0x00000000; + + ocr_value = (0x1FF << 15); + err = mmc_send_cmd(MMC_CMD0, argument, resp); + if (err != 1) + return err; + + argument = SD_CMD8_CHECK_PATTERN | SD_CMD8_2_7_3_6_V_RANGE; + err = mmc_send_cmd(MMC_SDCMD8, argument, resp); + hcs_val = (err == 1) ? + MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR : + MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE; + + argument = 0x0000 << 16; + err = mmc_send_cmd(MMC_CMD55, argument, resp); + if (err == 1) { + mmc_card_cur->card_type = SD_CARD; + ocr_value |= hcs_val; + ret_cmd41 = MMC_ACMD41; + } else { + mmc_card_cur->card_type = MMC_CARD; + ocr_value |= MMC_OCR_REG_ACCESS_MODE_SECTOR; + ret_cmd41 = MMC_CMD1; + OMAP_HSMMC_CON &= ~OD; + OMAP_HSMMC_CON |= OPENDRAIN; + } + + argument = ocr_value; + err = mmc_send_cmd(ret_cmd41, argument, resp); + if (err != 1) + return err; + + ocr_recvd = ((mmc_resp_r3 *) resp)->ocr; + + while (!(ocr_recvd & (0x1 << 31)) && (retry_cnt > 0)) { + retry_cnt--; + if (mmc_card_cur->card_type == SD_CARD) { + argument = 0x0000 << 16; + err = mmc_send_cmd(MMC_CMD55, argument, resp); + } + + argument = ocr_value; + err = mmc_send_cmd(ret_cmd41, argument, resp); + if (err != 1) + return err; + ocr_recvd = ((mmc_resp_r3 *) resp)->ocr; + } + + if (!(ocr_recvd & (0x1 << 31))) + return 0; + + if (mmc_card_cur->card_type == MMC_CARD) { + if ((ocr_recvd & MMC_OCR_REG_ACCESS_MODE_MASK) == + MMC_OCR_REG_ACCESS_MODE_SECTOR) { + mmc_card_cur->mode = SECTOR_MODE; + } else { + mmc_card_cur->mode = BYTE_MODE; + } + + ocr_recvd &= ~MMC_OCR_REG_ACCESS_MODE_MASK; + } else { + if ((ocr_recvd & MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK) + == MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR) { + mmc_card_cur->mode = SECTOR_MODE; + } else { + mmc_card_cur->mode = BYTE_MODE; + } + ocr_recvd &= ~MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK; + } + + ocr_recvd &= ~(0x1 << 31); + if (!(ocr_recvd & ocr_value)) + return 0; + + err = mmc_send_cmd(MMC_CMD2, argument, resp); + if (err != 1) + return err; + + if (mmc_card_cur->card_type == MMC_CARD) { + argument = mmc_card_cur->RCA << 16; + err = mmc_send_cmd(MMC_CMD3, argument, resp); + if (err != 1) + return err; + } else { + argument = 0x00000000; + err = mmc_send_cmd(MMC_SDCMD3, argument, resp); + if (err != 1) + return err; + + mmc_card_cur->RCA = ((mmc_resp_r6 *) resp)->newpublishedrca; + } + + OMAP_HSMMC_CON &= ~OD; + OMAP_HSMMC_CON |= NOOPENDRAIN; + return 1; +} + +unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, + mmc_csd_reg_t *cur_csd) +{ + mmc_extended_csd_reg_t ext_csd; + unsigned int size, count, blk_len, blk_no, card_size, argument; + unsigned char err; + unsigned int resp[4]; + + if (mmc_dev_data->mode == SECTOR_MODE) { + if (mmc_dev_data->card_type == SD_CARD) { + card_size = + (((mmc_sd2_csd_reg_t *) cur_csd)-> + c_size_lsb & MMC_SD2_CSD_C_SIZE_LSB_MASK) | + ((((mmc_sd2_csd_reg_t *) cur_csd)-> + c_size_msb & MMC_SD2_CSD_C_SIZE_MSB_MASK) + << MMC_SD2_CSD_C_SIZE_MSB_OFFSET); + mmc_dev_data->size = card_size * 1024; + if (mmc_dev_data->size == 0) + return 0; + } else { + argument = 0x00000000; + err = mmc_send_cmd(MMC_CMD8, argument, resp); + if (err != 1) + return err; + err = mmc_read_data((unsigned int *) &ext_csd); + if (err != 1) + return err; + mmc_dev_data->size = ext_csd.sectorcount; + + if (mmc_dev_data->size == 0) + mmc_dev_data->size = 8388608; + } + } else { + if (cur_csd->c_size_mult >= 8) + return 0; + + if (cur_csd->read_bl_len >= 12) + return 0; + + /* Compute size */ + count = 1 << (cur_csd->c_size_mult + 2); + card_size = (cur_csd->c_size_lsb & MMC_CSD_C_SIZE_LSB_MASK) | + ((cur_csd->c_size_msb & MMC_CSD_C_SIZE_MSB_MASK) + << MMC_CSD_C_SIZE_MSB_OFFSET); + blk_no = (card_size + 1) * count; + blk_len = 1 << cur_csd->read_bl_len; + size = blk_no * blk_len; + mmc_dev_data->size = size / MMCSD_SECTOR_SIZE; + if (mmc_dev_data->size == 0) + return 0; + } + return 1; +} + +unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes, + mmc_card_data *mmc_c, + unsigned long *output_buf) +{ + unsigned char err; + unsigned int argument; + unsigned int resp[4]; + unsigned int num_sec_val = + (num_bytes + (MMCSD_SECTOR_SIZE - 1)) / MMCSD_SECTOR_SIZE; + unsigned int sec_inc_val; + + if (num_sec_val == 0) + return 1; + + if (mmc_c->mode == SECTOR_MODE) { + argument = start_sec; + sec_inc_val = 1; + } else { + argument = start_sec * MMCSD_SECTOR_SIZE; + sec_inc_val = MMCSD_SECTOR_SIZE; + } + + while (num_sec_val) { + err = mmc_send_cmd(MMC_CMD17, argument, resp); + if (err != 1) + return err; + + err = mmc_read_data((unsigned int *) output_buf); + if (err != 1) + return err; + + output_buf += (MMCSD_SECTOR_SIZE / 4); + argument += sec_inc_val; + num_sec_val--; + } + return 1; +} + +unsigned char configure_mmc(mmc_card_data *mmc_card_cur) +{ + unsigned char ret_val; + unsigned int argument; + unsigned int resp[4]; + unsigned int trans_clk, trans_fact, trans_unit, retries = 2; + mmc_csd_reg_t Card_CSD; + unsigned char trans_speed; + + ret_val = mmc_init_setup(); + + if (ret_val != 1) + return ret_val; + + do { + ret_val = mmc_detect_card(mmc_card_cur); + retries--; + } while ((retries > 0) && (ret_val != 1)); + + argument = mmc_card_cur->RCA << 16; + ret_val = mmc_send_cmd(MMC_CMD9, argument, resp); + if (ret_val != 1) + return ret_val; + + ((unsigned int *) &Card_CSD)[3] = resp[3]; + ((unsigned int *) &Card_CSD)[2] = resp[2]; + ((unsigned int *) &Card_CSD)[1] = resp[1]; + ((unsigned int *) &Card_CSD)[0] = resp[0]; + + if (mmc_card_cur->card_type == MMC_CARD) + mmc_card_cur->version = Card_CSD.spec_vers; + + trans_speed = Card_CSD.tran_speed; + + ret_val = mmc_send_cmd(MMC_CMD4, MMC_DSR_DEFAULT << 16, resp); + if (ret_val != 1) + return ret_val; + + trans_unit = trans_speed & MMC_CSD_TRAN_SPEED_UNIT_MASK; + trans_fact = trans_speed & MMC_CSD_TRAN_SPEED_FACTOR_MASK; + + if (trans_unit > MMC_CSD_TRAN_SPEED_UNIT_100MHZ) + return 0; + + if ((trans_fact < MMC_CSD_TRAN_SPEED_FACTOR_1_0) || + (trans_fact > MMC_CSD_TRAN_SPEED_FACTOR_8_0)) + return 0; + + trans_unit >>= 0; + trans_fact >>= 3; + + trans_clk = mmc_transspeed_val[trans_fact - 1][trans_unit] * 2; + ret_val = mmc_clock_config(CLK_MISC, trans_clk); + + if (ret_val != 1) + return ret_val; + + argument = mmc_card_cur->RCA << 16; + ret_val = mmc_send_cmd(MMC_CMD7_SELECT, argument, resp); + if (ret_val != 1) + return ret_val; + + /* Configure the block length to 512 bytes */ + argument = MMCSD_SECTOR_SIZE; + ret_val = mmc_send_cmd(MMC_CMD16, argument, resp); + if (ret_val != 1) + return ret_val; + + /* get the card size in sectors */ + ret_val = mmc_read_cardsize(mmc_card_cur, &Card_CSD); + if (ret_val != 1) + return ret_val; + + return 1; +} +unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt, + void *dst) +{ + omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data, + (unsigned long *) dst); + return 1; +} + +int mmc_init(int verbose) +{ + unsigned char ret; + + ret = configure_mmc(&cur_card_data); + + if (ret == 1) { + mmc_blk_dev.if_type = IF_TYPE_MMC; + mmc_blk_dev.part_type = PART_TYPE_DOS; + mmc_blk_dev.dev = 0; + mmc_blk_dev.lun = 0; + mmc_blk_dev.type = 0; + + /* FIXME fill in the correct size (is set to 32MByte) */ + mmc_blk_dev.blksz = MMCSD_SECTOR_SIZE; + mmc_blk_dev.lba = 0x10000; + mmc_blk_dev.removable = 0; + mmc_blk_dev.block_read = mmc_bread; + + fat_register_device(&mmc_blk_dev, 1); + return 1; + } + else + return 0; +} + +int mmc_read(ulong src, uchar *dst, int size) +{ + return 0; +} + +int mmc_write(uchar *src, ulong dst, int size) +{ + return 0; +} + +int mmc2info(ulong addr) +{ + return 0; +} diff --git a/cpu/omap4/sys_info.c b/cpu/omap4/sys_info.c new file mode 100644 index 0000000..29d39e6 --- /dev/null +++ b/cpu/omap4/sys_info.c @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + return CPU_4430_ES1; + +} + + diff --git a/disk/Makefile b/disk/Makefile new file mode 100644 index 0000000..512b1cb --- /dev/null +++ b/disk/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +#CFLAGS += -DET_DEBUG -DDEBUG + +LIB = $(obj)libdisk.a + +COBJS = part.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/disk/part.c b/disk/part.c new file mode 100644 index 0000000..a367f13 --- /dev/null +++ b/disk/part.c @@ -0,0 +1,273 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#undef PART_DEBUG + +#ifdef PART_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + defined(CONFIG_MMC) || \ + defined(CONFIG_SYSTEMACE) ) + +/* ------------------------------------------------------------------------- */ +/* + * reports device info to the user + */ +void dev_print (block_dev_desc_t *dev_desc) +{ +#ifdef CONFIG_LBA48 + uint64_t lba512; /* number of blocks if 512bytes block size */ +#else + lbaint_t lba512; +#endif + + if (dev_desc->type==DEV_TYPE_UNKNOWN) { + return; + } + if (dev_desc->if_type==IF_TYPE_SCSI) { + printf ("(%d:%d) ", dev_desc->target,dev_desc->lun); + } + if (dev_desc->if_type==IF_TYPE_IDE) { + printf ("Model: %s Firm: %s Ser#: %s\n", + dev_desc->vendor, + dev_desc->revision, + dev_desc->product); + } else { + printf ("Vendor: %s Prod.: %s Rev: %s\n", + dev_desc->vendor, + dev_desc->product, + dev_desc->revision); + } + printf (" Type: "); + switch (dev_desc->type & 0x1F) { + case DEV_TYPE_HARDDISK: printf ("Hard Disk"); + break; + case DEV_TYPE_CDROM: printf ("CD ROM"); + break; + case DEV_TYPE_OPDISK: printf ("Optical Device"); + break; + case DEV_TYPE_TAPE: printf ("Tape"); + break; + default: printf ("# %02X #", dev_desc->type & 0x1F); + break; + } + if ((dev_desc->lba * dev_desc->blksz)>0L) { + ulong mb, mb_quot, mb_rem, gb, gb_quot, gb_rem; + lbaint_t lba; + + lba = dev_desc->lba; + + lba512 = (lba * (dev_desc->blksz/512)); + mb = (10 * lba512) / 2048; /* 2048 = (1024 * 1024) / 512 MB */ + /* round to 1 digit */ + mb_quot = mb / 10; + mb_rem = mb - (10 * mb_quot); + + gb = mb / 1024; + gb_quot = gb / 10; + gb_rem = gb - (10 * gb_quot); +#ifdef CONFIG_LBA48 + if (dev_desc->lba48) + printf (" Supports 48-bit addressing\n"); +#endif +#if defined(CFG_64BIT_LBA) && defined(CFG_64BIT_VSPRINTF) + printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%qd x %ld)\n", + mb_quot, mb_rem, + gb_quot, gb_rem, + lba, + dev_desc->blksz); +#else + printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\n", + mb_quot, mb_rem, + gb_quot, gb_rem, + (ulong)lba, + dev_desc->blksz); +#endif + } else { + printf (" Capacity: not available\n"); + } +} +#endif /* CFG_CMD_IDE || CFG_CMD_SCSI || CFG_CMD_USB || CONFIG_MMC */ + +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + (CONFIG_COMMANDS & CFG_CMD_MMC) || \ + defined(CONFIG_SYSTEMACE) ) + +#if defined(CONFIG_MAC_PARTITION) || \ + defined(CONFIG_DOS_PARTITION) || \ + defined(CONFIG_ISO_PARTITION) || \ + defined(CONFIG_AMIGA_PARTITION) + +void init_part (block_dev_desc_t * dev_desc) +{ +#ifdef CONFIG_ISO_PARTITION + if (test_part_iso(dev_desc) == 0) { + dev_desc->part_type = PART_TYPE_ISO; + return; + } +#endif + +#ifdef CONFIG_MAC_PARTITION + if (test_part_mac(dev_desc) == 0) { + dev_desc->part_type = PART_TYPE_MAC; + return; + } +#endif + +#ifdef CONFIG_DOS_PARTITION + if (test_part_dos(dev_desc) == 0) { + dev_desc->part_type = PART_TYPE_DOS; + return; + } +#endif + +#ifdef CONFIG_AMIGA_PARTITION + if (test_part_amiga(dev_desc) == 0) { + dev_desc->part_type = PART_TYPE_AMIGA; + return; + } +#endif +} + + +int get_partition_info (block_dev_desc_t *dev_desc, int part, disk_partition_t *info) +{ + switch (dev_desc->part_type) { +#ifdef CONFIG_MAC_PARTITION + case PART_TYPE_MAC: + if (get_partition_info_mac(dev_desc,part,info) == 0) { + PRINTF ("## Valid MAC partition found ##\n"); + return (0); + } + break; +#endif + +#ifdef CONFIG_DOS_PARTITION + case PART_TYPE_DOS: + if (get_partition_info_dos(dev_desc,part,info) == 0) { + PRINTF ("## Valid DOS partition found ##\n"); + return (0); + } + break; +#endif + +#ifdef CONFIG_ISO_PARTITION + case PART_TYPE_ISO: + if (get_partition_info_iso(dev_desc,part,info) == 0) { + PRINTF ("## Valid ISO boot partition found ##\n"); + return (0); + } + break; +#endif + +#ifdef CONFIG_AMIGA_PARTITION + case PART_TYPE_AMIGA: + if (get_partition_info_amiga(dev_desc, part, info) == 0) + { + PRINTF ("## Valid Amiga partition found ##\n"); + return (0); + } + break; +#endif + default: + break; + } + return (-1); +} + +static void print_part_header (const char *type, block_dev_desc_t * dev_desc) +{ + switch (dev_desc->if_type) { + case IF_TYPE_IDE: printf ("IDE"); + break; + case IF_TYPE_SCSI: printf ("SCSI"); + break; + case IF_TYPE_ATAPI: printf ("ATAPI"); + break; + case IF_TYPE_USB: printf ("USB"); + break; + case IF_TYPE_DOC: printf ("DOC"); + break; + default: printf ("UNKNOWN"); + break; + } + printf (" device %d -- Partition Type: %s\n\n", + dev_desc->dev, type); +} + +void print_part (block_dev_desc_t * dev_desc) +{ + + switch (dev_desc->part_type) { +#ifdef CONFIG_MAC_PARTITION + case PART_TYPE_MAC: + PRINTF ("## Testing for valid MAC partition ##\n"); + print_part_header ("MAC", dev_desc); + print_part_mac (dev_desc); + return; +#endif +#ifdef CONFIG_DOS_PARTITION + case PART_TYPE_DOS: + PRINTF ("## Testing for valid DOS partition ##\n"); + print_part_header ("DOS", dev_desc); + print_part_dos (dev_desc); + return; +#endif + +#ifdef CONFIG_ISO_PARTITION + case PART_TYPE_ISO: + PRINTF ("## Testing for valid ISO Boot partition ##\n"); + print_part_header ("ISO", dev_desc); + print_part_iso (dev_desc); + return; +#endif + +#ifdef CONFIG_AMIGA_PARTITION + case PART_TYPE_AMIGA: + PRINTF ("## Testing for a valid Amiga partition ##\n"); + print_part_header ("AMIGA", dev_desc); + print_part_amiga (dev_desc); + return; +#endif + } +} + + +#else /* neither MAC nor DOS nor ISO partition configured */ +# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION nor CONFIG_ISO_PARTITION configured! +#endif + +#endif /* (CONFIG_COMMANDS & CFG_CMD_IDE) || CONFIG_COMMANDS & CFG_CMD_SCSI) */ diff --git a/drivers/Makefile b/drivers/Makefile new file mode 100644 index 0000000..da3feda --- /dev/null +++ b/drivers/Makefile @@ -0,0 +1,84 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG -DDEBUG + +LIB = $(obj)libdrivers.a +COBJS = serial.o ns16550.o omap24xx_i2c.o + +ifeq ($(BOARD), omap3430sdp) +COBJS += k9f1g08r0a.o +endif + +ifeq ($(BOARD), omap3430labrador) +COBJS += k9f1g08r0a.o +endif + +ifeq ($(BOARD), omap3530beagle) +COBJS += k9f1g08r0a.o +endif + +ifeq ($(BOARD), omap3530gta04) +COBJS += k9f1g08r0a.o +endif + +ifeq ($(BOARD), omap3evm) +COBJS += k9f1g08r0a.o onenand.o +endif + +ifeq ($(BOARD), overo) +COBJS += k9f1g08r0a.o +endif + +ifeq ($(BOARD), omap2420h4) +COBJS += k9k1216.o +endif + +ifeq ($(BOARD), omap2430sdp) +COBJS += k9k1216.o +endif + +## Disabled for now: +## cs8900.o ct69000.o dataflash.o dc2114x.o ds1722.o \ +## lan91c96.o mw_eeprom.o natsemi.o \ +## smc91111.o smiLynxEM.o spi_eeprom.o sym53c8xx.o \ +## + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/k9f1g08r0a.c b/drivers/k9f1g08r0a.c new file mode 100644 index 0000000..988533c --- /dev/null +++ b/drivers/k9f1g08r0a.c @@ -0,0 +1,350 @@ +/* + * (C) Copyright 2004 Texas Instruments + * Jian Zhang + * + * Samsung K9F1G08R0AQ0C NAND chip driver for an OMAP2420 board + * + * This file is based on the following u-boot file: + * common/cmd_nand.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include +#include + +#ifdef CFG_NAND_K9F1G08R0A + +#define K9F1G08R0A_MFR 0xec /* Samsung */ +#define K9F1G08R0A_ID 0xa1 /* part # */ + +/* Since Micron and Samsung parts are similar in geometry and bus width + * we can use the same driver. Need to revisit to make this file independent + * of part/manufacturer + */ +#define MT29F1G_MFR 0x2c /* Micron */ +#define MT29F1G_MFR2 0x20 /* numonyx */ +#define MT29F1G_MFR3 0xad /* Hynix */ +#define MT29F1G_ID 0xa1 /* x8, 1GiB */ +#define MT29F2G_ID 0xba /* x16, 2GiB */ +#define MT29F4G_ID 0xbc /* x16, 4GiB */ + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE (ADDR_COLUMN | ADDR_PAGE) + +#define ADDR_OOB (0x4 | ADDR_COLUMN_PAGE) + +#define PAGE_SIZE 2048 +#define OOB_SIZE 64 +#define MAX_NUM_PAGES 64 + +#define ECC_CHECK_ENABLE +#define ECC_SIZE 24 +#define ECC_STEPS 3 + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %0, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +static int nand_read_page(u_char *buf, ulong page_addr); +static int nand_read_oob(u_char * buf, ulong page_addr); + +/* JFFS2 large page layout for 3-byte ECC per 256 bytes ECC layout */ +/* This is the only SW ECC supported by u-boot. So to load u-boot + * this should be supported */ +static u_char ecc_pos[] = + {40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63}; +static u_char eccvalid_pos = 4; + +static unsigned long chipsize = (256 << 20); + +#ifdef NAND_16BIT +static int bus_width = 16; +#else +static int bus_width = 8; +#endif + +/* NanD_Command: Send a flash command to the flash chip */ +static int NanD_Command(unsigned char command) +{ + NAND_CTL_SETCLE(NAND_ADDR); + + WRITE_NAND_COMMAND(command, NAND_ADDR); + NAND_CTL_CLRCLE(NAND_ADDR); + + if(command == NAND_CMD_RESET){ + unsigned char ret_val; + NanD_Command(NAND_CMD_STATUS); + do{ + ret_val = READ_NAND(NAND_ADDR);/* wait till ready */ + } while((ret_val & 0x40) != 0x40); + } + + NAND_WAIT_READY(); + return 0; +} + + +/* NanD_Address: Set the current address for the flash chip */ +static int NanD_Address(unsigned int numbytes, unsigned long ofs) +{ + uchar u; + + NAND_CTL_SETALE(NAND_ADDR); + + if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE + || numbytes == ADDR_OOB) + { + ushort col = ofs; + + u = col & 0xff; + WRITE_NAND_ADDRESS(u, NAND_ADDR); + + u = (col >> 8) & 0x07; + if (numbytes == ADDR_OOB) + u = u | ((bus_width == 16) ? (1 << 2) : (1 << 3)); + WRITE_NAND_ADDRESS(u, NAND_ADDR); + } + + if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE + || numbytes == ADDR_OOB) + { + u = (ofs >> 11) & 0xff; + WRITE_NAND_ADDRESS(u, NAND_ADDR); + u = (ofs >> 19) & 0xff; + WRITE_NAND_ADDRESS(u, NAND_ADDR); + + /* One more address cycle for devices > 128MiB */ + if (chipsize > (128 << 20)) { + u = (ofs >> 27) & 0xff; + WRITE_NAND_ADDRESS(u, NAND_ADDR); + } + } + + NAND_CTL_CLRALE(NAND_ADDR); + + NAND_WAIT_READY(); + return 0; +} + +int nand_readid(int *mfr, int *id) +{ + NAND_ENABLE_CE(); + + if (NanD_Command(NAND_CMD_RESET)) { + NAND_DISABLE_CE(); + return 1; + } + + if (NanD_Command(NAND_CMD_READID)) { + NAND_DISABLE_CE(); + return 1; + } + + NanD_Address(ADDR_COLUMN, 0); + + *mfr = READ_NAND(NAND_ADDR); + *id = READ_NAND(NAND_ADDR); + + NAND_DISABLE_CE(); + return 0; +} + +/* read chip mfr and id + * return 0 if they match board config + * return 1 if not + */ +int nand_chip() +{ + int mfr, id; + + NAND_ENABLE_CE(); + + if (NanD_Command(NAND_CMD_RESET)) { + printf("Err: RESET\n"); + NAND_DISABLE_CE(); + return 1; + } + + if (NanD_Command(NAND_CMD_READID)) { + printf("Err: READID\n"); + NAND_DISABLE_CE(); + return 1; + } + + NanD_Address(ADDR_COLUMN, 0); + + mfr = READ_NAND(NAND_ADDR); + id = READ_NAND(NAND_ADDR); + + NAND_DISABLE_CE(); + + if (((mfr == MT29F1G_MFR || mfr == MT29F1G_MFR2 || mfr == MT29F1G_MFR3) && + (id == MT29F1G_ID || id == MT29F2G_ID || id == MT29F4G_ID)) || + (mfr == K9F1G08R0A_MFR && (id == K9F1G08R0A_ID))) { + return 0; + } else { + if ((mfr == 0) && (id == 0)) { + printf("No NAND detected\n"); + return 0; + } else { + printf("Unknown chip: mfr was 0x%02x, id was 0x%02x\n", mfr, id); + return 1; + } + } +} + +/* read a block data to buf + * return 1 if the block is bad or ECC error can't be corrected for any page + * return 0 on sucess + */ +int nand_read_block(unsigned char *buf, ulong block_addr) +{ + int i, offset = 0; + +#ifdef ECC_CHECK_ENABLE + u16 oob_buf[OOB_SIZE >> 1]; + + /* check bad block */ + /* 0th word in spare area needs be 0xff */ + if (nand_read_oob(oob_buf, block_addr) || (oob_buf[0] & 0xff) != 0xff){ + printf("Skipped bad block at 0x%x\n", block_addr); + return 1; /* skip bad block */ + } +#endif + /* read the block page by page*/ + for (i=0; i> 1 : PAGE_SIZE; + p = buf; + for (cntr = 0; cntr < len; cntr++){ + *p++ = READ_NAND(NAND_ADDR); + delay(10); + } + +#ifdef ECC_CHECK_ENABLE + p = oob_buf; + len = (bus_width == 16) ? OOB_SIZE >> 1 : OOB_SIZE; + for (cntr = 0; cntr < len; cntr++){ + *p++ = READ_NAND(NAND_ADDR); + delay(10); + } + count = 0; + NAND_DISABLE_CE(); /* set pin high */ + + /* Pick the ECC bytes out of the oob data */ + for (cntr = 0; cntr < ECC_SIZE; cntr++) + ecc_code[cntr] = oob_buf[ecc_pos[cntr]]; + + for(count = 0; count < ECC_SIZE; count += ECC_STEPS) { + nand_calculate_ecc (buf, &ecc_calc[0]); + if (nand_correct_data (buf, &ecc_code[count], &ecc_calc[0]) == -1) { + printf ("ECC Failed, page 0x%08x\n", page_addr); + for (val=0; val <256; val++) + printf("%x ", buf[val]); + printf("\n"); + for (;;); + return 1; + } + buf += 256; + page_addr += 256; + } +#endif + return 0; +} + +/* read from the 16 bytes of oob data that correspond to a 512 / 2048 byte page. + */ +static int nand_read_oob(u_char *buf, ulong page_addr) +{ + u16 val; + int cntr; + int len; + +#ifdef NAND_16BIT + u16 *p; +#else + u_char *p; +#endif + p = buf; + len = (bus_width == 16) ? OOB_SIZE >> 1 : OOB_SIZE; + + NAND_ENABLE_CE(); /* set pin low */ + NanD_Command(NAND_CMD_READ0); + NanD_Address(ADDR_OOB, page_addr); + NanD_Command(NAND_CMD_READSTART); + NAND_WAIT_READY(); + + /* A delay seems to be helping here. needs more investigation */ + delay(10000); + for (cntr = 0; cntr < len; cntr++) + *p++ = READ_NAND(NAND_ADDR); + + NAND_WAIT_READY(); + NAND_DISABLE_CE(); /* set pin high */ + + return 0; +} + +#endif diff --git a/drivers/k9k1216.c b/drivers/k9k1216.c new file mode 100644 index 0000000..888fb6b --- /dev/null +++ b/drivers/k9k1216.c @@ -0,0 +1,258 @@ +/* + * (C) Copyright 2004 Texas Instruments + * Jian Zhang + * + * Samsung K9K1216Q0C NAND chip driver for an OMAP2420 board + * + * This file is based on the following u-boot file: + * common/cmd_nand.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CFG_NAND_K9K1216 + +#define K9K1216_MFR 0xec +#define K9K1216_ID 0x46 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define PAGE_SIZE 512 +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +static int nand_read_page(u_char *buf, ulong page_addr); +static int nand_read_oob(u_char * buf, ulong page_addr); + +/* JFFS2 512-byte-page ECC layout */ +static u_char ecc_pos[] = {0,1,2,3,6,7}; +static u_char eccvalid_pos = 4; + +/* NanD_Command: Send a flash command to the flash chip */ +static int NanD_Command(unsigned char command) +{ + NAND_CTL_SETCLE(NAND_ADDR); + WRITE_NAND_COMMAND(command, NAND_ADDR); + NAND_CTL_CLRCLE(NAND_ADDR); + + if(command == NAND_CMD_RESET){ + unsigned char ret_val; + NanD_Command(NAND_CMD_STATUS); + do{ + ret_val = READ_NAND(NAND_ADDR);/* wait till ready */ + } while((ret_val & 0x40) != 0x40); + } + + NAND_WAIT_READY(); + return 0; +} + +/* NanD_Address: Set the current address for the flash chip */ +static int NanD_Address(int numbytes, unsigned long ofs) +{ + int i; + + NAND_CTL_SETALE(NAND_ADDR); + + if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) + WRITE_NAND_ADDRESS(ofs, NAND_ADDR); + + ofs = ofs >> 9; + + if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) + for (i = 0; i < 3; i++, ofs = ofs >> 8) + WRITE_NAND_ADDRESS(ofs, NAND_ADDR); + + NAND_CTL_CLRALE(NAND_ADDR); + + NAND_WAIT_READY(); + return 0; +} + +/* read chip mfr and id + * return 0 if they match board config + * return 1 if not + */ +int nand_chip() +{ + int mfr, id; + + NAND_ENABLE_CE(); + + if (NanD_Command(NAND_CMD_RESET)) { + printf("Err: RESET\n"); + NAND_DISABLE_CE(); + return 1; + } + + if (NanD_Command(NAND_CMD_READID)) { + printf("Err: READID\n"); + NAND_DISABLE_CE(); + return 1; + } + + NanD_Address(ADDR_COLUMN, 0); + + mfr = READ_NAND(NAND_ADDR); + id = READ_NAND(NAND_ADDR); + + NAND_DISABLE_CE(); + + return (mfr != K9K1216_MFR || id != K9K1216_ID); +} + +/* read a block data to buf + * return 1 if the block is bad or ECC error can't be corrected for any page + * return 0 on sucess + */ +int nand_read_block(unsigned char *buf, ulong block_addr) +{ + int i, offset = 0; + uchar oob_buf[16]; + + /* check bad block */ + /* 0th and 5th words need be 0xffff */ + if (nand_read_oob(oob_buf, block_addr) || +// oob_buf[0] != 0xff || oob_buf[1] != 0xff || +// oob_buf[10] != 0xff || oob_buf[11] != 0xff ){ + oob_buf[5] != 0xff){ + printf("Skipped bad block at 0x%x\n", block_addr); + return 1; /* skip bad block */ + } + + /* read the block page by page*/ + for (i=0; i<32; i++){ + if (nand_read_page(buf+offset, block_addr + offset)) + return 1; + offset += PAGE_SIZE; + } + + return 0; +} +static count = 0; +/* read a page with ECC */ +static int nand_read_page(u_char *buf, ulong page_addr) +{ + u_char ecc_code[6]; + u_char ecc_calc[3]; + u_char oob_buf[16]; + u_char *p; + u16 val; + int cntr; + + NAND_ENABLE_CE(); + NanD_Command(NAND_CMD_READ0); + NanD_Address(ADDR_COLUMN_PAGE, page_addr); + NAND_WAIT_READY(); + + delay(500); /* we go through NFC need a bigger delay. 200 is not enough */ + + p = buf; + for (cntr = 0; cntr < 256; cntr++){ + val = READ_NAND(NAND_ADDR); + *p++ = val & 0xff; + *p++ = val >> 8; + } + + p = oob_buf; + for (cntr = 0; cntr < 8; cntr++){ + val = READ_NAND(NAND_ADDR); + *p++ = val & 0xff; + *p++ = val >> 8; + } + count = 1; + NAND_DISABLE_CE(); /* set pin high */ + + /* Pick the ECC bytes out of the oob data */ + for (cntr = 0; cntr < 6; cntr++) + ecc_code[cntr] = oob_buf[ecc_pos[cntr]]; + + if ((oob_buf[eccvalid_pos] & 0x0f) != 0x0f) { + nand_calculate_ecc (buf, &ecc_calc[0]); + if (nand_correct_data (buf, &ecc_code[0], &ecc_calc[0]) == -1) { + printf ("ECC Failed, page 0x%08x\n", page_addr); + for (val=0; val <256; val++) + printf("%x ", buf[val]); + printf("\n"); + for (;;); + return 1; + } + } + + if ((oob_buf[eccvalid_pos] & 0xf0) != 0xf0) { + nand_calculate_ecc (buf + 256, &ecc_calc[0]); + if (nand_correct_data (buf + 256, &ecc_code[3], &ecc_calc[0]) == -1) { + printf ("ECC Failed, page 0x%08x\n", page_addr+0x100); + for (val=0; val <256; val++) + printf("%x ", buf[val+256]); + printf("\n"); + for (;;); + return 1; + } + } + + return 0; +} + +/* read from the 16 bytes of oob data that correspond to a 512 byte page. + */ +static int nand_read_oob(u_char *buf, ulong page_addr) +{ + u16 val; + int cntr; + + NAND_ENABLE_CE(); /* set pin low */ + NanD_Command(NAND_CMD_READOOB); + NanD_Address(ADDR_COLUMN_PAGE, page_addr); + NAND_WAIT_READY(); + +/* do { + *(volatile u32 *)(0x6800A07c) = NAND_CMD_STATUS; + val = *(volatile u32 *)(0x6800A084); + printf("val = %x\n", val); + } while ((val & 0x40) != 0x40); +*/ + /* the above code from OSTBoot doesn't work, we use delay */ + delay(500); /* we go through NFC need a bigger delay. 200 is not enough */ + + for (cntr = 0; cntr < 8; cntr++){ + val = READ_NAND(NAND_ADDR); + *buf++ = val & 0xff; + *buf++ = val >> 8; + } + + NAND_WAIT_READY(); + NAND_DISABLE_CE(); /* set pin high */ + + return 0; +} + +#endif diff --git a/drivers/ns16550.c b/drivers/ns16550.c new file mode 100644 index 0000000..b5a5c12 --- /dev/null +++ b/drivers/ns16550.c @@ -0,0 +1,69 @@ +/* + * This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * COM1 NS16550 support + * originally from linux source (arch/ppc/boot/ns16550.c) + * modified to use CFG_ISA_MEM and new defines + */ + +#include + +#ifdef CFG_PRINTF +#ifdef CFG_NS16550 + +#include + +#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ +#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */ +#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */ + +void NS16550_init (NS16550_t com_port, int baud_divisor) +{ + com_port->ier = 0x00; +#ifdef CONFIG_OMAP + com_port->mdr1 = 0x7; /* mode select reset TL16C750*/ +#endif + com_port->lcr = LCR_BKSE | LCRVAL; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCRVAL; + com_port->mcr = MCRVAL; + com_port->fcr = FCRVAL; +#if defined(CONFIG_OMAP) + com_port->mdr1 = 0; /* select uart mode */ +#endif +} + +void NS16550_reinit (NS16550_t com_port, int baud_divisor) +{ + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCRVAL; + com_port->mcr = MCRVAL; + com_port->fcr = FCRVAL; +} + +void NS16550_putc (NS16550_t com_port, char c) +{ + while ((com_port->lsr & LSR_THRE) == 0); + com_port->thr = c; +} + +char NS16550_getc (NS16550_t com_port) +{ + while ((com_port->lsr & LSR_DR) == 0); + return (com_port->rbr); +} + +int NS16550_tstc (NS16550_t com_port) +{ + return ((com_port->lsr & LSR_DR) != 0); +} + +#endif +#endif diff --git a/drivers/omap24xx_i2c.c b/drivers/omap24xx_i2c.c new file mode 100644 index 0000000..7782e9d --- /dev/null +++ b/drivers/omap24xx_i2c.c @@ -0,0 +1,354 @@ +/* + * Basic I2C functions + * + * Copyright (c) 2004 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Author: Jian Zhang jzhang@ti.com, Texas Instruments + * + * Copyright (c) 2003 Wolfgang Denk, wd@denx.de + * Rewritten to fit into the current U-Boot framework + * + * Adapted for OMAP2420 I2C, r-woodruff2@ti.com + * + */ + +#include + +#if defined(CONFIG_DRIVER_OMAP24XX_I2C) || defined(CONFIG_DRIVER_OMAP34XX_I2C) + +#include +#include + +#define inb(a) __raw_readb(a) +#define outb(a,v) __raw_writeb(a,v) +#define inw(a) __raw_readw(a) +#define outw(a,v) __raw_writew(a,v) + +static void wait_for_bb (void); +static u16 wait_for_pin (void); +static void flush_fifo(void); + +void i2c_init (int speed, int slaveadd) +{ + u16 scl; + + outw(0x2, I2C_SYSC); /* for ES2 after soft reset */ + udelay(1000); + outw(0x0, I2C_SYSC); /* will probably self clear but */ + + if (inw (I2C_CON) & I2C_CON_EN) { + outw (0, I2C_CON); + udelay (50000); + } + + /* 12Mhz I2C module clock */ + outw (0, I2C_PSC); + speed = speed/1000; /* 100 or 400 */ + scl = ((12000/(speed*2)) - 7); /* use 7 when PSC = 0 */ + outw (scl, I2C_SCLL); + outw (scl, I2C_SCLH); + /* own address */ + outw (slaveadd, I2C_OA); + outw (I2C_CON_EN, I2C_CON); + + /* have to enable intrrupts or OMAP i2c module doesn't work */ + outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | + I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + udelay (1000); + flush_fifo(); + outw (0xFFFF, I2C_STAT); + outw (0, I2C_CNT); +} + +static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) +{ + int i2c_error = 0; + u16 status; + + /* wait until bus not busy */ + wait_for_bb (); + + /* one byte only */ + outw (1, I2C_CNT); + /* set slave address */ + outw (devaddr, I2C_SA); + /* no stop bit needed here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + + status = wait_for_pin (); + + if (status & I2C_STAT_XRDY) { + /* Important: have to use byte access */ + *(volatile u8 *) (I2C_DATA) = regoffset; + udelay (20000); + if (inw (I2C_STAT) & I2C_STAT_NACK) { + i2c_error = 1; + } + } else { + i2c_error = 1; + } + + if (!i2c_error) { + /* free bus, otherwise we can't use a combined transction */ + outw (0, I2C_CON); + while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { + udelay (10000); + /* Have to clear pending interrupt to clear I2C_STAT */ + outw (0xFFFF, I2C_STAT); + } + + wait_for_bb (); + /* set slave address */ + outw (devaddr, I2C_SA); + /* read one byte from slave */ + outw (1, I2C_CNT); + /* need stop bit here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, + I2C_CON); + + status = wait_for_pin (); + if (status & I2C_STAT_RRDY) { +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + *value = inb(I2C_DATA); +#else + *value = inw(I2C_DATA); +#endif + udelay (20000); + } else { + i2c_error = 1; + } + + if (!i2c_error) { + outw (I2C_CON_EN, I2C_CON); + while (inw (I2C_STAT) + || (inw (I2C_CON) & I2C_CON_MST)) { + udelay (10000); + outw (0xFFFF, I2C_STAT); + } + } + } + flush_fifo(); + outw (0xFFFF, I2C_STAT); + outw (0, I2C_CNT); + return i2c_error; +} + +static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) +{ + int i2c_error = 0; + u16 status, stat; + + /* wait until bus not busy */ + wait_for_bb (); + + /* two bytes */ + outw (2, I2C_CNT); + /* set slave address */ + outw (devaddr, I2C_SA); + /* stop bit needed here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, I2C_CON); + + /* wait until state change */ + status = wait_for_pin (); + + if (status & I2C_STAT_XRDY) { +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + /* send out 1 byte */ + outb(regoffset, I2C_DATA); + outw(I2C_STAT_XRDY, I2C_STAT); + status = wait_for_pin(); + if ((status & I2C_STAT_XRDY)) { + /* send out next 1 byte */ + outb(value, I2C_DATA); + outw(I2C_STAT_XRDY, I2C_STAT); + } else { + i2c_error = 1; + } +#else + /* send out two bytes */ + outw ((value << 8) + regoffset, I2C_DATA); +#endif + + /* must have enough delay to allow BB bit to go low */ + udelay (50000); + if (inw (I2C_STAT) & I2C_STAT_NACK) { + i2c_error = 1; + } + } else { + i2c_error = 1; + } + + if (!i2c_error) { + int eout = 200; + + outw (I2C_CON_EN, I2C_CON); + while ((stat = inw (I2C_STAT)) || (inw (I2C_CON) & I2C_CON_MST)) { + udelay (1000); + /* have to read to clear intrrupt */ + outw (0xFFFF, I2C_STAT); + if(--eout == 0) /* better leave with error than hang */ + break; + } + } + flush_fifo(); + outw (0xFFFF, I2C_STAT); + outw (0, I2C_CNT); + return i2c_error; +} + +static void flush_fifo(void) +{ u16 stat; + + /* note: if you try and read data when its not there or ready + * you get a bus error + */ + while(1){ + stat = inw(I2C_STAT); + if(stat == I2C_STAT_RRDY){ +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + inb(I2C_DATA); +#else + inw(I2C_DATA); +#endif + outw(I2C_STAT_RRDY,I2C_STAT); + udelay(1000); + }else + break; + } +} + +int i2c_probe (uchar chip) +{ + int res = 1; /* default = fail */ + + if (chip == inw (I2C_OA)) { + return res; + } + + /* wait until bus not busy */ + wait_for_bb (); + + /* try to read one byte */ + outw (1, I2C_CNT); + /* set slave address */ + outw (chip, I2C_SA); + /* stop bit needed here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + /* enough delay for the NACK bit set */ + udelay (50000); + + if (!(inw (I2C_STAT) & I2C_STAT_NACK)) { + res = 0; /* success case */ + flush_fifo(); + outw(0xFFFF, I2C_STAT); + } else { + outw(0xFFFF, I2C_STAT); /* failue, clear sources*/ + outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ + udelay(20000); + wait_for_bb (); + } + flush_fifo(); + outw (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ + outw(0xFFFF, I2C_STAT); + return res; +} + +int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + int i; + + if (alen > 1) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > 256) { + printf ("I2C read: address out of range\n"); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_read_byte (chip, addr + i, &buffer[i])) { + printf ("I2C read: I/O error\n"); + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + return 1; + } + } + + return 0; +} + +int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + int i; + + if (alen > 1) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > 256) { + printf ("I2C read: address out of range\n"); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_write_byte (chip, addr + i, buffer[i])) { + printf ("I2C read: I/O error\n"); + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + return 1; + } + } + + return 0; +} + +static void wait_for_bb (void) +{ + int timeout = 10; + u16 stat; + + outw(0xFFFF, I2C_STAT); /* clear current interruts...*/ + while ((stat = inw (I2C_STAT) & I2C_STAT_BB) && timeout--) { + outw (stat, I2C_STAT); + udelay (50000); + } + + if (timeout <= 0) { + printf ("timed out in wait_for_bb: I2C_STAT=%x\n", + inw (I2C_STAT)); + } + outw(0xFFFF, I2C_STAT); /* clear delayed stuff*/ +} + +static u16 wait_for_pin (void) +{ + u16 status; + int timeout = 10; + + do { + udelay (1000); + status = inw (I2C_STAT); + } while ( !(status & + (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | + I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | + I2C_STAT_AL)) && timeout--); + + if (timeout <= 0) { + printf ("timed out in wait_for_pin: I2C_STAT=%x\n", + inw (I2C_STAT)); + outw(0xFFFF, I2C_STAT); +} + return status; +} + +#endif /* CONFIG_DRIVER_OMAP24XX_I2C */ diff --git a/drivers/onenand.c b/drivers/onenand.c new file mode 100644 index 0000000..9902a0d --- /dev/null +++ b/drivers/onenand.c @@ -0,0 +1,238 @@ +/* + * (C) Copyright 2005 Samsung Electronis + * Kyungmin Park + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include + +#include "onenand_regs.h" + +#define onenand_readw(a) (*(volatile unsigned short *)(a)) +#define onenand_writew(v, a) ((*(volatile unsigned short *)(a)) = (u16) (v)) + +#define SAMSUNG_MFR_ID 0xEC +#define KFM1G16Q2A_DEV_ID 0x30 +#define KFN2G16Q2A_DEV_ID 0x40 + + +#define THIS_ONENAND(a) (ONENAND_ADDR + (a)) + +#define READ_INTERRUPT() \ + onenand_readw(THIS_ONENAND(ONENAND_REG_INTERRUPT)) + +#define READ_CTRL_STATUS() \ + onenand_readw(THIS_ONENAND(ONENAND_REG_CTRL_STATUS)) + +#define READ_ECC_STATUS() \ + onenand_readw(THIS_ONENAND(ONENAND_REG_ECC_STATUS)) + +#define SET_EMIFS_CS_CONFIG(v) \ + (*(volatile unsigned long *)(OMAP_EMIFS_CS_CONFIG) = (v)) + +#define onenand_block_address(block) (block) +#define onenand_sector_address(page) (page << 2) +#define onenand_buffer_address() ((1 << 3) << 8) +#define onenand_bufferram_address(block) (0) + +#if defined(CFG_SYNC_BURST_READ) && defined(CONFIG_OMAP1610) +static inline void set_sync_burst_read(void) +{ + unsigned int value; + value = 0 + | (0x1 << 15) /* Read Mode: Synchronous */ + | (0x4 << 12) /* Burst Read Latency: 4 cycles */ + | (0x4 << 9) /* Burst Length: 8 word */ + | (0x1 << 7) /* RDY signal plarity */ + | (0x1 << 6) /* INT signal plarity */ + | (0x1 << 5) /* I/O buffer enable */ + ; + onenand_writew(value, THIS_ONENAND(ONENAND_REG_SYS_CFG1)); + + value = 0 + | (4 << 16) /* Synchronous Burst Read */ + | (1 << 12) /* PGWST/WELEN */ + | (1 << 8) /* WRWST */ + | (4 << 4) /* RDWST */ + | (1 << 0) /* FCLKDIV => 48MHz */ + ; + SET_EMIFS_CS_CONFIG(value); +} + +static inline void set_async_read(void) +{ + unsigned int value; + value = 0 + | (0x0 << 15) /* Read Mode: Asynchronous */ + | (0x4 << 12) /* Burst Read Latency: 4 cycles */ + | (0x0 << 9) /* Burst Length: continuous */ + | (0x1 << 7) /* RDY signal plarity */ + | (0x1 << 6) /* INT signal plarity */ + | (0x0 << 5) /* I/O buffer disable */ + ; + onenand_writew(value, THIS_ONENAND(ONENAND_REG_SYS_CFG1)); + + value = 0 + | (0 << 16) /* Asynchronous Read */ + | (1 << 12) /* PGWST/WELEN */ + | (1 << 8) /* WRWST */ + | (3 << 4) /* RDWST */ + | (1 << 0) /* FCLKDIV => 48MHz */ + ; + SET_EMIFS_CS_CONFIG(value); +} +#else +#define set_sync_burst_read(...) do { } while (0) +#define set_async_read(...) do { } while (0) +#endif + +int +onenand_chip() +{ + unsigned short mf_id, dev_id; + mf_id = (*(volatile unsigned short *)(THIS_ONENAND(ONENAND_REG_MANUFACTURER_ID))); + dev_id = (*(volatile unsigned short *)(THIS_ONENAND(ONENAND_REG_DEVICE_ID))); + + if(mf_id == SAMSUNG_MFR_ID) { + if (dev_id == KFM1G16Q2A_DEV_ID) { + printf("Detected Samsung MuxOneNAND1G Flash \r\n"); + return 0; + } else if (dev_id == KFN2G16Q2A_DEV_ID) { + printf("Detected Samsung MuxOneNAND2G Flash \r\n"); + return 0; + } else { + printf(" ONENAND Flash unsupported\r\n"); + return 1; + } + } else { + printf("ONENAND Flash Unsupported\r\n"); + return 1; + } +} + +/* read a page with ECC */ +static inline int onenand_read_page(ulong block, ulong page, u_char *buf) +{ + unsigned long *base; + +#ifndef __HAVE_ARCH_MEMCPY32 + unsigned int offset, value; + unsigned long *p; + unsigned int ctrl, ecc; + unsigned short bbmarker; +#endif + + onenand_writew(onenand_block_address(block), + THIS_ONENAND(ONENAND_REG_START_ADDRESS1)); + + onenand_writew(onenand_sector_address(page), + THIS_ONENAND(ONENAND_REG_START_ADDRESS8)); + + onenand_writew(onenand_buffer_address(), + THIS_ONENAND(ONENAND_REG_START_BUFFER)); + + onenand_writew(onenand_bufferram_address(block), + THIS_ONENAND(ONENAND_REG_START_ADDRESS2)); + + onenand_writew(ONENAND_INT_CLEAR, THIS_ONENAND(ONENAND_REG_INTERRUPT)); + + onenand_writew(ONENAND_CMD_READ, THIS_ONENAND(ONENAND_REG_COMMAND)); + +#ifndef __HAVE_ARCH_MEMCPY32 + p = (unsigned long *) buf; +#endif + base = (unsigned long *) (ONENAND_ADDR + ONENAND_DATARAM); + + while (!(READ_INTERRUPT() & ONENAND_INT_MASTER)) + continue; + + ctrl = READ_CTRL_STATUS(); + + if (ctrl & ONENAND_CTRL_ERROR) { + hang(); + } + + if (READ_INTERRUPT() & ONENAND_INT_READ) { + + ecc = READ_ECC_STATUS(); + if (ecc & ONENAND_ECC_2BIT_ALL) { + hang(); + } + + /* Check if the block is bad. Bad block markers */ + /* are stored in spare area of 1st or 2nd page */ + if ((page == 0) || (page == 1)) + { + unsigned long *spareArea = (unsigned long *) (ONENAND_ADDR + ONENAND_SPARERAM); + bbmarker = *spareArea; + /* for bad block markers */ + if (bbmarker != 0xFFFF){ + return 1; + } + } + } + +#ifdef __HAVE_ARCH_MEMCPY32 + /* 32 bytes boundary memory copy */ + memcpy32(buf, base, ONENAND_PAGE_SIZE); +#else + for (offset = 0; offset < (ONENAND_PAGE_SIZE >> 2); offset++) { + value = *(base + offset); + *p++ = value; + } +#endif + + return 0; +} + +#define ONENAND_START_PAGE 0 +#define ONENAND_PAGES_PER_BLOCK 64 + +/** + * onenand_read_block - Read a block data to buf + * @return 0 on sucess + */ + +int onenand_read_block(unsigned char *buf, ulong block) +{ + int page, offset = 0; + + set_sync_burst_read(); + + /* NOTE: you must read page from page 1 of block 0 */ + /* read the block page by page*/ + for (page = ONENAND_START_PAGE; + page < ONENAND_PAGES_PER_BLOCK; page++) { + + if (onenand_read_page(block, page, buf + offset)){ + set_async_read(); + return 1; + } + + offset += ONENAND_PAGE_SIZE; + } + + set_async_read(); + + return 0; +} + diff --git a/drivers/onenand_regs.h b/drivers/onenand_regs.h new file mode 100644 index 0000000..d8acc8c --- /dev/null +++ b/drivers/onenand_regs.h @@ -0,0 +1,167 @@ +/* + * linux/include/linux/mtd/onenand_regs.h + * + * OneNAND Register header file + * + * Copyright (C) 2005 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ONENAND_REG_H +#define __ONENAND_REG_H + +/* Memory Address Map Translation (Word order) */ +#define ONENAND_MEMORY_MAP(x) ((x) << 1) + +/* + * External BufferRAM area + */ +#define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000) +#define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200) +#define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010) + +/* + * OneNAND Registers + */ +#define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000) +#define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001) +#define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002) +#define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003) +#define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004) +#define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005) +#define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006) + +#define ONENAND_REG_START_ADDRESS1 ONENAND_MEMORY_MAP(0xF100) +#define ONENAND_REG_START_ADDRESS2 ONENAND_MEMORY_MAP(0xF101) +#define ONENAND_REG_START_ADDRESS3 ONENAND_MEMORY_MAP(0xF102) +#define ONENAND_REG_START_ADDRESS4 ONENAND_MEMORY_MAP(0xF103) +#define ONENAND_REG_START_ADDRESS5 ONENAND_MEMORY_MAP(0xF104) +#define ONENAND_REG_START_ADDRESS6 ONENAND_MEMORY_MAP(0xF105) +#define ONENAND_REG_START_ADDRESS7 ONENAND_MEMORY_MAP(0xF106) +#define ONENAND_REG_START_ADDRESS8 ONENAND_MEMORY_MAP(0xF107) + +#define ONENAND_REG_START_BUFFER ONENAND_MEMORY_MAP(0xF200) +#define ONENAND_REG_COMMAND ONENAND_MEMORY_MAP(0xF220) +#define ONENAND_REG_SYS_CFG1 ONENAND_MEMORY_MAP(0xF221) +#define ONENAND_REG_SYS_CFG2 ONENAND_MEMORY_MAP(0xF222) +#define ONENAND_REG_CTRL_STATUS ONENAND_MEMORY_MAP(0xF240) +#define ONENAND_REG_INTERRUPT ONENAND_MEMORY_MAP(0xF241) +#define ONENAND_REG_START_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24C) +#define ONENAND_REG_END_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24D) +#define ONENAND_REG_WP_STATUS ONENAND_MEMORY_MAP(0xF24E) + +#define ONENAND_REG_ECC_STATUS ONENAND_MEMORY_MAP(0xFF00) +#define ONENAND_REG_ECC_M0 ONENAND_MEMORY_MAP(0xFF01) +#define ONENAND_REG_ECC_S0 ONENAND_MEMORY_MAP(0xFF02) +#define ONENAND_REG_ECC_M1 ONENAND_MEMORY_MAP(0xFF03) +#define ONENAND_REG_ECC_S1 ONENAND_MEMORY_MAP(0xFF04) +#define ONENAND_REG_ECC_M2 ONENAND_MEMORY_MAP(0xFF05) +#define ONENAND_REG_ECC_S2 ONENAND_MEMORY_MAP(0xFF06) +#define ONENAND_REG_ECC_M3 ONENAND_MEMORY_MAP(0xFF07) +#define ONENAND_REG_ECC_S3 ONENAND_MEMORY_MAP(0xFF08) + +/* + * Device ID Register F001h (R) + */ +#define ONENAND_DEVICE_DENSITY_SHIFT (4) +#define ONENAND_DEVICE_IS_DDP (1 << 3) +#define ONENAND_DEVICE_IS_DEMUX (1 << 2) +#define ONENAND_DEVICE_VCC_MASK (0x3) + +#define ONENAND_DEVICE_DENSITY_512Mb (0x002) + +/* + * Version ID Register F002h (R) + */ +#define ONENAND_VERSION_PROCESS_SHIFT (8) + +/* + * Start Address 1 F100h (R/W) + */ +#define ONENAND_DDP_SHIFT (15) + +/* + * Start Address 8 F107h (R/W) + */ +#define ONENAND_FPA_MASK (0x3f) +#define ONENAND_FPA_SHIFT (2) +#define ONENAND_FSA_MASK (0x03) + +/* + * Start Buffer Register F200h (R/W) + */ +#define ONENAND_BSA_MASK (0x03) +#define ONENAND_BSA_SHIFT (8) +#define ONENAND_BSA_BOOTRAM (0 << 2) +#define ONENAND_BSA_DATARAM0 (2 << 2) +#define ONENAND_BSA_DATARAM1 (3 << 2) +#define ONENAND_BSC_MASK (0x03) + +/* + * Command Register F220h (R/W) + */ +#define ONENAND_CMD_READ (0x00) +#define ONENAND_CMD_READOOB (0x13) +#define ONENAND_CMD_PROG (0x80) +#define ONENAND_CMD_PROGOOB (0x1A) +#define ONENAND_CMD_UNLOCK (0x23) +#define ONENAND_CMD_LOCK (0x2A) +#define ONENAND_CMD_LOCK_TIGHT (0x2C) +#define ONENAND_CMD_ERASE (0x94) +#define ONENAND_CMD_RESET (0xF0) +#define ONENAND_CMD_READID (0x90) + +/* NOTE: Those are not *REAL* commands */ +#define ONENAND_CMD_BUFFERRAM (0x1978) + +/* + * System Configuration 1 Register F221h (R, R/W) + */ +#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15) +#define ONENAND_SYS_CFG1_BRL (12) +#define ONENAND_SYS_CFG1_BL (9) +#define ONENAND_SYS_CFG1_NO_ECC (1 << 8) +#define ONENAND_SYS_CFG1_RDY (1 << 7) +#define ONENAND_SYS_CFG1_INT (1 << 6) +#define ONENAND_SYS_CFG1_IOBE (1 << 5) +#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4) + +/* + * Controller Status Register F240h (R) + */ +#define ONENAND_CTRL_ONGO (1 << 15) +#define ONENAND_CTRL_LOCK (1 << 14) +#define ONENAND_CTRL_LOAD (1 << 13) +#define ONENAND_CTRL_PROGRAM (1 << 12) +#define ONENAND_CTRL_ERASE (1 << 11) +#define ONENAND_CTRL_ERROR (1 << 10) +#define ONENAND_CTRL_RSTB (1 << 7) + +/* + * Interrupt Status Register F241h (R) + */ +#define ONENAND_INT_MASTER (1 << 15) +#define ONENAND_INT_READ (1 << 7) +#define ONENAND_INT_WRITE (1 << 6) +#define ONENAND_INT_ERASE (1 << 5) +#define ONENAND_INT_RESET (1 << 4) +#define ONENAND_INT_CLEAR (0 << 0) + +/* + * NAND Flash Write Protection Status Register F24Eh (R) + */ +#define ONENAND_WP_US (1 << 2) +#define ONENAND_WP_LS (1 << 1) +#define ONENAND_WP_LTS (1 << 0) + +/* + * ECC Status Reigser FF00h (R) + */ +#define ONENAND_ECC_1BIT (1 << 0) +#define ONENAND_ECC_2BIT (1 << 1) +#define ONENAND_ECC_2BIT_ALL (0xAAAA) + +#endif /* __ONENAND_REG_H */ diff --git a/drivers/serial.c b/drivers/serial.c new file mode 100644 index 0000000..026acf9 --- /dev/null +++ b/drivers/serial.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CFG_PRINTF +#ifdef CFG_NS16550_SERIAL + +#include +#ifdef CFG_NS87308 +#include +#endif + +#if CONFIG_CONS_INDEX == 1 +static NS16550_t console = (NS16550_t) CFG_NS16550_COM1; +#elif CONFIG_CONS_INDEX == 2 +static NS16550_t console = (NS16550_t) CFG_NS16550_COM2; +#elif CONFIG_CONS_INDEX == 3 +static NS16550_t console = (NS16550_t) CFG_NS16550_COM3; +#elif CONFIG_CONS_INDEX == 4 +static NS16550_t console = (NS16550_t) CFG_NS16550_COM4; +#else +#error no valid console defined +#endif + +static int calc_divisor (void) +{ + return (CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE); +} + +int serial_init (void) +{ + int clock_divisor = calc_divisor(); + +#ifdef CFG_NS87308 + initialise_ns87308(); +#endif + + NS16550_init(console, clock_divisor); + + return (0); +} + +void +serial_putc(const char c) +{ + if (c == '\n') + NS16550_putc(console, '\r'); + + NS16550_putc(console, c); +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + + +int +serial_getc(void) +{ + return NS16550_getc(console); +} + +int +serial_tstc(void) +{ + return NS16550_tstc(console); +} + +void +serial_setbrg (void) +{ + int clock_divisor; + + clock_divisor = calc_divisor(); + NS16550_reinit(console, clock_divisor); +} + +#endif +#endif diff --git a/fs/Makefile b/fs/Makefile new file mode 100644 index 0000000..a2f61e7 --- /dev/null +++ b/fs/Makefile @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# + +SUBDIRS := fat + +$(obj).depend all: + @for dir in $(SUBDIRS) ; do \ + $(MAKE) -C $$dir $@ ; done diff --git a/fs/fat/Makefile b/fs/fat/Makefile new file mode 100644 index 0000000..2fa428c --- /dev/null +++ b/fs/fat/Makefile @@ -0,0 +1,45 @@ +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)libfat.a + +AOBJS = +COBJS = fat.o file.o + +SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) + +all: $(LIB) $(AOBJS) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/fs/fat/fat.c b/fs/fat/fat.c new file mode 100644 index 0000000..e32cb62 --- /dev/null +++ b/fs/fat/fat.c @@ -0,0 +1,960 @@ +/* + * fat.c + * + * R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg + * + * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6 + * 2003-03-10 - kharris@nexus-tech.net - ported to uboot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#ifdef CFG_CMD_FAT + +/* + * Convert a string to lowercase. + */ +static void +downcase(char *str) +{ + while (*str != '\0') { + TOLOWER(*str); + str++; + } +} + +static block_dev_desc_t *cur_dev = NULL; +static unsigned long part_offset = 0; +static int cur_part = 1; + +#define DOS_PART_TBL_OFFSET 0x1be +#define DOS_PART_MAGIC_OFFSET 0x1fe +#define DOS_FS_TYPE_OFFSET 0x52 + +int strncmp(const char * cs,const char * ct,size_t count) +{ + register signed char __res = 0; + + while (count) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + count--; + } + + return __res; +} + +char * strcpy(char * dest,const char *src) +{ + char *tmp = dest; + + while ((*dest++ = *src++) != '\0') + /* nothing */; + return tmp; +} + +int strcmp(const char * cs,const char * ct) +{ + register signed char __res; + + while (1) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + } + + return __res; +} +void * memcpy(void * dest,const void *src,size_t count) +{ + char *tmp = (char *) dest, *s = (char *) src; + + while (count--) + *tmp++ = *s++; + + return dest; +} + + +int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr) +{ + startblock += part_offset; + if (cur_dev == NULL) + return -1; + if (cur_dev->block_read) { + return cur_dev->block_read (cur_dev->dev, startblock, getsize, (unsigned long *)bufptr); + } + return -1; +} + + +int +fat_register_device(block_dev_desc_t *dev_desc, int part_no) +{ + unsigned char buffer[SECTOR_SIZE]; + + if (!dev_desc->block_read) + return -1; + cur_dev=dev_desc; + /* check if we have a MBR (on floppies we have only a PBR) */ + if (dev_desc->block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) { + printf ("** Can't read from device %d **\n", dev_desc->dev); + return -1; + } + if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || + buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) { + /* no signature found */ + return -1; + } + if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { + /* ok, we assume we are on a PBR only */ + cur_part = 1; + part_offset=0; + } + else { +#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || (CONFIG_COMMANDS & CFG_CMD_MMC) || defined(CONFIG_SYSTEMACE) + disk_partition_t info; + if(!get_partition_info(dev_desc, part_no, &info)) { + part_offset = info.start; + cur_part = part_no; + } + else { + printf ("** Partition %d not valid on device %d **\n",part_no,dev_desc->dev); + return -1; + } +#else + part_offset = buffer[DOS_PART_TBL_OFFSET+8] | + buffer[DOS_PART_TBL_OFFSET+9] <<8 | + buffer[DOS_PART_TBL_OFFSET+10]<<16 | + buffer[DOS_PART_TBL_OFFSET+11]<<24; + + cur_part = 1; +#endif + } + return 0; +} + + +/* + * Get the first occurence of a directory delimiter ('/' or '\') in a string. + * Return index into string if found, -1 otherwise. + */ +static int +dirdelim(char *str) +{ + char *start = str; + + while (*str != '\0') { + if (ISDIRDELIM(*str)) return str - start; + str++; + } + return -1; +} + + +/* + * Match volume_info fs_type strings. + * Return 0 on match, -1 otherwise. + */ +static int +compare_sign(char *str1, char *str2) +{ + char *end = str1+SIGNLEN; + + while (str1 != end) { + if (*str1 != *str2) { + return -1; + } + str1++; + str2++; + } + + return 0; +} + + +/* + * Extract zero terminated short name from a directory entry. + */ +static void get_name (dir_entry *dirent, char *s_name) +{ + char *ptr; + + memcpy (s_name, dirent->name, 8); + s_name[8] = '\0'; + ptr = s_name; + while (*ptr && *ptr != ' ') + ptr++; + if (dirent->ext[0] && dirent->ext[0] != ' ') { + *ptr = '.'; + ptr++; + memcpy (ptr, dirent->ext, 3); + ptr[3] = '\0'; + while (*ptr && *ptr != ' ') + ptr++; + } + *ptr = '\0'; + if (*s_name == DELETED_FLAG) + *s_name = '\0'; + else if (*s_name == aRING) + *s_name = 'å'; + downcase (s_name); +} + +/* + * Get the entry at index 'entry' in a FAT (12/16/32) table. + * On failure 0x00 is returned. + */ +static __u32 +get_fatent(fsdata *mydata, __u32 entry) +{ + __u32 bufnum; + __u32 offset; + __u32 ret = 0x00; + + switch (mydata->fatsize) { + case 32: + bufnum = entry / FAT32BUFSIZE; + offset = entry - bufnum * FAT32BUFSIZE; + break; + case 16: + bufnum = entry / FAT16BUFSIZE; + offset = entry - bufnum * FAT16BUFSIZE; + break; + case 12: + bufnum = entry / FAT12BUFSIZE; + offset = entry - bufnum * FAT12BUFSIZE; + break; + + default: + /* Unsupported FAT size */ + return ret; + } + /* Read a new block of FAT entries into the cache. */ + if (bufnum != mydata->fatbufnum) { + int getsize = FATBUFSIZE/FS_BLOCK_SIZE; + __u8 *bufptr = mydata->fatbuf; + __u32 fatlength = mydata->fatlength; + __u32 startblock = bufnum * FATBUFBLOCKS; + unsigned long i; + + fatlength *= SECTOR_SIZE; /* We want it in bytes now */ + startblock += mydata->fat_sect; /* Offset from start of disk */ + + if (getsize > fatlength) getsize = fatlength; + if (disk_read(startblock, getsize, bufptr) < 0) { + FAT_DPRINT("Error reading FAT blocks\n"); + return ret; + } + mydata->fatbufnum = bufnum; + } + + /* Get the actual entry from the table */ + switch (mydata->fatsize) { + case 32: + ret = FAT2CPU32(((__u32*)mydata->fatbuf)[offset]); + break; + case 16: + ret = FAT2CPU16(((__u16*)mydata->fatbuf)[offset]); + break; + case 12: { + __u32 off16 = (offset*3)/4; + __u16 val1, val2; + + switch (offset & 0x3) { + case 0: + ret = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); + ret &= 0xfff; + break; + case 1: + val1 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); + val1 &= 0xf000; + val2 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16+1]); + val2 &= 0x00ff; + ret = (val2 << 4) | (val1 >> 12); + break; + case 2: + val1 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); + val1 &= 0xff00; + val2 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16+1]); + val2 &= 0x000f; + ret = (val2 << 8) | (val1 >> 8); + break; + case 3: + ret = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]);; + ret = (ret & 0xfff0) >> 4; + break; + default: + break; + } + } + break; + } + FAT_DPRINT("ret: %d, offset: %d\n", ret, offset); + + return ret; +} + +static int memcmp(__u8 *p1, __u8 *p2, unsigned long len) +{ + while(len-- > 0) { + __u8 diff=(*p1++ - *p2++); + if(diff) + return diff; + } + return 0; // equal +} + +/* + * Read at most 'size' bytes from the specified cluster into 'buffer'. + * Return 0 on success, -1 otherwise. + */ +static int +get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) +{ + int idx = 0; + __u32 startsect; + __u8 tmpbuf[FS_BLOCK_SIZE]; + + if (clustnum > 0) { + startsect = mydata->data_begin + clustnum*mydata->clust_size; + } else { + startsect = mydata->rootdir_sect; + } + + // sacrifice speed for reliability (RAM-Test) + + idx = size/FS_BLOCK_SIZE; + while(idx-- > 0) { // read full blocks + if (disk_read(startsect, 1 , tmpbuf) < 0) { + FAT_DPRINT("Error reading data\n"); + return -1; + } + memcpy(buffer, tmpbuf, FS_BLOCK_SIZE); + if(memcmp(buffer, tmpbuf, FS_BLOCK_SIZE) != 0) { + FAT_ERROR("Memory error at 0x%8x\n", buffer); + return -1; + } + startsect++; + buffer += FS_BLOCK_SIZE; + } + + if(size % FS_BLOCK_SIZE) { // read last fragment + idx= size/FS_BLOCK_SIZE; + if (disk_read(startsect, 1, tmpbuf) < 0) { + FAT_DPRINT("Error reading data\n"); + return -1; + } + + memcpy(buffer, tmpbuf, size % FS_BLOCK_SIZE); + if(memcmp(buffer, tmpbuf, size % FS_BLOCK_SIZE) != 0) { + FAT_ERROR("Memory error at 0x%8x\n", buffer); + return -1; + } + return 0; + } + + return 0; +} + + +/* + * Read at most 'maxsize' bytes from the file associated with 'dentptr' + * into 'buffer'. + * Return the number of bytes read or -1 on fatal errors. + */ +static long +get_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, + unsigned long maxsize) +{ + unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0; + unsigned int bytesperclust = mydata->clust_size * SECTOR_SIZE; + __u32 curclust = START(dentptr); + __u32 endclust, newclust; + unsigned long actsize; + + FAT_DPRINT("Filesize: %ld bytes\n", filesize); + + if (maxsize > 0 && filesize > maxsize) filesize = maxsize; + + FAT_DPRINT("Reading: %ld bytes\n", filesize); + + actsize=bytesperclust; + endclust=curclust; + do { + /* search for consecutive clusters */ + while(actsize < filesize) { + newclust = get_fatent(mydata, endclust); + if((newclust -1)!=endclust) + goto getit; + if (newclust <= 0x0001 || newclust >= 0xfffff0) { + FAT_DPRINT("curclust: 0x%x\n", newclust); + FAT_DPRINT("Invalid FAT entry\n"); + return gotsize; + } + endclust=newclust; + actsize+= bytesperclust; + } + /* actsize >= file size */ + actsize -= bytesperclust; + /* get remaining clusters */ + if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) { + FAT_ERROR("Error reading cluster\n"); + return -1; + } + /* get remaining bytes */ + gotsize += (int)actsize; + filesize -= actsize; + buffer += actsize; + actsize= filesize; + if (get_cluster(mydata, endclust, buffer, (int)actsize) != 0) { + FAT_ERROR("Error reading cluster\n"); + return -1; + } + gotsize+=actsize; + return gotsize; +getit: + if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) { + FAT_ERROR("Error reading cluster\n"); + return -1; + } + gotsize += (int)actsize; + filesize -= actsize; + buffer += actsize; + curclust = get_fatent(mydata, endclust); + if (curclust <= 0x0001 || curclust >= 0xfffff0) { + FAT_DPRINT("curclust: 0x%x\n", curclust); + FAT_ERROR("Invalid FAT entry\n"); + return gotsize; + } + actsize=bytesperclust; + endclust=curclust; + } while (1); +} + + +#ifdef CONFIG_SUPPORT_VFAT +/* + * Extract the file name information from 'slotptr' into 'l_name', + * starting at l_name[*idx]. + * Return 1 if terminator (zero byte) is found, 0 otherwise. + */ +static int +slot2str(dir_slot *slotptr, char *l_name, int *idx) +{ + int j; + + for (j = 0; j <= 8; j += 2) { + l_name[*idx] = slotptr->name0_4[j]; + if (l_name[*idx] == 0x00) return 1; + (*idx)++; + } + for (j = 0; j <= 10; j += 2) { + l_name[*idx] = slotptr->name5_10[j]; + if (l_name[*idx] == 0x00) return 1; + (*idx)++; + } + for (j = 0; j <= 2; j += 2) { + l_name[*idx] = slotptr->name11_12[j]; + if (l_name[*idx] == 0x00) return 1; + (*idx)++; + } + + return 0; +} + +/* Calculate short name checksum */ +static __u8 +mkcksum(const char *str) +{ + int i; + __u8 ret = 0; + + for (i = 0; i < 11; i++) { + ret = (((ret&1)<<7)|((ret&0xfe)>>1)) + str[i]; + } + + return ret; +} +#endif + + +/* + * Get the directory entry associated with 'filename' from the directory + * starting at 'startsect' + */ + + +static dir_entry *get_dentfromdir (fsdata * mydata, int startsect, + char *filename, dir_entry * retdent, + int dols) +{ + +} + +#if 0 +__u8 get_dentfromdir_block[MAX_CLUSTSIZE]; +static dir_entry *get_dentfromdir (fsdata * mydata, int startsect, + char *filename, dir_entry * retdent, + int dols) +{ + __u16 prevcksum = 0xffff; + __u32 curclust = START (retdent); + int files = 0, dirs = 0; + + while (1) { + dir_entry *dentptr; + int i; + + if (get_cluster (mydata, curclust, get_dentfromdir_block, + mydata->clust_size * SECTOR_SIZE) != 0) { + FAT_DPRINT ("Error: reading directory block\n"); + return NULL; + } + dentptr = (dir_entry *) get_dentfromdir_block; + for (i = 0; i < DIRENTSPERCLUST; i++) { + char s_name[14], l_name[256]; + + l_name[0] = '\0'; + if (dentptr->name[0] == DELETED_FLAG) { + dentptr++; + continue; + } + if ((dentptr->attr & ATTR_VOLUME)) { + /* Volume label or VFAT entry */ + dentptr++; + continue; + } + if (dentptr->name[0] == 0) { + if (dols) { + printf ("\n%d file(s), %d dir(s)\n\n", files, dirs); + } + FAT_DPRINT ("Dentname == NULL - %d\n", i); + return NULL; + } +#ifdef CONFIG_SUPPORT_VFAT + if (dols && mkcksum (dentptr->name) == prevcksum) { + dentptr++; + continue; + } +#endif + get_name (dentptr, s_name); + if (dols) { + int isdir = (dentptr->attr & ATTR_DIR); + char dirc; + int doit = 0; + + if (isdir) { + dirs++; + dirc = '/'; + doit = 1; + } else { + dirc = ' '; + if (s_name[0] != 0) { + files++; + doit = 1; + } + } + if (doit) { + if (dirc == ' ') { + printf (" %8ld %s%c\n", + (long) FAT2CPU32 (dentptr->size), s_name, + dirc); + } else { + printf (" %s%c\n", s_name, dirc); + } + } + dentptr++; + continue; + } + if (strcmp (filename, s_name) && strcmp (filename, l_name)) { + FAT_DPRINT ("Mismatch: |%s|%s|\n", s_name, l_name); + dentptr++; + continue; + } + memcpy (retdent, dentptr, sizeof (dir_entry)); + + FAT_DPRINT ("DentName: %s", s_name); + FAT_DPRINT (", start: 0x%x", START (dentptr)); + FAT_DPRINT (", size: 0x%x %s\n", + FAT2CPU32 (dentptr->size), + (dentptr->attr & ATTR_DIR) ? "(DIR)" : ""); + + return retdent; + } + curclust = get_fatent (mydata, curclust); + if (curclust <= 0x0001 || curclust >= 0xfffff0) { + FAT_DPRINT ("curclust: 0x%x\n", curclust); + FAT_ERROR ("Invalid FAT entry\n"); + return NULL; + } + } + + return NULL; +} +#endif + + +/* + * Read boot sector and volume info from a FAT filesystem + */ +static int +read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) +{ + __u8 block[FS_BLOCK_SIZE]; + volume_info *vistart; + + printf("Reading boot sector\n"); + + if (disk_read(0, 1, block) < 0) { + FAT_DPRINT("Error: reading block\n"); + return -1; + } + + memcpy(bs, block, sizeof(boot_sector)); + bs->reserved = FAT2CPU16(bs->reserved); + bs->fat_length = FAT2CPU16(bs->fat_length); + bs->secs_track = FAT2CPU16(bs->secs_track); + bs->heads = FAT2CPU16(bs->heads); +#if 0 /* UNUSED */ + bs->hidden = FAT2CPU32(bs->hidden); +#endif + bs->total_sect = FAT2CPU32(bs->total_sect); + + /* FAT32 entries */ + if (bs->fat_length == 0) { + /* Assume FAT32 */ + bs->fat32_length = FAT2CPU32(bs->fat32_length); + bs->flags = FAT2CPU16(bs->flags); + bs->root_cluster = FAT2CPU32(bs->root_cluster); + bs->info_sector = FAT2CPU16(bs->info_sector); + bs->backup_boot = FAT2CPU16(bs->backup_boot); + vistart = (volume_info*) (block + sizeof(boot_sector)); + *fatsize = 32; + } else { + vistart = (volume_info*) &(bs->fat32_length); + *fatsize = 0; + } + memcpy(volinfo, vistart, sizeof(volume_info)); + + /* Terminate fs_type string. Writing past the end of vistart + is ok - it's just the buffer. */ + vistart->fs_type[8] = '\0'; + + if (*fatsize == 32) { + if (compare_sign(FAT32_SIGN, vistart->fs_type) == 0) { + return 0; + } + } else { + if (compare_sign(FAT12_SIGN, vistart->fs_type) == 0) { + *fatsize = 12; + return 0; + } + if (compare_sign(FAT16_SIGN, vistart->fs_type) == 0) { + *fatsize = 16; + return 0; + } + } + + FAT_DPRINT("Error: broken fs_type sign\n"); + return -1; +} + +#if 0 +__u8 do_fat_read_block[MAX_CLUSTSIZE]; /* Block buffer */ +#endif + +__u8 *fnamecopy = 0x80500000; +__u8 *do_fat_read_block = 0x80500880; + +boot_sector bs; +volume_info volinfo; +fsdata datablock; + +long +do_fat_read(const char *filename, void *buffer, unsigned long maxsize, + int dols) +{ +#if CONFIG_NIOS /* NIOS CPU cannot access big automatic arrays */ + static +#endif + fsdata *mydata = &datablock; + dir_entry *dentptr; + __u16 prevcksum = 0xffff; + char *subname = ""; + int rootdir_size, cursect, curclus; + int idx, isdir = 0; + int files = 0, dirs = 0; + long ret = 0; + int firsttime; + + if (read_bootsectandvi (&bs, &volinfo, &mydata->fatsize)) { + printf ("Error: reading boot sector\n"); + return -1; + } + if (mydata->fatsize == 32) { + mydata->fatlength = bs.fat32_length; + } else { + mydata->fatlength = bs.fat_length; + } + mydata->fat_sect = bs.reserved; + cursect = mydata->rootdir_sect + = mydata->fat_sect + mydata->fatlength * bs.fats; + curclus = bs.root_cluster; // For FAT32 only + mydata->clust_size = bs.cluster_size; + if (mydata->fatsize == 32) { + rootdir_size = mydata->clust_size; + mydata->data_begin = mydata->rootdir_sect /* + rootdir_size */ + - (mydata->clust_size * 2); + } else { + rootdir_size = ((bs.dir_entries[1] * (int) 256 + bs.dir_entries[0]) + * sizeof (dir_entry)) / SECTOR_SIZE; + mydata->data_begin = mydata->rootdir_sect + rootdir_size + - (mydata->clust_size * 2); + } + mydata->fatbufnum = -1; + + FAT_DPRINT ("FAT%d, fatlength: %d\n", mydata->fatsize, + mydata->fatlength); + FAT_DPRINT ("Rootdir begins at sector: %d, offset: %x, size: %d\n" + "Data begins at: %d\n", + mydata->rootdir_sect, mydata->rootdir_sect * SECTOR_SIZE, + rootdir_size, mydata->data_begin); + FAT_DPRINT ("Cluster size: %d\n", mydata->clust_size); + + /* "cwd" is always the root... */ + while (ISDIRDELIM (*filename)) + filename++; + /* Make a copy of the filename and convert it to lowercase */ + strcpy (fnamecopy, filename); + downcase (fnamecopy); + if (*fnamecopy == '\0') { + if (!dols){ + printf("\n not there\n"); + return -1; + } + dols = LS_ROOT; + } else if ((idx = dirdelim (fnamecopy)) >= 0) { + isdir = 1; + fnamecopy[idx] = '\0'; + subname = fnamecopy + idx + 1; + /* Handle multiple delimiters */ + while (ISDIRDELIM (*subname)) + subname++; + } else if (dols) { + isdir = 1; + } + + while (1) { + int i; + + if (disk_read (cursect, mydata->clust_size, do_fat_read_block) < 0) { + printf ("Error: reading rootdir block\n"); + return -1; + } + dentptr = (dir_entry *) do_fat_read_block; + for (i = 0; i < DIRENTSPERBLOCK; i++) { + char s_name[14], l_name[256]; + + l_name[0] = '\0'; + if ((dentptr->attr & ATTR_VOLUME)) { + /* Volume label or VFAT entry */ + dentptr++; + continue; + } else if (dentptr->name[0] == 0) { + FAT_DPRINT ("RootDentname == NULL - %d\n", i); + if (dols == LS_ROOT) { + printf ("\n%d file(s), %d dir(s)\n\n", files, dirs); + return 0; + } + return -1; + } +#ifdef CONFIG_SUPPORT_VFAT + else if (dols == LS_ROOT + && mkcksum (dentptr->name) == prevcksum) { + dentptr++; + continue; + } +#endif + get_name (dentptr, s_name); + if (dols == LS_ROOT) { + int isdir = (dentptr->attr & ATTR_DIR); + char dirc; + int doit = 0; + + if (isdir) { + dirc = '/'; + if (s_name[0] != 0) { + dirs++; + doit = 1; + } + } else { + dirc = ' '; + if (s_name[0] != 0) { + files++; + doit = 1; + } + } + if (doit) { + if (dirc == ' ') { + printf (" %8ld %s%c\n", + (long) FAT2CPU32 (dentptr->size), s_name, + dirc); + } else { + printf (" %s%c\n", s_name, dirc); + } + } + dentptr++; + continue; + } + if (strcmp (fnamecopy, s_name) && strcmp (fnamecopy, l_name)) { + FAT_DPRINT ("RootMismatch: |%s|%s|\n", s_name, l_name); + dentptr++; + continue; + } + if (isdir && !(dentptr->attr & ATTR_DIR)) + return -1; + + FAT_DPRINT ("RootName: %s", s_name); + FAT_DPRINT (", start: 0x%x", START (dentptr)); + FAT_DPRINT (", size: 0x%x %s\n", + FAT2CPU32 (dentptr->size), isdir ? "(DIR)" : ""); + + goto rootdir_done; /* We got a match */ + } + + if (mydata->fatsize != 32) + cursect++; + else { + // FAT32 does not guarantee contiguous root directory + curclus = get_fatent (mydata, curclus); + cursect = (curclus * mydata->clust_size) + mydata->data_begin; + + FAT_DPRINT ("root clus %d sector %d\n", curclus, cursect); + } + } + rootdir_done: + + firsttime = 1; + while (isdir) { + int startsect = mydata->data_begin + + START (dentptr) * mydata->clust_size; + dir_entry dent; + char *nextname = NULL; + + dent = *dentptr; + dentptr = &dent; + idx = dirdelim (subname); + if (idx >= 0) { + subname[idx] = '\0'; + nextname = subname + idx + 1; + /* Handle multiple delimiters */ + while (ISDIRDELIM (*nextname)) + nextname++; + if (dols && *nextname == '\0') + firsttime = 0; + } else { + if (dols && firsttime) { + firsttime = 0; + } else { + isdir = 0; + } + } + + if (get_dentfromdir (mydata, startsect, subname, dentptr, + isdir ? 0 : dols) == NULL) { + if (dols && !isdir) + return 0; + return -1; + } + + if (idx >= 0) { + if (!(dentptr->attr & ATTR_DIR)) + return -1; + subname = nextname; + } + } + ret = get_contents (mydata, dentptr, buffer, maxsize); + FAT_DPRINT ("Size: %d, got: %ld\n", FAT2CPU32 (dentptr->size), ret); + + return ret; +} + + +int +file_fat_detectfs(void) +{ + boot_sector bs; + volume_info volinfo; + int fatsize; + char vol_label[12]; + + if(cur_dev==NULL) { + printf("No current device\n"); + return 1; + } +#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || (CONFIG_MMC) + printf("Interface: "); + switch(cur_dev->if_type) { + case IF_TYPE_IDE : printf("IDE"); break; + case IF_TYPE_SCSI : printf("SCSI"); break; + case IF_TYPE_ATAPI : printf("ATAPI"); break; + case IF_TYPE_USB : printf("USB"); break; + case IF_TYPE_DOC : printf("DOC"); break; + case IF_TYPE_MMC : printf("MMC"); break; + default : printf("Unknown"); + } + printf("\n Device %d: ",cur_dev->dev); + dev_print(cur_dev); +#endif + if(read_bootsectandvi(&bs, &volinfo, &fatsize)) { + printf("\nNo valid FAT fs found\n"); + return 1; + } + memcpy (vol_label, volinfo.volume_label, 11); + vol_label[11] = '\0'; + volinfo.fs_type[5]='\0'; + printf("Partition %d: Filesystem: %s \"%s\"\n",cur_part,volinfo.fs_type,vol_label); + return 0; +} + + +int +file_fat_ls(const char *dir) +{ + return do_fat_read(dir, NULL, 0, LS_YES); +} + + +long +file_fat_read(const char *filename, void *buffer, unsigned long maxsize) +{ + long ret; + ret = do_fat_read(filename, buffer, maxsize, LS_NO); + return ret; +} + +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FAT) */ diff --git a/fs/fat/file.c b/fs/fat/file.c new file mode 100644 index 0000000..5994271 --- /dev/null +++ b/fs/fat/file.c @@ -0,0 +1,209 @@ +/* + * file.c + * + * Mini "VFS" by Marcus Sundberg + * + * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6 + * 2003-03-10 - kharris@nexus-tech.net - ported to uboot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_FAT) + +/* Supported filesystems */ +static const struct filesystem filesystems[] = { + { file_fat_detectfs, file_fat_ls, file_fat_read, "FAT" }, +}; +#define NUM_FILESYS (sizeof(filesystems)/sizeof(struct filesystem)) + +/* The filesystem which was last detected */ +static int current_filesystem = FSTYPE_NONE; + +/* The current working directory */ +#define CWD_LEN 511 +char file_cwd[CWD_LEN+1] = "/"; + +const char * +file_getfsname(int idx) +{ + if (idx < 0 || idx >= NUM_FILESYS) return NULL; + + return filesystems[idx].name; +} + + +static void +pathcpy(char *dest, const char *src) +{ + char *origdest = dest; + + do { + if (dest-file_cwd >= CWD_LEN) { + *dest = '\0'; + return; + } + *(dest) = *(src); + if (*src == '\0') { + if (dest-- != origdest && ISDIRDELIM(*dest)) { + *dest = '\0'; + } + return; + } + ++dest; + if (ISDIRDELIM(*src)) { + while (ISDIRDELIM(*src)) src++; + } else { + src++; + } + } while (1); +} + + +int +file_cd(const char *path) +{ + if (ISDIRDELIM(*path)) { + while (ISDIRDELIM(*path)) path++; + strncpy(file_cwd+1, path, CWD_LEN-1); + } else { + const char *origpath = path; + char *tmpstr = file_cwd; + int back = 0; + + while (*tmpstr != '\0') tmpstr++; + do { + tmpstr--; + } while (ISDIRDELIM(*tmpstr)); + + while (*path == '.') { + path++; + while (*path == '.') { + path++; + back++; + } + if (*path != '\0' && !ISDIRDELIM(*path)) { + path = origpath; + back = 0; + break; + } + while (ISDIRDELIM(*path)) path++; + origpath = path; + } + + while (back--) { + /* Strip off path component */ + while (!ISDIRDELIM(*tmpstr)) { + tmpstr--; + } + if (tmpstr == file_cwd) { + /* Incremented again right after the loop. */ + tmpstr--; + break; + } + /* Skip delimiters */ + while (ISDIRDELIM(*tmpstr)) tmpstr--; + } + tmpstr++; + if (*path == '\0') { + if (tmpstr == file_cwd) { + *tmpstr = '/'; + tmpstr++; + } + *tmpstr = '\0'; + return 0; + } + *tmpstr = '/'; + pathcpy(tmpstr+1, path); + } + + return 0; +} + + +int +file_detectfs(void) +{ + int i; + + current_filesystem = FSTYPE_NONE; + + for (i = 0; i < NUM_FILESYS; i++) { + if (filesystems[i].detect() == 0) { + strcpy(file_cwd, "/"); + current_filesystem = i; + break; + } + } + + return current_filesystem; +} + + +int +file_ls(const char *dir) +{ + char fullpath[1024]; + const char *arg; + + if (current_filesystem == FSTYPE_NONE) { + printf("Can't list files without a filesystem!\n"); + return -1; + } + + if (ISDIRDELIM(*dir)) { + arg = dir; + } else { + sprintf(fullpath, "%s/%s", file_cwd, dir); + arg = fullpath; + } + return filesystems[current_filesystem].ls(arg); +} + + +long +file_read(const char *filename, void *buffer, unsigned long maxsize) +{ + char fullpath[1024]; + const char *arg; + + if (current_filesystem == FSTYPE_NONE) { + printf("Can't load file without a filesystem!\n"); + return -1; + } + + if (ISDIRDELIM(*filename)) { + arg = filename; + } else { + sprintf(fullpath, "%s/%s", file_cwd, filename); + arg = fullpath; + } + + return filesystems[current_filesystem].read(arg, buffer, maxsize); +} + +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FAT) */ diff --git a/include/asm/arch-arm1136/bits.h b/include/asm/arch-arm1136/bits.h new file mode 100644 index 0000000..dc3273e --- /dev/null +++ b/include/asm/arch-arm1136/bits.h @@ -0,0 +1,49 @@ +/* bits.h + * Copyright (c) 2004 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef __bits_h +#define __bits_h 1 + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif + diff --git a/include/asm/arch-arm1136/clocks.h b/include/asm/arch-arm1136/clocks.h new file mode 100644 index 0000000..8e00d2e --- /dev/null +++ b/include/asm/arch-arm1136/clocks.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP24XX_CLOCKS_H_ +#define _OMAP24XX_CLOCKS_H_ + +#define COMMIT_DIVIDERS 0x1 +#define MODE_BYPASS_FAST 0x2 +#define APLL_LOCK 0xc +#define DPLL_LOCK 0x3 /* DPLL lock */ +#define LDELAY 12000000 + +#if defined(CONFIG_OMAP242X) +#include +#elif defined(CONFIG_OMAP243X) +#include +#endif + +#define S12M 12000000 +#define S13M 13000000 +#define S19_2M 19200000 +#define S24M 24000000 +#define S26M 26000000 +#define S38_4M 38400000 + +#endif + + + + + + + + diff --git a/include/asm/arch-arm1136/clocks242x.h b/include/asm/arch-arm1136/clocks242x.h new file mode 100644 index 0000000..0ae1c4e --- /dev/null +++ b/include/asm/arch-arm1136/clocks242x.h @@ -0,0 +1,147 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP242X_CLOCKS_H_ +#define _OMAP242X_CLOCKS_H_ + +/****************************************************************************; +; PRCM Scheme I +; +; Enable clocks and DPLL for: +; DPLL=330, DPLLout=660 M=1,N=55 CM_CLKSEL1_PLL[21:8] 12/2*55 +; Core=660 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=330 (mpu domain) 2 CM_CLKSEL_MPU[4:0] +; DSPF=220 (dsp domain) 3 CM_CLKSEL_DSP[4:0] +; DSPI=110 6 CM_CLKSEL_DSP[6:5] +; DSP_S activated CM_CLKSEL_DSP[7] +; IVAF=165 (dsp domain) 4 CM_CLKSEL_DSP[12:8] +; IVAF=82.5 auto +; IVAI auto +; IVA_MPU auto +; IVA_S bypass CM_CLKSEL_DSP[13] +; GFXF=82.5 (gfx domain) 8 CM_CLKSEL_FGX[2:0] +; SSI_SSRF=220 3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=110 auto +; L3=165Mhz (sdram) 4 CM_CLKSEL1_CORE[4:0] +; L4=82.5Mhz 8 +; C_L4_USB=41.25 16 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define I_DPLL_OUT_X2 0x2 /* x2 core out */ +#define I_MPU_DIV 0x2 /* mpu = core/2 */ +#define I_DSP_DIV 0x3c3 /* dsp & iva divider */ +#define I_GFX_DIV 0x2 +#define I_BUS_DIV 0x04601044 +#ifdef INPUT_CLK_13MHZ +#define I_DPLL_330 0x0114AC00 /* 13MHz */ +#else +#define I_DPLL_330 0x01837100 /* 12MHz */ +#endif + +/****************************************************************************; +; PRCM Scheme II +; +; Enable clocks and DPLL for: +; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 +; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] +; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] +; DSPI=100 6 CM_CLKSEL_DSP[6:5] +; DSP_S bypass CM_CLKSEL_DSP[7] +; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8] +; IVAF=100 auto +; IVAI auto +; IVA_MPU auto +; IVA_S bypass CM_CLKSEL_DSP[13] +; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0] +; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=100 auto +; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0] +; L4=100Mhz 6 +; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define II_DPLL_OUT_X2 0x2 /* x2 core out */ +#define II_MPU_DIV 0x2 /* mpu = core/2 */ +#define II_DSP_DIV 0x343 /* dsp & iva divider */ +#define II_GFX_DIV 0x2 +#define II_BUS_DIV 0x04601026 +#ifdef INPUT_CLK_13MHZ +#define II_DPLL_300 0x0112CC00 /* 13MHz */ +#else +#define II_DPLL_300 0x01832100 /* 12MHz */ +#endif + +/****************************************************************************; +; PRCM Scheme III +; +; Enable clocks and DPLL for: +; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 +; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] +; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] +; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] +; DSP_S ACTIVATED CM_CLKSEL_DSP[7] +; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8] +; IVAF=88.67 auto +; IVAI auto +; IVA_MPU auto +; IVA_S ACTIVATED CM_CLKSEL_DSP[13] +; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]: +; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=88.67 auto +; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0] +; L4=66.5Mhz /8 +; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define III_DPLL_OUT_X2 0x2 /* x2 core out */ +#define III_MPU_DIV 0x2 /* mpu = core/2 */ +#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ +#define III_GFX_DIV 0x2 +#define III_BUS_DIV 0x08301044 +#ifdef INPUT_CLK_13MHZ +#define III_DPLL_266 0x0110AC00 /* 13MHz */ +#else +#define III_DPLL_266 0x01885500 /* 12MHz */ +#endif + +/* set defaults for boot up */ +#ifdef PRCM_CONFIG_I +# define DPLL_OUT I_DPLL_OUT_X2 +# define MPU_DIV I_MPU_DIV +# define DSP_DIV I_DSP_DIV +# define GFX_DIV I_GFX_DIV +# define BUS_DIV I_BUS_DIV +# define DPLL_VAL I_DPLL_266 +#elif PRCM_CONFIG_II +# define DPLL_OUT II_DPLL_OUT_X2 +# define MPU_DIV II_MPU_DIV +# define DSP_DIV II_DSP_DIV +# define GFX_DIV II_GFX_DIV +# define BUS_DIV II_BUS_DIV +# define DPLL_VAL II_DPLL_300 +#elif PRCM_CONFIG_III +# define DPLL_OUT III_DPLL_OUT_X2 +# define MPU_DIV III_MPU_DIV +# define DSP_DIV III_DSP_DIV +# define GFX_DIV III_GFX_DIV +# define BUS_DIV III_BUS_DIV +# define DPLL_VAL III_DPLL_266 +#endif + +#endif diff --git a/include/asm/arch-arm1136/clocks243x.h b/include/asm/arch-arm1136/clocks243x.h new file mode 100644 index 0000000..18d2e46 --- /dev/null +++ b/include/asm/arch-arm1136/clocks243x.h @@ -0,0 +1,223 @@ +/* + * (C) Copyright 2005 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP243X_CLOCKS_H_ +#define _OMAP243X_CLOCKS_H_ + +/* cm_clksel core fields not ratio governed */ +#define RX_CLKSEL_DSS1 (0x10 << 8) +#define RX_CLKSEL_DSS2 (0x0 << 13) +#define RX_CLKSEL_SSI (0x5 << 20) + +/* 2430 Ratio's */ +/* 2430-Ratio Config 1 */ +#define R1_CLKSEL_L3 (4 << 0) +#define R1_CLKSEL_L4 (2 << 5) +#define R1_CLKSEL_USB (4 << 25) +#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \ + | RX_CLKSEL_DSS1 | R1_CLKSEL_L4 | R1_CLKSEL_L3 +#define R1_CLKSEL_MPU (2 << 0) +#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU +#define R1_CLKSEL_DSP (2 << 0) +#define R1_CLKSEL_DSP_IF (2 << 5) +#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF +#define R1_CLKSEL_GFX (2 << 0) +#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX +#define R1_CLKSEL_MDM (4 << 0) +#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM + +/* 2430-Ratio Config 2 */ +#define R2_CLKSEL_L3 (6 << 0) +#define R2_CLKSEL_L4 (2 << 5) +#define R2_CLKSEL_USB (2 << 25) +#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \ + | RX_CLKSEL_DSS1 | R2_CLKSEL_L4 | R2_CLKSEL_L3 +#define R2_CLKSEL_MPU (2 << 0) +#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU +#define R2_CLKSEL_DSP (2 << 0) +#define R2_CLKSEL_DSP_IF (3 << 5) +#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF +#define R2_CLKSEL_GFX (2 << 0) +#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX +#define R2_CLKSEL_MDM (6 << 0) +#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM + +/* 2430-Ratio Boot */ +#define RB_CLKSEL_L3 (1 << 0) +#define RB_CLKSEL_L4 (1 << 5) +#define RB_CLKSEL_USB (1 << 25) +#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \ + | RX_CLKSEL_DSS1 | RB_CLKSEL_L4 | RB_CLKSEL_L3 +#define RB_CLKSEL_MPU (1 << 0) +#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU +#define RB_CLKSEL_DSP (1 << 0) +#define RB_CLKSEL_DSP_IF (1 << 5) +#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF +#define RB_CLKSEL_GFX (1 << 0) +#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX +#define RB_CLKSEL_MDM (1 << 0) +#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM + +/* 2430 Target modes: Along with each configuration the CPU has several modes + * which goes along with them. Modes mainly are the addition of descrite DPLL + * combinations to go along with a ratio. + */ +/* hardware goverend */ +#define MX_48M_SRC (0 << 3) +#define MX_54M_SRC (0 << 5) +#define MX_APLLS_CLIKIN_12 (3 << 23) +#define MX_APLLS_CLIKIN_13 (2 << 23) +#define MX_APLLS_CLIKIN_19_2 (0 << 23) + +/* 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed */ + +/* boot (boot) */ +#define MB_DPLL_MULT (1 << 12) +#define MB_DPLL_DIV (0 << 8) +#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ + | MB_DPLL_MULT | MX_APLLS_CLIKIN_12 + +#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ + | MB_DPLL_MULT | MX_APLLS_CLIKIN_13 + +#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ + | MB_DPLL_MULT | MX_APLLS_CLIKIN_19 + +/* #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz */ + +#define M2_DPLL_MULT_12 (55 << 12) +#define M2_DPLL_DIV_12 (1 << 8) +#define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_12 \ + | M2_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 +/* Use 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, relock time issue */ +#define M2_DPLL_MULT_13 (330 << 12) +#define M2_DPLL_DIV_13 (12 << 8) +#define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_13 \ + | M2_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 +#define M2_DPLL_MULT_19 (275 << 12) +#define M2_DPLL_DIV_19 (15 << 8) +#define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_19 \ + | M2_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 + +/* #3 (ratio2) DPLL = 330*2 = 660MHz, L3=110MHz */ +#define M3_DPLL_MULT_12 (55 << 12) +#define M3_DPLL_DIV_12 (1 << 8) +#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_12 \ + | M3_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 +#define M3_DPLL_MULT_13 (330 << 12) +#define M3_DPLL_DIV_13 (12 << 8) +#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_13 \ + | M3_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 +#define M3_DPLL_MULT_19 (275 << 12) +#define M3_DPLL_DIV_19 (15 << 8) +#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_19 \ + | M3_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 + +/* #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz*/ +#define M4_DPLL_MULT_12 (133 << 12) +#define M4_DPLL_DIV_12 (3 << 8) +#define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_12 \ + | M4_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 +#define M4_DPLL_MULT_13 (399 << 12) +#define M4_DPLL_DIV_13 (12 << 8) +#define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_13 \ + | M4_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 +#define M4_DPLL_MULT_19 (145 << 12) +#define M4_DPLL_DIV_19 (6 << 8) +#define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_19 \ + | M4_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 + +/* #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz, L3=133MHz */ +#define M5A_DPLL_MULT_12 (133 << 12) +#define M5A_DPLL_DIV_12 (5 << 8) +#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_12 \ + | M5A_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 +#define M5A_DPLL_MULT_13 (266 << 12) +#define M5A_DPLL_DIV_13 (12 << 8) +#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_13 \ + | M5A_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 +#define M5A_DPLL_MULT_19 (180 << 12) +#define M5A_DPLL_DIV_19 (12 << 8) +#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_19 \ + | M5A_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 + +/* #5b (ratio1) target DPLL = 200*2 = 400MHz, L3=100MHz */ +#define M5B_DPLL_MULT_12 (50 << 12) +#define M5B_DPLL_DIV_12 (2 << 8) +#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_12 \ + | M5B_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 +#define M5B_DPLL_MULT_13 (200 << 12) +#define M5B_DPLL_DIV_13 (12 << 8) + +#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_13 \ + | M5B_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 +#define M5B_DPLL_MULT_19 (125 << 12) +#define M5B_DPLL_DIV_19 (31 << 8) +#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_19 \ + | M5B_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 + +/* 2430 - chassis (sedna) */ + /* 165 (ratio1) same as above #2 */ + /* 150 (ratio1)*/ + /* 133 (ratio2) same as above #4 */ + /* 110 (ratio2) same as above #3*/ + /* 104 (ratio2)*/ + /* boot (boot) */ + +/* high and low operation value */ +#define MX_CLKSEL2_PLL_2x_VAL (2 << 0) +#define MX_CLKSEL2_PLL_1x_VAL (1 << 0) + +/* set defaults for boot up */ +#if defined(PRCM_CONFIG_2) /* ARM-330MHz IVA2-330MHz L3-165MHz */ +# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL +# define MPU_DIV R1_CLKSEL_MPU +# define DSP_DIV R1_CM_CLKSEL_DSP_VAL +# define GFX_DIV R1_CM_CLKSEL_GFX_VAL +# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL +# define DPLL_VAL M2_CM_CLKSEL1_PLL_13_VAL +# define MDM_DIV R2_CM_CLKSEL_MDM_VAL +#elif defined(PRCM_CONFIG_3) /* ARM-330MHz IVA2-330MHz L3-110MHz */ +# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL +# define MPU_DIV R2_CLKSEL_MPU +# define DSP_DIV R2_CM_CLKSEL_DSP_VAL +# define GFX_DIV R2_CM_CLKSEL_GFX_VAL +# define BUS_DIV R2_CM_CLKSEL1_CORE_VAL +# define DPLL_VAL M3_CM_CLKSEL1_PLL_13_VAL +# define MDM_DIV R2_CM_CLKSEL_MDM_VAL +#elif defined(PRCM_CONFIG_5A) /* ARM-266MHz IVA2-266MHz L3-133MHz */ +# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL +# define MPU_DIV R1_CLKSEL_MPU +# define DSP_DIV R1_CM_CLKSEL_DSP_VAL +# define GFX_DIV R1_CM_CLKSEL_GFX_VAL +# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL +# define DPLL_VAL M5A_CM_CLKSEL1_PLL_13_VAL +# define MDM_DIV R2_CM_CLKSEL_MDM_VAL +#elif defined(PRCM_CONFIG_5B) /* ARM-200MHz IVA2-200MHz L3-100MHz */ +# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL +# define MPU_DIV R1_CLKSEL_MPU +# define DSP_DIV R1_CM_CLKSEL_DSP_VAL +# define GFX_DIV R1_CM_CLKSEL_GFX_VAL +# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL +# define DPLL_VAL M5B_CM_CLKSEL1_PLL_13_VAL +# define MDM_DIV R1_CM_CLKSEL_MDM_VAL +#endif + +#endif diff --git a/include/asm/arch-arm1136/mem.h b/include/asm/arch-arm1136/mem.h new file mode 100644 index 0000000..2a3da73 --- /dev/null +++ b/include/asm/arch-arm1136/mem.h @@ -0,0 +1,383 @@ + +/* + * (C) Copyright 2004-2005 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP24XX_MEM_H_ +#define _OMAP24XX_MEM_H_ + +#define SDRC_CS0_OSET 0x0 +#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ + +#ifndef __ASSEMBLY__ +/* struct's for holding data tables for current boards, they are getting used + early in init when NO global access are there */ +struct sdrc_data_s { + u32 sdrc_sharing; + u32 sdrc_mdcfg_0_ddr; + u32 sdrc_mdcfg_0_sdr; + u32 sdrc_actim_ctrla_0; + u32 sdrc_actim_ctrlb_0; + u32 sdrc_rfr_ctrl; + u32 sdrc_mr_0_ddr; + u32 sdrc_mr_0_sdr; + u32 sdrc_dllab_ctrl; +} /*__attribute__ ((packed))*/; +typedef struct sdrc_data_s sdrc_data_t; + +typedef enum { + STACKED = 0, + IP_DDR = 1, + COMBO_DDR = 2, + IP_SDR = 3, +} mem_t; + +#endif + +/* set the 243x-SDRC incoming address convention */ +#if defined(SDRC_B_R_C) +#define B_ALL (0 << 6) /* bank-row-column */ +#elif defined(SDRC_B1_R_B0_C) +#define B_ALL (1 << 6) /* bank1-row-bank0-column */ +#elif defined(SDRC_R_B_C) +#define B_ALL (2 << 6) /* row-bank-column */ +#endif + +/* Slower full frequency range default timings for x32 operation*/ +#define H4_2420_SDRC_SHARING 0x00000100 +#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */ +#define H4_2420_SDRC_MR_0_SDR 0x00000031 +#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */ +#define SDP_2430_SDRC_MDCFG_0_DDR (0x02584019|B_ALL) /* Infin ddr module */ +#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */ +#define H4_2420_SDRC_MR_0_DDR 0x00000032 + +#define H4_2422_SDRC_SHARING 0x00004b00 +#define H4_2422_SDRC_MDCFG_MONO_DDR 0x01A02011 /* stacked mono die ddr on 2422 */ +#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked dual die ddr on 2422 */ +#define H4_2422_SDRC_MR_0_DDR 0x00000032 + +#define H4_2423_SDRC_SHARING 0x00004900 /* 2420POP board cke1 not connected */ +#define H4_2423_SDRC_MDCFG_0_DDR 0x01A02011 /* stacked dual die ddr on 2423 */ +#define H4_2423_SDRC_MDCFG_1_DDR 0x00801011 /* stacked dual die ddr on 2423 */ + +/* ES1 work around timings */ +#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */ +#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020 +#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */ + +/* optimized timings good for current shipping parts */ +#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485 +#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e +#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */ +#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ +#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50 = 0x3de */ +#define SDP_24XX_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50 = 0x4e2 */ +#define H4_242X_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 90deg, allow DPLLout*1 to work (combo)*/ +#define H4_242X_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 90deg, for ES2 */ +#define SDP_24XX_SDRC_DLLAB_CTRL_165MHz 0x0000170C /* 72deg, code will recalc dll load */ + +/* Infineon part of 2430SDP (133MHz optimized) ~ 7.5ns + * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 + * TDPL = 15/7.5 = 2 + * TRRD = 15/2.5 = 2 + * TRCD = 22.5/7.5 = 3 + * TRP = 22.5/7.5 = 3 + * TRAS = 45/7.5 = 6 + * TRC = 65/7.5 = 8.6->9 + * TRFC = 75/7.5 = 10 + * ACTIMB + * TCKE = 2 + * XSR = 120/7.5 = 16 + */ +#define TDAL_133 5 +#define TDPL_133 2 +#define TRRD_133 2 +#define TRCD_133 3 +#define TRP_133 3 +#define TRAS_133 6 +#define TRC_133 9 +#define TRFC_133 10 +#define V_ACTIMA_133 ((TRFC_133 << 27) | (TRC_133 << 22) | (TRAS_133 << 18) |(TRP_133 << 15) | \ + (TRCD_133 << 12) |(TRRD_133 << 9) |(TDPL_133 << 6) | (TDAL_133)) + +#define TCKE_133 2 +#define XSR_133 16 +#define V_ACTIMB_133 ((TCKE_133 << 12) | (XSR_133 << 0)) + +/* Infineon part of 2430SDP (165MHz optimized) 6.06ns + * ACTIMA + * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 + * TDPL (Twr) = 15/6 = 2.5 -> 3 + * TRRD = 12/6 = 2 + * TRCD = 18/6 = 3 + * TRP = 18/6 = 3 + * TRAS = 42/6 = 7 + * TRC = 60/6 = 10 + * TRFC = 72/6 = 12 + * ACTIMB + * TCKE = 2 + * XSR = 120/6 = 20 + */ +#define TDAL_165 6 +#define TDPL_165 3 +#define TRRD_165 2 +#define TRCD_165 3 +#define TRP_165 3 +#define TRAS_165 7 +#define TRC_165 10 +#define TRFC_165 12 +#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) |(TRP_165 << 15) | \ + (TRCD_165 << 12) |(TRRD_165 << 9) |(TDPL_165 << 6) | (TDAL_165)) + +#define TCKE_165 2 +#define XSR_165 20 +#define V_ACTIMB_165 ((TCKE_165 << 12) | (XSR_165 << 0)) + +#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) +# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133 +# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2420_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_100MHz +# define SDP_2430_SDRC_DLLAB_CTRL 0x0000730E +# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2422_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_100MHz +#elif defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3) +# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz +# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133 +# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz +# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz +# define H4_2420_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_133MHz +# define SDP_2430_SDRC_DLLAB_CTRL 0x0000730E +# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz +# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz +# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz +# define H4_2422_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_133MHz +#elif defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) +# define H4_2420_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 +# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 +# define H4_2420_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 +# define H4_2420_SDRC_RFR_CTRL SDP_24XX_SDRC_RFR_CTRL_165MHz +# define H4_2420_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz +# define SDP_2430_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz +# define H4_2422_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 +# define H4_2422_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 +# define H4_2422_SDRC_RFR_CTRL SDP_24XX_SDRC_RFR_CTRL_165MHz +# define H4_2422_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz +#endif + +/* + * GPMC settings - + * Definitions is as per the following format + * # define _GPMC_CONFIG + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of the same. + * if values are independent of the board, this definition will be present in this file + * if values are dependent on the board, then this should go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * STNOR - Intel Strata Flash + * SMNAND - Samsung NAND + * MPDB - H4 MPDB board + * SBNOR - Sibley NOR + * ONNAND - Samsung One NAND + * + * include/configs/file.h contains the following defn - for all CS we are interested + * #define OMAP24XX_GPMC_CSx PART + * #define OMAP24XX_GPMC_CSx_SIZE Size + * #define OMAP24XX_GPMC_CSx_MAP Map + * Where: + * x - CS number + * PART - Part Name as defined above + * SIZE - how big is the mapping to be + * GPMC_SIZE_128M - 0x8 + * GPMC_SIZE_64M - 0xC + * GPMC_SIZE_32M - 0xE + * GPMC_SIZE_16M - 0xF + * MAP - Map this CS to which address(GPMC address space)- Absolute address + * >>24 before being used. + */ + +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) /* L3 at 100MHz */ +# define SMNAND_GPMC_CONFIG1 0x0 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x00000A80 +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x000f0f01 +# define STNOR_GPMC_CONFIG3 0x00050502 +# define STNOR_GPMC_CONFIG4 0x0C060C06 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x0 /* 0? Not defined so far... this value is reset val as per gpmc doc */ +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001F1F00 +# define MPDB_GPMC_CONFIG3 0x00080802 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x031A1F1F +# define MPDB_GPMC_CONFIG6 0x000003C2 +#endif + +#if defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3) /* L3 at 133MHz */ +# define SMNAND_GPMC_CONFIG1 0x00001800 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x00000A80 +# define SMNAND_GPMC_CONFIG7 0x00000C44 + +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x10081008 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x000004c4 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x000004C4 + +# define SIBNOR_GPMC_CONFIG1 0x3 +# define SIBNOR_GPMC_CONFIG2 0x00151501 +# define SIBNOR_GPMC_CONFIG3 0x00060602 +# define SIBNOR_GPMC_CONFIG4 0x10081008 +# define SIBNOR_GPMC_CONFIG5 0x01131F1F +# define SIBNOR_GPMC_CONFIG6 0x00000000 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000c0c01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0c040c04 +# define ONENAND_GPMC_CONFIG5 0x010C1010 +# define ONENAND_GPMC_CONFIG6 0x00000000 + +# define PCMCIA_GPMC_CONFIG1 0x01E91200 +# define PCMCIA_GPMC_CONFIG2 0x001E1E01 +# define PCMCIA_GPMC_CONFIG3 0x00020203 +# define PCMCIA_GPMC_CONFIG4 0x1D041D04 +# define PCMCIA_GPMC_CONFIG5 0x031D1F1F +# define PCMCIA_GPMC_CONFIG6 0x000004C4 +#endif /* endif CFG_PRCM_III */ + +#if defined (PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) /* L3 at 165MHz */ +# define SMNAND_GPMC_CONFIG1 0x00001800 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x00000A80 +# define SMNAND_GPMC_CONFIG7 0x00000C44 + +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x11091109 +# define STNOR_GPMC_CONFIG5 0x01141F1F +# define STNOR_GPMC_CONFIG6 0x000004c4 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1c0b1c0a +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x000004C4 + +# define SIBNOR_GPMC_CONFIG1 0x3 +# define SIBNOR_GPMC_CONFIG2 0x00151501 +# define SIBNOR_GPMC_CONFIG3 0x00060602 +# define SIBNOR_GPMC_CONFIG4 0x11091109 +# define SIBNOR_GPMC_CONFIG5 0x01141F1F +# define SIBNOR_GPMC_CONFIG6 0x00000000 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000F0F01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0F040F04 +# define ONENAND_GPMC_CONFIG5 0x010F1010 +# define ONENAND_GPMC_CONFIG6 0x00000000 + +# define PCMCIA_GPMC_CONFIG1 0x01E91200 +# define PCMCIA_GPMC_CONFIG2 0x001E1E01 +# define PCMCIA_GPMC_CONFIG3 0x00020203 +# define PCMCIA_GPMC_CONFIG4 0x1D041D04 +# define PCMCIA_GPMC_CONFIG5 0x031D1F1F +# define PCMCIA_GPMC_CONFIG6 0x000004C4 + +#endif + +#if 0 +/* Board Specific Settings for each of the configurations for chips + * whose values change as per platform. - None currently + */ +#if CONFIG_OMAP24XXH4 +#include +#endif + +#if CONFIG_2430SDP +#include +#endif + +#endif /* if 0 */ + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#define PROC_NOR 1 +#define PROC_NAND 2 +#define PISMO_SIBLEY0 3 +#define PISMO_SIBLEY1 4 +#define PISMO_ONENAND 5 +#define DBG_MPDB 6 +#define PISMO_PCMCIA 7 + +/* make it readable for the gpmc_init */ +#define PROC_NOR_BASE FLASH_BASE +#define PROC_NAND_BASE NAND_BASE +#define PISMO_SIB0_BASE SIBLEY_MAP1 +#define PISMO_SIB1_BASE SIBLEY_MAP2 +#define PISMO_ONEN_BASE ONENAND_MAP +#define DBG_MPDB_BASE DEBUG_BASE +#define PISMO_PCMCIA_BASE PCMCIA_BASE + +#endif /* endif _OMAP24XX_MEM_H_ */ diff --git a/include/asm/arch-arm1136/omap2420.h b/include/asm/arch-arm1136/omap2420.h new file mode 100644 index 0000000..2164b68 --- /dev/null +++ b/include/asm/arch-arm1136/omap2420.h @@ -0,0 +1,223 @@ +/* + * Copyright (C) 2005 Texas Instruments, + * + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP2420_SYS_H_ +#define _OMAP2420_SYS_H_ + +#include + + +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + + +/* + * 2420 specific Section + */ + +/* CONTROL */ +#define OMAP2420_CTRL_BASE (0x48000000) +#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) + +/* TAP information */ +#define OMAP2420_TAP_BASE (0x48014000) +#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) + +/* GPMC */ +#define OMAP2420_GPMC_BASE (0x6800A000) +#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) +#define GPMC_SYSSTATUS (OMAP2420_GPMC_BASE+0x14) +#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) +#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) +#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) +#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) +#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) +#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) +#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) +#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) +#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) +#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) +#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) +#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) +#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) +#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) +#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) + +/* SMS */ +#define OMAP2420_SMS_BASE 0x68008000 +#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) + +/* SDRC */ +#define OMAP2420_SDRC_BASE 0x68009000 +#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) +#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) +#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) +#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) +#define SDRC_DLLA_STATUS (OMAP2420_SDRC_BASE+0x64) +#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) +#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) +#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) +#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) +#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) +#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) +#define SDRC_MCFG_1 (OMAP2420_SDRC_BASE+0xB0) +#define SDRC_MR_1 (OMAP2420_SDRC_BASE+0xB4) +#define SDRC_EMR2_1 (OMAP2420_SDRC_BASE+0xBC) +#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) +#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) +#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) +#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) +#define SDRC_RFR_CTRL1 (OMAP2420_SDRC_BASE+0xD4) +#define SDRC_MANUAL_1 (OMAP2420_SDRC_BASE+0xD8) + +#define OMAP2420_SDRC_CS0 0x80000000 +#define OMAP2420_SDRC_CS1 0xA0000000 + +#define LOADDLL BIT2 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET BIT1 +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + + +/* UART */ +#define OMAP2420_UART1 0x4806A000 +#define OMAP2420_UART2 0x4806C000 +#define OMAP2420_UART3 0x4806E000 + +/* General Purpose Timers */ +#define OMAP2420_GPT1 0x48028000 +#define OMAP2420_GPT2 0x4802A000 +#define OMAP2420_GPT3 0x48078000 +#define OMAP2420_GPT4 0x4807A000 +#define OMAP2420_GPT5 0x4807C000 +#define OMAP2420_GPT6 0x4807E000 +#define OMAP2420_GPT7 0x48080000 +#define OMAP2420_GPT8 0x48082000 +#define OMAP2420_GPT9 0x48084000 +#define OMAP2420_GPT10 0x48086000 +#define OMAP2420_GPT11 0x48088000 +#define OMAP2420_GPT12 0x4808A000 + +/* timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE 0x48020000 +#define WD2_BASE 0x48022000 +#define WD3_BASE 0x48024000 +#define WD4_BASE 0x48026000 +#define WWPS 0x34 /* r */ +#define WSPR 0x48 /* rw */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define OMAP2420_CM_BASE 0x48008000 +#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) +#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) +#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) +#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) +#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) +#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) +#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) +#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) +#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) +#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) +#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) +#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) +#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) +#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) +#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) +#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) + +/* + * H4 specific Section + */ + +/* + * The 2420's chip selects are programmable. The mask ROM + * does configure CS0 to 0x08000000 before dispatch. So, if + * you want your code to live below that address, you have to + * be prepared to jump though hoops, to reset the base address. + */ +#if defined(CONFIG_OMAP2420H4) +/* GPMC */ +#ifdef CONFIG_VIRTIO_A /* Pre version B */ +# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ +# define H4_CS1_BASE 0x04000000 /* debug board */ +# define H4_CS2_BASE 0x0A000000 /* wifi board */ +#else +# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ +# define H4_CS1_BASE 0x08000000 /* debug board */ +# define H4_CS2_BASE 0x0A000000 /* wifi board */ +#endif + +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) + +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +#define PERIFERAL_PORT_BASE 0x480FE003 + +/* FPGA on Debug board.*/ +#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) +#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) +#endif /* endif CONFIG_2420H4 */ + +#endif + diff --git a/include/asm/arch-arm1136/omap2430.h b/include/asm/arch-arm1136/omap2430.h new file mode 100644 index 0000000..cf2b0f9 --- /dev/null +++ b/include/asm/arch-arm1136/omap2430.h @@ -0,0 +1,255 @@ +/* + * (C) Copyright 2004-2005 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP2430_SYS_H_ +#define _OMAP2430_SYS_H_ + +#include + + +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + +/* device type */ +#define DEVICE_MASK (BIT8|BIT9|BIT10) +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* + * 2430 specific Section + */ +#define OMAP243X_CORE_L4_IO_BASE 0x48000000 +#define OMAP243X_WAKEUP_L4_IO_BASE 0x49000000 +#define OMAP24XX_L4_IO_BASE OMAP243X_CORE_L4_IO_BASE + + +/* CONTROL */ +#define OMAP24XX_CTRL_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x2000) +#define CONTROL_STATUS (OMAP24XX_CTRL_BASE + 0x2F8) + +/* TAP information */ +#define OMAP24XX_TAP_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0xA000) +#define TAP_IDCODE_REG (OMAP24XX_TAP_BASE+0x204) + +/* + GPMC : In 2430 NOR and NAND can coexist. + During NAND booting , NAND is at CS0 and NOR at CS1 + and Debug FPGA is GPMC_CS5 +*/ +#define OMAP24XX_GPMC_BASE (0x6E000000) + +#define GPMC_SYSCONFIG (OMAP24XX_GPMC_BASE+0x10) +#define GPMC_SYSSTATUS (OMAP24XX_GPMC_BASE+0x14) +#define GPMC_IRQENABLE (OMAP24XX_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP24XX_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP24XX_GPMC_BASE+0x50) +#define GPMC_CONFIG1_0 (OMAP24XX_GPMC_BASE+0x60) +#define GPMC_CONFIG2_0 (OMAP24XX_GPMC_BASE+0x64) +#define GPMC_CONFIG3_0 (OMAP24XX_GPMC_BASE+0x68) +#define GPMC_CONFIG4_0 (OMAP24XX_GPMC_BASE+0x6C) +#define GPMC_CONFIG5_0 (OMAP24XX_GPMC_BASE+0x70) +#define GPMC_CONFIG6_0 (OMAP24XX_GPMC_BASE+0x74) +#define GPMC_CONFIG7_0 (OMAP24XX_GPMC_BASE+0x78) +#define GPMC_CONFIG1_1 (OMAP24XX_GPMC_BASE+0x90) +#define GPMC_CONFIG2_1 (OMAP24XX_GPMC_BASE+0x94) +#define GPMC_CONFIG3_1 (OMAP24XX_GPMC_BASE+0x98) +#define GPMC_CONFIG4_1 (OMAP24XX_GPMC_BASE+0x9C) +#define GPMC_CONFIG5_1 (OMAP24XX_GPMC_BASE+0xA0) +#define GPMC_CONFIG6_1 (OMAP24XX_GPMC_BASE+0xA4) +#define GPMC_CONFIG7_1 (OMAP24XX_GPMC_BASE+0xA8) +#define GPMC_CONFIG1_5 (OMAP24XX_GPMC_BASE+0x150) +#define GPMC_CONFIG2_5 (OMAP24XX_GPMC_BASE+0x154) +#define GPMC_CONFIG3_5 (OMAP24XX_GPMC_BASE+0x158) +#define GPMC_CONFIG4_5 (OMAP24XX_GPMC_BASE+0x15C) +#define GPMC_CONFIG5_5 (OMAP24XX_GPMC_BASE+0x160) +#define GPMC_CONFIG6_5 (OMAP24XX_GPMC_BASE+0x164) +#define GPMC_CONFIG7_5 (OMAP24XX_GPMC_BASE+0x168) + + +/* SMS */ +#define OMAP24XX_SMS_BASE 0x6C000000 +#define SMS_SYSCONFIG (OMAP24XX_SMS_BASE+0x10) + +/* SDRC */ +#define OMAP24XX_SDRC_BASE 0x6D000000 +#define OMAP24XX_SDRC_CS0 0x80000000 +#define OMAP24XX_SDRC_CS1 0xA0000000 +#define SDRC_SYSCONFIG (OMAP24XX_SDRC_BASE+0x10) +#define SDRC_STATUS (OMAP24XX_SDRC_BASE+0x14) +#define SDRC_SHARING (OMAP24XX_SDRC_BASE+0x44) +#define SDRC_DLLA_CTRL (OMAP24XX_SDRC_BASE+0x60) +#define SDRC_DLLA_STATUS (OMAP24XX_SDRC_BASE+0x64) +#define SDRC_DLLB_CTRL (OMAP24XX_SDRC_BASE+0x68) +#define SDRC_POWER (OMAP24XX_SDRC_BASE+0x70) +#define SDRC_MCFG_0 (OMAP24XX_SDRC_BASE+0x80) +#define SDRC_MR_0 (OMAP24XX_SDRC_BASE+0x84) +#define SDRC_ACTIM_CTRLA_0 (OMAP24XX_SDRC_BASE+0x9C) +#define SDRC_ACTIM_CTRLB_0 (OMAP24XX_SDRC_BASE+0xA0) +#define SDRC_MCFG_1 (OMAP24XX_SDRC_BASE+0xB0) +#define SDRC_ACTIM_CTRLA_1 (OMAP24XX_SDRC_BASE+0xC4) +#define SDRC_ACTIM_CTRLB_1 (OMAP24XX_SDRC_BASE+0xC8) +#define SDRC_RFR_CTRL (OMAP24XX_SDRC_BASE+0xA4) +#define SDRC_MANUAL_0 (OMAP24XX_SDRC_BASE+0xA8) +#define SDRC_RFR_CTRL1 (OMAP24XX_SDRC_BASE+0xD4) + +#define LOADDLL BIT2 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET BIT1 +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + + +/* UART */ +#define OMAP2430_UART1 0x4806A000 +#define OMAP2430_UART2 0x4806C000 +#define OMAP2430_UART3 0x4806E000 + +/* General Purpose Timers */ +#define OMAP24XX_GPT1 (OMAP243X_WAKEUP_L4_IO_BASE+0x18000) +#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000) +#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000) +#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000) +#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000) +#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000) +#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000) +#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000) +#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000) +#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000) +#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000) +#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000 + +/* timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x14000) +#define WD2_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x16000) +#define WD3_BASE (OMAP24XX_L4_IO_BASE+0x24000) /* not present */ +#define WD4_BASE (OMAP24XX_L4_IO_BASE+0x26000) + +/* 32KTIMER */ +#define SYNC_32KTIMER_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x20000) +#define S32K_CR (SYNC_32KTIMER_BASE+0x10) + +#define WWPS 0x34 /* r */ +#define WSPR 0x48 /* rw */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define OMAP24XX_CM_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x06000) + +#define PRCM_CLKSRC_CTRL (OMAP24XX_CM_BASE+0x060) +#define PRCM_CLKOUT_CTRL (OMAP24XX_CM_BASE+0x070) +#define PRCM_CLKEMUL_CTRL (OMAP24XX_CM_BASE+0x078) +#define PRCM_CLKCFG_CTRL (OMAP24XX_CM_BASE+0x080) +#define PRCM_CLKCFG_STATUS (OMAP24XX_CM_BASE+0x084) +#define CM_CLKSEL_MPU (OMAP24XX_CM_BASE+0x140) +#define CM_FCLKEN1_CORE (OMAP24XX_CM_BASE+0x200) +#define CM_FCLKEN2_CORE (OMAP24XX_CM_BASE+0x204) +#define CM_ICLKEN1_CORE (OMAP24XX_CM_BASE+0x210) +#define CM_ICLKEN2_CORE (OMAP24XX_CM_BASE+0x214) +#define CM_CLKSEL1_CORE (OMAP24XX_CM_BASE+0x240) +#define CM_CLKSEL_WKUP (OMAP24XX_CM_BASE+0x440) +#define CM_CLKSEL2_CORE (OMAP24XX_CM_BASE+0x244) +#define CM_FCLKEN_GFX (OMAP24XX_CM_BASE+0x300) +#define CM_ICLKEN_GFX (OMAP24XX_CM_BASE+0x310) +#define CM_CLKSEL_GFX (OMAP24XX_CM_BASE+0x340) +#define RM_RSTCTRL_GFX (OMAP24XX_CM_BASE+0x350) +#define CM_FCLKEN_WKUP (OMAP24XX_CM_BASE+0x400) +#define CM_ICLKEN_WKUP (OMAP24XX_CM_BASE+0x410) +#define PM_RSTCTRL_WKUP (OMAP24XX_CM_BASE+0x450) +#define CM_CLKEN_PLL (OMAP24XX_CM_BASE+0x500) +#define CM_IDLEST_CKGEN (OMAP24XX_CM_BASE+0x520) +#define CM_CLKSEL1_PLL (OMAP24XX_CM_BASE+0x540) +#define CM_CLKSEL2_PLL (OMAP24XX_CM_BASE+0x544) +#define CM_CLKSEL_DSP (OMAP24XX_CM_BASE+0x840) +#define CM_CLKSEL_MDM (OMAP24XX_CM_BASE+0xC40) + +/* SMX-APE */ +#define SMX_APE_BASE 0x68000000 +#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) +#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) + +/* IVA2 */ +#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) + +/* + * The 2430's chip selects are programmable. The mask ROM + * does configure CS0 to 0x08000000 before dispatch. So, if + * you want your code to live below that address, you have to + * be prepared to jump though hoops, to reset the base address. + */ +#if defined(CONFIG_OMAP243X) + +/* GPMC */ +/* This is being used by the macros in mem.h. PHYS_FLASH_1 is defined to H4_CS0_BASE */ +# define H4_CS1_BASE 0x09000000 /* flash (64 Meg aligned) */ +#define CFG_FLASH_BASE H4_CS1_BASE +#define DEBUG_BASE 0x08000000 + +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) + +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +#define PERIFERAL_PORT_BASE 0x480FE003 + +#endif /* endif CONFIG_2430SDP */ + +#endif + diff --git a/include/asm/arch-arm1136/sizes.h b/include/asm/arch-arm1136/sizes.h new file mode 100644 index 0000000..3dddd8e --- /dev/null +++ b/include/asm/arch-arm1136/sizes.h @@ -0,0 +1,50 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_31M 0x01F00000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __sizes_h */ + diff --git a/include/asm/arch-arm1136/sys_info.h b/include/asm/arch-arm1136/sys_info.h new file mode 100644 index 0000000..94a09cd --- /dev/null +++ b/include/asm/arch-arm1136/sys_info.h @@ -0,0 +1,139 @@ +/* + * Copyright 2005 (C) Texas Instruments, + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP24XX_SYS_INFO_H_ +#define _OMAP24XX_SYS_INFO_H_ + +#if 0 +typedef struct h4_system_data { + /* base board info */ + u32 base_b_rev; /* rev from base board i2c */ + /* cpu board info */ + u32 cpu_b_rev; /* rev from cpu board i2c */ + u32 cpu_b_mux; /* mux type on daughter board */ + u32 cpu_b_ddr_type; /* mem type */ + u32 cpu_b_ddr_speed; /* ddr speed rating */ + u32 cpu_b_switches; /* boot ctrl switch settings */ + /* cpu info */ + u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ + u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ +} h4_sys_data; + +#endif + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_2420 0x2420 +#define CPU_2422 0x2422 /* 2420 + 64M stacked */ +#define CPU_2423 0x2423 /* 2420 + 96M stacked */ +#define CPU_2430 0x2430 + +/* 242x real hardware: + * ES1 = rev 0 + * ES2 = rev 1 + * ES2.05 = rev 2 + * ES2.1 = rev 3 + * ES2.1.1 = rev 4 + */ + +/* 242x code defines: + * ES1 = 0+1 = 1 + * ES2 = 1+1 = 2 + * ES2.05 = 2+1 = 3 + * ES2.1 = 3+1 = 4 + * Es2.1.1 = 4+1 = 5 + */ +#define CPU_2422_ES1 1 +#define CPU_2422_ES2 2 +#define CPU_2422_ES2_05 3 +#define CPU_2422_ES2_1 4 +#define CPU_2422_ES2_1_1 5 + +#define CPU_2420_ES1 1 +#define CPU_2420_ES2 2 +#define CPU_2420_ES2_05 3 +#define CPU_2420_ES2_1 4 +#define CPU_2420_ES2_1_1 5 + +#define CPU_242X_ES1 1 +#define CPU_242X_ES2 2 +#define CPU_242X_ES2_05 3 +#define CPU_242X_ES2_1 4 +#define CPU_242X_ES2_1_1 5 + +#define CPU_2420_2422_ES1 1 +#define CPU_2420_2422_ES2_1 4 + +/* 243x real hardware: + * ES1 = rev 0 + * ES2 = rev 1 + * + * 243x code defines: + * ES1 = 0+1 = 1 + * ES2 = 1+1 = 2 + */ +#define CPU_2430_ES1 1 +#define CPU_2430_ES2 2 + +#ifdef VPOM2430 +# define CPU_2430_VIRTIO 3 +#else +# define CPU_2430_VIRTIO 1 +#endif +#define CPU_2430_ZEBU 0xD + +#define CPU_2420_CHIPID 0x0B5D9000 +#define CPU_2430_CHIPID 0x0B68A000 +#define CPU_24XX_ID_MASK 0x0FFFF000 +#define CPU_242X_REV_MASK 0xF0000000 +#define CPU_242X_PID_MASK 0x000F0000 + +#define BOARD_H4_MENELAUS 1 +#define BOARD_H4_SDP 2 +#define BOARD_H4_MENELAUS_HRP 3 +#define BOARD_SDP_2430 4 + +#define GPMC_MUXED 1 +#define GPMC_NONMUXED 0 + +#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ +#define TYPE_NOR 0x000 +#define TYPE_ONENAND 0x800 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ + +#endif diff --git a/include/asm/arch-arm926ejs/sizes.h b/include/asm/arch-arm926ejs/sizes.h new file mode 100644 index 0000000..ef0b99b --- /dev/null +++ b/include/asm/arch-arm926ejs/sizes.h @@ -0,0 +1,51 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307 + * USA + */ +/* DO NOT EDIT!! - this file automatically generated + * from .s file by awk -f s2h.awk + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __sizes_h */ diff --git a/include/asm/arch-omap3/bits.h b/include/asm/arch-omap3/bits.h new file mode 100644 index 0000000..8522335 --- /dev/null +++ b/include/asm/arch-omap3/bits.h @@ -0,0 +1,48 @@ +/* bits.h + * Copyright (c) 2004 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef __bits_h +#define __bits_h 1 + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif diff --git a/include/asm/arch-omap3/clocks.h b/include/asm/arch-omap3/clocks.h new file mode 100644 index 0000000..4f93a96 --- /dev/null +++ b/include/asm/arch-omap3/clocks.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP34XX_CLOCKS_H_ +#define _OMAP34XX_CLOCKS_H_ + +#define LDELAY 12000000 + +#define S12M 12000000 +#define S13M 13000000 +#define S19_2M 19200000 +#define S24M 24000000 +#define S26M 26000000 +#define S38_4M 38400000 + +#define FCK_IVA2_ON 0x00000001 +#define FCK_CORE1_ON 0x03fffe29 +#define ICK_CORE1_ON 0x3ffffffb +#define ICK_CORE2_ON 0x0000001f +#define FCK_WKUP_ON 0x000000e9 +#define ICK_WKUP_ON 0x0000003f +#define FCK_DSS_ON 0x00000005 +#define ICK_DSS_ON 0x00000001 +#define FCK_CAM_ON 0x00000001 +#define ICK_CAM_ON 0x00000001 +#define FCK_PER_ON 0x0003ffff +#define ICK_PER_ON 0x0003ffff + +#include + +#endif diff --git a/include/asm/arch-omap3/clocks343x.h b/include/asm/arch-omap3/clocks343x.h new file mode 100644 index 0000000..7aedaa1 --- /dev/null +++ b/include/asm/arch-omap3/clocks343x.h @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP343X_CLOCKS_H_ +#define _OMAP343X_CLOCKS_H_ + +#define PLL_STOP 1 /* PER & IVA */ +#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ +#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ +#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ + +/* The following configurations are OPP and SysClk value independant + * and hence are defined here. All the other DPLL related values are + * tabulated in lowlevel_init.S. + */ + +/* CORE DPLL */ +# define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ +# define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ +# define CORE_FUSB_DIV 2 /* 41.5MHz: */ +# define CORE_L4_DIV 2 /* 83MHz : L4 */ +# define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ +# define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ +# define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ + +/* PER DPLL */ +# define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ +# define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ +# define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */ +# define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ + +# define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) + +#ifdef PRCM_CLK_CFG2_332MHZ +# define M_12 0xA6 +# define N_12 0x05 +# define FSEL_12 0x07 +# define M2_12 0x01 /* M3 of 2 */ + +# define M_12_ES1 0x19F +# define N_12_ES1 0x0E +# define FSL_12_ES1 0x03 +# define M2_12_ES1 0x1 /* M3 of 2 */ + +# define M_13 0x14C +# define N_13 0x0C +# define FSEL_13 0x03 +# define M2_13 0x01 /* M3 of 2 */ + +# define M_13_ES1 0x1B2 +# define N_13_ES1 0x10 +# define FSL_13_ES1 0x03 +# define M2_13_ES1 0x01 /* M3 of 2 */ + +# define M_19p2 0x19F +# define N_19p2 0x17 +# define FSEL_19p2 0x03 +# define M2_19p2 0x01 /* M3 of 2 */ + +# define M_19p2_ES1 0x19F +# define N_19p2_ES1 0x17 +# define FSL_19p2_ES1 0x03 +# define M2_19p2_ES1 0x01 /* M3 of 2 */ + +# define M_26 0xA6 +# define N_26 0x0C +# define FSEL_26 0x07 +# define M2_26 0x01 /* M3 of 2 */ + +# define M_26_ES1 0x1B2 +# define N_26_ES1 0x21 +# define FSL_26_ES1 0x03 +# define M2_26_ES1 0x01 /* M3 of 2 */ + +# define M_38p4 0x19F +# define N_38p4 0x2F +# define FSEL_38p4 0x03 +# define M2_38p4 0x01 /* M3 of 2 */ + +# define M_38p4_ES1 0x19F +# define N_38p4_ES1 0x2F +# define FSL_38p4_ES1 0x03 +# define M2_38p4_ES1 0x01 /* M3 of 2 */ + +#elif defined(PRCM_CLK_CFG2_266MHZ) +# define M_12 0x85 +# define N_12 0x05 +# define FSEL_12 0x07 +# define M2_12 0x02 /* M3 of 2 */ + +# define M_12_ES1 0x85 /* 0x10A */ +# define N_12_ES1 0x05 /* 0x05 */ +# define FSL_12_ES1 0x07 /* 0x7 */ +# define M2_12_ES1 0x2 /* 0x2 with an M3 of 4*/ + +# define M_13 0x10A +# define N_13 0x0C +# define FSEL_13 0x3 +# define M2_13 0x1 /* M3 of 2 */ + +# define M_13_ES1 0x10A /* 0x214 */ +# define N_13_ES1 0x0C /* 0xC */ +# define FSL_13_ES1 0x3 /* 0x3 */ +# define M2_13_ES1 0x1 /* 0x2 with an M3 of 4*/ + +# define M_19p2 0x115 +# define N_19p2 0x13 +# define FSEL_19p2 0x03 +# define M2_19p2 0x01 /* M3 of 2 */ + +# define M_19p2_ES1 0x115 /* 0x299 */ +# define N_19p2_ES1 0x13 /* 0x17 */ +# define FSL_19p2_ES1 0x03 /* 0x03 */ +# define M2_19p2_ES1 0x01 /* 0x2 with M3 of 4 */ + +# define M_26 0x85 +# define N_26 0x0C +# define FSEL_26 0x07 +# define M2_26 0x01 /* M3 of 2 */ + +# define M_26_ES1 0x85 /* 0x10A */ +# define N_26_ES1 0x0C /* 0xC */ +# define FSL_26_ES1 0x07 /* 0x7 */ +# define M2_26_ES1 0x01 /* 0x2 with an M3 of 4 */ + +# define M_38p4 0x11C +# define N_38p4 0x28 +# define FSEL_38p4 0x03 +# define M2_38p4 0x01 /* M3 of 2 */ + +# define M_38p4_ES1 0x11C /* 0x299 */ +# define N_38p4_ES1 0x28 /* 0x2f */ +# define FSL_38p4_ES1 0x03 /* 0x3 */ +# define M2_38p4_ES1 0x01 /* 0x2 with an M3 of 4*/ + + # endif + +#endif /* endif _OMAP343X_CLOCKS_H_ */ diff --git a/include/asm/arch-omap3/cpu.h b/include/asm/arch-omap3/cpu.h new file mode 100644 index 0000000..0828e73 --- /dev/null +++ b/include/asm/arch-omap3/cpu.h @@ -0,0 +1,257 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _OMAP34XX_CPU_H +#define _OMAP34XX_CPU_H +#include + +/* Register offsets of common modules */ +/* Control */ +#define CONTROL_STATUS (OMAP34XX_CTRL_BASE + 0x2F0) +#define OMAP34XX_MCR (OMAP34XX_CTRL_BASE + 0x8C) +#define CONTROL_SCALABLE_OMAP_STATUS (OMAP34XX_CTRL_BASE + 0x44C) +#define CONTROL_SCALABLE_OMAP_OCP (OMAP34XX_CTRL_BASE + 0x534) + + +/* Tap Information */ +#define TAP_IDCODE_REG (OMAP34XX_TAP_BASE+0x204) +#define PRODUCTION_ID (OMAP34XX_TAP_BASE+0x208) + +/* device type */ +#define DEVICE_MASK (BIT8|BIT9|BIT10) +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* We are not concerned with BIT5 as it only determines + * the prirotiy between memory or perpheral booting + */ +#define SYSBOOT_MASK (BIT0|BIT1|BIT2|BIT3|BIT4) + +/* GPMC CS3/cs4/cs6 not avaliable */ +#define GPMC_BASE (OMAP34XX_GPMC_BASE) +#define GPMC_SYSCONFIG (OMAP34XX_GPMC_BASE+0x10) +#define GPMC_IRQSTATUS (OMAP34XX_GPMC_BASE+0x18) +#define GPMC_IRQENABLE (OMAP34XX_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP34XX_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) +#define GPMC_STATUS (OMAP34XX_GPMC_BASE+0x54) + +#define GPMC_CONFIG_CS0 (OMAP34XX_GPMC_BASE+0x60) +#define GPMC_CONFIG_WIDTH (0x30) + +#define GPMC_CONFIG1 (0x00) +#define GPMC_CONFIG2 (0x04) +#define GPMC_CONFIG3 (0x08) +#define GPMC_CONFIG4 (0x0C) +#define GPMC_CONFIG5 (0x10) +#define GPMC_CONFIG6 (0x14) +#define GPMC_CONFIG7 (0x18) +#define GPMC_NAND_CMD (0x1C) +#define GPMC_NAND_ADR (0x20) +#define GPMC_NAND_DAT (0x24) + +#define GPMC_ECC_CONFIG (0x1F4) +#define GPMC_ECC_CONTROL (0x1F8) +#define GPMC_ECC_SIZE_CONFIG (0x1FC) +#define GPMC_ECC1_RESULT (0x200) +#define GPMC_ECC2_RESULT (0x204) +#define GPMC_ECC3_RESULT (0x208) +#define GPMC_ECC4_RESULT (0x20C) +#define GPMC_ECC5_RESULT (0x210) +#define GPMC_ECC6_RESULT (0x214) +#define GPMC_ECC7_RESULT (0x218) +#define GPMC_ECC8_RESULT (0x21C) +#define GPMC_ECC9_RESULT (0x220) + + +/* GPMC Mapping */ +# define FLASH_BASE 0x10000000 /* NOR flash (aligned to 256 Meg) */ +# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (aligned to 64 Meg) */ +# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (aligned to 256 Meg) */ +# define DEBUG_BASE 0x08000000 /* debug board */ +# define NAND_BASE 0x30000000 /* NAND addr (actual size small port)*/ +# define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ +# define ONENAND_MAP 0x20000000 /* OneNand addr (actual size small port */ + +/* SMS */ +#define SMS_SYSCONFIG (OMAP34XX_SMS_BASE+0x10) +#define SMS_RG_ATT0 (OMAP34XX_SMS_BASE+0x48) +#define SMS_CLASS_ARB0 (OMAP34XX_SMS_BASE+0xD0) +#define BURSTCOMPLETE_GROUP7 BIT31 + +/* SDRC */ +#define SDRC_SYSCONFIG (OMAP34XX_SDRC_BASE+0x10) +#define SDRC_STATUS (OMAP34XX_SDRC_BASE+0x14) +#define SDRC_CS_CFG (OMAP34XX_SDRC_BASE+0x40) +#define SDRC_SHARING (OMAP34XX_SDRC_BASE+0x44) +#define SDRC_DLLA_CTRL (OMAP34XX_SDRC_BASE+0x60) +#define SDRC_DLLA_STATUS (OMAP34XX_SDRC_BASE+0x64) +#define SDRC_DLLB_CTRL (OMAP34XX_SDRC_BASE+0x68) +#define SDRC_DLLB_STATUS (OMAP34XX_SDRC_BASE+0x6C) +#define DLLPHASE BIT1 +#define LOADDLL BIT2 +#define DLL_DELAY_MASK 0xFF00 +#define DLL_NO_FILTER_MASK (BIT8|BIT9) + +#define SDRC_POWER (OMAP34XX_SDRC_BASE+0x70) +#define WAKEUPPROC BIT26 + +#define SDRC_MCFG_0 (OMAP34XX_SDRC_BASE+0x80) +#define SDRC_MCFG_1 (OMAP34XX_SDRC_BASE+0xB0) +#define SDRC_MR_0 (OMAP34XX_SDRC_BASE+0x84) +#define SDRC_MR_1 (OMAP34XX_SDRC_BASE+0xB4) +#define SDRC_ACTIM_CTRLA_0 (OMAP34XX_SDRC_BASE+0x9C) +#define SDRC_ACTIM_CTRLB_0 (OMAP34XX_SDRC_BASE+0xA0) +#define SDRC_ACTIM_CTRLA_1 (OMAP34XX_SDRC_BASE+0xC4) +#define SDRC_ACTIM_CTRLB_1 (OMAP34XX_SDRC_BASE+0xC8) +#define SDRC_RFR_CTRL_0 (OMAP34XX_SDRC_BASE+0xA4) +#define SDRC_RFR_CTRL_1 (OMAP34XX_SDRC_BASE+0xD4) +#define SDRC_MANUAL_0 (OMAP34XX_SDRC_BASE+0xA8) +#define SDRC_MANUAL_1 (OMAP34XX_SDRC_BASE+0xD8) +#define OMAP34XX_SDRC_CS0 0x80000000 +#define OMAP34XX_SDRC_CS1 0xA0000000 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET BIT1 +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + +/* timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ +#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ + +/* Watchdog */ +#define WWPS 0x34 /* r */ +#define WSPR 0x48 /* rw */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define CM_FCLKEN_IVA2 0x48004000 +#define CM_CLKEN_PLL_IVA2 0x48004004 +#define CM_IDLEST_PLL_IVA2 0x48004024 +#define CM_CLKSEL1_PLL_IVA2 0x48004040 +#define CM_CLKSEL2_PLL_IVA2 0x48004044 +#define CM_CLKEN_PLL_MPU 0x48004904 +#define CM_IDLEST_PLL_MPU 0x48004924 +#define CM_CLKSEL1_PLL_MPU 0x48004940 +#define CM_CLKSEL2_PLL_MPU 0x48004944 +#define CM_FCLKEN1_CORE 0x48004a00 +#define CM_ICLKEN1_CORE 0x48004a10 +#define CM_ICLKEN2_CORE 0x48004a14 +#define CM_CLKSEL_CORE 0x48004a40 +#define CM_FCLKEN_GFX 0x48004b00 +#define CM_ICLKEN_GFX 0x48004b10 +#define CM_CLKSEL_GFX 0x48004b40 +#define CM_FCLKEN_WKUP 0x48004c00 +#define CM_ICLKEN_WKUP 0x48004c10 +#define CM_CLKSEL_WKUP 0x48004c40 +#define CM_IDLEST_WKUP 0x48004c20 +#define CM_CLKEN_PLL 0x48004d00 +#define CM_IDLEST_CKGEN 0x48004d20 +#define CM_CLKSEL1_PLL 0x48004d40 +#define CM_CLKSEL2_PLL 0x48004d44 +#define CM_CLKSEL3_PLL 0x48004d48 +#define CM_FCLKEN_DSS 0x48004e00 +#define CM_ICLKEN_DSS 0x48004e10 +#define CM_CLKSEL_DSS 0x48004e40 +#define CM_FCLKEN_CAM 0x48004f00 +#define CM_ICLKEN_CAM 0x48004f10 +#define CM_CLKSEL_CAM 0x48004F40 +#define CM_FCLKEN_PER 0x48005000 +#define CM_ICLKEN_PER 0x48005010 +#define CM_CLKSEL_PER 0x48005040 +#define CM_CLKSEL1_EMU 0x48005140 + +#define PRM_CLKSEL 0x48306d40 +#define PRM_RSTCTRL 0x48307250 +#define PRM_CLKSRC_CTRL 0x48307270 + +#define SYSCLKDIV_2 (0x1 << 7) + +/* SMX-APE */ +#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) +#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) +#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) + +#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) +#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) +#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) +#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) + +#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) +#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) +#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) + +#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) +#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) +#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) +#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) + +#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) +#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) +#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) + +#define IVA2_REQ_INFO_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x68) +#define IVA2_READ_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x70) +#define IVA2_WRITE_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x78) + +#define IVA2_REQ_INFO_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x88) +#define IVA2_READ_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x90) +#define IVA2_WRITE_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x98) + +#define IVA2_REQ_INFO_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xA8) +#define IVA2_READ_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB0) +#define IVA2_WRITE_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB8) + +/* I2C base */ +#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) +#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) +#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) + +#endif diff --git a/include/asm/arch-omap3/gpio.h b/include/asm/arch-omap3/gpio.h new file mode 100644 index 0000000..30f633c --- /dev/null +++ b/include/asm/arch-omap3/gpio.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _GPIO_H +#define _GPIO_H + +#define OMAP24XX_GPIO_REVISION 0x0000 +#define OMAP24XX_GPIO_SYSCONFIG 0x0010 +#define OMAP24XX_GPIO_SYSSTATUS 0x0014 +#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 +#define OMAP24XX_GPIO_IRQSTATUS2 0x0028 +#define OMAP24XX_GPIO_IRQENABLE2 0x002c +#define OMAP24XX_GPIO_IRQENABLE1 0x001c +#define OMAP24XX_GPIO_WAKE_EN 0x0020 +#define OMAP24XX_GPIO_CTRL 0x0030 +#define OMAP24XX_GPIO_OE 0x0034 +#define OMAP24XX_GPIO_DATAIN 0x0038 +#define OMAP24XX_GPIO_DATAOUT 0x003c +#define OMAP24XX_GPIO_LEVELDETECT0 0x0040 +#define OMAP24XX_GPIO_LEVELDETECT1 0x0044 +#define OMAP24XX_GPIO_RISINGDETECT 0x0048 +#define OMAP24XX_GPIO_FALLINGDETECT 0x004c +#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 +#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 +#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 +#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 +#define OMAP24XX_GPIO_CLEARWKUENA 0x0080 +#define OMAP24XX_GPIO_SETWKUENA 0x0084 +#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 +#define OMAP24XX_GPIO_SETDATAOUT 0x0094 + +struct gpio_bank { + void *base; + int method; +}; + +#define METHOD_GPIO_24XX 4 + +/* This is the interface */ + +/* Request a gpio before using it */ +int omap_request_gpio(int gpio); +/* Reset and free a gpio after using it */ +void omap_free_gpio(int gpio); +/* Sets the gpio as input or output */ +void omap_set_gpio_direction(int gpio, int is_input); +/* Set or clear a gpio output */ +void omap_set_gpio_dataout(int gpio, int enable); +/* Get the value of a gpio input */ +int omap_get_gpio_datain(int gpio); + +#endif /* _GPIO_H_ */ diff --git a/include/asm/arch-omap3/i2c.h b/include/asm/arch-omap3/i2c.h new file mode 100644 index 0000000..28ae5ca --- /dev/null +++ b/include/asm/arch-omap3/i2c.h @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _I2C_H_ +#define _I2C_H_ + +#define I2C_DEFAULT_BASE I2C_BASE1 + +#define I2C_REV (I2C_DEFAULT_BASE + 0x00) +#define I2C_IE (I2C_DEFAULT_BASE + 0x04) +#define I2C_STAT (I2C_DEFAULT_BASE + 0x08) +#define I2C_IV (I2C_DEFAULT_BASE + 0x0c) +#define I2C_BUF (I2C_DEFAULT_BASE + 0x14) +#define I2C_CNT (I2C_DEFAULT_BASE + 0x18) +#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c) +#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20) +#define I2C_CON (I2C_DEFAULT_BASE + 0x24) +#define I2C_OA (I2C_DEFAULT_BASE + 0x28) +#define I2C_SA (I2C_DEFAULT_BASE + 0x2c) +#define I2C_PSC (I2C_DEFAULT_BASE + 0x30) +#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34) +#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38) +#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c) + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_GC_IE (1 << 5) +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_SBD (1 << 15) /* Single byte data */ +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_GC (1 << 5) +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ + +/* I2C Buffer Configuration Register (I2C_BUF): */ + +#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ +#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 15) /* I2C module enable */ +#define I2C_CON_BE (1 << 14) /* Big endian mode */ +#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ + /* (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ + +/* I2C System Test Register (I2C_SYSTEST): */ + +#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ +#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ +#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ +#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ +#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ +#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ +#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ +#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ + +#define I2C_SCLL_SCLL (0) +#define I2C_SCLL_SCLL_M (0xFF) +#define I2C_SCLL_HSSCLL (8) +#define I2C_SCLH_HSSCLL_M (0xFF) +#define I2C_SCLH_SCLH (0) +#define I2C_SCLH_SCLH_M (0xFF) +#define I2C_SCLH_HSSCLH (8) +#define I2C_SCLH_HSSCLH_M (0xFF) + +#define OMAP_I2C_STANDARD 100 +#define OMAP_I2C_FAST_MODE 400 +#define OMAP_I2C_HIGH_SPEED 3400 + +#define SYSTEM_CLOCK_12 12000 +#define SYSTEM_CLOCK_13 13000 +#define SYSTEM_CLOCK_192 19200 +#define SYSTEM_CLOCK_96 96000 + +#define I2C_IP_CLK SYSTEM_CLOCK_96 +#define I2C_PSC_MAX (0x0f) +#define I2C_PSC_MIN (0x00) + +#endif /* _I2C_H_ */ diff --git a/include/asm/arch-omap3/mem.h b/include/asm/arch-omap3/mem.h new file mode 100644 index 0000000..284c665 --- /dev/null +++ b/include/asm/arch-omap3/mem.h @@ -0,0 +1,589 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP34XX_MEM_H_ +#define _OMAP34XX_MEM_H_ + +#define SDRC_CS0_OSET 0x0 +#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ + +#ifndef __ASSEMBLY__ + +typedef enum { + STACKED = 0, + IP_DDR = 1, + COMBO_DDR = 2, + IP_SDR = 3, +} mem_t; + + +/* Memory that can be connected to GPMC */ +#define GPMC_NOR 0 +#define GPMC_NAND 1 +#define GPMC_MDOC 2 +#define GPMC_ONENAND 3 +#define MMC_NAND 4 +#define MMC_ONENAND 5 +#define GPMC_NONE 6 +#define GPMC_ONENAND_TRY 7 + +#endif + +/* set the 343x-SDRC incoming address convention */ +#if defined(SDRC_B_R_C) +#define B_ALL (0 << 6) /* bank-row-column */ +#elif defined(SDRC_B1_R_B0_C) +#define B_ALL (1 << 6) /* bank1-row-bank0-column */ +#elif defined(SDRC_R_B_C) +#define B_ALL (2 << 6) /* row-bank-column */ +#endif + +/* Future memory combinations based on past */ +#define SDP_SDRC_MDCFG_MONO_DDR 0x0 +#define SDP_COMBO_MDCFG_0_DDR 0x0 +#define SDP_SDRC_MDCFG_0_SDR 0x0 + +/* Slower full frequency range default timings for x32 operation*/ +#define SDP_SDRC_SHARING 0x00000100 +#define SDP_SDRC_MR_0_SDR 0x00000031 + +#ifdef CONFIG_3430ZEBU +#define SDP_SDRC_MDCFG_0_DDR (0x02582019|B_ALL) /* Infin ddr module */ +#else +#define SDP_SDRC_MDCFG_0_DDR (0x02584019|B_ALL) +#define SDP_SDRC_MDCFG_0_DDR_MICRON_XM (0x03588019|B_ALL) +#define SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM (0x04590019|B_ALL) +#define SDP_SDRC_MDCFG_0_DDR_HYNIX (0x03588019|B_ALL) +#endif + +#define SDP_SDRC_MR_0_DDR 0x00000032 + +/* Diabling power down mode using CKE pin */ +#define SDP_SDRC_POWER_POP 0x00000081 + +/* optimized timings good for current shipping parts */ +#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ +#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ + +#define DLL_OFFSET 0 +#define DLL_WRITEDDRCLKX2DIS 1 +#define DLL_ENADLL 1 +#define DLL_LOCKDLL 0 +#define DLL_DLLPHASE_72 0 +#define DLL_DLLPHASE_90 1 + +// rkw - need to find of 90/72 degree recommendation for speed like before. +#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ + (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) + +/* Infineon part of 3430SDP (133MHz optimized) ~ 7.5ns + * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 + * TDPL = 15/7.5 = 2 + * TRRD = 15/2.5 = 2 + * TRCD = 22.5/7.5 = 3 + * TRP = 22.5/7.5 = 3 + * TRAS = 45/7.5 = 6 + * TRC = 65/7.5 = 8.6->9 + * TRFC = 75/7.5 = 10 + * ACTIMB + * TCKE = 2 + * XSR = 120/7.5 = 16 + */ +#define INFINEON_TDAL_133 5 +#define INFINEON_TDPL_133 2 +#define INFINEON_TRRD_133 2 +#define INFINEON_TRCD_133 3 +#define INFINEON_TRP_133 3 +#define INFINEON_TRAS_133 6 +#define INFINEON_TRC_133 9 +#define INFINEON_TRFC_133 10 +#define INFINEON_V_ACTIMA_133 ((INFINEON_TRFC_133 << 27) | (INFINEON_TRC_133 << 22) | (INFINEON_TRAS_133 << 18) \ + |(INFINEON_TRP_133 << 15) | (INFINEON_TRCD_133 << 12) |(INFINEON_TRRD_133 << 9) |(INFINEON_TDPL_133 << 6) \ + | (INFINEON_TDAL_133)) + +#define INFINEON_TWTR_133 1 +#define INFINEON_TCKE_133 2 +#define INFINEON_TXP_133 2 +#define INFINEON_XSR_133 16 +#define INFINEON_V_ACTIMB_133 ((INFINEON_TCKE_133 << 12) | (INFINEON_XSR_133 << 0)) | \ + (INFINEON_TXP_133 << 8) | (INFINEON_TWTR_133 << 16) + +#define INFINEON_V_ACTIMA_100 INFINEON_V_ACTIMA_133 +#define INFINEON_V_ACTIMB_100 INFINEON_V_ACTIMB_133 + + +/* Infineon part of 3430SDP (165MHz optimized) 6.06ns + * ACTIMA + * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 + * TDPL (Twr) = 15/6 = 2.5 -> 3 + * TRRD = 12/6 = 2 + * TRCD = 18/6 = 3 + * TRP = 18/6 = 3 + * TRAS = 42/6 = 7 + * TRC = 60/6 = 10 + * TRFC = 72/6 = 12 + * ACTIMB + * TCKE = 2 + * XSR = 120/6 = 20 + */ +#define INFINEON_TDAL_165 6 +#define INFINEON_TDPL_165 3 +#define INFINEON_TRRD_165 2 +#define INFINEON_TRCD_165 3 +#define INFINEON_TRP_165 3 +#define INFINEON_TRAS_165 7 +#define INFINEON_TRC_165 10 +#define INFINEON_TRFC_165 12 +#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) \ + | (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) |(INFINEON_TRRD_165 << 9) | \ + (INFINEON_TDPL_165 << 6) | (INFINEON_TDAL_165)) + +#define INFINEON_TWTR_165 1 +#define INFINEON_TCKE_165 2 +#define INFINEON_TXP_165 2 +#define INFINEON_XSR_165 20 +#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | (INFINEON_XSR_165 << 0)) | \ + (INFINEON_TXP_165 << 8) | (INFINEON_TWTR_165 << 16) + +/* Micron part of 3430 EVM (133MHz optimized) ~ 7.5ns + * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 + * TDPL = 15/7.5 = 2 + * TRRD = 15/7.5 = 2 + * TRCD = 22.5/7.5 = 3 + * TRP = 22.5/7.5 = 3 + * TRAS = 45/7.5 = 6 + * TRC = 75/7.5 = 10 + * TRFC = 125/7.5 = 16.6->17 + * ACTIMB + * TWTR = 1 + * TCKE = 1 + * TXSR = 138/7.5 = 18.3->19 + * TXP = 25/7.5 = 3.3->4 + */ +#define MICRON_TDAL_133 5 +#define MICRON_TDPL_133 2 +#define MICRON_TRRD_133 2 +#define MICRON_TRCD_133 3 +#define MICRON_TRP_133 3 +#define MICRON_TRAS_133 6 +#define MICRON_TRC_133 10 +#define MICRON_TRFC_133 17 +#define MICRON_V_ACTIMA_133 ((MICRON_TRFC_133 << 27) | (MICRON_TRC_133 << 22) | (MICRON_TRAS_133 << 18) \ + |(MICRON_TRP_133 << 15) | (MICRON_TRCD_133 << 12) |(MICRON_TRRD_133 << 9) |(MICRON_TDPL_133 << 6) \ + | (MICRON_TDAL_133)) + +#define MICRON_TWTR_133 1 +#define MICRON_TCKE_133 1 +#define MICRON_TXSR_133 19 +#define MICRON_TXP_133 4 +#define MICRON_V_ACTIMB_133 ((MICRON_TWTR_133 << 16) | (MICRON_TCKE_133 << 12) | (MICRON_TXP_133 << 8) \ + | (MICRON_TXSR_133 << 0)) + +#define MICRON_V_ACTIMA_100 MICRON_V_ACTIMA_133 +#define MICRON_V_ACTIMB_100 MICRON_V_ACTIMB_133 + +/* Micron part of 3430 EVM (165MHz optimized) 6.06ns + * ACTIMA + * TDAL = Twr/Tck + Trp/tck = 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6 + * TDPL (Twr) = 15/6 = 2.5 -> 3 + * TRRD = 12/6 = 2 + * TRCD = 18/6 = 3 + * TRP = 18/6 = 3 + * TRAS = 42/6 = 7 + * TRC = 60/6 = 10 + * TRFC = 125/6 = 21 + * ACTIMB + * TWTR = 1 + * TCKE = 1 + * TXSR = 138/6 = 23 + * TXP = 25/6 = 4.1 ~5 + */ +#define MICRON_TDAL_165 6 +#define MICRON_TDPL_165 3 +#define MICRON_TRRD_165 2 +#define MICRON_TRCD_165 3 +#define MICRON_TRP_165 3 +#define MICRON_TRAS_165 7 +#define MICRON_TRC_165 10 +#define MICRON_TRFC_165 21 +#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) \ + | (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) |(MICRON_TRRD_165 << 9) | \ + (MICRON_TDPL_165 << 6) | (MICRON_TDAL_165)) + +#define MICRON_TWTR_165 1 +#define MICRON_TCKE_165 1 +#define MICRON_TXP_165 5 +#define MICRON_XSR_165 23 +#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | (MICRON_XSR_165 << 0)) | \ + (MICRON_TXP_165 << 8) | (MICRON_TWTR_165 << 16) + +/* Micron part (200MHz optimized) 5 ns + */ +#define MICRON_TDAL_200 6 +#define MICRON_TDPL_200 3 +#define MICRON_TRRD_200 2 +#define MICRON_TRCD_200 3 +#define MICRON_TRP_200 3 +#define MICRON_TRAS_200 8 +#define MICRON_TRC_200 11 +#define MICRON_TRFC_200 15 +#define MICRON_V_ACTIMA_200 ((MICRON_TRFC_200 << 27) | (MICRON_TRC_200 << 22) | (MICRON_TRAS_200 << 18) \ + | (MICRON_TRP_200 << 15) | (MICRON_TRCD_200 << 12) |(MICRON_TRRD_200 << 9) | \ + (MICRON_TDPL_200 << 6) | (MICRON_TDAL_200)) + +#define MICRON_TWTR_200 2 +#define MICRON_TCKE_200 4 +#define MICRON_TXP_200 2 +#define MICRON_XSR_200 23 +#define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | (MICRON_XSR_200 << 0)) | \ + (MICRON_TXP_200 << 8) | (MICRON_TWTR_200 << 16) + +/* NUMONYX part of IGEP0020 (165MHz optimized) 6.06ns + * ACTIMA + * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 + * TDPL (Twr) = 15/6 = 2.5 -> 3 + * TRRD = 12/6 = 2 + * TRCD = 22.5/6 = 3.75 -> 4 + * TRP = 18/6 = 3 + * TRAS = 42/6 = 7 + * TRC = 60/6 = 10 + * TRFC = 140/6 = 23.3 -> 24 + * ACTIMB + * TWTR = 2 + * TCKE = 2 + * TXSR = 200/6 = 33.3 -> 34 + * TXP = 1.0 + 1.1 = 2.1 -> 3 ¿? + */ +#define NUMONYX_TDAL_165 6 +#define NUMONYX_TDPL_165 3 +#define NUMONYX_TRRD_165 2 +#define NUMONYX_TRCD_165 4 +#define NUMONYX_TRP_165 3 +#define NUMONYX_TRAS_165 7 +#define NUMONYX_TRC_165 10 +#define NUMONYX_TRFC_165 24 +#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) \ + | (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) |(NUMONYX_TRRD_165 << 9) | \ + (NUMONYX_TDPL_165 << 6) | (NUMONYX_TDAL_165)) + +#define NUMONYX_TWTR_165 2 +#define NUMONYX_TCKE_165 2 +#define NUMONYX_TXP_165 3 +#define NUMONYX_XSR_165 34 +#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | (NUMONYX_XSR_165 << 0)) | \ + (NUMONYX_TXP_165 << 8) | (NUMONYX_TWTR_165 << 16) + +/* + * Hynix part of Overo (165MHz optimized) 6.06ns + * ACTIMA + * ACTIMA + * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 + * TDPL (Twr) = 15/6 = 2.5 -> 3 + * TRRD = 12/6 = 2 + * TRCD = 18/6 = 3 + * TRP = 18/6 = 3 + * TRAS = 42/6 = 7 + * TRC = 60/6 = 10 + * TRFC = 97.5/6 = 17 + * ACTIMB + * TWTR = 1 + * TCKE = 1 + * TXP = 1+1 + * XSR = 140/6 = 24 + */ +#define HYNIX_TDAL_165 6 +#define HYNIX_TDPL_165 3 +#define HYNIX_TRRD_165 2 +#define HYNIX_TRCD_165 3 +#define HYNIX_TRP_165 3 +#define HYNIX_TRAS_165 7 +#define HYNIX_TRC_165 10 +#define HYNIX_TRFC_165 21 +#define HYNIX_V_ACTIMA_165 ((HYNIX_TRFC_165 << 27) | \ + (HYNIX_TRC_165 << 22) | (HYNIX_TRAS_165 << 18) | \ + (HYNIX_TRP_165 << 15) | (HYNIX_TRCD_165 << 12) | \ + (HYNIX_TRRD_165 << 9) | (HYNIX_TDPL_165 << 6) | \ + (HYNIX_TDAL_165)) + +#define HYNIX_TWTR_165 1 +#define HYNIX_TCKE_165 1 +#define HYNIX_TXP_165 2 +#define HYNIX_XSR_165 24 +#define HYNIX_V_ACTIMB_165 ((HYNIX_TCKE_165 << 12) | \ + (HYNIX_XSR_165 << 0) | (HYNIX_TXP_165 << 8) | \ + (HYNIX_TWTR_165 << 16)) + +/* New and compatability speed defines */ +#if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) +# define L3_100MHZ /* Use with <= 100MHz SDRAM */ +#elif defined (PRCM_CLK_CFG2_266MHZ) || defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) +# define L3_133MHZ /* Use with <= 133MHz SDRAM*/ +#elif defined(PRCM_CLK_CFG2_332MHZ) || defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) +# define L3_165MHZ /* Use with <= 165MHz SDRAM (L3=166 on 3430) */ +#endif + +#if defined(L3_100MHZ) +# define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_100 +# define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_100 +#elif defined(L3_133MHZ) +# define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_133 +# define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_133 +#elif defined(L3_165MHZ) +# define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_165 +# define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_165 +# define NUMONYX_SDRC_ACTIM_CTRLA_0 NUMONYX_V_ACTIMA_165 +# define NUMONYX_SDRC_ACTIM_CTRLB_0 NUMONYX_V_ACTIMB_165 +#endif + + +#if defined(L3_100MHZ) +# define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_100 +# define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_100 +#elif defined(L3_133MHZ) +# define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_133 +# define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_133 +#elif defined(L3_165MHZ) +# define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_165 +# define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_165 +#endif + +#if defined(L3_100MHZ) +# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_100MHz +#elif defined(L3_133MHZ) +# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_133MHz +#elif defined(L3_165MHZ) +# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz +#endif + +/* + * GPMC settings - + * Definitions is as per the following format + * # define _GPMC_CONFIG + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * STNOR - Intel Strata Flash + * SMNAND - Samsung NAND + * M_NAND - Micron Large page x16 NAND + * MPDB - H4 MPDB board + * SBNOR - Sibley NOR + * ONNAND - Samsung One NAND + * + * include/configs/file.h contains the defn - for all CS we are interested + * #define OMAP34XX_GPMC_CSx PART + * #define OMAP34XX_GPMC_CSx_SIZE Size + * #define OMAP34XX_GPMC_CSx_MAP Map + * Where: + * x - CS number + * PART - Part Name as defined above + * SIZE - how big is the mapping to be + * GPMC_SIZE_128M - 0x8 + * GPMC_SIZE_64M - 0xC + * GPMC_SIZE_32M - 0xE + * GPMC_SIZE_16M - 0xF + * MAP - Map this CS to which address(GPMC address space)- Absolute address + * >>24 before being used. + */ +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#if defined(L3_100MHZ) +# define SMNAND_GPMC_CONFIG1 0x0 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x00000A80 + +# define M_NAND_GPMC_CONFIG1 0x00001800 +# define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2 +# define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3 +# define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4 +# define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5 +# define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6 +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x000f0f01 +# define STNOR_GPMC_CONFIG3 0x00050502 +# define STNOR_GPMC_CONFIG4 0x0C060C06 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x0 /* 0? */ +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001F1F00 +# define MPDB_GPMC_CONFIG3 0x00080802 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x031A1F1F +# define MPDB_GPMC_CONFIG6 0x000003C2 +#endif + +#if defined(L3_133MHZ) +# define SMNAND_GPMC_CONFIG1 0x00000800 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x00000A80 +# define SMNAND_GPMC_CONFIG7 0x00000C44 + +# define M_NAND_GPMC_CONFIG1 0x00001800 +# define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2 +# define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3 +# define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4 +# define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5 +# define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6 +# define M_NAND_GPMC_CONFIG7 SMNAND_GPMC_CONFIG7 + +# define STNOR_GPMC_CONFIG1 0x1203 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x10081008 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x000004c4 + +# define SIBNOR_GPMC_CONFIG1 0x1200 +# define SIBNOR_GPMC_CONFIG2 0x001f1f00 +# define SIBNOR_GPMC_CONFIG3 0x00080802 +# define SIBNOR_GPMC_CONFIG4 0x1C091C09 +# define SIBNOR_GPMC_CONFIG5 0x01131F1F +# define SIBNOR_GPMC_CONFIG6 0x000003C2 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x000004C4 + +# define P2_GPMC_CONFIG1 0x0 +# define P2_GPMC_CONFIG2 0x0 +# define P2_GPMC_CONFIG3 0x0 +# define P2_GPMC_CONFIG4 0x0 +# define P2_GPMC_CONFIG5 0x0 +# define P2_GPMC_CONFIG6 0x0 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000c0c01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0c040c04 +# define ONENAND_GPMC_CONFIG5 0x010C1010 +# define ONENAND_GPMC_CONFIG6 0x00000000 + +#endif /* endif L3_133MHZ */ + +#if defined (L3_165MHZ) +# define SMNAND_GPMC_CONFIG1 0x00000800 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x1F0F0A80 +# define SMNAND_GPMC_CONFIG7 0x00000C44 + +# define M_NAND_GPMC_CONFIG1 0x00001800 +# define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2 +# define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3 +# define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4 +# define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5 +# define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6 +# define M_NAND_GPMC_CONFIG7 SMNAND_GPMC_CONFIG7 + +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x11091109 +# define STNOR_GPMC_CONFIG5 0x01141F1F +# define STNOR_GPMC_CONFIG6 0x000004c4 + +# define SIBNOR_GPMC_CONFIG1 0x1200 +# define SIBNOR_GPMC_CONFIG2 0x001f1f00 +# define SIBNOR_GPMC_CONFIG3 0x00080802 +# define SIBNOR_GPMC_CONFIG4 0x1C091C09 +# define SIBNOR_GPMC_CONFIG5 0x01131F1F +# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 + +# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 +# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 +# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 +# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 +# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F +# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1c0b1c0a +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x1F0F04C4 + +# define P2_GPMC_CONFIG1 0x0 +# define P2_GPMC_CONFIG2 0x0 +# define P2_GPMC_CONFIG3 0x0 +# define P2_GPMC_CONFIG4 0x0 +# define P2_GPMC_CONFIG5 0x0 +# define P2_GPMC_CONFIG6 0x0 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000F0F01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0F040F04 +# define ONENAND_GPMC_CONFIG5 0x010F1010 +# define ONENAND_GPMC_CONFIG6 0x1F060000 + +#endif + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#define PISMO1_NOR 1 +#define PISMO1_NAND 2 +#define PISMO2_CS0 3 +#define PISMO2_CS1 4 +#define PISMO1_ONENAND 5 +#define POP_ONENAND 5 +#define DBG_MPDB 6 +#define PISMO2_NAND_CS0 7 +#define PISMO2_NAND_CS1 8 + +/* make it readable for the gpmc_init */ +#define PISMO1_NOR_BASE FLASH_BASE +#define PISMO1_NAND_BASE NAND_BASE +#define PISMO2_CS0_BASE PISMO2_MAP1 +#define PISMO1_ONEN_BASE ONENAND_MAP +#define POP_ONEN_BASE ONENAND_MAP +#define DBG_MPDB_BASE DEBUG_BASE + +#endif /* endif _OMAP34XX_MEM_H_ */ diff --git a/include/asm/arch-omap3/mmc.h b/include/asm/arch-omap3/mmc.h new file mode 100644 index 0000000..8631aae --- /dev/null +++ b/include/asm/arch-omap3/mmc.h @@ -0,0 +1,235 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_H +#define MMC_H + +#include "mmc_host_def.h" + +/* Responses */ +#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK) +#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) + +/* All supported commands */ +#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD7_DESELECT (INDEX(7) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE) +#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) +#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) + +#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16) +#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16) +#define MMC_DSR_DEFAULT (0x0404) +#define SD_CMD8_CHECK_PATTERN (0xAA) +#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8) + +/* Clock Configurations and Macros */ + +#define MMC_CLOCK_REFERENCE (96) +#define MMC_RELATIVE_CARD_ADDRESS (0x1234) +#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80) +#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400) +#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1) +#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u)) + +#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29) +#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29) +#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29) + +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30) +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30) +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30) + +#define MMC_SD2_CSD_C_SIZE_LSB_MASK (0xFFFF) +#define MMC_SD2_CSD_C_SIZE_MSB_MASK (0x003F) +#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET (16) +#define MMC_CSD_C_SIZE_LSB_MASK (0x0003) +#define MMC_CSD_C_SIZE_MSB_MASK (0x03FF) +#define MMC_CSD_C_SIZE_MSB_OFFSET (2) + +#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0) +#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3) +#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0) +#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3) +#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3) + +typedef struct { + unsigned not_used:1; + unsigned crc:7; + unsigned ecc:2; + unsigned file_format:2; + unsigned tmp_write_protect:1; + unsigned perm_write_protect:1; + unsigned copy:1; + unsigned file_format_grp:1; + unsigned content_prot_app:1; + unsigned reserved_1:4; + unsigned write_bl_partial:1; + unsigned write_bl_len:4; + unsigned r2w_factor:3; + unsigned default_ecc:2; + unsigned wp_grp_enable:1; + unsigned wp_grp_size:5; + unsigned erase_grp_mult:5; + unsigned erase_grp_size:5; + unsigned c_size_mult:3; + unsigned vdd_w_curr_max:3; + unsigned vdd_w_curr_min:3; + unsigned vdd_r_curr_max:3; + unsigned vdd_r_curr_min:3; + unsigned c_size_lsb:2; + unsigned c_size_msb:10; + unsigned reserved_2:2; + unsigned dsr_imp:1; + unsigned read_blk_misalign:1; + unsigned write_blk_misalign:1; + unsigned read_bl_partial:1; + unsigned read_bl_len:4; + unsigned ccc:12; + unsigned tran_speed:8; + unsigned nsac:8; + unsigned taac:8; + unsigned reserved_3:2; + unsigned spec_vers:4; + unsigned csd_structure:2; +} mmc_csd_reg_t; + +/* csd for sd2.0 */ +typedef struct { + unsigned not_used:1; + unsigned crc:7; + unsigned reserved_1:2; + unsigned file_format:2; + unsigned tmp_write_protect:1; + unsigned perm_write_protect:1; + unsigned copy:1; + unsigned file_format_grp:1; + unsigned reserved_2:5; + unsigned write_bl_partial:1; + unsigned write_bl_len:4; + unsigned r2w_factor:3; + unsigned reserved_3:2; + unsigned wp_grp_enable:1; + unsigned wp_grp_size:7; + unsigned sector_size:7; + unsigned erase_blk_len:1; + unsigned reserved_4:1; + unsigned c_size_lsb:16; + unsigned c_size_msb:6; + unsigned reserved_5:6; + unsigned dsr_imp:1; + unsigned read_blk_misalign:1; + unsigned write_blk_misalign:1; + unsigned read_bl_partial:1; + unsigned read_bl_len:4; + unsigned ccc:12; + unsigned tran_speed:8; + unsigned nsac:8; + unsigned taac:8; + unsigned reserved_6:6; + unsigned csd_structure:2; +} mmc_sd2_csd_reg_t; + +/* extended csd - 512 bytes long */ +typedef struct { + unsigned char reserved_1[181]; + unsigned char erasedmemorycontent; + unsigned char reserved_2; + unsigned char buswidthmode; + unsigned char reserved_3; + unsigned char highspeedinterfacetiming; + unsigned char reserved_4; + unsigned char powerclass; + unsigned char reserved_5; + unsigned char commandsetrevision; + unsigned char reserved_6; + unsigned char commandset; + unsigned char extendedcsdrevision; + unsigned char reserved_7; + unsigned char csdstructureversion; + unsigned char reserved_8; + unsigned char cardtype; + unsigned char reserved_9[3]; + unsigned char powerclass_52mhz_1_95v; + unsigned char powerclass_26mhz_1_95v; + unsigned char powerclass_52mhz_3_6v; + unsigned char powerclass_26mhz_3_6v; + unsigned char reserved_10; + unsigned char minreadperf_4b_26mhz; + unsigned char minwriteperf_4b_26mhz; + unsigned char minreadperf_8b_26mhz_4b_52mhz; + unsigned char minwriteperf_8b_26mhz_4b_52mhz; + unsigned char minreadperf_8b_52mhz; + unsigned char minwriteperf_8b_52mhz; + unsigned char reserved_11; + unsigned int sectorcount; + unsigned char reserved_12[288]; + unsigned char supportedcommandsets; + unsigned char reserved_13[7]; +} mmc_extended_csd_reg_t; + +/* mmc sd responce */ +typedef struct { + unsigned int ocr; +} mmc_resp_r3; + +typedef struct { + unsigned short cardstatus; + unsigned short newpublishedrca; +} mmc_resp_r6; + +extern mmc_card_data mmc_dev; + +unsigned char mmc_lowlevel_init(void); +unsigned char mmc_send_command(unsigned int cmd, unsigned int arg, + unsigned int *response); +unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd); +unsigned char mmc_set_opendrain(unsigned char state); +unsigned char mmc_read_data(unsigned int *output_buf); + +#endif /* MMC_H */ diff --git a/include/asm/arch-omap3/mmc_host_def.h b/include/asm/arch-omap3/mmc_host_def.h new file mode 100644 index 0000000..408d1e2 --- /dev/null +++ b/include/asm/arch-omap3/mmc_host_def.h @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +/* + * OMAP HSMMC register definitions + */ +#define OMAP_HSMMC_SYSCONFIG (*(volatile unsigned int *) 0x4809C010) +#define OMAP_HSMMC_SYSSTATUS (*(volatile unsigned int *) 0x4809C014) +#define OMAP_HSMMC_CON (*(volatile unsigned int *) 0x4809C02C) +#define OMAP_HSMMC_BLK (*(volatile unsigned int *) 0x4809C104) +#define OMAP_HSMMC_ARG (*(volatile unsigned int *) 0x4809C108) +#define OMAP_HSMMC_CMD (*(volatile unsigned int *) 0x4809C10C) +#define OMAP_HSMMC_RSP10 (*(volatile unsigned int *) 0x4809C110) +#define OMAP_HSMMC_RSP32 (*(volatile unsigned int *) 0x4809C114) +#define OMAP_HSMMC_RSP54 (*(volatile unsigned int *) 0x4809C118) +#define OMAP_HSMMC_RSP76 (*(volatile unsigned int *) 0x4809C11C) +#define OMAP_HSMMC_DATA (*(volatile unsigned int *) 0x4809C120) +#define OMAP_HSMMC_PSTATE (*(volatile unsigned int *) 0x4809C124) +#define OMAP_HSMMC_HCTL (*(volatile unsigned int *) 0x4809C128) +#define OMAP_HSMMC_SYSCTL (*(volatile unsigned int *) 0x4809C12C) +#define OMAP_HSMMC_STAT (*(volatile unsigned int *) 0x4809C130) +#define OMAP_HSMMC_IE (*(volatile unsigned int *) 0x4809C134) +#define OMAP_HSMMC_CAPA (*(volatile unsigned int *) 0x4809C140) + +/* T2 Register definitions */ +#define CONTROL_DEV_CONF0 (*(volatile unsigned int *) 0x48002274) +#define CONTROL_PBIAS_LITE (*(volatile unsigned int *) 0x48002520) + +/* + * OMAP HS MMC Bit definitions + */ +#define MMC_SOFTRESET (0x1 << 1) +#define RESETDONE (0x1 << 0) +#define NOOPENDRAIN (0x0 << 0) +#define OPENDRAIN (0x1 << 0) +#define OD (0x1 << 0) +#define INIT_NOINIT (0x0 << 1) +#define INIT_INITSTREAM (0x1 << 1) +#define HR_NOHOSTRESP (0x0 << 2) +#define STR_BLOCK (0x0 << 3) +#define MODE_FUNC (0x0 << 4) +#define DW8_1_4BITMODE (0x0 << 5) +#define MIT_CTO (0x0 << 6) +#define CDP_ACTIVEHIGH (0x0 << 7) +#define WPP_ACTIVEHIGH (0x0 << 8) +#define RESERVED_MASK (0x3 << 9) +#define CTPL_MMC_SD (0x0 << 11) +#define BLEN_512BYTESLEN (0x200 << 0) +#define NBLK_STPCNT (0x0 << 16) +#define DE_DISABLE (0x0 << 0) +#define BCE_DISABLE (0x0 << 1) +#define ACEN_DISABLE (0x0 << 2) +#define DDIR_OFFSET (4) +#define DDIR_MASK (0x1 << 4) +#define DDIR_WRITE (0x0 << 4) +#define DDIR_READ (0x1 << 4) +#define MSBS_SGLEBLK (0x0 << 5) +#define RSP_TYPE_OFFSET (16) +#define RSP_TYPE_MASK (0x3 << 16) +#define RSP_TYPE_NORSP (0x0 << 16) +#define RSP_TYPE_LGHT136 (0x1 << 16) +#define RSP_TYPE_LGHT48 (0x2 << 16) +#define RSP_TYPE_LGHT48B (0x3 << 16) +#define CCCE_NOCHECK (0x0 << 19) +#define CCCE_CHECK (0x1 << 19) +#define CICE_NOCHECK (0x0 << 20) +#define CICE_CHECK (0x1 << 20) +#define DP_OFFSET (21) +#define DP_MASK (0x1 << 21) +#define DP_NO_DATA (0x0 << 21) +#define DP_DATA (0x1 << 21) +#define CMD_TYPE_NORMAL (0x0 << 22) +#define INDEX_OFFSET (24) +#define INDEX_MASK (0x3f << 24) +#define INDEX(i) (i << 24) +#define DATI_MASK (0x1 << 1) +#define DATI_CMDDIS (0x1 << 1) +#define DTW_1_BITMODE (0x0 << 1) +#define DTW_4_BITMODE (0x1 << 1) +#define SDBP_PWROFF (0x0 << 8) +#define SDBP_PWRON (0x1 << 8) +#define SDVS_1V8 (0x5 << 9) +#define SDVS_3V0 (0x6 << 9) +#define ICE_MASK (0x1 << 0) +#define ICE_STOP (0x0 << 0) +#define ICS_MASK (0x1 << 1) +#define ICS_NOTREADY (0x0 << 1) +#define ICE_OSCILLATE (0x1 << 0) +#define CEN_MASK (0x1 << 2) +#define CEN_DISABLE (0x0 << 2) +#define CEN_ENABLE (0x1 << 2) +#define CLKD_OFFSET (6) +#define CLKD_MASK (0x3FF << 6) +#define DTO_MASK (0xF << 16) +#define DTO_15THDTO (0xE << 16) +#define SOFTRESETALL (0x1 << 24) +#define CC_MASK (0x1 << 0) +#define TC_MASK (0x1 << 1) +#define BWR_MASK (0x1 << 4) +#define BRR_MASK (0x1 << 5) +#define ERRI_MASK (0x1 << 15) +#define IE_CC (0x01 << 0) +#define IE_TC (0x01 << 1) +#define IE_BWR (0x01 << 4) +#define IE_BRR (0x01 << 5) +#define IE_CTO (0x01 << 16) +#define IE_CCRC (0x01 << 17) +#define IE_CEB (0x01 << 18) +#define IE_CIE (0x01 << 19) +#define IE_DTO (0x01 << 20) +#define IE_DCRC (0x01 << 21) +#define IE_DEB (0x01 << 22) +#define IE_CERR (0x01 << 28) +#define IE_BADA (0x01 << 29) + +#define VS30_3V0SUP (1 << 25) +#define VS18_1V8SUP (1 << 26) + +/* Driver definitions */ +#define MMCSD_SECTOR_SIZE (512) +#define MMC_CARD 0 +#define SD_CARD 1 +#define BYTE_MODE 0 +#define SECTOR_MODE 1 +#define CLK_INITSEQ 0 +#define CLK_400KHZ 1 +#define CLK_MISC 2 + +typedef struct { + unsigned int card_type; + unsigned int version; + unsigned int mode; + unsigned int size; + unsigned int RCA; +} mmc_card_data; + +#define mmc_reg_out(addr, mask, val)\ + (addr) = (((addr)) & (~(mask))) | ((val) & (mask)); + +#endif /* MMC_HOST_DEF_H */ diff --git a/include/asm/arch-omap3/mux.h b/include/asm/arch-omap3/mux.h new file mode 100644 index 0000000..ca140a9 --- /dev/null +++ b/include/asm/arch-omap3/mux.h @@ -0,0 +1,437 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Syed Mohammed Khasim + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP3430_MUX_H_ +#define _OMAP3430_MUX_H_ + +/* + * OFF_PD - Off mode pull type down + * OFF_PU - Off mode pull type up + * OFF_OUT_PTD - Off Mode Mux low for OUT + * OFF_OUT_PTU - Off Mode Mux high for OUT + * OFF_IN - Off Mode Mux set to IN + * OFF_OUT - Off Mode Mux set to OUT + * OFF_EN - Off Mode Mux Enable + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + */ + +#define OFF_PD (1 << 12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 11) +#define OFF_OUT_PTU (1 << 11) +#define OFF_IN (1 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (1 << 9) + +#define IEN (1 << 8) + +#define IDIS (0 << 8) +#define PTU (1 << 4) +#define PTD (0 << 4) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif /* #ifdef CONFIG_OFF_PADCONF */ + +/* + * To get the actual address the offset has to added + * with OMAP34XX_CTRL_BASE to get the actual address + */ + +/*SDRC*/ +#define CONTROL_PADCONF_SDRC_D0 0x0030 +#define CONTROL_PADCONF_SDRC_D1 0x0032 +#define CONTROL_PADCONF_SDRC_D2 0x0034 +#define CONTROL_PADCONF_SDRC_D3 0x0036 +#define CONTROL_PADCONF_SDRC_D4 0x0038 +#define CONTROL_PADCONF_SDRC_D5 0x003A +#define CONTROL_PADCONF_SDRC_D6 0x003C +#define CONTROL_PADCONF_SDRC_D7 0x003E +#define CONTROL_PADCONF_SDRC_D8 0x0040 +#define CONTROL_PADCONF_SDRC_D9 0x0042 +#define CONTROL_PADCONF_SDRC_D10 0x0044 +#define CONTROL_PADCONF_SDRC_D11 0x0046 +#define CONTROL_PADCONF_SDRC_D12 0x0048 +#define CONTROL_PADCONF_SDRC_D13 0x004A +#define CONTROL_PADCONF_SDRC_D14 0x004C +#define CONTROL_PADCONF_SDRC_D15 0x004E +#define CONTROL_PADCONF_SDRC_D16 0x0050 +#define CONTROL_PADCONF_SDRC_D17 0x0052 +#define CONTROL_PADCONF_SDRC_D18 0x0054 +#define CONTROL_PADCONF_SDRC_D19 0x0056 +#define CONTROL_PADCONF_SDRC_D20 0x0058 +#define CONTROL_PADCONF_SDRC_D21 0x005A +#define CONTROL_PADCONF_SDRC_D22 0x005C +#define CONTROL_PADCONF_SDRC_D23 0x005E +#define CONTROL_PADCONF_SDRC_D24 0x0060 +#define CONTROL_PADCONF_SDRC_D25 0x0062 +#define CONTROL_PADCONF_SDRC_D26 0x0064 +#define CONTROL_PADCONF_SDRC_D27 0x0066 +#define CONTROL_PADCONF_SDRC_D28 0x0068 +#define CONTROL_PADCONF_SDRC_D29 0x006A +#define CONTROL_PADCONF_SDRC_D30 0x006C +#define CONTROL_PADCONF_SDRC_D31 0x006E +#define CONTROL_PADCONF_SDRC_CLK 0x0070 +#define CONTROL_PADCONF_SDRC_DQS0 0x0072 +#define CONTROL_PADCONF_SDRC_DQS1 0x0074 +#define CONTROL_PADCONF_SDRC_DQS2 0x0076 +#define CONTROL_PADCONF_SDRC_DQS3 0x0078 +/*GPMC*/ +#define CONTROL_PADCONF_GPMC_A1 0x007A +#define CONTROL_PADCONF_GPMC_A2 0x007C +#define CONTROL_PADCONF_GPMC_A3 0x007E +#define CONTROL_PADCONF_GPMC_A4 0x0080 +#define CONTROL_PADCONF_GPMC_A5 0x0082 +#define CONTROL_PADCONF_GPMC_A6 0x0084 +#define CONTROL_PADCONF_GPMC_A7 0x0086 +#define CONTROL_PADCONF_GPMC_A8 0x0088 +#define CONTROL_PADCONF_GPMC_A9 0x008A +#define CONTROL_PADCONF_GPMC_A10 0x008C +#define CONTROL_PADCONF_GPMC_D0 0x008E +#define CONTROL_PADCONF_GPMC_D1 0x0090 +#define CONTROL_PADCONF_GPMC_D2 0x0092 +#define CONTROL_PADCONF_GPMC_D3 0x0094 +#define CONTROL_PADCONF_GPMC_D4 0x0096 +#define CONTROL_PADCONF_GPMC_D5 0x0098 +#define CONTROL_PADCONF_GPMC_D6 0x009A +#define CONTROL_PADCONF_GPMC_D7 0x009C +#define CONTROL_PADCONF_GPMC_D8 0x009E +#define CONTROL_PADCONF_GPMC_D9 0x00A0 +#define CONTROL_PADCONF_GPMC_D10 0x00A2 +#define CONTROL_PADCONF_GPMC_D11 0x00A4 +#define CONTROL_PADCONF_GPMC_D12 0x00A6 +#define CONTROL_PADCONF_GPMC_D13 0x00A8 +#define CONTROL_PADCONF_GPMC_D14 0x00AA +#define CONTROL_PADCONF_GPMC_D15 0x00AC +#define CONTROL_PADCONF_GPMC_nCS0 0x00AE +#define CONTROL_PADCONF_GPMC_nCS1 0x00B0 +#define CONTROL_PADCONF_GPMC_nCS2 0x00B2 +#define CONTROL_PADCONF_GPMC_nCS3 0x00B4 +#define CONTROL_PADCONF_GPMC_nCS4 0x00B6 +#define CONTROL_PADCONF_GPMC_nCS5 0x00B8 +#define CONTROL_PADCONF_GPMC_nCS6 0x00BA +#define CONTROL_PADCONF_GPMC_nCS7 0x00BC +#define CONTROL_PADCONF_GPMC_CLK 0x00BE +#define CONTROL_PADCONF_GPMC_nADV_ALE 0x00C0 +#define CONTROL_PADCONF_GPMC_nOE 0x00C2 +#define CONTROL_PADCONF_GPMC_nWE 0x00C4 +#define CONTROL_PADCONF_GPMC_nBE0_CLE 0x00C6 +#define CONTROL_PADCONF_GPMC_nBE1 0x00C8 +#define CONTROL_PADCONF_GPMC_nWP 0x00CA +#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC +#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE +#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 +#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 +/*DSS*/ +#define CONTROL_PADCONF_DSS_PCLK 0x00D4 +#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 +#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 +#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA +#define CONTROL_PADCONF_DSS_DATA0 0x00DC +#define CONTROL_PADCONF_DSS_DATA1 0x00DE +#define CONTROL_PADCONF_DSS_DATA2 0x00E0 +#define CONTROL_PADCONF_DSS_DATA3 0x00E2 +#define CONTROL_PADCONF_DSS_DATA4 0x00E4 +#define CONTROL_PADCONF_DSS_DATA5 0x00E6 +#define CONTROL_PADCONF_DSS_DATA6 0x00E8 +#define CONTROL_PADCONF_DSS_DATA7 0x00EA +#define CONTROL_PADCONF_DSS_DATA8 0x00EC +#define CONTROL_PADCONF_DSS_DATA9 0x00EE +#define CONTROL_PADCONF_DSS_DATA10 0x00F0 +#define CONTROL_PADCONF_DSS_DATA11 0x00F2 +#define CONTROL_PADCONF_DSS_DATA12 0x00F4 +#define CONTROL_PADCONF_DSS_DATA13 0x00F6 +#define CONTROL_PADCONF_DSS_DATA14 0x00F8 +#define CONTROL_PADCONF_DSS_DATA15 0x00FA +#define CONTROL_PADCONF_DSS_DATA16 0x00FC +#define CONTROL_PADCONF_DSS_DATA17 0x00FE +#define CONTROL_PADCONF_DSS_DATA18 0x0100 +#define CONTROL_PADCONF_DSS_DATA19 0x0102 +#define CONTROL_PADCONF_DSS_DATA20 0x0104 +#define CONTROL_PADCONF_DSS_DATA21 0x0106 +#define CONTROL_PADCONF_DSS_DATA22 0x0108 +#define CONTROL_PADCONF_DSS_DATA23 0x010A +/*CAMERA*/ +#define CONTROL_PADCONF_CAM_HS 0x010C +#define CONTROL_PADCONF_CAM_VS 0x010E +#define CONTROL_PADCONF_CAM_XCLKA 0x0110 +#define CONTROL_PADCONF_CAM_PCLK 0x0112 +#define CONTROL_PADCONF_CAM_FLD 0x0114 +#define CONTROL_PADCONF_CAM_D0 0x0116 +#define CONTROL_PADCONF_CAM_D1 0x0118 +#define CONTROL_PADCONF_CAM_D2 0x011A +#define CONTROL_PADCONF_CAM_D3 0x011C +#define CONTROL_PADCONF_CAM_D4 0x011E +#define CONTROL_PADCONF_CAM_D5 0x0120 +#define CONTROL_PADCONF_CAM_D6 0x0122 +#define CONTROL_PADCONF_CAM_D7 0x0124 +#define CONTROL_PADCONF_CAM_D8 0x0126 +#define CONTROL_PADCONF_CAM_D9 0x0128 +#define CONTROL_PADCONF_CAM_D10 0x012A +#define CONTROL_PADCONF_CAM_D11 0x012C +#define CONTROL_PADCONF_CAM_XCLKB 0x012E +#define CONTROL_PADCONF_CAM_WEN 0x0130 +#define CONTROL_PADCONF_CAM_STROBE 0x0132 +#define CONTROL_PADCONF_CSI2_DX0 0x0134 +#define CONTROL_PADCONF_CSI2_DY0 0x0136 +#define CONTROL_PADCONF_CSI2_DX1 0x0138 +#define CONTROL_PADCONF_CSI2_DY1 0x013A +/*Audio Interface */ +#define CONTROL_PADCONF_McBSP2_FSX 0x013C +#define CONTROL_PADCONF_McBSP2_CLKX 0x013E +#define CONTROL_PADCONF_McBSP2_DR 0x0140 +#define CONTROL_PADCONF_McBSP2_DX 0x0142 +#define CONTROL_PADCONF_ +#define CONTROL_PADCONF_MMC1_CLK 0x0144 +#define CONTROL_PADCONF_MMC1_CMD 0x0146 +#define CONTROL_PADCONF_MMC1_DAT0 0x0148 +#define CONTROL_PADCONF_MMC1_DAT1 0x014A +#define CONTROL_PADCONF_MMC1_DAT2 0x014C +#define CONTROL_PADCONF_MMC1_DAT3 0x014E +#define CONTROL_PADCONF_MMC1_DAT4 0x0150 +#define CONTROL_PADCONF_MMC1_DAT5 0x0152 +#define CONTROL_PADCONF_MMC1_DAT6 0x0154 +#define CONTROL_PADCONF_MMC1_DAT7 0x0156 +/*Wireless LAN */ +#define CONTROL_PADCONF_MMC2_CLK 0x0158 +#define CONTROL_PADCONF_MMC2_CMD 0x015A +#define CONTROL_PADCONF_MMC2_DAT0 0x015C +#define CONTROL_PADCONF_MMC2_DAT1 0x015E +#define CONTROL_PADCONF_MMC2_DAT2 0x0160 +#define CONTROL_PADCONF_MMC2_DAT3 0x0162 +#define CONTROL_PADCONF_MMC2_DAT4 0x0164 +#define CONTROL_PADCONF_MMC2_DAT5 0x0166 +#define CONTROL_PADCONF_MMC2_DAT6 0x0168 +#define CONTROL_PADCONF_MMC2_DAT7 0x016A +/*Bluetooth*/ +#define CONTROL_PADCONF_McBSP3_DX 0x016C +#define CONTROL_PADCONF_McBSP3_DR 0x016E +#define CONTROL_PADCONF_McBSP3_CLKX 0x0170 +#define CONTROL_PADCONF_McBSP3_FSX 0x0172 +#define CONTROL_PADCONF_UART2_CTS 0x0174 +#define CONTROL_PADCONF_UART2_RTS 0x0176 +#define CONTROL_PADCONF_UART2_TX 0x0178 +#define CONTROL_PADCONF_UART2_RX 0x017A +/*Modem Interface */ +#define CONTROL_PADCONF_UART1_TX 0x017C +#define CONTROL_PADCONF_UART1_RTS 0x017E +#define CONTROL_PADCONF_UART1_CTS 0x0180 +#define CONTROL_PADCONF_UART1_RX 0x0182 +#define CONTROL_PADCONF_McBSP4_CLKX 0x0184 +#define CONTROL_PADCONF_McBSP4_DR 0x0186 +#define CONTROL_PADCONF_McBSP4_DX 0x0188 +#define CONTROL_PADCONF_McBSP4_FSX 0x018A +#define CONTROL_PADCONF_McBSP1_CLKR 0x018C +#define CONTROL_PADCONF_McBSP1_FSR 0x018E +#define CONTROL_PADCONF_McBSP1_DX 0x0190 +#define CONTROL_PADCONF_McBSP1_DR 0x0192 +#define CONTROL_PADCONF_McBSP_CLKS 0x0194 +#define CONTROL_PADCONF_McBSP1_FSX 0x0196 +#define CONTROL_PADCONF_McBSP1_CLKX 0x0198 +/*Serial Interface*/ +#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A +#define CONTROL_PADCONF_UART3_RTS_SD 0x019C +#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E +#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 +#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 +#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 +#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 +#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 +#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA +#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC +#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE +#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 +#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 +#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 +#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 +#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 +#define CONTROL_PADCONF_I2C1_SCL 0x01BA +#define CONTROL_PADCONF_I2C1_SDA 0x01BC +#define CONTROL_PADCONF_I2C2_SCL 0x01BE +#define CONTROL_PADCONF_I2C2_SDA 0x01C0 +#define CONTROL_PADCONF_I2C3_SCL 0x01C2 +#define CONTROL_PADCONF_I2C3_SDA 0x01C4 +#define CONTROL_PADCONF_I2C4_SCL 0x0A00 +#define CONTROL_PADCONF_I2C4_SDA 0x0A02 +#define CONTROL_PADCONF_HDQ_SIO 0x01C6 +#define CONTROL_PADCONF_McSPI1_CLK 0x01C8 +#define CONTROL_PADCONF_McSPI1_SIMO 0x01CA +#define CONTROL_PADCONF_McSPI1_SOMI 0x01CC +#define CONTROL_PADCONF_McSPI1_CS0 0x01CE +#define CONTROL_PADCONF_McSPI1_CS1 0x01D0 +#define CONTROL_PADCONF_McSPI1_CS2 0x01D2 +#define CONTROL_PADCONF_McSPI1_CS3 0x01D4 +#define CONTROL_PADCONF_McSPI2_CLK 0x01D6 +#define CONTROL_PADCONF_McSPI2_SIMO 0x01D8 +#define CONTROL_PADCONF_McSPI2_SOMI 0x01DA +#define CONTROL_PADCONF_McSPI2_CS0 0x01DC +#define CONTROL_PADCONF_McSPI2_CS1 0x01DE +/*Control and debug */ +#define CONTROL_PADCONF_SYS_32K 0x0A04 +#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 +#define CONTROL_PADCONF_SYS_nIRQ 0x01E0 +#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A +#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C +#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E +#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 +#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 +#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 +#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 +#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 +#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A +#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 +#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C +#define CONTROL_PADCONF_JTAG_TCK 0x0A1E +#define CONTROL_PADCONF_JTAG_TMS 0x0A20 +#define CONTROL_PADCONF_JTAG_TDI 0x0A22 +#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 +#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 +#define CONTROL_PADCONF_ETK_CLK 0x0A28 +#define CONTROL_PADCONF_ETK_CTL 0x0A2A +#define CONTROL_PADCONF_ETK_D0 0x0A2C +#define CONTROL_PADCONF_ETK_D1 0x0A2E +#define CONTROL_PADCONF_ETK_D2 0x0A30 +#define CONTROL_PADCONF_ETK_D3 0x0A32 +#define CONTROL_PADCONF_ETK_D4 0x0A34 +#define CONTROL_PADCONF_ETK_D5 0x0A36 +#define CONTROL_PADCONF_ETK_D6 0x0A38 +#define CONTROL_PADCONF_ETK_D7 0x0A3A +#define CONTROL_PADCONF_ETK_D8 0x0A3C +#define CONTROL_PADCONF_ETK_D9 0x0A3E +#define CONTROL_PADCONF_ETK_D10 0x0A40 +#define CONTROL_PADCONF_ETK_D11 0x0A42 +#define CONTROL_PADCONF_ETK_D12 0x0A44 +#define CONTROL_PADCONF_ETK_D13 0x0A46 +#define CONTROL_PADCONF_ETK_D14 0x0A48 +#define CONTROL_PADCONF_ETK_D15 0x0A4A + +#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 +#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA +#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC +#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE +#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 +#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 +#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 +#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 +#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 +#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA +#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC +#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE +#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 +#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 +#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 +#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 +#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 +#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA + +/*Die to Die */ +#define CONTROL_PADCONF_d2d_mcad0 0x01E4 +#define CONTROL_PADCONF_d2d_mcad1 0x01E6 +#define CONTROL_PADCONF_d2d_mcad2 0x01E8 +#define CONTROL_PADCONF_d2d_mcad3 0x01EA +#define CONTROL_PADCONF_d2d_mcad4 0x01EC +#define CONTROL_PADCONF_d2d_mcad5 0x01EE +#define CONTROL_PADCONF_d2d_mcad6 0x01F0 +#define CONTROL_PADCONF_d2d_mcad7 0x01F2 +#define CONTROL_PADCONF_d2d_mcad8 0x01F4 +#define CONTROL_PADCONF_d2d_mcad9 0x01F6 +#define CONTROL_PADCONF_d2d_mcad10 0x01F8 +#define CONTROL_PADCONF_d2d_mcad11 0x01FA +#define CONTROL_PADCONF_d2d_mcad12 0x01FC +#define CONTROL_PADCONF_d2d_mcad13 0x01FE +#define CONTROL_PADCONF_d2d_mcad14 0x0200 +#define CONTROL_PADCONF_d2d_mcad15 0x0202 +#define CONTROL_PADCONF_d2d_mcad16 0x0204 +#define CONTROL_PADCONF_d2d_mcad17 0x0206 +#define CONTROL_PADCONF_d2d_mcad18 0x0208 +#define CONTROL_PADCONF_d2d_mcad19 0x020A +#define CONTROL_PADCONF_d2d_mcad20 0x020C +#define CONTROL_PADCONF_d2d_mcad21 0x020E +#define CONTROL_PADCONF_d2d_mcad22 0x0210 +#define CONTROL_PADCONF_d2d_mcad23 0x0212 +#define CONTROL_PADCONF_d2d_mcad24 0x0214 +#define CONTROL_PADCONF_d2d_mcad25 0x0216 +#define CONTROL_PADCONF_d2d_mcad26 0x0218 +#define CONTROL_PADCONF_d2d_mcad27 0x021A +#define CONTROL_PADCONF_d2d_mcad28 0x021C +#define CONTROL_PADCONF_d2d_mcad29 0x021E +#define CONTROL_PADCONF_d2d_mcad30 0x0220 +#define CONTROL_PADCONF_d2d_mcad31 0x0222 +#define CONTROL_PADCONF_d2d_mcad32 0x0224 +#define CONTROL_PADCONF_d2d_mcad33 0x0226 +#define CONTROL_PADCONF_d2d_mcad34 0x0228 +#define CONTROL_PADCONF_d2d_mcad35 0x022A +#define CONTROL_PADCONF_d2d_mcad36 0x022C +#define CONTROL_PADCONF_d2d_clk26mi 0x022E +#define CONTROL_PADCONF_d2d_nrespwron 0x0230 +#define CONTROL_PADCONF_d2d_nreswarm 0x0232 +#define CONTROL_PADCONF_d2d_arm9nirq 0x0234 +#define CONTROL_PADCONF_d2d_uma2p6fiq 0x0236 +#define CONTROL_PADCONF_d2d_spint 0x0238 +#define CONTROL_PADCONF_d2d_frint 0x023A +#define CONTROL_PADCONF_d2d_dmareq0 0x023C +#define CONTROL_PADCONF_d2d_dmareq1 0x023E +#define CONTROL_PADCONF_d2d_dmareq2 0x0240 +#define CONTROL_PADCONF_d2d_dmareq3 0x0242 +#define CONTROL_PADCONF_d2d_n3gtrst 0x0244 +#define CONTROL_PADCONF_d2d_n3gtdi 0x0246 +#define CONTROL_PADCONF_d2d_n3gtdo 0x0248 +#define CONTROL_PADCONF_d2d_n3gtms 0x024A +#define CONTROL_PADCONF_d2d_n3gtck 0x024C +#define CONTROL_PADCONF_d2d_n3grtck 0x024E +#define CONTROL_PADCONF_d2d_mstdby 0x0250 +#define CONTROL_PADCONF_d2d_swakeup 0x0A4C +#define CONTROL_PADCONF_d2d_idlereq 0x0252 +#define CONTROL_PADCONF_d2d_idleack 0x0254 +#define CONTROL_PADCONF_d2d_mwrite 0x0256 +#define CONTROL_PADCONF_d2d_swrite 0x0258 +#define CONTROL_PADCONF_d2d_mread 0x025A +#define CONTROL_PADCONF_d2d_sread 0x025C +#define CONTROL_PADCONF_d2d_mbusflag 0x025E +#define CONTROL_PADCONF_d2d_sbusflag 0x0260 +#define CONTROL_PADCONF_sdrc_cke0 0x0262 +#define CONTROL_PADCONF_sdrc_cke1 0x0264 + +#endif diff --git a/include/asm/arch-omap3/omap3430.h b/include/asm/arch-omap3/omap3430.h new file mode 100644 index 0000000..117d752 --- /dev/null +++ b/include/asm/arch-omap3/omap3430.h @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP3430_SYS_H_ +#define _OMAP3430_SYS_H_ + +#include + +/* + * 3430 specific Section + */ + +/* Stuff on L3 Interconnect */ +#define SMX_APE_BASE 0x68000000 + +/* L3 Firewall */ +#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048) +#define A_READPERM0 (SMX_APE_BASE + 0x05050) +#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058) + +/* GPMC */ +#define OMAP34XX_GPMC_BASE (0x6E000000) + +/* SMS */ +#define OMAP34XX_SMS_BASE 0x6C000000 + +/* SDRC */ +#define OMAP34XX_SDRC_BASE 0x6D000000 + +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 + +#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000 + +#define OMAP34XX_L4_PER 0x49000000 + +#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE + +/* CONTROL */ +#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE+0x2000) + +/* TAP information dont know for 3430*/ +#define OMAP34XX_TAP_BASE (0x49000000) /*giving some junk for virtio */ + +/* UART */ +#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE+0x6a000) +#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE+0x6c000) +#define OMAP34XX_UART3 (OMAP34XX_L4_PER+0x20000) + +/* General Purpose Timers */ +#define OMAP34XX_GPT1 0x48318000 +#define OMAP34XX_GPT2 0x49032000 +#define OMAP34XX_GPT3 0x49034000 +#define OMAP34XX_GPT4 0x49036000 +#define OMAP34XX_GPT5 0x49038000 +#define OMAP34XX_GPT6 0x4903A000 +#define OMAP34XX_GPT7 0x4903C000 +#define OMAP34XX_GPT8 0x4903E000 +#define OMAP34XX_GPT9 0x49040000 +#define OMAP34XX_GPT10 0x48086000 +#define OMAP34XX_GPT11 0x48088000 +#define OMAP34XX_GPT12 0x48304000 + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE (0x4830C000) +#define WD2_BASE (0x48314000) +#define WD3_BASE (0x49030000) + +/* 32KTIMER */ +#define SYNC_32KTIMER_BASE (0x48320000) +#define S32K_CR (SYNC_32KTIMER_BASE+0x10) + +/* omap3 GPIO registers */ +#define OMAP34XX_GPIO1_BASE 0x48310000 +#define OMAP34XX_GPIO2_BASE 0x49050000 +#define OMAP34XX_GPIO3_BASE 0x49052000 +#define OMAP34XX_GPIO4_BASE 0x49054000 +#define OMAP34XX_GPIO5_BASE 0x49056000 +#define OMAP34XX_GPIO6_BASE 0x49058000 + +/* + * SDP3430 specific Section + */ + +/* + * The 343x's chip selects are programmable. The mask ROM + * does configure CS0 to 0x08000000 before dispatch. So, if + * you want your code to live below that address, you have to + * be prepared to jump though hoops, to reset the base address. + * Same as in SDP3430 + */ +#ifdef CONFIG_OMAP34XX +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) + +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC +#endif + +#if defined(CONFIG_3430SDP) || defined(CONFIG_OMAP3EVM) +/* FPGA on Debug board.*/ +#define ETH_CONTROL_REG (DEBUG_BASE+0x30b) +#define LAN_RESET_REGISTER (DEBUG_BASE+0x1c) + +#define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60) +#define LED_REGISTER (DEBUG_BASE+0x40) +#define FPGA_REV_REGISTER (DEBUG_BASE+0x10) +#define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800) +#define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900) +#define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00) +#define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00) +#define ENHANCED_UI_EE_NAME "750-2075" +#endif + +/* + * 343x real hardware: + * ES1 = rev 0 + * + * ES2 onwards, the value maps to contents of IDCODE register [31:28]. + * + * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing. + */ +#define CPU_3XX_ES10 0 +#define CPU_3XX_ES20 1 +#define CPU_3XX_ES21 2 +#define CPU_3XX_ES30 3 +#define CPU_3XX_ES31 4 +#define CPU_3XX_ES312 7 +#define CPU_3XX_MAX_REV 8 + +#define CPU_3XX_ID_SHIFT 28 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +/* + * Control idcode register contains hawkeye and revision info + */ +#define CONTROL_IDCODE 0x4830A204 +#define CONTROL_OMAP_STATUS 0x4800244C + +/* + * Hawkeye values + */ +#define HAWKEYE_OMAP34XX 0xb7ae +#define HAWKEYE_AM35XX 0xb868 +#define HAWKEYE_OMAP36XX 0xb891 + +#define HAWKEYE_SHIFT 12 + +/* + * Define CPU families + */ +#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */ +#define CPU_AM35XX 0x3500 /* AM35xx devices */ +#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */ + +/* + * Control status register values corresponding to cpu variants + */ +#define OMAP3503 0x5c00 +#define OMAP3515 0x1c00 +#define OMAP3525 0x4c00 +#define OMAP3530 0x0c00 + +#define AM3505 0x5c00 +#define AM3517 0x1c00 + +#define OMAP3730 0x0c00 + +#endif /* _OMAP3430_SYS_H_ */ diff --git a/include/asm/arch-omap3/rev.h b/include/asm/arch-omap3/rev.h new file mode 100755 index 0000000..c0e95d4 --- /dev/null +++ b/include/asm/arch-omap3/rev.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * + * Richard Woodruff + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP34XX_REV_H_ +#define _OMAP34XX_REV_H_ + +#define CDB_DDR_COMBO /* combo part on cpu daughter card */ +#define CDB_DDR_IPDB /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_3430 0x3430 + +#define CPU_3430_ES1 1 +#define CPU_3430_ES2 1 + +#endif diff --git a/include/asm/arch-omap3/sizes.h b/include/asm/arch-omap3/sizes.h new file mode 100644 index 0000000..aaba18f --- /dev/null +++ b/include/asm/arch-omap3/sizes.h @@ -0,0 +1,49 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_31M 0x01F00000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __sizes_h */ diff --git a/include/asm/arch-omap3/sys_info.h b/include/asm/arch-omap3/sys_info.h new file mode 100644 index 0000000..18e2b49 --- /dev/null +++ b/include/asm/arch-omap3/sys_info.h @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP34XX_SYS_INFO_H_ +#define _OMAP34XX_SYS_INFO_H_ + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_3430 0x3430 + +/* 343x real hardware: + * ES1 = rev 0 + */ + +/* 343x code defines: + * ES1 = 0+1 = 1 + * ES1 = 1+1 = 1 + */ +#define CPU_3430_ES1 1 +#define CPU_3430_ES2 2 + +/* Currently Virtio models this one */ +#define CPU_3430_CHIPID 0x0B68A000 + +#define GPMC_MUXED 1 +#define GPMC_NONMUXED 0 + +#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ +#define TYPE_NOR 0x000 +#define TYPE_ONENAND 0x800 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ +#define I2C_TRITON2 0x4B /* addres of power group */ + +#define BOOT_FAST_XIP 0x1f + +/* SDP definitions according to FPGA Rev. Is this OK?? */ +#define SDP_3430_V1 0x1 +#define SDP_3430_V2 0x2 + +#define BOARD_3430_LABRADOR 0x80 +#define BOARD_3430_LABRADOR_V1 0x1 + +#endif diff --git a/include/asm/arch-omap3/sys_proto.h b/include/asm/arch-omap3/sys_proto.h new file mode 100644 index 0000000..7ac53a2 --- /dev/null +++ b/include/asm/arch-omap3/sys_proto.h @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP34XX_SYS_PROTO_H_ +#define _OMAP34XX_SYS_PROTO_H_ + +void prcm_init(void); +void per_clocks_enable(void); + +void memif_init(void); +void sdrc_init(void); +void do_sdrc_init(u32,u32); +void gpmc_init(void); + +void ether_init(void); +void watchdog_init(void); +void set_muxconf_regs(void); + +u32 get_cpu_type(void); +u32 get_cpu_rev(void); +u32 cpu_is_3410(void); +u32 get_mem_type(void); +u32 get_sysboot_value(void); +u32 get_gpmc0_base(void); +u32 is_gpmc_muxed(void); +u32 get_gpmc0_type(void); +u32 get_gpmc0_width(void); +u32 get_board_type(void); +void display_board_info(u32); +void update_mux(u32,u32); +u32 get_sdr_cs_size(u32 offset); +u32 running_in_sdram(void); +u32 running_in_sram(void); +u32 running_in_flash(void); +u32 running_from_internal_boot(void); +u32 get_device_type(void); + +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); +void sdelay(unsigned long loops); + +#endif diff --git a/include/asm/arch-omap4/bits.h b/include/asm/arch-omap4/bits.h new file mode 100644 index 0000000..541dd97 --- /dev/null +++ b/include/asm/arch-omap4/bits.h @@ -0,0 +1,48 @@ +/* bits.h + * Copyright (c) 2004-2009 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef __bits_h +#define __bits_h 1 + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif diff --git a/include/asm/arch-omap4/clocks.h b/include/asm/arch-omap4/clocks.h new file mode 100644 index 0000000..a65cbda --- /dev/null +++ b/include/asm/arch-omap4/clocks.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2006-2009 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP44XX_CLOCKS_H_ +#define _OMAP44XX_CLOCKS_H_ + +#define LDELAY 12000000 + +#define S12M 12000000 +#define S13M 13000000 +#define S16_8M 16800000 +#define S19_2M 19200000 +#define S24M 24000000 +#define S26M 26000000 +#define S27M 27000000 +#define S38_4M 38400000 + +#include + +#endif diff --git a/include/asm/arch-omap4/clocks443x.h b/include/asm/arch-omap4/clocks443x.h new file mode 100644 index 0000000..63280f7 --- /dev/null +++ b/include/asm/arch-omap4/clocks443x.h @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2006-2009 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP443X_CLOCKS_H_ +#define _OMAP443X_CLOCKS_H_ + +#define PLL_STOP 1 /* PER & IVA */ +#define PLL_MN_POWER_BYPASS 4 +#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ +#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ +#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ + +/* The following configurations are OPP and SysClk value independant + * and hence are defined here. All the other DPLL related values are + * tabulated in lowlevel_init.S. + */ + +/* CORE DPLL */ +# define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ +# define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ +# define CORE_FUSB_DIV 2 /* 41.5MHz: */ +# define CORE_L4_DIV 2 /* 83MHz : L4 */ +# define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ +# define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ +# define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ + +/* PER DPLL */ +# define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ +# define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ +# define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */ +# define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ + +# define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) + +#ifdef PRCM_CLK_CFG2_332MHZ +# define M_12 0xA6 +# define N_12 0x05 +# define FSEL_12 0x07 +# define M2_12 0x01 /* M3 of 2 */ + +# define M_12_ES1 0x0E +# define FSL_12_ES1 0x03 +# define M2_12_ES1 0x1 /* M3 of 2 */ + +# define M_13 0x14C +# define N_13 0x0C +# define FSEL_13 0x03 +# define M2_13 0x01 /* M3 of 2 */ + +# define M_13_ES1 0x1B2 +# define N_13_ES1 0x10 +# define FSL_13_ES1 0x03 +# define M2_13_ES1 0x01 /* M3 of 2 */ + +# define M_19p2 0x19F +# define N_19p2 0x17 +# define FSEL_19p2 0x03 +# define M2_19p2 0x01 /* M3 of 2 */ + +# define M_19p2_ES1 0x19F +# define N_19p2_ES1 0x17 +# define FSL_19p2_ES1 0x03 +# define M2_19p2_ES1 0x01 /* M3 of 2 */ + +# define M_26 0xA6 +# define N_26 0x0C +# define FSEL_26 0x07 +# define M2_26 0x01 /* M3 of 2 */ + +# define M_26_ES1 0x1B2 +# define N_26_ES1 0x21 +# define FSL_26_ES1 0x03 +# define M2_26_ES1 0x01 /* M3 of 2 */ + +# define M_38p4 0x19F +# define N_38p4 0x2F +# define FSEL_38p4 0x03 +# define M2_38p4 0x01 /* M3 of 2 */ + +# define M_38p4_ES1 0x19F +# define N_38p4_ES1 0x2F +# define FSL_38p4_ES1 0x03 +# define M2_38p4_ES1 0x01 /* M3 of 2 */ + +#elif defined(PRCM_CLK_CFG2_266MHZ) +# define M_12 0x85 +# define N_12 0x05 +# define FSEL_12 0x07 +# define M2_12 0x02 /* M3 of 2 */ + +# define M_12_ES1 0x85 /* 0x10A */ +# define N_12_ES1 0x05 /* 0x05 */ +# define FSL_12_ES1 0x07 /* 0x7 */ +# define M2_12_ES1 0x2 /* 0x2 with an M3 of 4*/ + +# define M_13 0x10A +# define N_13 0x0C +# define FSEL_13 0x3 +# define M2_13 0x1 /* M3 of 2 */ + +# define M_13_ES1 0x10A /* 0x214 */ +# define N_13_ES1 0x0C /* 0xC */ +# define FSL_13_ES1 0x3 /* 0x3 */ +# define M2_13_ES1 0x1 /* 0x2 with an M3 of 4*/ + +# define M_19p2 0x115 +# define N_19p2 0x13 +# define FSEL_19p2 0x03 +# define M2_19p2 0x01 /* M3 of 2 */ + +# define M_19p2_ES1 0x115 /* 0x299 */ +# define N_19p2_ES1 0x13 /* 0x17 */ +# define FSL_19p2_ES1 0x03 /* 0x03 */ +# define M2_19p2_ES1 0x01 /* 0x2 with M3 of 4 */ + +# define M_26 0x85 +# define N_26 0x0C +# define FSEL_26 0x07 +# define M2_26 0x01 /* M3 of 2 */ + +# define M_26_ES1 0x85 /* 0x10A */ +# define N_26_ES1 0x0C /* 0xC */ +# define FSL_26_ES1 0x07 /* 0x7 */ +# define M2_26_ES1 0x01 /* 0x2 with an M3 of 4 */ + +# define M_38p4 0x11C +# define N_38p4 0x28 +# define FSEL_38p4 0x03 +# define M2_38p4 0x01 /* M3 of 2 */ + +# define M_38p4_ES1 0x11C /* 0x299 */ +# define N_38p4_ES1 0x28 /* 0x2f */ +# define FSL_38p4_ES1 0x03 /* 0x3 */ +# define M2_38p4_ES1 0x01 /* 0x2 with an M3 of 4*/ + +#endif + +#endif /* endif _OMAP443X_CLOCKS_H_ */ diff --git a/include/asm/arch-omap4/cpu.h b/include/asm/arch-omap4/cpu.h new file mode 100644 index 0000000..94aeb9f --- /dev/null +++ b/include/asm/arch-omap4/cpu.h @@ -0,0 +1,464 @@ +/* + * (C) Copyright 2006-2009 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _OMAP44XX_CPU_H +#define _OMAP44XX_CPU_H +#include + +/* Register offsets of common modules */ +/* Control */ +#define CONTROL_STATUS (OMAP44XX_CTRL_BASE + 0x2F0) +#define OMAP44XX_MCR (OMAP44XX_CTRL_BASE + 0x8C) +#define CONTROL_SCALABLE_OMAP_STATUS (OMAP44XX_CTRL_BASE + 0x44C) +#define CONTROL_SCALABLE_OMAP_OCP (OMAP44XX_CTRL_BASE + 0x534) + + +/* Tap Information */ +#define TAP_IDCODE_REG (OMAP44XX_TAP_BASE+0x204) +#define PRODUCTION_ID (OMAP44XX_TAP_BASE+0x208) + +/* device type */ +#define DEVICE_MASK (BIT8|BIT9|BIT10) +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* GPMC CS3/cs4/cs6 not avaliable */ +#define GPMC_BASE (OMAP44XX_GPMC_BASE) +#define GPMC_SYSCONFIG (OMAP44XX_GPMC_BASE+0x10) +#define GPMC_IRQSTATUS (OMAP44XX_GPMC_BASE+0x18) +#define GPMC_IRQENABLE (OMAP44XX_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP44XX_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP44XX_GPMC_BASE+0x50) +#define GPMC_STATUS (OMAP44XX_GPMC_BASE+0x54) + +#define GPMC_CONFIG_CS0 (OMAP44XX_GPMC_BASE+0x60) +#define GPMC_CONFIG_WIDTH (0x30) + +#define GPMC_CONFIG1 (0x00) +#define GPMC_CONFIG2 (0x04) +#define GPMC_CONFIG3 (0x08) +#define GPMC_CONFIG4 (0x0C) +#define GPMC_CONFIG5 (0x10) +#define GPMC_CONFIG6 (0x14) +#define GPMC_CONFIG7 (0x18) +#define GPMC_NAND_CMD (0x1C) +#define GPMC_NAND_ADR (0x20) +#define GPMC_NAND_DAT (0x24) + +#define GPMC_ECC_CONFIG (0x1F4) +#define GPMC_ECC_CONTROL (0x1F8) +#define GPMC_ECC_SIZE_CONFIG (0x1FC) +#define GPMC_ECC1_RESULT (0x200) +#define GPMC_ECC2_RESULT (0x204) +#define GPMC_ECC3_RESULT (0x208) +#define GPMC_ECC4_RESULT (0x20C) +#define GPMC_ECC5_RESULT (0x210) +#define GPMC_ECC6_RESULT (0x214) +#define GPMC_ECC7_RESULT (0x218) +#define GPMC_ECC8_RESULT (0x21C) +#define GPMC_ECC9_RESULT (0x220) + +#define GPMC_PREFETCH_CONFIG1 (0x1e0) +#define GPMC_PREFETCH_CONFIG2 (0x1e4) +#define GPMC_PREFETCH_CONTROL (0x1ec) +#define GPMC_PREFETCH_STATUS (0x1f0) + +/* GPMC Mapping */ +# define FLASH_BASE 0x10000000 /* NOR flash (aligned to 256 Meg) */ +# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (aligned to 64 Meg) */ +# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (aligned to 256 Meg) */ +# define DEBUG_BASE 0x08000000 /* debug board */ +# define NAND_BASE 0x30000000 /* NAND addr (actual size small port)*/ +# define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ +# define ONENAND_MAP 0x20000000 /* OneNand addr (actual size small port */ + +/* DMM */ +#define DMM_SYSCONFIG (OMAP44XX_DMM_BASE+0x10) +#define DMM_LISA_MAP (OMAP44XX_DMM_BASE+0x100) + +/* SMS */ +#define SMS_SYSCONFIG (OMAP44XX_SMS_BASE+0x10) +#define SMS_RG_ATT0 (OMAP44XX_SMS_BASE+0x48) +#define SMS_CLASS_ARB0 (OMAP44XX_SMS_BASE+0xD0) +#define BURSTCOMPLETE_GROUP7 BIT31 + +#define SDRC_CS_CFG (OMAP44XX_SDRC_BASE+0x40) +#define OMAP44XX_SDRC_CS0 0x80000000 +#define SDRC_POWER (OMAP44XX_SDRC_BASE+0x70) +#define SDRC_MCFG_0 (OMAP44XX_SDRC_BASE+0x80) +#define SDRC_MR_0 (OMAP44XX_SDRC_BASE+0x84) + +/* timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ +#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ + +/* Watchdog */ +#define WWPS 0x34 /* r */ +#define WSPR 0x48 /* rw */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* FIXME */ +#define PRM_RSTCTRL 0x48307250 + /* PRCM */ +#define CM_SYS_CLKSEL 0x4a306110 + +/* PRM.CKGEN module registers */ +#define CM_ABE_PLL_REF_CLKSEL 0x4a30610c + + +/* PRM.WKUP_CM module registers */ +#define CM_WKUP_CLKSTCTRL 0x4a307800 +#define CM_WKUP_L4WKUP_CLKCTRL 0x4a307820 +#define CM_WKUP_WDT1_CLKCTRL 0x4a307828 +#define CM_WKUP_WDT2_CLKCTRL 0x4a307830 +#define CM_WKUP_GPIO1_CLKCTRL 0x4a307838 +#define CM_WKUP_TIMER1_CLKCTRL 0x4a307840 +#define CM_WKUP_TIMER12_CLKCTRL 0x4a307848 +#define CM_WKUP_SYNCTIMER_CLKCTRL 0x4a307850 +#define CM_WKUP_USIM_CLKCTRL 0x4a307858 +#define CM_WKUP_SARRAM_CLKCTRL 0x4a307860 +#define CM_WKUP_KEYBOARD_CLKCTRL 0x4a307878 +#define CM_WKUP_RTC_CLKCTRL 0x4a307880 +#define CM_WKUP_BANDGAP_CLKCTRL 0x4a307888 + +/* CM1.CKGEN module registers */ +#define CM_CLKSEL_CORE 0x4a004100 +#define CM_CLKSEL_ABE 0x4a004108 +#define CM_DLL_CTRL 0x4a004110 +#define CM_CLKMODE_DPLL_CORE 0x4a004120 +#define CM_IDLEST_DPLL_CORE 0x4a004124 +#define CM_AUTOIDLE_DPLL_CORE 0x4a004128 +#define CM_CLKSEL_DPLL_CORE 0x4a00412c +#define CM_DIV_M2_DPLL_CORE 0x4a004130 +#define CM_DIV_M3_DPLL_CORE 0x4a004134 +#define CM_DIV_M4_DPLL_CORE 0x4a004138 +#define CM_DIV_M5_DPLL_CORE 0x4a00413c +#define CM_DIV_M6_DPLL_CORE 0x4a004140 +#define CM_DIV_M7_DPLL_CORE 0x4a004144 +#define CM_SSC_DELTAMSTEP_DPLL_CORE 0x4a004148 +#define CM_SSC_MODFREQDIV_DPLL_CORE 0x4a00414c +#define CM_EMU_OVERRIDE_DPLL_CORE 0x4a004150 +#define CM_CLKMODE_DPLL_MPU 0x4a004160 +#define CM_IDLEST_DPLL_MPU 0x4a004164 +#define CM_AUTOIDLE_DPLL_MPU 0x4a004168 +#define CM_CLKSEL_DPLL_MPU 0x4a00416c +#define CM_DIV_M2_DPLL_MPU 0x4a004170 +#define CM_SSC_DELTAMSTEP_DPLL_MPU 0x4a004188 +#define CM_SSC_MODFREQDIV_DPLL_MPU 0x4a00418c +#define CM_BYPCLK_DPLL_MPU 0x4a00419c +#define CM_CLKMODE_DPLL_IVA 0x4a0041a0 +#define CM_IDLEST_DPLL_IVA 0x4a0041a4 +#define CM_AUTOIDLE_DPLL_IVA 0x4a0041a8 +#define CM_CLKSEL_DPLL_IVA 0x4a0041ac +#define CM_DIV_M4_DPLL_IVA 0x4a0041b8 +#define CM_DIV_M5_DPLL_IVA 0x4a0041bc +#define CM_SSC_DELTAMSTEP_DPLL_IVA 0x4a0041c8 +#define CM_SSC_MODFREQDIV_DPLL_IVA 0x4a0041cc +#define CM_BYPCLK_DPLL_IVA 0x4a0041dc +#define CM_CLKMODE_DPLL_ABE 0x4a0041e0 +#define CM_IDLEST_DPLL_ABE 0x4a0041e4 +#define CM_AUTOIDLE_DPLL_ABE 0x4a0041e8 +#define CM_CLKSEL_DPLL_ABE 0x4a0041ec +#define CM_DIV_M2_DPLL_ABE 0x4a0041f0 +#define CM_DIV_M3_DPLL_ABE 0x4a0041f4 +#define CM_SSC_DELTAMSTEP_DPLL_ABE 0x4a004208 +#define CM_SSC_MODFREQDIV_DPLL_ABE 0x4a00420c +#define CM_CLKMODE_DPLL_DDRPHY 0x4a004220 +#define CM_IDLEST_DPLL_DDRPHY 0x4a004224 +#define CM_AUTOIDLE_DPLL_DDRPHY 0x4a004228 +#define CM_CLKSEL_DPLL_DDRPHY 0x4a00422c +#define CM_DIV_M2_DPLL_DDRPHY 0x4a004230 +#define CM_DIV_M4_DPLL_DDRPHY 0x4a004238 +#define CM_DIV_M5_DPLL_DDRPHY 0x4a00423c +#define CM_DIV_M6_DPLL_DDRPHY 0x4a004240 +#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY 0x4a004248 + +/* CM1.ABE register offsets */ +#define CM1_ABE_CLKSTCTRL 0x4a004500 +#define CM1_ABE_L4ABE_CLKCTRL 0x4a004520 +#define CM1_ABE_AESS_CLKCTRL 0x4a004528 +#define CM1_ABE_PDM_CLKCTRL 0x4a004530 +#define CM1_ABE_DMIC_CLKCTRL 0x4a004538 +#define CM1_ABE_MCASP_CLKCTRL 0x4a004540 +#define CM1_ABE_MCBSP1_CLKCTRL 0x4a004548 +#define CM1_ABE_MCBSP2_CLKCTRL 0x4a004550 +#define CM1_ABE_MCBSP3_CLKCTRL 0x4a004558 +#define CM1_ABE_SLIMBUS_CLKCTRL 0x4a004560 +#define CM1_ABE_TIMER5_CLKCTRL 0x4a004568 +#define CM1_ABE_TIMER6_CLKCTRL 0x4a004570 +#define CM1_ABE_TIMER7_CLKCTRL 0x4a004578 +#define CM1_ABE_TIMER8_CLKCTRL 0x4a004580 +#define CM1_ABE_WDT3_CLKCTRL 0x4a004588 + +/* CM1.DSP register offsets */ +#define DSP_CLKSTCTRL 0x4a004400 +#define DSP_DSP_CLKCTRL 0x4a004420 + +/* CM2.CKGEN module registers */ +#define CM_CLKSEL_DUCATI_ISS_ROOT 0x4a008100 +#define CM_CLKSEL_USB_60MHz 0x4a008104 +#define CM_SCALE_FCLK 0x4a008108 +#define CM_CORE_DVFS_PERF1 0x4a008110 +#define CM_CORE_DVFS_PERF2 0x4a008114 +#define CM_CORE_DVFS_PERF3 0x4a008118 +#define CM_CORE_DVFS_PERF4 0x4a00811c +#define CM_CORE_DVFS_CURRENT 0x4a008124 +#define CM_IVA_DVFS_PERF_TESLA 0x4a008128 +#define CM_IVA_DVFS_PERF_IVAHD 0x4a00812c +#define CM_IVA_DVFS_PERF_ABE 0x4a008130 +#define CM_IVA_DVFS_CURRENT 0x4a008138 +#define CM_CLKMODE_DPLL_PER 0x4a008140 +#define CM_IDLEST_DPLL_PER 0x4a008144 +#define CM_AUTOIDLE_DPLL_PER 0x4a008148 +#define CM_CLKSEL_DPLL_PER 0x4a00814c +#define CM_DIV_M2_DPLL_PER 0x4a008150 +#define CM_DIV_M3_DPLL_PER 0x4a008154 +#define CM_DIV_M4_DPLL_PER 0x4a008158 +#define CM_DIV_M5_DPLL_PER 0x4a00815c +#define CM_DIV_M6_DPLL_PER 0x4a008160 +#define CM_DIV_M7_DPLL_PER 0x4a008164 +#define CM_SSC_DELTAMSTEP_DPLL_PER 0x4a008168 +#define CM_SSC_MODFREQDIV_DPLL_PER 0x4a00816c +#define CM_EMU_OVERRIDE_DPLL_PER 0x4a008170 +#define CM_CLKMODE_DPLL_USB 0x4a008180 +#define CM_IDLEST_DPLL_USB 0x4a008184 +#define CM_AUTOIDLE_DPLL_USB 0x4a008188 +#define CM_CLKSEL_DPLL_USB 0x4a00818c +#define CM_DIV_M2_DPLL_USB 0x4a008190 +#define CM_SSC_DELTAMSTEP_DPLL_USB 0x4a0081a8 +#define CM_SSC_MODFREQDIV_DPLL_USB 0x4a0081ac +#define CM_CLKDCOLDO_DPLL_USB 0x4a0081b4 +#define CM_CLKMODE_DPLL_UNIPRO 0x4a0081c0 +#define CM_IDLEST_DPLL_UNIPRO 0x4a0081c4 +#define CM_AUTOIDLE_DPLL_UNIPRO 0x4a0081c8 +#define CM_CLKSEL_DPLL_UNIPRO 0x4a0081cc +#define CM_DIV_M2_DPLL_UNIPRO 0x4a0081d0 +#define CM_SSC_DELTAMSTEP_DPLL_UNIPRO 0x4a0081e8 +#define CM_SSC_MODFREQDIV_DPLL_UNIPRO 0x4a0081ec + +/* CM2.CORE module registers */ +#define CM_L3_1_CLKSTCTRL 0x4a008700 +#define CM_L3_1_DYNAMICDEP 0x4a008708 +#define CM_L3_1_L3_1_CLKCTRL 0x4a008720 +#define CM_L3_2_CLKSTCTRL 0x4a008800 +#define CM_L3_2_DYNAMICDEP 0x4a008808 +#define CM_L3_2_L3_2_CLKCTRL 0x4a008820 +#define CM_L3_2_GPMC_CLKCTRL 0x4a008828 +#define CM_L3_2_OCMC_RAM_CLKCTRL 0x4a008830 +#define CM_DUCATI_CLKSTCTRL 0x4a008900 +#define CM_DUCATI_STATICDEP 0x4a008904 +#define CM_DUCATI_DYNAMICDEP 0x4a008908 +#define CM_DUCATI_DUCATI_CLKCTRL 0x4a008920 +#define CM_SDMA_CLKSTCTRL 0x4a008a00 +#define CM_SDMA_STATICDEP 0x4a008a04 +#define CM_SDMA_DYNAMICDEP 0x4a008a08 +#define CM_SDMA_SDMA_CLKCTRL 0x4a008a20 +#define CM_MEMIF_CLKSTCTRL 0x4a008b00 +#define CM_MEMIF_DMM_CLKCTRL 0x4a008b20 +#define CM_MEMIF_EMIF_FW_CLKCTRL 0x4a008b28 +#define CM_MEMIF_EMIF_1_CLKCTRL 0x4a008b30 +#define CM_MEMIF_EMIF_2_CLKCTRL 0x4a008b38 +#define CM_MEMIF_DLL_CLKCTRL 0x4a008b40 +#define CM_MEMIF_EMIF_H1_CLKCTRL 0x4a008b50 +#define CM_MEMIF_EMIF_H2_CLKCTRL 0x4a008b58 +#define CM_MEMIF_DLL_H_CLKCTRL 0x4a008b60 +#define CM_D2D_CLKSTCTRL 0x4a008c00 +#define CM_D2D_STATICDEP 0x4a008c04 +#define CM_D2D_DYNAMICDEP 0x4a008c08 +#define CM_D2D_SAD2D_CLKCTRL 0x4a008c20 +#define CM_D2D_MODEM_ICR_CLKCTRL 0x4a008c28 +#define CM_D2D_SAD2D_FW_CLKCTRL 0x4a008c30 +#define CM_L4CFG_CLKSTCTRL 0x4a008d00 +#define CM_L4CFG_DYNAMICDEP 0x4a008d08 +#define CM_L4CFG_L4_CFG_CLKCTRL 0x4a008d20 +#define CM_L4CFG_HW_SEM_CLKCTRL 0x4a008d28 +#define CM_L4CFG_MAILBOX_CLKCTRL 0x4a008d30 +#define CM_L4CFG_SAR_ROM_CLKCTRL 0x4a008d38 +#define CM_L3INSTR_CLKSTCTRL 0x4a008e00 +#define CM_L3INSTR_L3_3_CLKCTRL 0x4a008e20 +#define CM_L3INSTR_L3_INSTR_CLKCTRL 0x4a008e28 +#define CM_L3INSTR_OCP_WP1_CLKCTRL 0x4a008e40 + +/* CM2.L4PER register offsets */ +#define CM_L4PER_CLKSTCTRL 0x4a009400 +#define CM_L4PER_DYNAMICDEP 0x4a009408 +#define CM_L4PER_ADC_CLKCTRL 0x4a009420 +#define CM_L4PER_DMTIMER10_CLKCTRL 0x4a009428 +#define CM_L4PER_DMTIMER11_CLKCTRL 0x4a009430 +#define CM_L4PER_DMTIMER2_CLKCTRL 0x4a009438 +#define CM_L4PER_DMTIMER3_CLKCTRL 0x4a009440 +#define CM_L4PER_DMTIMER4_CLKCTRL 0x4a009448 +#define CM_L4PER_DMTIMER9_CLKCTRL 0x4a009450 +#define CM_L4PER_ELM_CLKCTRL 0x4a009458 +#define CM_L4PER_GPIO2_CLKCTRL 0x4a009460 +#define CM_L4PER_GPIO3_CLKCTRL 0x4a009468 +#define CM_L4PER_GPIO4_CLKCTRL 0x4a009470 +#define CM_L4PER_GPIO5_CLKCTRL 0x4a009478 +#define CM_L4PER_GPIO6_CLKCTRL 0x4a009480 +#define CM_L4PER_HDQ1W_CLKCTRL 0x4a009488 +#define CM_L4PER_HECC1_CLKCTRL 0x4a009490 +#define CM_L4PER_HECC2_CLKCTRL 0x4a009498 +#define CM_L4PER_I2C1_CLKCTRL 0x4a0094a0 +#define CM_L4PER_I2C2_CLKCTRL 0x4a0094a8 +#define CM_L4PER_I2C3_CLKCTRL 0x4a0094b0 +#define CM_L4PER_I2C4_CLKCTRL 0x4a0094b8 +#define CM_L4PER_L4PER_CLKCTRL 0x4a0094c0 +#define CM_L4PER_MCASP2_CLKCTRL 0x4a0094d0 +#define CM_L4PER_MCASP3_CLKCTRL 0x4a0094d8 +#define CM_L4PER_MCBSP4_CLKCTRL 0x4a0094e0 +#define CM_L4PER_MGATE_CLKCTRL 0x4a0094e8 +#define CM_L4PER_MCSPI1_CLKCTRL 0x4a0094f0 +#define CM_L4PER_MCSPI2_CLKCTRL 0x4a0094f8 +#define CM_L4PER_MCSPI3_CLKCTRL 0x4a009500 +#define CM_L4PER_MCSPI4_CLKCTRL 0x4a009508 +#define CM_L4PER_MMCSD3_CLKCTRL 0x4a009520 +#define CM_L4PER_MMCSD4_CLKCTRL 0x4a009528 +#define CM_L4PER_MSPROHG_CLKCTRL 0x4a009530 +#define CM_L4PER_SLIMBUS2_CLKCTRL 0x4a009538 +#define CM_L4PER_UART1_CLKCTRL 0x4a009540 +#define CM_L4PER_UART2_CLKCTRL 0x4a009548 +#define CM_L4PER_UART3_CLKCTRL 0x4a009550 +#define CM_L4PER_UART4_CLKCTRL 0x4a009558 +#define CM_L4PER_MMCSD5_CLKCTRL 0x4a009560 +#define CM_L4PER_I2C5_CLKCTRL 0x4a009568 +#define CM_L4SEC_CLKSTCTRL 0x4a009580 +#define CM_L4SEC_STATICDEP 0x4a009584 +#define CM_L4SEC_DYNAMICDEP 0x4a009588 +#define CM_L4SEC_AES1_CLKCTRL 0x4a0095a0 +#define CM_L4SEC_AES2_CLKCTRL 0x4a0095a8 +#define CM_L4SEC_DES3DES_CLKCTRL 0x4a0095b0 +#define CM_L4SEC_PKAEIP29_CLKCTRL 0x4a0095b8 +#define CM_L4SEC_RNG_CLKCTRL 0x4a0095c0 +#define CM_L4SEC_SHA2MD51_CLKCTRL 0x4a0095c8 +#define CM_L4SEC_CRYPTODMA_CLKCTRL 0x4a0095d8 + +/* CM2.IVAHD */ +#define IVAHD_CLKSTCTRL 0x4a008f00 +#define IVAHD_IVAHD_CLKCTRL 0x4a008f20 +#define IVAHD_SL2_CLKCTRL 0x4a008f28 + +/* CM2.L3INIT */ +#define CM_L3INIT_HSMMC1_CLKCTRL 0x4a009328 +#define CM_L3INIT_HSMMC2_CLKCTRL 0x4a009330 +#define CM_L3INIT_HSI_CLKCTRL 0x4a009338 +#define CM_L3INIT_UNIPRO1_CLKCTRL 0x4a009340 +#define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4a009358 +#define CM_L3INIT_HSUSBOTG_CLKCTRL 0x4a009360 +#define CM_L3INIT_HSUSBTLL_CLKCTRL 0x4a009368 +#define CM_L3INIT_P1500_CLKCTRL 0x4a009378 +#define CM_L3INIT_FSUSB_CLKCTRL 0x4a0093d0 +#define CM_L3INIT_USBPHY_CLKCTRL 0x4a0093e0 + +/* CM2.CAM */ +#define CM_CAM_CLKSTCTRL 0x4a009000 +#define CM_CAM_ISS_CLKCTRL 0x4a009020 +#define CM_CAM_FDIF_CLKCTRL 0x4a009028 + +/* CM2.DSS */ +#define CM_DSS_CLKSTCTRL 0x4a009100 +#define CM_DSS_DSS_CLKCTRL 0x4a009120 +#define CM_DSS_DEISS_CLKCTRL 0x4a009128 + +/* CM2.SGX */ +#define CM_SGX_CLKSTCTRL 0x4a009200 +#define CM_SGX_SGX_CLKCTRL 0x4a009220 + +/* SMX-APE */ +#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) +#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) +#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) + +#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) +#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) +#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) +#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) + +#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) +#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) +#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) + +#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) +#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) +#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) +#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) + +#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) +#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) +#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) + +#define IVA2_REQ_INFO_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x68) +#define IVA2_READ_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x70) +#define IVA2_WRITE_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x78) + +#define IVA2_REQ_INFO_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x88) +#define IVA2_READ_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x90) +#define IVA2_WRITE_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x98) + +#define IVA2_REQ_INFO_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xA8) +#define IVA2_READ_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB0) +#define IVA2_WRITE_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB8) + +/* I2C base */ +#define I2C_BASE1 (OMAP44XX_L4_PER + 0x70000) +#define I2C_BASE2 (OMAP44XX_L4_PER + 0x72000) +#define I2C_BASE3 (OMAP44XX_L4_PER + 0x60000) + +#ifdef CONFIG_LCD + extern void lcd_disable(void); + extern void lcd_panel_disable(void); +#endif + +/* Silicon revisions */ +#define OMAP4430_SILICON_ID_INVALID 0 +#define OMAP4430_ES1_0 1 +#define OMAP4430_ES2_0 2 +#define OMAP4430_ES2_1 3 + +#ifndef __ASSEMBLY__ +/*Functions for silicon revision */ +unsigned int omap_revision(void); +unsigned int cortex_a9_rev(void); + +void big_delay(unsigned int count); +#endif + +#endif diff --git a/include/asm/arch-omap4/mem.h b/include/asm/arch-omap4/mem.h new file mode 100644 index 0000000..e277eca --- /dev/null +++ b/include/asm/arch-omap4/mem.h @@ -0,0 +1,285 @@ +/* + * (C) Copyright 2006-2009 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP44XX_MEM_H_ +#define _OMAP44XX_MEM_H_ + +#ifndef __ASSEMBLY__ + +typedef enum { + STACKED = 0, + IP_DDR = 1, + COMBO_DDR = 2, + IP_SDR = 3, +} mem_t; + +/* Memory that can be connected to GPMC */ +#define GPMC_NOR 0 +#define GPMC_NAND 1 +#define GPMC_MDOC 2 +#define GPMC_ONENAND 3 +#define MMC_NAND 4 +#define MMC_ONENAND 5 +#define GPMC_NONE 6 +#define GPMC_ONENAND_TRY 7 + +#endif + + +/* New and compatability speed defines */ +#if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II)\ + || defined(PRCM_CONFIG_5B) +# define L3_100MHZ /* Use with <= 100MHz SDRAM */ +#elif defined(PRCM_CLK_CFG2_266MHZ) || defined(PRCM_CONFIG_III)\ + || defined(PRCM_CONFIG_5A) +# define L3_133MHZ /* Use with <= 133MHz SDRAM*/ +#elif defined(PRCM_CLK_CFG2_332MHZ) || defined(PRCM_CONFIG_I) \ + || defined(PRCM_CONFIG_2) +# define L3_165MHZ /* Use with <= 165MHz SDRAM (L3=166 on 4430) */ +#endif + +/* + * GPMC settings - + * Definitions is as per the following format + * # define _GPMC_CONFIG + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * STNOR - Intel Strata Flash + * SMNAND - Samsung NAND + * M_NAND - Micron Large page x16 NAND + * MPDB - H4 MPDB board + * SBNOR - Sibley NOR + * ONNAND - Samsung One NAND + * + * include/configs/file.h contains the defn - for all CS we are interested + * #define OMAP44XX_GPMC_CSx PART + * #define OMAP44XX_GPMC_CSx_SIZE Size + * #define OMAP44XX_GPMC_CSx_MAP Map + * Where: + * x - CS number + * PART - Part Name as defined above + * SIZE - how big is the mapping to be + * GPMC_SIZE_128M - 0x8 + * GPMC_SIZE_64M - 0xC + * GPMC_SIZE_32M - 0xE + * GPMC_SIZE_16M - 0xF + * MAP - Map this CS to which address(GPMC address space)- Absolute address + * >>24 before being used. + */ +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#if defined(L3_100MHZ) +# define SMNAND_GPMC_CONFIG1 0x0 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x00000A80 + +# define M_NAND_GPMC_CONFIG1 0x00001800 +# define M_NAND_GPMC_CONFIG2 0x00141400 +# define M_NAND_GPMC_CONFIG3 0x00141400 +# define M_NAND_GPMC_CONFIG4 0x0F010F01 +# define M_NAND_GPMC_CONFIG5 0x010C1414 +# define M_NAND_GPMC_CONFIG6 0x1f0f0A80 + +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x000f0f01 +# define STNOR_GPMC_CONFIG3 0x00050502 +# define STNOR_GPMC_CONFIG4 0x0C060C06 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x1F0F0000 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001F1F00 +# define MPDB_GPMC_CONFIG3 0x00080802 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x031A1F1F +# define MPDB_GPMC_CONFIG6 0x000003C2 +#endif + +#if defined(L3_133MHZ) +# define SMNAND_GPMC_CONFIG1 0x00000800 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x1F0F0A80 +# define SMNAND_GPMC_CONFIG7 0x00000C44 + +# define M_NAND_GPMC_CONFIG1 0x00001800 /* might reuse smnand, with |= 1000 */ +# define M_NAND_GPMC_CONFIG2 0x00141400 +# define M_NAND_GPMC_CONFIG3 0x00141400 +# define M_NAND_GPMC_CONFIG4 0x0F010F01 +# define M_NAND_GPMC_CONFIG5 0x010C1414 +# define M_NAND_GPMC_CONFIG6 0x1F0F0A80 +# define M_NAND_GPMC_CONFIG7 0x00000C44 + +# define STNOR_GPMC_CONFIG1 0x1203 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x10081008 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x1F0F04c4 + +# define SIBNOR_GPMC_CONFIG1 0x1200 +# define SIBNOR_GPMC_CONFIG2 0x001f1f00 +# define SIBNOR_GPMC_CONFIG3 0x00080802 +# define SIBNOR_GPMC_CONFIG4 0x1C091C09 +# define SIBNOR_GPMC_CONFIG5 0x01131F1F +# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 + +/* ES1 SDP and ES1 chip Debug FPGA */ +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x000004C4 + +/* ES2 SDP and ES2 chip Debug FPGA */ +# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 +# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 +# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 +# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 +# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F +# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 + +# define P2_GPMC_CONFIG1 0x0 +# define P2_GPMC_CONFIG2 0x0 +# define P2_GPMC_CONFIG3 0x0 +# define P2_GPMC_CONFIG4 0x0 +# define P2_GPMC_CONFIG5 0x0 +# define P2_GPMC_CONFIG6 0x0 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000c0c01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0c040c04 +# define ONENAND_GPMC_CONFIG5 0x010C1010 +# define ONENAND_GPMC_CONFIG6 0x1F060000 + +#endif /* endif L3_133MHZ */ + +#if defined(L3_165MHZ) +# define SMNAND_GPMC_CONFIG1 0x00000800 +# define SMNAND_GPMC_CONFIG2 0x00060600 +# define SMNAND_GPMC_CONFIG3 0x00060401 +# define SMNAND_GPMC_CONFIG4 0x05010801 +# define SMNAND_GPMC_CONFIG5 0x00090B0B +# define SMNAND_GPMC_CONFIG6 0x050001C0 +# define SMNAND_GPMC_CONFIG7 0x00000C44 + +# define M_NAND_GPMC_CONFIG1 0x00001800 +# define M_NAND_GPMC_CONFIG2 0x00141400 +# define M_NAND_GPMC_CONFIG3 0x00141400 +# define M_NAND_GPMC_CONFIG4 0x0F010F01 +# define M_NAND_GPMC_CONFIG5 0x010C1414 +# define M_NAND_GPMC_CONFIG6 0x1F0F0A80 +# define M_NAND_GPMC_CONFIG7 0x00000C44 + +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x11091109 +# define STNOR_GPMC_CONFIG5 0x01141F1F +# define STNOR_GPMC_CONFIG6 0x1F0F04c4 + +# define SIBNOR_GPMC_CONFIG1 0x1200 +# define SIBNOR_GPMC_CONFIG2 0x001f1f00 +# define SIBNOR_GPMC_CONFIG3 0x00080802 +# define SIBNOR_GPMC_CONFIG4 0x1C091C09 +# define SIBNOR_GPMC_CONFIG5 0x01131F1F +# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 + +# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 +# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 +# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 +# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 +# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F +# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1c0b1c0a +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x1F0F04C4 + +# define LAB_ENET_GPMC_CONFIG1 0x00611000 +# define LAB_ENET_GPMC_CONFIG2 0x001F1F01 +# define LAB_ENET_GPMC_CONFIG3 0x00080803 +# define LAB_ENET_GPMC_CONFIG4 0x1D091D09 +# define LAB_ENET_GPMC_CONFIG5 0x041D1F1F +# define LAB_ENET_GPMC_CONFIG6 0x1D0904C4 + +# define P2_GPMC_CONFIG1 0x0 +# define P2_GPMC_CONFIG2 0x0 +# define P2_GPMC_CONFIG3 0x0 +# define P2_GPMC_CONFIG4 0x0 +# define P2_GPMC_CONFIG5 0x0 +# define P2_GPMC_CONFIG6 0x0 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000F0F01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0F040F04 +# define ONENAND_GPMC_CONFIG5 0x010F1010 +# define ONENAND_GPMC_CONFIG6 0x1F060000 + +#endif + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#define PISMO1_NOR 1 +#define PISMO1_NAND 2 +#define PISMO2_CS0 3 +#define PISMO2_CS1 4 +#define PISMO1_ONENAND 5 +#define DBG_MPDB 6 +#define PISMO2_NAND_CS0 7 +#define PISMO2_NAND_CS1 8 + +/* make it readable for the gpmc_init */ +#define PISMO1_NOR_BASE FLASH_BASE +#define PISMO1_NAND_BASE NAND_BASE +#define PISMO2_CS0_BASE PISMO2_MAP1 +#define PISMO1_ONEN_BASE ONENAND_MAP +#define DBG_MPDB_BASE DEBUG_BASE + +#endif /* endif _OMAP44XX_MEM_H_ */ diff --git a/include/asm/arch-omap4/mmc.h b/include/asm/arch-omap4/mmc.h new file mode 100644 index 0000000..8631aae --- /dev/null +++ b/include/asm/arch-omap4/mmc.h @@ -0,0 +1,235 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_H +#define MMC_H + +#include "mmc_host_def.h" + +/* Responses */ +#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK) +#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) + +/* All supported commands */ +#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD7_DESELECT (INDEX(7) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE) +#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) +#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) + +#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16) +#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16) +#define MMC_DSR_DEFAULT (0x0404) +#define SD_CMD8_CHECK_PATTERN (0xAA) +#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8) + +/* Clock Configurations and Macros */ + +#define MMC_CLOCK_REFERENCE (96) +#define MMC_RELATIVE_CARD_ADDRESS (0x1234) +#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80) +#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400) +#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1) +#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u)) + +#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29) +#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29) +#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29) + +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30) +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30) +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30) + +#define MMC_SD2_CSD_C_SIZE_LSB_MASK (0xFFFF) +#define MMC_SD2_CSD_C_SIZE_MSB_MASK (0x003F) +#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET (16) +#define MMC_CSD_C_SIZE_LSB_MASK (0x0003) +#define MMC_CSD_C_SIZE_MSB_MASK (0x03FF) +#define MMC_CSD_C_SIZE_MSB_OFFSET (2) + +#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0) +#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3) +#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0) +#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3) +#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3) + +typedef struct { + unsigned not_used:1; + unsigned crc:7; + unsigned ecc:2; + unsigned file_format:2; + unsigned tmp_write_protect:1; + unsigned perm_write_protect:1; + unsigned copy:1; + unsigned file_format_grp:1; + unsigned content_prot_app:1; + unsigned reserved_1:4; + unsigned write_bl_partial:1; + unsigned write_bl_len:4; + unsigned r2w_factor:3; + unsigned default_ecc:2; + unsigned wp_grp_enable:1; + unsigned wp_grp_size:5; + unsigned erase_grp_mult:5; + unsigned erase_grp_size:5; + unsigned c_size_mult:3; + unsigned vdd_w_curr_max:3; + unsigned vdd_w_curr_min:3; + unsigned vdd_r_curr_max:3; + unsigned vdd_r_curr_min:3; + unsigned c_size_lsb:2; + unsigned c_size_msb:10; + unsigned reserved_2:2; + unsigned dsr_imp:1; + unsigned read_blk_misalign:1; + unsigned write_blk_misalign:1; + unsigned read_bl_partial:1; + unsigned read_bl_len:4; + unsigned ccc:12; + unsigned tran_speed:8; + unsigned nsac:8; + unsigned taac:8; + unsigned reserved_3:2; + unsigned spec_vers:4; + unsigned csd_structure:2; +} mmc_csd_reg_t; + +/* csd for sd2.0 */ +typedef struct { + unsigned not_used:1; + unsigned crc:7; + unsigned reserved_1:2; + unsigned file_format:2; + unsigned tmp_write_protect:1; + unsigned perm_write_protect:1; + unsigned copy:1; + unsigned file_format_grp:1; + unsigned reserved_2:5; + unsigned write_bl_partial:1; + unsigned write_bl_len:4; + unsigned r2w_factor:3; + unsigned reserved_3:2; + unsigned wp_grp_enable:1; + unsigned wp_grp_size:7; + unsigned sector_size:7; + unsigned erase_blk_len:1; + unsigned reserved_4:1; + unsigned c_size_lsb:16; + unsigned c_size_msb:6; + unsigned reserved_5:6; + unsigned dsr_imp:1; + unsigned read_blk_misalign:1; + unsigned write_blk_misalign:1; + unsigned read_bl_partial:1; + unsigned read_bl_len:4; + unsigned ccc:12; + unsigned tran_speed:8; + unsigned nsac:8; + unsigned taac:8; + unsigned reserved_6:6; + unsigned csd_structure:2; +} mmc_sd2_csd_reg_t; + +/* extended csd - 512 bytes long */ +typedef struct { + unsigned char reserved_1[181]; + unsigned char erasedmemorycontent; + unsigned char reserved_2; + unsigned char buswidthmode; + unsigned char reserved_3; + unsigned char highspeedinterfacetiming; + unsigned char reserved_4; + unsigned char powerclass; + unsigned char reserved_5; + unsigned char commandsetrevision; + unsigned char reserved_6; + unsigned char commandset; + unsigned char extendedcsdrevision; + unsigned char reserved_7; + unsigned char csdstructureversion; + unsigned char reserved_8; + unsigned char cardtype; + unsigned char reserved_9[3]; + unsigned char powerclass_52mhz_1_95v; + unsigned char powerclass_26mhz_1_95v; + unsigned char powerclass_52mhz_3_6v; + unsigned char powerclass_26mhz_3_6v; + unsigned char reserved_10; + unsigned char minreadperf_4b_26mhz; + unsigned char minwriteperf_4b_26mhz; + unsigned char minreadperf_8b_26mhz_4b_52mhz; + unsigned char minwriteperf_8b_26mhz_4b_52mhz; + unsigned char minreadperf_8b_52mhz; + unsigned char minwriteperf_8b_52mhz; + unsigned char reserved_11; + unsigned int sectorcount; + unsigned char reserved_12[288]; + unsigned char supportedcommandsets; + unsigned char reserved_13[7]; +} mmc_extended_csd_reg_t; + +/* mmc sd responce */ +typedef struct { + unsigned int ocr; +} mmc_resp_r3; + +typedef struct { + unsigned short cardstatus; + unsigned short newpublishedrca; +} mmc_resp_r6; + +extern mmc_card_data mmc_dev; + +unsigned char mmc_lowlevel_init(void); +unsigned char mmc_send_command(unsigned int cmd, unsigned int arg, + unsigned int *response); +unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd); +unsigned char mmc_set_opendrain(unsigned char state); +unsigned char mmc_read_data(unsigned int *output_buf); + +#endif /* MMC_H */ diff --git a/include/asm/arch-omap4/mmc_host_def.h b/include/asm/arch-omap4/mmc_host_def.h new file mode 100644 index 0000000..0abc841 --- /dev/null +++ b/include/asm/arch-omap4/mmc_host_def.h @@ -0,0 +1,168 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_HOST_DEFINITIONS_H +#define MMC_HOST_DEFINITIONS_H + +#define OMAP_HSMMC1_BASE 0x4809C100 +#define OMAP_HSMMC2_BASE 0x480B4100 + +/* + * OMAP HSMMC register definitions + */ + +#define OMAP_HSMMC_SYSCONFIG (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x010)) +#define OMAP_HSMMC_SYSSTATUS (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x014)) +#define OMAP_HSMMC_CON (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x02C)) +#define OMAP_HSMMC_BLK (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x104)) +#define OMAP_HSMMC_ARG (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x108)) +#define OMAP_HSMMC_CMD (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x10C)) +#define OMAP_HSMMC_RSP10 (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x110)) +#define OMAP_HSMMC_RSP32 (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x114)) +#define OMAP_HSMMC_RSP54 (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x118)) +#define OMAP_HSMMC_RSP76 (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x11C)) +#define OMAP_HSMMC_DATA (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x120)) +#define OMAP_HSMMC_PSTATE (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x124)) +#define OMAP_HSMMC_HCTL (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x128)) +#define OMAP_HSMMC_SYSCTL (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x12C)) +#define OMAP_HSMMC_STAT (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x130)) +#define OMAP_HSMMC_IE (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x134)) +#define OMAP_HSMMC_CAPA (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x140)) + +/* T2 Register definitions */ +#define CONTROL_PBIAS_LITE (*(volatile unsigned int *) 0x4A100600) +#define CONTROL_CONF_MMC1 (*(volatile unsigned int *) 0x4A100628) + +/* + * OMAP HS MMC Bit definitions + */ +#define MMC_SOFTRESET (0x1 << 1) +#define RESETDONE (0x1 << 0) +#define NOOPENDRAIN (0x0 << 0) +#define OPENDRAIN (0x1 << 0) +#define OD (0x1 << 0) +#define INIT_NOINIT (0x0 << 1) +#define INIT_INITSTREAM (0x1 << 1) +#define HR_NOHOSTRESP (0x0 << 2) +#define STR_BLOCK (0x0 << 3) +#define MODE_FUNC (0x0 << 4) +#define DW8_1_4BITMODE (0x0 << 5) +#define MIT_CTO (0x0 << 6) +#define CDP_ACTIVEHIGH (0x0 << 7) +#define WPP_ACTIVEHIGH (0x0 << 8) +#define RESERVED_MASK (0x3 << 9) +#define CTPL_MMC_SD (0x0 << 11) +#define BLEN_512BYTESLEN (0x200 << 0) +#define NBLK_STPCNT (0x0 << 16) +#define DE_DISABLE (0x0 << 0) +#define BCE_DISABLE (0x0 << 1) +#define ACEN_DISABLE (0x0 << 2) +#define DDIR_OFFSET (4) +#define DDIR_MASK (0x1 << 4) +#define DDIR_WRITE (0x0 << 4) +#define DDIR_READ (0x1 << 4) +#define MSBS_SGLEBLK (0x0 << 5) +#define RSP_TYPE_OFFSET (16) +#define RSP_TYPE_MASK (0x3 << 16) +#define RSP_TYPE_NORSP (0x0 << 16) +#define RSP_TYPE_LGHT136 (0x1 << 16) +#define RSP_TYPE_LGHT48 (0x2 << 16) +#define RSP_TYPE_LGHT48B (0x3 << 16) +#define CCCE_NOCHECK (0x0 << 19) +#define CCCE_CHECK (0x1 << 19) +#define CICE_NOCHECK (0x0 << 20) +#define CICE_CHECK (0x1 << 20) +#define DP_OFFSET (21) +#define DP_MASK (0x1 << 21) +#define DP_NO_DATA (0x0 << 21) +#define DP_DATA (0x1 << 21) +#define CMD_TYPE_NORMAL (0x0 << 22) +#define INDEX_OFFSET (24) +#define INDEX_MASK (0x3f << 24) +#define INDEX(i) (i << 24) +#define DATI_MASK (0x1 << 1) +#define DATI_CMDDIS (0x1 << 1) +#define DTW_1_BITMODE (0x0 << 1) +#define DTW_4_BITMODE (0x1 << 1) +#define SDBP_PWROFF (0x0 << 8) +#define SDBP_PWRON (0x1 << 8) +#define SDVS_1V8 (0x5 << 9) +#define SDVS_3V0 (0x6 << 9) +#define ICE_MASK (0x1 << 0) +#define ICE_STOP (0x0 << 0) +#define ICS_MASK (0x1 << 1) +#define ICS_NOTREADY (0x0 << 1) +#define ICE_OSCILLATE (0x1 << 0) +#define CEN_MASK (0x1 << 2) +#define CEN_DISABLE (0x0 << 2) +#define CEN_ENABLE (0x1 << 2) +#define CLKD_OFFSET (6) +#define CLKD_MASK (0x3FF << 6) +#define DTO_MASK (0xF << 16) +#define DTO_15THDTO (0xE << 16) +#define SOFTRESETALL (0x1 << 24) +#define CC_MASK (0x1 << 0) +#define TC_MASK (0x1 << 1) +#define BWR_MASK (0x1 << 4) +#define BRR_MASK (0x1 << 5) +#define ERRI_MASK (0x1 << 15) +#define IE_CC (0x01 << 0) +#define IE_TC (0x01 << 1) +#define IE_BWR (0x01 << 4) +#define IE_BRR (0x01 << 5) +#define IE_CTO (0x01 << 16) +#define IE_CCRC (0x01 << 17) +#define IE_CEB (0x01 << 18) +#define IE_CIE (0x01 << 19) +#define IE_DTO (0x01 << 20) +#define IE_DCRC (0x01 << 21) +#define IE_DEB (0x01 << 22) +#define IE_CERR (0x01 << 28) +#define IE_BADA (0x01 << 29) + +#define VS30_3V0SUP (1 << 25) +#define VS18_1V8SUP (1 << 26) + +/* Driver definitions */ +#define MMCSD_SECTOR_SIZE (512) +#define MMC_CARD 0 +#define SD_CARD 1 +#define BYTE_MODE 0 +#define SECTOR_MODE 1 +#define CLK_INITSEQ 0 +#define CLK_400KHZ 1 +#define CLK_MISC 2 + +typedef struct { + unsigned int card_type; + unsigned int version; + unsigned int mode; + unsigned int size; + unsigned int RCA; +} mmc_card_data; + +#define mmc_reg_out(addr, mask, val) \ + (addr) = (((addr)) & (~(mask)) ) | ( (val) & (mask)); + +#endif /* MMC_HOST_DEFINITIONS_H */ diff --git a/include/asm/arch-omap4/mux.h b/include/asm/arch-omap4/mux.h new file mode 100644 index 0000000..d6505bf --- /dev/null +++ b/include/asm/arch-omap4/mux.h @@ -0,0 +1,392 @@ +/* Copyright 2009 + * Texas Instruments, + * Syed Rafiuddin + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP4430_MUX_H_ +#define _OMAP4430_MUX_H_ + +/* + * OFF_PD - Off mode pull type down + * OFF_PU - Off mode pull type up + * OFF_OUT_PTD - Off Mode Mux low for OUT + * OFF_OUT_PTU - Off Mode Mux high for OUT + * OFF_IN - Off Mode Mux set to IN + * OFF_OUT - Off Mode Mux set to OUT + * OFF_EN - Off Mode Mux Enable + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + */ +#ifdef CONFIG_OFF_PADCONF +#define OFF_PD (1 << 12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (2 << 10) +#define OFF_IN (1 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (1 << 9) +#else +#define OFF_PD (0 << 12) +#define OFF_PU (0 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (0 << 10) +#define OFF_IN (0 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (0 << 9) +#endif + +#define IEN (1 << 8) +#define IDIS (0 << 8) +#define PTU (3 << 3) +#define PTD (1 << 3) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif /* #ifdef CONFIG_OFF_PADCONF */ + +/* + * To get the actual address the offset has to added + * with OMAP44XX_CTRL_BASE to get the actual address + */ + +/* OMAP4 SPECIFIC PADCONF REGISTERS */ + +#define CONTROL_PADCONF_CORE_REVISION 0x0000 +#define CONTROL_PADCONF_CORE_HWINFO 0x0004 +#define CONTROL_PADCONF_CORE_SYSCONFIG 0x0010 +#define CONTROL_PADCONF_GPMC_AD0 0x0040 +#define CONTROL_PADCONF_GPMC_AD1 0x0042 +#define CONTROL_PADCONF_GPMC_AD2 0x0044 +#define CONTROL_PADCONF_GPMC_AD3 0x0046 +#define CONTROL_PADCONF_GPMC_AD4 0x0048 +#define CONTROL_PADCONF_GPMC_AD5 0x004A +#define CONTROL_PADCONF_GPMC_AD6 0x004C +#define CONTROL_PADCONF_GPMC_AD7 0x004E +#define CONTROL_PADCONF_GPMC_AD8 0x0050 +#define CONTROL_PADCONF_GPMC_AD9 0x0052 +#define CONTROL_PADCONF_GPMC_AD10 0x0054 +#define CONTROL_PADCONF_GPMC_AD11 0x0056 +#define CONTROL_PADCONF_GPMC_AD12 0x0058 +#define CONTROL_PADCONF_GPMC_AD13 0x005A +#define CONTROL_PADCONF_GPMC_AD14 0x005C +#define CONTROL_PADCONF_GPMC_AD15 0x005E +#define CONTROL_PADCONF_GPMC_A16 0x0060 +#define CONTROL_PADCONF_GPMC_A17 0x0062 +#define CONTROL_PADCONF_GPMC_A18 0x0064 +#define CONTROL_PADCONF_GPMC_A19 0x0066 +#define CONTROL_PADCONF_GPMC_A20 0x0068 +#define CONTROL_PADCONF_GPMC_A21 0x006A +#define CONTROL_PADCONF_GPMC_A22 0x006C +#define CONTROL_PADCONF_GPMC_A23 0x006E +#define CONTROL_PADCONF_GPMC_A24 0x0070 +#define CONTROL_PADCONF_GPMC_A25 0x0072 +#define CONTROL_PADCONF_GPMC_NCS0 0x0074 +#define CONTROL_PADCONF_GPMC_NCS1 0x0076 +#define CONTROL_PADCONF_GPMC_NCS2 0x0078 +#define CONTROL_PADCONF_GPMC_NCS3 0x007A +#define CONTROL_PADCONF_GPMC_NWP 0x007C +#define CONTROL_PADCONF_GPMC_CLK 0x007E +#define CONTROL_PADCONF_GPMC_NADV_ALE 0x0080 +#define CONTROL_PADCONF_GPMC_NOE 0x0082 +#define CONTROL_PADCONF_GPMC_NWE 0x0084 +#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x0086 +#define CONTROL_PADCONF_GPMC_NBE1 0x0088 +#define CONTROL_PADCONF_GPMC_WAIT0 0x008A +#define CONTROL_PADCONF_GPMC_WAIT1 0x008C +#define CONTROL_PADCONF_C2C_DATA11 0x008E +#define CONTROL_PADCONF_C2C_DATA12 0x0090 +#define CONTROL_PADCONF_C2C_DATA13 0x0092 +#define CONTROL_PADCONF_C2C_DATA14 0x0094 +#define CONTROL_PADCONF_C2C_DATA15 0x0096 +#define CONTROL_PADCONF_HDMI_HPD 0x0098 +#define CONTROL_PADCONF_HDMI_CEC 0x009A +#define CONTROL_PADCONF_HDMI_DDC_SCL 0x009C +#define CONTROL_PADCONF_HDMI_DDC_SDA 0x009E +#define CONTROL_PADCONF_CSI21_DX0 0x00A0 +#define CONTROL_PADCONF_CSI21_DY0 0x00A2 +#define CONTROL_PADCONF_CSI21_DX1 0x00A4 +#define CONTROL_PADCONF_CSI21_DY1 0x00A6 +#define CONTROL_PADCONF_CSI21_DX2 0x00A8 +#define CONTROL_PADCONF_CSI21_DY2 0x00AA +#define CONTROL_PADCONF_CSI21_DX3 0x00AC +#define CONTROL_PADCONF_CSI21_DY3 0x00AE +#define CONTROL_PADCONF_CSI21_DX4 0x00B0 +#define CONTROL_PADCONF_CSI21_DY4 0x00B2 +#define CONTROL_PADCONF_CSI22_DX0 0x00B4 +#define CONTROL_PADCONF_CSI22_DY0 0x00B6 +#define CONTROL_PADCONF_CSI22_DX1 0x00B8 +#define CONTROL_PADCONF_CSI22_DY1 0x00BA +#define CONTROL_PADCONF_CAM_SHUTTER 0x00BC +#define CONTROL_PADCONF_CAM_STROBE 0x00BE +#define CONTROL_PADCONF_CAM_GLOBALRESET 0x00C0 +#define CONTROL_PADCONF_USBB1_ULPITLL_CLK 0x00C2 +#define CONTROL_PADCONF_USBB1_ULPITLL_STP 0x00C4 +#define CONTROL_PADCONF_USBB1_ULPITLL_DIR 0x00C6 +#define CONTROL_PADCONF_USBB1_ULPITLL_NXT 0x00C8 +#define CONTROL_PADCONF_USBB1_ULPITLL_DAT0 0x00CA +#define CONTROL_PADCONF_USBB1_ULPITLL_DAT1 0x00CC +#define CONTROL_PADCONF_USBB1_ULPITLL_DAT2 0x00CE +#define CONTROL_PADCONF_USBB1_ULPITLL_DAT3 0x00D0 +#define CONTROL_PADCONF_USBB1_ULPITLL_DAT4 0x00D2 +#define CONTROL_PADCONF_USBB1_ULPITLL_DAT5 0x00D4 +#define CONTROL_PADCONF_USBB1_ULPITLL_DAT6 0x00D6 +#define CONTROL_PADCONF_USBB1_ULPITLL_DAT7 0x00D8 +#define CONTROL_PADCONF_USBB1_HSIC_DATA 0x00DA +#define CONTROL_PADCONF_USBB1_HSIC_STROBE 0x00DC +#define CONTROL_PADCONF_USBC1_ICUSB_DP 0x00DE +#define CONTROL_PADCONF_USBC1_ICUSB_DM 0x00E0 +#define CONTROL_PADCONF_SDMMC1_CLK 0x00E2 +#define CONTROL_PADCONF_SDMMC1_CMD 0x00E4 +#define CONTROL_PADCONF_SDMMC1_DAT0 0x00E6 +#define CONTROL_PADCONF_SDMMC1_DAT1 0x00E8 +#define CONTROL_PADCONF_SDMMC1_DAT2 0x00EA +#define CONTROL_PADCONF_SDMMC1_DAT3 0x00EC +#define CONTROL_PADCONF_SDMMC1_DAT4 0x00EE +#define CONTROL_PADCONF_SDMMC1_DAT5 0x00F0 +#define CONTROL_PADCONF_SDMMC1_DAT6 0x00F2 +#define CONTROL_PADCONF_SDMMC1_DAT7 0x00F4 +#define CONTROL_PADCONF_ABE_MCBSP2_CLKX 0x00F6 +#define CONTROL_PADCONF_ABE_MCBSP2_DR 0x00F8 +#define CONTROL_PADCONF_ABE_MCBSP2_DX 0x00FA +#define CONTROL_PADCONF_ABE_MCBSP2_FSX 0x00FC +#define CONTROL_PADCONF_ABE_MCBSP1_CLKX 0x00FE +#define CONTROL_PADCONF_ABE_MCBSP1_DR 0x0100 +#define CONTROL_PADCONF_ABE_MCBSP1_DX 0x0102 +#define CONTROL_PADCONF_ABE_MCBSP1_FSX 0x0104 +#define CONTROL_PADCONF_ABE_PDM_UL_DATA 0x0106 +#define CONTROL_PADCONF_ABE_PDM_DL_DATA 0x0108 +#define CONTROL_PADCONF_ABE_PDM_FRAME 0x010A +#define CONTROL_PADCONF_ABE_PDM_LB_CLK 0x010C +#define CONTROL_PADCONF_ABE_CLKS 0x010E +#define CONTROL_PADCONF_ABE_DMIC_CLK1 0x0110 +#define CONTROL_PADCONF_ABE_DMIC_DIN1 0x0112 +#define CONTROL_PADCONF_ABE_DMIC_DIN2 0x0114 +#define CONTROL_PADCONF_ABE_DMIC_DIN3 0x0116 +#define CONTROL_PADCONF_UART2_CTS 0x0118 +#define CONTROL_PADCONF_UART2_RTS 0x011A +#define CONTROL_PADCONF_UART2_RX 0x011C +#define CONTROL_PADCONF_UART2_TX 0x011E +#define CONTROL_PADCONF_HDQ_SIO 0x0120 +#define CONTROL_PADCONF_I2C1_SCL 0x0122 +#define CONTROL_PADCONF_I2C1_SDA 0x0124 +#define CONTROL_PADCONF_I2C2_SCL 0x0126 +#define CONTROL_PADCONF_I2C2_SDA 0x0128 +#define CONTROL_PADCONF_I2C3_SCL 0x012A +#define CONTROL_PADCONF_I2C3_SDA 0x012C +#define CONTROL_PADCONF_I2C4_SCL 0x012E +#define CONTROL_PADCONF_I2C4_SDA 0x0130 +#define CONTROL_PADCONF_MCSPI1_CLK 0x0132 +#define CONTROL_PADCONF_MCSPI1_SOMI 0x0134 +#define CONTROL_PADCONF_MCSPI1_SIMO 0x0136 +#define CONTROL_PADCONF_MCSPI1_CS0 0x0138 +#define CONTROL_PADCONF_MCSPI1_CS1 0x013A +#define CONTROL_PADCONF_MCSPI1_CS2 0x013C +#define CONTROL_PADCONF_MCSPI1_CS3 0x013E +#define CONTROL_PADCONF_UART3_CTS_RCTX 0x0140 +#define CONTROL_PADCONF_UART3_RTS_SD 0x0142 +#define CONTROL_PADCONF_UART3_RX_IRRX 0x0144 +#define CONTROL_PADCONF_UART3_TX_IRTX 0x0146 +#define CONTROL_PADCONF_SDMMC5_CLK 0x0148 +#define CONTROL_PADCONF_SDMMC5_CMD 0x014A +#define CONTROL_PADCONF_SDMMC5_DAT0 0x014C +#define CONTROL_PADCONF_SDMMC5_DAT1 0x014E +#define CONTROL_PADCONF_SDMMC5_DAT2 0x0150 +#define CONTROL_PADCONF_SDMMC5_DAT3 0x0152 +#define CONTROL_PADCONF_MCSPI4_CLK 0x0154 +#define CONTROL_PADCONF_MCSPI4_SIMO 0x0156 +#define CONTROL_PADCONF_MCSPI4_SOMI 0x0158 +#define CONTROL_PADCONF_MCSPI4_CS0 0x015A +#define CONTROL_PADCONF_UART4_RX 0x015C +#define CONTROL_PADCONF_UART4_TX 0x015E +#define CONTROL_PADCONF_USBB2_ULPITLL_CLK 0x0160 +#define CONTROL_PADCONF_USBB2_ULPITLL_STP 0x0162 +#define CONTROL_PADCONF_USBB2_ULPITLL_DIR 0x0164 +#define CONTROL_PADCONF_USBB2_ULPITLL_NXT 0x0166 +#define CONTROL_PADCONF_USBB2_ULPITLL_DAT0 0x0168 +#define CONTROL_PADCONF_USBB2_ULPITLL_DAT1 0x016A +#define CONTROL_PADCONF_USBB2_ULPITLL_DAT2 0x016C +#define CONTROL_PADCONF_USBB2_ULPITLL_DAT3 0x016E +#define CONTROL_PADCONF_USBB2_ULPITLL_DAT4 0x0170 +#define CONTROL_PADCONF_USBB2_ULPITLL_DAT5 0x0172 +#define CONTROL_PADCONF_USBB2_ULPITLL_DAT6 0x0174 +#define CONTROL_PADCONF_USBB2_ULPITLL_DAT7 0x0176 +#define CONTROL_PADCONF_USBB2_HSIC_DATA 0x0178 +#define CONTROL_PADCONF_USBB2_HSIC_STROBE 0x017A +#define CONTROL_PADCONF_UNIPRO_TX0 0x017C +#define CONTROL_PADCONF_UNIPRO_TY0 0x017E +#define CONTROL_PADCONF_UNIPRO_TX1 0x0180 +#define CONTROL_PADCONF_UNIPRO_TY1 0x0182 +#define CONTROL_PADCONF_UNIPRO_TX2 0x0184 +#define CONTROL_PADCONF_UNIPRO_TY2 0x0186 +#define CONTROL_PADCONF_UNIPRO_RX0 0x0188 +#define CONTROL_PADCONF_UNIPRO_RY0 0x018A +#define CONTROL_PADCONF_UNIPRO_RX1 0x018C +#define CONTROL_PADCONF_UNIPRO_RY1 0x018E +#define CONTROL_PADCONF_UNIPRO_RX2 0x0190 +#define CONTROL_PADCONF_UNIPRO_RY2 0x0192 +#define CONTROL_PADCONF_USBA0_OTG_CE 0x0194 +#define CONTROL_PADCONF_USBA0_OTG_DP 0x0196 +#define CONTROL_PADCONF_USBA0_OTG_DM 0x0198 +#define CONTROL_PADCONF_FREF_CLK1_OUT 0x019A +#define CONTROL_PADCONF_FREF_CLK2_OUT 0x019C +#define CONTROL_PADCONF_SYS_NIRQ1 0x019E +#define CONTROL_PADCONF_SYS_NIRQ2 0x01A0 +#define CONTROL_PADCONF_SYS_BOOT0 0x01A2 +#define CONTROL_PADCONF_SYS_BOOT1 0x01A4 +#define CONTROL_PADCONF_SYS_BOOT2 0x01A6 +#define CONTROL_PADCONF_SYS_BOOT3 0x01A8 +#define CONTROL_PADCONF_SYS_BOOT4 0x01AA +#define CONTROL_PADCONF_SYS_BOOT5 0x01AC +#define CONTROL_PADCONF_DPM_EMU0 0x01AE +#define CONTROL_PADCONF_DPM_EMU1 0x01B0 +#define CONTROL_PADCONF_DPM_EMU2 0x01B2 +#define CONTROL_PADCONF_DPM_EMU3 0x01B4 +#define CONTROL_PADCONF_DPM_EMU4 0x01B6 +#define CONTROL_PADCONF_DPM_EMU5 0x01B8 +#define CONTROL_PADCONF_DPM_EMU6 0x01BA +#define CONTROL_PADCONF_DPM_EMU7 0x01BC +#define CONTROL_PADCONF_DPM_EMU8 0x01BE +#define CONTROL_PADCONF_DPM_EMU9 0x01C0 +#define CONTROL_PADCONF_DPM_EMU10 0x01C2 +#define CONTROL_PADCONF_DPM_EMU11 0x01C4 +#define CONTROL_PADCONF_DPM_EMU12 0x01C6 +#define CONTROL_PADCONF_DPM_EMU13 0x01C8 +#define CONTROL_PADCONF_DPM_EMU14 0x01CA +#define CONTROL_PADCONF_DPM_EMU15 0x01CC +#define CONTROL_PADCONF_DPM_EMU16 0x01CE +#define CONTROL_PADCONF_DPM_EMU17 0x01D0 +#define CONTROL_PADCONF_DPM_EMU18 0x01D2 +#define CONTROL_PADCONF_DPM_EMU19 0x01D4 +#define CONTROL_PADCONF_WAKEUPEVENT_0 0x01D8 +#define CONTROL_PADCONF_WAKEUPEVENT_1 0x01DC +#define CONTROL_PADCONF_WAKEUPEVENT_2 0x01E0 +#define CONTROL_PADCONF_WAKEUPEVENT_3 0x01E4 +#define CONTROL_PADCONF_WAKEUPEVENT_4 0x01E8 +#define CONTROL_PADCONF_WAKEUPEVENT_5 0x01EC +#define CONTROL_PADCONF_WAKEUPEVENT_6 0x01F0 + +#define CONTROL_PADCONF_GLOBAL 0x05A2 +#define CONTROL_PADCONF_MODE 0x05A4 +#define CONTROL_SMART1IO_PADCONF_0 0x05A8 +#define CONTROL_SMART1IO_PADCONF_1 0x05AC +#define CONTROL_SMART2IO_PADCONF_0 0x05B0 +#define CONTROL_SMART2IO_PADCONF_1 0x05B4 +#define CONTROL_SMART3IO_PADCONF_0 0x05B8 +#define CONTROL_SMART3IO_PADCONF_1 0x05BC +#define CONTROL_SMART3IO_PADCONF_2 0x05C0 +#define CONTROL_USBB_HSIC 0x05C4 +#define CONTROL_SLIMBUS 0x05C8 +#define CONTROL_PBIASLITE 0x0600 +#define CONTROL_I2C_0 0x0604 +#define CONTROL_CAMERA_RX 0x0608 +#define CONTROL_AVDAC 0x060C +#define CONTROL_HDMI_TX_PHY 0x0610 +#define CONTROL_MMC2 0x0614 +#define CONTROL_DSIPHY 0x0618 +#define CONTROL_MCBSPLP 0x061C +#define CONTROL_USB2PHYCORE 0x0620 +#define CONTROL_I2C_1 0x0624 +#define CONTROL_MMC1 0x0628 +#define CONTROL_HSI 0x062C +#define CONTROL_USB 0x0630 +#define CONTROL_HDQ 0x0634 +#define CONTROL_LPDDR2IO1_0 0x0638 +#define CONTROL_LPDDR2IO1_1 0x063C +#define CONTROL_LPDDR2IO1_2 0x0640 +#define CONTROL_LPDDR2IO1_3 0x0644 +#define CONTROL_LPDDR2IO2_0 0x0648 +#define CONTROL_LPDDR2IO2_1 0x064C +#define CONTROL_LPDDR2IO2_2 0x0650 +#define CONTROL_LPDDR2IO2_3 0x0654 +#define CONTROL_BUS_HOLD 0x0658 +#define CONTROL_C2C 0x065C +#define CONTROL_CORE_CONTROL_SPARE_RW 0x0660 +#define CONTROL_CORE_CONTROL_SPARE_R 0x0664 +#define CONTROL_CORE_CONTROL_SPARE_R_C0 0x0668 +#define CONTROL_EFUSE_1 0x0700 +#define CONTROL_EFUSE_2 0x0704 +#define CONTROL_EFUSE_3 0x0708 +#define CONTROL_EFUSE_4 0x070C + +#define CONTROL_PADCONF_WKUP_REVISION 0x0000 +#define CONTROL_PADCONF_WKUP_HWINFO 0x0004 +#define CONTROL_PADCONF_WKUP_SYSCONFIG 0x0010 +#define CONTROL_WKUP_PAD0_SIM_IO 0x0040 +#define CONTROL_WKUP_PAD1_SIM_CLK 0x0042 +#define CONTROL_WKUP_PAD0_SIM_RESET 0x0044 +#define CONTROL_WKUP_PAD1_SIM_CD 0x0046 +#define CONTROL_WKUP_PAD0_SIM_PWRCTRL 0x0048 +#define CONTROL_WKUP_PAD1_SR_SCL 0x004A +#define CONTROL_WKUP_PAD0_SR_SDA 0x004C +#define CONTROL_WKUP_PAD1_FREF_XTAL_IN 0x004E +#define CONTROL_WKUP_PAD0_FREF_SLICER_IN 0x0050 +#define CONTROL_WKUP_PAD1_FREF_CLK_IOREQ 0x0052 +#define CONTROL_WKUP_PAD0_FREF_CLK0_OUT 0x0054 +#define CONTROL_WKUP_PAD1_FREF_CLK3_REQ 0x0056 +#define CONTROL_WKUP_PAD0_FREF_CLK3_OUT 0x0058 +#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x005A +#define CONTROL_WKUP_PAD0_FREF_CLK4_OUT 0x005C +#define CONTROL_WKUP_PAD1_SYS_32K 0x005E +#define CONTROL_WKUP_PAD0_SYS_NRESPWRON 0x0060 +#define CONTROL_WKUP_PAD1_SYS_NRESWARM 0x0062 +#define CONTROL_WKUP_PAD0_SYS_PWR_REQ 0x0064 +#define CONTROL_WKUP_PAD1_SYS_PWRON_RESET 0x0066 +#define CONTROL_WKUP_PAD0_SYS_BOOT6 0x0068 +#define CONTROL_WKUP_PAD1_SYS_BOOT7 0x006A +#define CONTROL_WKUP_PAD0_JTAG_NTRST 0x006C +#define CONTROL_WKUP_PAD1_JTAG_TCK 0x006D +#define CONTROL_WKUP_PAD0_JTAG_RTCK 0x0070 +#define CONTROL_WKUP_PAD1_JTAG_TMS_TMSC 0x0072 +#define CONTROL_WKUP_PAD0_JTAG_TDI 0x0074 +#define CONTROL_WKUP_PAD1_JTAG_TDO 0x0076 +#define CONTROL_PADCONF_WAKEUPEVENT_0 0x007C +#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 +#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 +#define CONTROL_PADCONF_MODE 0x05A8 +#define CONTROL_XTAL_OSCILLATOR 0x05AC +#define CONTROL_CONTROL_I2C_2 0x0604 +#define CONTROL_CONTROL_JTAG 0x0608 +#define CONTROL_CONTROL_SYS 0x060C +#define CONTROL_WKUP_CONTROL_SPARE_RW 0x0614 +#define CONTROL_WKUP_CONTROL_SPARE_R 0x0618 +#define CONTROL_WKUP_CONTROL_SPARE_R_C0 0x061C + +#endif diff --git a/include/asm/arch-omap4/omap4430.h b/include/asm/arch-omap4/omap4430.h new file mode 100644 index 0000000..2f83621 --- /dev/null +++ b/include/asm/arch-omap4/omap4430.h @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2006-2009 + * Texas Instruments, + * Richard Woodruff + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP4430_SYS_H_ +#define _OMAP4430_SYS_H_ + +#include + +/* + * 4430 specific Section + */ + +/* Stuff on L3 Interconnect */ +#define SMX_APE_BASE 0x68000000 + +/* L3 Firewall */ +#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048) +#define A_READPERM0 (SMX_APE_BASE + 0x05050) +#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058) + +/* GPMC */ +#define OMAP44XX_GPMC_BASE (0x50000000) + +/* DMM */ +#define OMAP44XX_DMM_BASE 0x4E000000 + +/* SMS */ +#define OMAP44XX_SMS_BASE 0x6C000000 + +/* SDRC */ +#define OMAP44XX_SDRC_BASE 0x6D000000 + + +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP44XX_CORE_L4_IO_BASE 0x4A000000 + +#define OMAP44XX_WAKEUP_L4_IO_BASE 0x4A300000 + +#define OMAP44XX_L4_PER 0x48000000 + +#define OMAP44XX_L4_IO_BASE OMAP44XX_CORE_L4_IO_BASE + +/* CONTROL */ +//#define OMAP44XX_CTRL_BASE (OMAP44XX_L4_IO_BASE+0x2000) +#define OMAP44XX_CTRL_BASE 0x4a100000 + +/* TAP information dont know for 3430*/ +#define OMAP44XX_TAP_BASE (0x49000000) /*giving some junk for virtio */ + +/* UART */ +#define OMAP44XX_UART1 (OMAP44XX_L4_PER+0x6a000) +#define OMAP44XX_UART2 (OMAP44XX_L4_PER+0x6c000) +#define OMAP44XX_UART3 (OMAP44XX_L4_PER+0x20000) + +/* General Purpose Timers */ +#define OMAP44XX_GPT1 0x48318000 +#define OMAP44XX_GPT2 0x48032000 +#define OMAP44XX_GPT3 0x48034000 +#define OMAP44XX_GPT4 0x48036000 +#define OMAP44XX_GPT5 0x40138000 +#define OMAP44XX_GPT6 0x4013A000 +#define OMAP44XX_GPT7 0x4013C000 +#define OMAP44XX_GPT8 0x4013E000 +#define OMAP44XX_GPT9 0x48040000 +#define OMAP44XX_GPT10 0x48086000 +#define OMAP44XX_GPT11 0x48088000 +#define OMAP44XX_GPT12 0x48304000 + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE (0x4A322000) +#define WD2_BASE (0x4A314000) +#define WD3_BASE (0x40130000) + +/* 32KTIMER */ +#define SYNC_32KTIMER_BASE (0x48320000) +#define S32K_CR (SYNC_32KTIMER_BASE+0x10) + +/* + * SDP4430 specific Section + */ + +/* + * The 443x's chip selects are programmable. The mask ROM + * does configure CS0 to 0x08000000 before dispatch. So, if + * you want your code to live below that address, you have to + * be prepared to jump though hoops, to reset the base address. + * Same as in SDP4430 + */ +#ifdef CONFIG_OMAP44XX +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00300000 +#define SRAM_OFFSET2 0x0000D000 +#define SRAM_OFFSET3 0x00000800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2|SRAM_OFFSET3) +#define LOW_LEVEL_SRAM_STACK 0x4030DFFC +#endif + +#if defined(CONFIG_4430SDP) +/* FPGA on Debug board.*/ +# define ETH_CONTROL_REG (DEBUG_BASE+0x30b) +# define LAN_RESET_REGISTER (DEBUG_BASE+0x1c) + +# define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60) +# define LED_REGISTER (DEBUG_BASE+0x40) +# define FPGA_REV_REGISTER (DEBUG_BASE+0x10) +# define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800) +# define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900) +# define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00) +# define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00) +# define ENHANCED_UI_EE_NAME "750-2075" +#endif + +#endif /* _OMAP4430_SYS_H_ */ diff --git a/include/asm/arch-omap4/rev.h b/include/asm/arch-omap4/rev.h new file mode 100644 index 0000000..18498bb --- /dev/null +++ b/include/asm/arch-omap4/rev.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2006-2009 + * Texas Instruments, + * + * Richard Woodruff + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP44XX_REV_H_ +#define _OMAP44XX_REV_H_ + +#define CDB_DDR_COMBO /* combo part on cpu daughter card */ +#define CDB_DDR_IPDB /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_4430 0x4430 + +#define CPU_4430_ES1 1 + +#endif diff --git a/include/asm/arch-omap4/sizes.h b/include/asm/arch-omap4/sizes.h new file mode 100644 index 0000000..f4e57f5 --- /dev/null +++ b/include/asm/arch-omap4/sizes.h @@ -0,0 +1,48 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_31M 0x01F00000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __sizes_h */ diff --git a/include/asm/arch-omap4/sys_info.h b/include/asm/arch-omap4/sys_info.h new file mode 100644 index 0000000..bd90397 --- /dev/null +++ b/include/asm/arch-omap4/sys_info.h @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2006-2009 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP44XX_SYS_INFO_H_ +#define _OMAP44XX_SYS_INFO_H_ + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_4430 0x4430 + +/* 343x real hardware: + * ES1 = rev 0 + */ + +/* 343x code defines: + * ES1 = 0+1 = 1 + * ES1 = 1+1 = 1 + */ +#define CPU_4430_ES1 1 + +/* Currently Virtio models this one */ +#define CPU_4430_CHIPID 0x0B68A000 + +#define GPMC_MUXED 1 +#define GPMC_NONMUXED 0 + +#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ +#define TYPE_NOR 0x000 +#define TYPE_ONENAND 0x800 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ +#define I2C_TRITON2 0x4B /* addres of power group */ + +#define BOOT_FAST_XIP 0x1f + +/* SDP definitions according to FPGA Rev. Is this OK?? */ +#define SDP_4430_VIRTIO 0x1 +#define SDP_4430_V1 0x2 + +#define BOARD_4430_LABRADOR 0x80 +#define BOARD_4430_LABRADOR_V1 0x1 + +#endif diff --git a/include/asm/arch-omap4/sys_proto.h b/include/asm/arch-omap4/sys_proto.h new file mode 100644 index 0000000..eda9c5e --- /dev/null +++ b/include/asm/arch-omap4/sys_proto.h @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP44XX_SYS_PROTO_H_ +#define _OMAP44XX_SYS_PROTO_H_ + +void prcm_init(void); +void per_clocks_enable(void); +void configure_core_dpll_no_lock(void); +void lock_core_dpll(void); +void lock_core_dpll_shadow(void); + +void memif_init(void); +void sdrc_init(void); +void do_sdrc_init(u32, u32); +void gpmc_init(void); + +void ether_init(void); +void watchdog_init(void); +void set_muxconf_regs(void); + +u32 get_cpu_type(void); +u32 get_cpu_rev(void); +u32 get_mem_type(void); +u32 get_sysboot_value(void); +u32 get_gpmc0_base(void); +u32 is_gpmc_muxed(void); +u32 get_gpmc0_type(void); +u32 get_gpmc0_width(void); +u32 get_board_type(void); +void display_board_info(u32); +void update_mux(u32, u32); +u32 get_sdr_cs_size(u32 offset); +u32 running_in_sdram(void); +u32 running_in_sram(void); +u32 running_in_flash(void); +u32 running_from_internal_boot(void); +u32 get_device_type(void); + +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); +void sdelay(unsigned long loops); + +#endif diff --git a/include/asm/atomic.h b/include/asm/atomic.h new file mode 100644 index 0000000..ba9e4b7 --- /dev/null +++ b/include/asm/atomic.h @@ -0,0 +1,113 @@ +/* + * linux/include/asm-arm/atomic.h + * + * Copyright (c) 1996 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + * 13-04-1997 RMK Made functions atomic! + * 07-12-1997 RMK Upgraded for v2.1. + * 26-08-1998 PJB Added #ifdef __KERNEL__ + */ +#ifndef __ASM_ARM_ATOMIC_H +#define __ASM_ARM_ATOMIC_H + +#include + +#ifdef CONFIG_SMP +#error SMP not supported +#endif + +typedef struct { volatile int counter; } atomic_t; + +#define ATOMIC_INIT(i) { (i) } + +#ifdef __KERNEL__ +#include + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v,i) (((v)->counter) = (i)) + +static inline void atomic_add(int i, volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic_sub(int i, volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} + +static inline void atomic_inc(volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter += 1; + local_irq_restore(flags); +} + +static inline void atomic_dec(volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter -= 1; + local_irq_restore(flags); +} + +static inline int atomic_dec_and_test(volatile atomic_t *v) +{ + unsigned long flags; + int val; + + local_irq_save(flags); + val = v->counter; + v->counter = val -= 1; + local_irq_restore(flags); + + return val == 0; +} + +static inline int atomic_add_negative(int i, volatile atomic_t *v) +{ + unsigned long flags; + int val; + + local_irq_save(flags); + val = v->counter; + v->counter = val += i; + local_irq_restore(flags); + + return val < 0; +} + +static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) +{ + unsigned long flags; + + local_irq_save(flags); + *addr &= ~mask; + local_irq_restore(flags); +} + +/* Atomic operations are already serializing on ARM */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() + +#endif +#endif diff --git a/include/asm/byteorder.h b/include/asm/byteorder.h new file mode 100755 index 0000000..c3489f1 --- /dev/null +++ b/include/asm/byteorder.h @@ -0,0 +1,32 @@ +/* + * linux/include/asm-arm/byteorder.h + * + * ARM Endian-ness. In little endian mode, the data bus is connected such + * that byte accesses appear as: + * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 + * and word accesses (data or instruction) appear as: + * d0...d31 + * + * When in big endian mode, byte accesses appear as: + * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 + * and word accesses (data or instruction) appear as: + * d0...d31 + */ +#ifndef __ASM_ARM_BYTEORDER_H +#define __ASM_ARM_BYTEORDER_H + + +#include + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#ifdef __ARMEB__ +#include +#else +#include +#endif + +#endif diff --git a/include/asm/errno.h b/include/asm/errno.h new file mode 100644 index 0000000..39dc515 --- /dev/null +++ b/include/asm/errno.h @@ -0,0 +1,155 @@ +/* + * U-boot - errno.h Error number defines + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _GENERIC_ERRNO_H +#define _GENERIC_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +#endif diff --git a/include/asm/io.h b/include/asm/io.h new file mode 100644 index 0000000..f4ae307 --- /dev/null +++ b/include/asm/io.h @@ -0,0 +1,335 @@ +/* + * linux/include/asm-arm/io.h + * + * Copyright (C) 1996-2000 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Modifications: + * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both + * constant addresses and variable addresses. + * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture + * specific IO header files. + * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. + * 04-Apr-1999 PJB Added check_signature. + * 12-Dec-1999 RMK More cleanups + * 18-Jun-2000 RMK Removed virt_to_* and friends definitions + */ +#ifndef __ASM_ARM_IO_H +#define __ASM_ARM_IO_H + +#ifdef __KERNEL__ + +#include +#include +#include +#if 0 /* XXX###XXX */ +#include +#endif /* XXX###XXX */ + +static inline void sync(void) +{ +} + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +/* + * Generic virtual read/write. Note that we don't support half-word + * read/writes. We define __arch_*[bl] here, and leave __arch_*w + * to the architecture specific code. + */ +#define __arch_getb(a) (*(volatile unsigned char *)(a)) +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_getl(a) (*(volatile unsigned int *)(a)) + +#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) + +extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); +extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); +extern void __raw_writesl(unsigned int addr, const void *data, int longlen); + +extern void __raw_readsb(unsigned int addr, void *data, int bytelen); +extern void __raw_readsw(unsigned int addr, void *data, int wordlen); +extern void __raw_readsl(unsigned int addr, void *data, int longlen); + +#define __raw_writeb(v,a) __arch_putb(v,a) +#define __raw_writew(v,a) __arch_putw(v,a) +#define __raw_writel(v,a) __arch_putl(v,a) + +#define __raw_readb(a) __arch_getb(a) +#define __raw_readw(a) __arch_getw(a) +#define __raw_readl(a) __arch_getl(a) + +#define writeb(v,a) __arch_putb(v,a) +#define writew(v,a) __arch_putw(v,a) +#define writel(v,a) __arch_putl(v,a) + +#define readb(a) __arch_getb(a) +#define readw(a) __arch_getw(a) +#define readl(a) __arch_getl(a) + +/* + * The compiler seems to be incapable of optimising constants + * properly. Spell it out to the compiler in some cases. + * These are only valid for small values of "off" (< 1<<12) + */ +#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) +#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) +#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) + +#define __raw_base_readb(base,off) __arch_base_getb(base,off) +#define __raw_base_readw(base,off) __arch_base_getw(base,off) +#define __raw_base_readl(base,off) __arch_base_getl(base,off) + +/* + * Now, pick up the machine-defined IO definitions + */ +#if 0 /* XXX###XXX */ +#include +#endif /* XXX###XXX */ + +/* + * IO port access primitives + * ------------------------- + * + * The ARM doesn't have special IO access instructions; all IO is memory + * mapped. Note that these are defined to perform little endian accesses + * only. Their primary purpose is to access PCI and ISA peripherals. + * + * Note that for a big endian machine, this implies that the following + * big endian mode connectivity is in place, as described by numerous + * ARM documents: + * + * PCI: D0-D7 D8-D15 D16-D23 D24-D31 + * ARM: D24-D31 D16-D23 D8-D15 D0-D7 + * + * The machine specific io.h include defines __io to translate an "IO" + * address to a memory address. + * + * Note that we prevent GCC re-ordering or caching values in expressions + * by introducing sequence points into the in*() definitions. Note that + * __raw_* do not guarantee this behaviour. + * + * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. + */ +#ifdef __io +#define outb(v,p) __raw_writeb(v,__io(p)) +#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) +#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) + +#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) +#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) +#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) + +#define outsb(p,d,l) __raw_writesb(__io(p),d,l) +#define outsw(p,d,l) __raw_writesw(__io(p),d,l) +#define outsl(p,d,l) __raw_writesl(__io(p),d,l) + +#define insb(p,d,l) __raw_readsb(__io(p),d,l) +#define insw(p,d,l) __raw_readsw(__io(p),d,l) +#define insl(p,d,l) __raw_readsl(__io(p),d,l) +#endif + +#define outb_p(val,port) outb((val),(port)) +#define outw_p(val,port) outw((val),(port)) +#define outl_p(val,port) outl((val),(port)) +#define inb_p(port) inb((port)) +#define inw_p(port) inw((port)) +#define inl_p(port) inl((port)) + +#define outsb_p(port,from,len) outsb(port,from,len) +#define outsw_p(port,from,len) outsw(port,from,len) +#define outsl_p(port,from,len) outsl(port,from,len) +#define insb_p(port,to,len) insb(port,to,len) +#define insw_p(port,to,len) insw(port,to,len) +#define insl_p(port,to,len) insl(port,to,len) + +/* + * ioremap and friends. + * + * ioremap takes a PCI memory address, as specified in + * linux/Documentation/IO-mapping.txt. If you want a + * physical address, use __ioremap instead. + */ +extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); +extern void __iounmap(void *addr); + +/* + * Generic ioremap support. + * + * Define: + * iomem_valid_addr(off,size) + * iomem_to_phys(off) + */ +#ifdef iomem_valid_addr +#define __arch_ioremap(off,sz,nocache) \ + ({ \ + unsigned long _off = (off), _size = (sz); \ + void *_ret = (void *)0; \ + if (iomem_valid_addr(_off, _size)) \ + _ret = __ioremap(iomem_to_phys(_off),_size,0); \ + _ret; \ + }) + +#define __arch_iounmap __iounmap +#endif + +#define ioremap(off,sz) __arch_ioremap((off),(sz),0) +#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) +#define iounmap(_addr) __arch_iounmap(_addr) + +/* + * DMA-consistent mapping functions. These allocate/free a region of + * uncached, unwrite-buffered mapped memory space for use with DMA + * devices. This is the "generic" version. The PCI specific version + * is in pci.h + */ +extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); +extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); +extern void consistent_sync(void *vaddr, size_t size, int rw); + +/* + * String version of IO memory access ops: + */ +extern void _memcpy_fromio(void *, unsigned long, size_t); +extern void _memcpy_toio(unsigned long, const void *, size_t); +extern void _memset_io(unsigned long, int, size_t); + +extern void __readwrite_bug(const char *fn); + +/* + * If this architecture has PCI memory IO, then define the read/write + * macros. These should only be used with the cookie passed from + * ioremap. + */ +#ifdef __mem_pci + +#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) +#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) +#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) + +#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) +#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) +#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) + +#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) +#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) +#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) + +#define eth_io_copy_and_sum(s,c,l,b) \ + eth_copy_and_sum((s),__mem_pci(c),(l),(b)) + +static inline int +check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#elif !defined(readb) + +#define readb(addr) (__readwrite_bug("readb"),0) +#define readw(addr) (__readwrite_bug("readw"),0) +#define readl(addr) (__readwrite_bug("readl"),0) +#define writeb(v,addr) __readwrite_bug("writeb") +#define writew(v,addr) __readwrite_bug("writew") +#define writel(v,addr) __readwrite_bug("writel") + +#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") + +#define check_signature(io,sig,len) (0) + +#endif /* __mem_pci */ + +/* + * If this architecture has ISA IO, then define the isa_read/isa_write + * macros. + */ +#ifdef __mem_isa + +#define isa_readb(addr) __raw_readb(__mem_isa(addr)) +#define isa_readw(addr) __raw_readw(__mem_isa(addr)) +#define isa_readl(addr) __raw_readl(__mem_isa(addr)) +#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) +#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) +#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) +#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) +#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) +#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) + +#define isa_eth_io_copy_and_sum(a,b,c,d) \ + eth_copy_and_sum((a),__mem_isa(b),(c),(d)) + +static inline int +isa_check_signature(unsigned long io_addr, const unsigned char *signature, + int length) +{ + int retval = 0; + do { + if (isa_readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +#else /* __mem_isa */ + +#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) +#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) +#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) +#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") +#define isa_writew(val,addr) __readwrite_bug("isa_writew") +#define isa_writel(val,addr) __readwrite_bug("isa_writel") +#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") +#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") +#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") + +#define isa_eth_io_copy_and_sum(a,b,c,d) \ + __readwrite_bug("isa_eth_io_copy_and_sum") + +#define isa_check_signature(io,sig,len) (0) + +#endif /* __mem_isa */ +#endif /* __KERNEL__ */ +#endif /* __ASM_ARM_IO_H */ diff --git a/include/asm/memory.h b/include/asm/memory.h new file mode 100644 index 0000000..c3b2afd --- /dev/null +++ b/include/asm/memory.h @@ -0,0 +1,137 @@ +/* + * linux/include/asm-arm/memory.h + * + * Copyright (C) 2000-2002 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Note: this file should not be included by non-asm/.h files + */ +#ifndef __ASM_ARM_MEMORY_H +#define __ASM_ARM_MEMORY_H + +#if 0 /* XXX###XXX */ + +#include +#include + +/* + * PFNs are used to describe any physical page; this means + * PFN 0 == physical address 0. + * + * This is the PFN of the first RAM page in the kernel + * direct-mapped view. We assume this is the first page + * of RAM in the mem_map as well. + */ +#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) + +/* + * These are *only* valid on the kernel direct mapped RAM memory. + */ +static inline unsigned long virt_to_phys(void *x) +{ + return __virt_to_phys((unsigned long)(x)); +} + +static inline void *phys_to_virt(unsigned long x) +{ + return (void *)(__phys_to_virt((unsigned long)(x))); +} + +#define __pa(x) __virt_to_phys((unsigned long)(x)) +#define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) + +/* + * Virtual <-> DMA view memory address translations + * Again, these are *only* valid on the kernel direct mapped RAM + * memory. Use of these is *depreciated*. + */ +#define virt_to_bus(x) (__virt_to_bus((unsigned long)(x))) +#define bus_to_virt(x) ((void *)(__bus_to_virt((unsigned long)(x)))) + +/* + * Conversion between a struct page and a physical address. + * + * Note: when converting an unknown physical address to a + * struct page, the resulting pointer must be validated + * using VALID_PAGE(). It must return an invalid struct page + * for any physical address not corresponding to a system + * RAM address. + * + * page_to_pfn(page) convert a struct page * to a PFN number + * pfn_to_page(pfn) convert a _valid_ PFN number to struct page * + * pfn_valid(pfn) indicates whether a PFN number is valid + * + * virt_to_page(k) convert a _valid_ virtual address to struct page * + * virt_addr_valid(k) indicates whether a virtual address is valid + */ +#ifndef CONFIG_DISCONTIGMEM + +#define page_to_pfn(page) (((page) - mem_map) + PHYS_PFN_OFFSET) +#define pfn_to_page(pfn) ((mem_map + (pfn)) - PHYS_PFN_OFFSET) +#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) + +#define virt_to_page(kaddr) (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)) +#define virt_addr_valid(kaddr) ((kaddr) >= PAGE_OFFSET && (kaddr) < (unsigned long)high_memory) + +#define PHYS_TO_NID(addr) (0) + +#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) + +#else + +/* + * This is more complex. We have a set of mem_map arrays spread + * around in memory. + */ +#define page_to_pfn(page) \ + (((page) - page_zone(page)->zone_mem_map) \ + + (page_zone(page)->zone_start_paddr >> PAGE_SHIFT)) + +#define pfn_to_page(pfn) \ + (PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT)) + +#define pfn_valid(pfn) \ + ({ \ + unsigned int node = PFN_TO_NID(pfn); \ + struct pglist_data *nd = NODE_DATA(node); \ + ((node < NR_NODES) && \ + ((pfn - (nd->node_start_paddr >> PAGE_SHIFT)) < nd->node_size));\ + }) + +#define virt_to_page(kaddr) \ + (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) + +#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < NR_NODES) + +/* + * Common discontigmem stuff. + * PHYS_TO_NID is used by the ARM kernel/setup.c + */ +#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) + +/* + * 2.4 compatibility + * + * VALID_PAGE returns a non-zero value if given page pointer is valid. + * This assumes all node's mem_maps are stored within the node they + * refer to. This is actually inherently buggy. + */ +#define VALID_PAGE(page) \ +({ unsigned int node = KVADDR_TO_NID(page); \ + ((node < NR_NODES) && \ + ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size)); \ +}) + +#endif + +/* + * We should really eliminate virt_to_bus() here - it's depreciated. + */ +#define page_to_bus(page) (virt_to_bus(page_address(page))) + +#endif /* XXX###XXX */ + +#endif /* __ASM_ARM_MEMORY_H */ diff --git a/include/asm/posix_types.h b/include/asm/posix_types.h new file mode 100644 index 0000000..c412486 --- /dev/null +++ b/include/asm/posix_types.h @@ -0,0 +1,79 @@ +/* + * linux/include/asm-arm/posix_types.h + * + * Copyright (C) 1996-1998 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + */ +#ifndef __ARCH_ARM_POSIX_TYPES_H +#define __ARCH_ARM_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) + +#undef __FD_CLR +#define __FD_CLR(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) + +#undef __FD_ISSET +#define __FD_ISSET(fd, fdsetp) \ + ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) \ + (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) + +#endif + +#endif diff --git a/include/asm/setup.h b/include/asm/setup.h new file mode 100644 index 0000000..89df4dc --- /dev/null +++ b/include/asm/setup.h @@ -0,0 +1,269 @@ +/* + * linux/include/asm/setup.h + * + * Copyright (C) 1997-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Structure passed to kernel to tell it about the + * hardware it's running on. See linux/Documentation/arm/Setup + * for more info. + * + * NOTE: + * This file contains two ways to pass information from the boot + * loader to the kernel. The old struct param_struct is deprecated, + * but it will be kept in the kernel for 5 years from now + * (2001). This will allow boot loaders to convert to the new struct + * tag way. + */ +#ifndef __ASMARM_SETUP_H +#define __ASMARM_SETUP_H + +/* + * Usage: + * - do not go blindly adding fields, add them at the end + * - when adding fields, don't rely on the address until + * a patch from me has been released + * - unused fields should be zero (for future expansion) + * - this structure is relatively short-lived - only + * guaranteed to contain useful data in setup_arch() + */ +#define COMMAND_LINE_SIZE 1024 + +/* This is the old deprecated way to pass parameters to the kernel */ +struct param_struct { + union { + struct { + unsigned long page_size; /* 0 */ + unsigned long nr_pages; /* 4 */ + unsigned long ramdisk_size; /* 8 */ + unsigned long flags; /* 12 */ +#define FLAG_READONLY 1 +#define FLAG_RDLOAD 4 +#define FLAG_RDPROMPT 8 + unsigned long rootdev; /* 16 */ + unsigned long video_num_cols; /* 20 */ + unsigned long video_num_rows; /* 24 */ + unsigned long video_x; /* 28 */ + unsigned long video_y; /* 32 */ + unsigned long memc_control_reg; /* 36 */ + unsigned char sounddefault; /* 40 */ + unsigned char adfsdrives; /* 41 */ + unsigned char bytes_per_char_h; /* 42 */ + unsigned char bytes_per_char_v; /* 43 */ + unsigned long pages_in_bank[4]; /* 44 */ + unsigned long pages_in_vram; /* 60 */ + unsigned long initrd_start; /* 64 */ + unsigned long initrd_size; /* 68 */ + unsigned long rd_start; /* 72 */ + unsigned long system_rev; /* 76 */ + unsigned long system_serial_low; /* 80 */ + unsigned long system_serial_high; /* 84 */ + unsigned long mem_fclk_21285; /* 88 */ + } s; + char unused[256]; + } u1; + union { + char paths[8][128]; + struct { + unsigned long magic; + char n[1024 - sizeof(unsigned long)]; + } s; + } u2; + char commandline[COMMAND_LINE_SIZE]; +}; + + +/* + * The new way of passing information: a list of tagged entries + */ + +/* The list ends with an ATAG_NONE node. */ +#define ATAG_NONE 0x00000000 + +struct tag_header { + u32 size; + u32 tag; +}; + +/* The list must start with an ATAG_CORE node */ +#define ATAG_CORE 0x54410001 + +struct tag_core { + u32 flags; /* bit 0 = read-only */ + u32 pagesize; + u32 rootdev; +}; + +/* it is allowed to have multiple ATAG_MEM nodes */ +#define ATAG_MEM 0x54410002 + +struct tag_mem32 { + u32 size; + u32 start; /* physical start address */ +}; + +/* VGA text type displays */ +#define ATAG_VIDEOTEXT 0x54410003 + +struct tag_videotext { + u8 x; + u8 y; + u16 video_page; + u8 video_mode; + u8 video_cols; + u16 video_ega_bx; + u8 video_lines; + u8 video_isvga; + u16 video_points; +}; + +/* describes how the ramdisk will be used in kernel */ +#define ATAG_RAMDISK 0x54410004 + +struct tag_ramdisk { + u32 flags; /* bit 0 = load, bit 1 = prompt */ + u32 size; /* decompressed ramdisk size in _kilo_ bytes */ + u32 start; /* starting block of floppy-based RAM disk image */ +}; + +/* describes where the compressed ramdisk image lives (virtual address) */ +/* + * this one accidentally used virtual addresses - as such, + * its depreciated. + */ +#define ATAG_INITRD 0x54410005 + +/* describes where the compressed ramdisk image lives (physical address) */ +#define ATAG_INITRD2 0x54420005 + +struct tag_initrd { + u32 start; /* physical start address */ + u32 size; /* size of compressed ramdisk image in bytes */ +}; + +/* board serial number. "64 bits should be enough for everybody" */ +#define ATAG_SERIAL 0x54410006 + +struct tag_serialnr { + u32 low; + u32 high; +}; + +/* board revision */ +#define ATAG_REVISION 0x54410007 + +struct tag_revision { + u32 rev; +}; + +/* initial values for vesafb-type framebuffers. see struct screen_info + * in include/linux/tty.h + */ +#define ATAG_VIDEOLFB 0x54410008 + +struct tag_videolfb { + u16 lfb_width; + u16 lfb_height; + u16 lfb_depth; + u16 lfb_linelength; + u32 lfb_base; + u32 lfb_size; + u8 red_size; + u8 red_pos; + u8 green_size; + u8 green_pos; + u8 blue_size; + u8 blue_pos; + u8 rsvd_size; + u8 rsvd_pos; +}; + +/* command line: \0 terminated string */ +#define ATAG_CMDLINE 0x54410009 + +struct tag_cmdline { + char cmdline[1]; /* this is the minimum size */ +}; + +/* acorn RiscPC specific information */ +#define ATAG_ACORN 0x41000101 + +struct tag_acorn { + u32 memc_control_reg; + u32 vram_pages; + u8 sounddefault; + u8 adfsdrives; +}; + +/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ +#define ATAG_MEMCLK 0x41000402 + +struct tag_memclk { + u32 fmemclk; +}; + +struct tag { + struct tag_header hdr; + union { + struct tag_core core; + struct tag_mem32 mem; + struct tag_videotext videotext; + struct tag_ramdisk ramdisk; + struct tag_initrd initrd; + struct tag_serialnr serialnr; + struct tag_revision revision; + struct tag_videolfb videolfb; + struct tag_cmdline cmdline; + + /* + * Acorn specific + */ + struct tag_acorn acorn; + + /* + * DC21285 specific + */ + struct tag_memclk memclk; + } u; +}; + +struct tagtable { + u32 tag; + int (*parse)(const struct tag *); +}; + +#define __tag __attribute__((unused, __section__(".taglist"))) +#define __tagtable(tag, fn) \ +static struct tagtable __tagtable_##fn __tag = { tag, fn } + +#define tag_member_present(tag,member) \ + ((unsigned long)(&((struct tag *)0L)->member + 1) \ + <= (tag)->hdr.size * 4) + +#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) +#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) + +#define for_each_tag(t,base) \ + for (t = base; t->hdr.size; t = tag_next(t)) + +/* + * Memory map description + */ +#define NR_BANKS 8 + +struct meminfo { + int nr_banks; + unsigned long end; + struct { + unsigned long start; + unsigned long size; + int node; + } bank[NR_BANKS]; +}; + +extern struct meminfo meminfo; + +#endif diff --git a/include/asm/sizes.h b/include/asm/sizes.h new file mode 100644 index 0000000..f8d92ca --- /dev/null +++ b/include/asm/sizes.h @@ -0,0 +1,52 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* DO NOT EDIT!! - this file automatically generated + * from .s file by awk -f s2h.awk + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif + +/* END */ diff --git a/include/asm/string.h b/include/asm/string.h new file mode 100644 index 0000000..c3ea582 --- /dev/null +++ b/include/asm/string.h @@ -0,0 +1,47 @@ +#ifndef __ASM_ARM_STRING_H +#define __ASM_ARM_STRING_H + +/* + * We don't do inline string functions, since the + * optimised inline asm versions are not small. + */ + +#undef __HAVE_ARCH_STRRCHR +extern char * strrchr(const char * s, int c); + +#undef __HAVE_ARCH_STRCHR +extern char * strchr(const char * s, int c); + +#undef __HAVE_ARCH_MEMCPY +extern void * memcpy(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMMOVE +extern void * memmove(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMCHR +extern void * memchr(const void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMZERO +#undef __HAVE_ARCH_MEMSET +extern void * memset(void *, int, __kernel_size_t); + +#if 0 +extern void __memzero(void *ptr, __kernel_size_t n); + +#define memset(p,v,n) \ + ({ \ + if ((n) != 0) { \ + if (__builtin_constant_p((v)) && (v) == 0) \ + __memzero((p),(n)); \ + else \ + memset((p),(v),(n)); \ + } \ + (p); \ + }) + +#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); }) +#else +extern void memzero(void *ptr, __kernel_size_t n); +#endif + +#endif diff --git a/include/asm/types.h b/include/asm/types.h new file mode 100644 index 0000000..efc3052 --- /dev/null +++ b/include/asm/types.h @@ -0,0 +1,51 @@ +#ifndef __ASM_ARM_TYPES_H +#define __ASM_ARM_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; + +#endif /* __KERNEL__ */ + +#endif diff --git a/include/asm/x-load-arm.h b/include/asm/x-load-arm.h new file mode 100644 index 0000000..eef268e --- /dev/null +++ b/include/asm/x-load-arm.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2004 + * Texas Instruments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _X_LOAD_ARM_H_ +#define _X_LOAD_ARM_H_ 1 + +/* for the following variables, see start.S */ +extern ulong _armboot_start; /* code start */ +extern ulong _bss_start; /* code + data end == BSS start */ +extern ulong _bss_end; /* BSS end */ + +#endif /* _X_LOAD_ARM_H_ */ diff --git a/include/command.h b/include/command.h new file mode 100644 index 0000000..a2936ad --- /dev/null +++ b/include/command.h @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Definitions for Command Processor + */ +#ifndef __COMMAND_H +#define __COMMAND_H + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef __ASSEMBLY__ +/* + * Monitor Command Table + */ + +struct cmd_tbl_s { + char *name; /* Command Name */ + int maxargs; /* maximum number of arguments */ + int repeatable; /* autorepeat allowed? */ + /* Implementation function */ + int (*cmd)(struct cmd_tbl_s *, int, int, char *[]); + char *usage; /* Usage message (short) */ +#ifdef CFG_LONGHELP + char *help; /* Help message (long) */ +#endif +#ifdef CONFIG_AUTO_COMPLETE + /* do auto completion on the arguments */ + int (*complete)(int argc, char *argv[], char last_char, int maxv, char *cmdv[]); +#endif +}; + +typedef struct cmd_tbl_s cmd_tbl_t; + +extern cmd_tbl_t __u_boot_cmd_start; +extern cmd_tbl_t __u_boot_cmd_end; + + +/* common/command.c */ +cmd_tbl_t *find_cmd(const char *cmd); + +#ifdef CONFIG_AUTO_COMPLETE +extern void install_auto_complete(void); +extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp); +#endif + +/* + * Monitor Command + * + * All commands use a common argument format: + * + * void function (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + */ + +typedef void command_t (cmd_tbl_t *, int, int, char *[]); + +#endif /* __ASSEMBLY__ */ + +/* + * Command Flags: + */ +#define CMD_FLAG_REPEAT 0x0001 /* repeat last command */ +#define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */ + +/* + * Configurable monitor commands definitions have been moved + * to include/cmd_confdefs.h + */ + + +#define Struct_Section __attribute__ ((unused,section (".u_boot_cmd"))) + +#ifdef CFG_LONGHELP + +#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \ +cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage, help} + +#else /* no long help info */ + +#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \ +cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage} + +#endif /* CFG_LONGHELP */ + +#endif /* __COMMAND_H */ diff --git a/include/common.h b/include/common.h new file mode 100644 index 0000000..5a6f4c9 --- /dev/null +++ b/include/common.h @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2004 + * Texas Instruments + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __COMMON_H_ +#define __COMMON_H_ 1 + +#undef _LINUX_CONFIG_H +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +typedef unsigned char uchar; +typedef volatile unsigned long vu_long; +typedef volatile unsigned short vu_short; +typedef volatile unsigned char vu_char; + +#include +#include +#include + +#ifdef CONFIG_ARM +#define asmlinkage /* nothing */ +#endif + + +#ifdef CONFIG_ARM +# include +# include /* ARM version to be fixed! */ +#endif /* CONFIG_ARM */ + +#ifdef CFG_PRINTF +#define printf(fmt,args...) serial_printf (fmt ,##args) +#define getc() serial_getc() +#else +#define printf(fmt,args...) +#define getc() ' ' +#endif /* CFG_PRINTF */ + +/* board/$(BOARD)/$(BOARD).c */ +int board_init (void); +int nand_init (void); +int mmc_boot (unsigned char *buf); +void board_hang (void); + +/* cpu/$(CPU)/cpu.c */ +int cpu_init (void); +#ifdef CFG_UDELAY +void udelay (unsigned long usec); +#endif + +/* nand driver */ +#define NAND_CMD_READ0 0 +#define NAND_CMD_READ1 1 +#define NAND_CMD_READOOB 0x50 +#define NAND_CMD_STATUS 0x70 +#define NAND_CMD_READID 0x90 +#define NAND_CMD_RESET 0xff + +/* Extended Commands for Large page devices */ +#define NAND_CMD_READSTART 0x30 + +int nand_chip(void); +int nand_read_block(uchar *buf, ulong block_addr); + +int onenand_chip(void); +int onenand_read_block(unsigned char *buf, ulong block); + + +#ifdef CFG_PRINTF + +/* serial driver */ +int serial_init (void); +void serial_setbrg (void); +void serial_putc (const char); +void serial_puts (const char *); +int serial_getc (void); +int serial_tstc (void); + +/* lib/printf.c */ +void serial_printf (const char *fmt, ...); +#endif + +/* lib/crc.c */ +void nand_calculate_ecc (const u_char *dat, u_char *ecc_code); +int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc); + +/* lib/board.c */ +void hang (void) __attribute__ ((noreturn)); +#endif /* __COMMON_H_ */ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h new file mode 100644 index 0000000..7495d7f --- /dev/null +++ b/include/configs/omap2420h4.h @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2004 - 2005 Texas Instruments. + * + * X-Loader Configuation settings for the TI OMAP H4 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* serial printf facility takes about 3.5K */ +#define CFG_PRINTF +//#undef CFG_PRINTF + +/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ +//#define CFG_UDELAY + +/* + * High Level Configuration Options + */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP2420 1 /* which is in a 2420 */ +#define CONFIG_OMAP2420H4 1 /* and on a H4 board */ + +#define CONFIG_OMAP242X + +#define PRCM_CONFIG_II 1 +//#define PRCM_CONFIG_III 1 +#define CONFIG_PARTIAL_SRAM 1 + +//#define CFG_SDRAM_DDR 1 +#define CFG_SDRAM_COMBO 2 +//#define CFG_SDRAM_SDR 3 +//#define CFG_SDRAM_STACKED 4 + +/* Chipselect and NAND information : + Since we share the mem.h from u-boot, we define few macros here + so as to pick the right gpmc values from there for the macros in mem.h +*/ +/* NAND fixed at CS5 */ +#define OMAP24XX_GPMC_CS0 SMNAND +#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_64M +#define OMAP24XX_GPMC_CS0_MAP CFG_FLASH_BASE +#define CFG_NAND_BOOT +#define NAND_LEGACY + +#include /* get chip and board defs */ + +#define V_SCLK 12000000 +/* input clock of PLL */ +/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ +#define CONFIG_SYS_CLK_FREQ V_SCLK + +#ifdef CFG_PRINTF + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ +#define CFG_NS16550_COM1 OMAP2420_UART1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* UART1 on H4 */ + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_PBSIZE 256 + +#endif /* CFG_PRINTF */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LOADADDR 0x80000000 + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Board NAND Info. + */ +#define CFG_NAND_K9K1216 /* Samsung 16-bit 64MB chip */ + +#define NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/ + +/* H4 NAND is partitioned: + * 0x0000000 - 0x0010000 Booting Image + * 0x0010000 - 0x0050000 U-Boot Image + * 0x0050000 - 0x0080000 U-Boot Env Data (X-loader doesn't care) + * 0x0080000 - 0x4000000 depends on application + */ +#define NAND_UBOOT_START 0x0040000 +#define NAND_UBOOT_END 0x0080000 +#define NAND_BLOCK_SIZE 0x4000 + +#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0) +#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0) +#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0) +#define READ_NAND(adr) (*(volatile u16 *)0x6800A084) + +#define NAND_WAIT_READY() + +#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0) +#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0) + +#define NAND_CTL_CLRALE(adr) +#define NAND_CTL_SETALE(adr) +#define NAND_CTL_CLRCLE(adr) +#define NAND_CTL_SETCLE(adr) +#define NAND_DISABLE_CE() +#define NAND_ENABLE_CE() + + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap2430sdp.h b/include/configs/omap2430sdp.h new file mode 100644 index 0000000..3fda61f --- /dev/null +++ b/include/configs/omap2430sdp.h @@ -0,0 +1,178 @@ +/* + * (C) Copyright 2004 Texas Instruments. + * + * X-Loader Configuation settings for the TI OMAP H4 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* serial printf facility takes about 3.5K */ +#define CFG_PRINTF +//#undef CFG_PRINTF + +/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ +//#define CFG_UDELAY + +/* + * High Level Configuration Options + */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP2430H4 1 /* and on a H4 board */ + +#define CONFIG_OMAP243X 1 + +//#define PRCM_CONFIG_5A 1 +#define PRCM_CONFIG_2 1 /* 2430 ES2+330ARM+DDR-165-PISMO */ + +#define OMAP2430_SQUARE_CLOCK_INPUT 1 + +/* Memory type */ +//#define CFG_SDRAM_DDR 1 /* not tested */ +//#define CFG_SDRAM_COMBO 2 /* not tested */ +#define CFG_2430SDRAM_DDR 3 +//#define CFG_SDRAM_STACKED 4 /* not tested */ + +/* The actual register values are defined in u-boot- mem.h */ +/* SDRAM Bank Allocation method */ +//#define SDRC_B_R_C 1 +//#define SDRC_B1_R_B0_C 1 +#define SDRC_R_B_C 1 + +/* Boot type */ +//#define CFG_NAND 1 +#define CFG_ONENAND 1 + +# define NAND_BASE 0x0C000000 /* NAND flash */ +# define ONENAND_BASE 0x20000000 /* OneNand flash */ + +#ifdef CFG_NAND +#define NAND_LEGACY +#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_64M +#define OMAP24XX_GPMC_CS0_MAP NAND_BASE +#else +#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_128M +#define OMAP24XX_GPMC_CS0_MAP ONENAND_BASE +#define ONENAND_ADDR ONENAND_BASE /* physical address to access OneNAND at CS0*/ +#endif + +/* Another dependency on u-boot */ +#define sdelay delay + +#include /* get chip and board defs */ + +#define V_SCLK 13000000 +/* input clock of PLL */ +/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ +#define CONFIG_SYS_CLK_FREQ V_SCLK + +#ifdef CFG_PRINTF + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ +#define CFG_NS16550_COM1 OMAP2430_UART1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* UART1 on 2430SDP */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_PBSIZE 256 + +#endif /* CFG_PRINTF */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LOADADDR 0x80008000 + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#ifdef CFG_NAND + +/*----------------------------------------------------------------------- + * Board NAND Info. + */ +#define CFG_NAND_K9K1216 /* Samsung 16-bit 64MB chip */ + +/* NAND is partitioned: + * 0x0000000 - 0x0010000 Booting Image + * 0x0010000 - 0x0050000 U-Boot Image + * 0x0050000 - 0x0080000 U-Boot Env Data (X-loader doesn't care) + * 0x0080000 - 0x00B0000 Kernel Image + * 0x00B0000 - 0x4000000 depends on application + */ +#define NAND_UBOOT_START 0x0040000 +#define NAND_UBOOT_END 0x0080000 +#define NAND_BLOCK_SIZE 0x4000 + +#define GPMC_CONFIG (OMAP24XX_GPMC_BASE+0x50) +#define GPMC_NAND_COMMAND_0 (OMAP24XX_GPMC_BASE+0x7C) +#define GPMC_NAND_ADDRESS_0 (OMAP24XX_GPMC_BASE+0x80) +#define GPMC_NAND_DATA_0 (OMAP24XX_GPMC_BASE+0x84) + +#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0) +#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0) +#define WRITE_NAND(d, adr) do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0) +#define READ_NAND(adr) (*(volatile u16 *)GPMC_NAND_DATA_0) +#define NAND_WAIT_READY() +#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) + +#define NAND_CTL_CLRALE(adr) +#define NAND_CTL_SETALE(adr) +#define NAND_CTL_CLRCLE(adr) +#define NAND_CTL_SETCLE(adr) +#define NAND_DISABLE_CE() +#define NAND_ENABLE_CE() + +#else +/*----------------------------------------------------------------------- + * Board oneNAND Info. + */ +#define CFG_SYNC_BURST_READ 1 + +/* OneNAND is partitioned: + * 0x0000000 - 0x0080000 X-Loader + * 0x0080000 - 0x00c0000 U-boot Image + * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care) + * 0x00e0000 - 0x0120000 Kernel Image + * 0x0120000 - 0x4000000 depends on application + */ + +#define ONENAND_START_BLOCK 4 +#define ONENAND_END_BLOCK 6 +#define ONENAND_PAGE_SIZE 2048 /* 2KB */ +#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ + +#endif // oneNAND +#endif /* __CONFIG_H */ diff --git a/include/configs/omap3430labrador.h b/include/configs/omap3430labrador.h new file mode 100644 index 0000000..b5a9c54 --- /dev/null +++ b/include/configs/omap3430labrador.h @@ -0,0 +1,211 @@ +/* + * (C) Copyright 2006 + * Texas Instruments + * Richard Woodruff + * + * X-Loader Configuation settings for the TI OMAP SDP3430 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* configure for GTA04 with DM3730 */ +#define CONFIG_OMAP36XX 1 /* or 36XX (DM3730) */ +#define PRCM_CLK_CFG2_400MHZ 1 + +/* serial printf facility takes about 3.5K */ +#define CFG_PRINTF +//#undef CFG_PRINTF + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_3430LABRADOR 1 /* working on Labrador */ +//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ + +#include /* get chip and board defs */ + +/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ +//#define CFG_UDELAY + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ + +#if (V_OSCK > 19200000) +#define V_SCLK (V_OSCK >> 1) +#else +#define V_SCLK V_OSCK +#endif + +#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ +//#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=500MHz - VDD1=1.20v */ + +/* Memory type */ +#define CFG_3430SDRAM_DDR 1 + +/* The actual register values are defined in u-boot- mem.h */ +/* SDRAM Bank Allocation method */ +//#define SDRC_B_R_C 1 +//#define SDRC_B1_R_B0_C 1 +#define SDRC_R_B_C 1 + +/* Boot type */ +#define CFG_NAND 1 +//#define CFG_ONENAND 1 + +# define NAND_BASE_ADR NAND_BASE /* NAND flash */ +# define ONENAND_BASE ONENAND_MAP /* OneNand flash */ + +#ifdef CFG_NAND +#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M /* u = ofdon't need so much for nand port */ +#define OMAP34XX_GPMC_CS0_MAP NAND_BASE_ADR +#else +#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M +#define OMAP34XX_GPMC_CS0_MAP ONENAND_BASE +#define ONENAND_ADDR ONENAND_BASE /* physical address of OneNAND at CS0*/ +#endif + + +#ifdef CFG_PRINTF + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (48000000) +#define CFG_NS16550_COM3 OMAP34XX_UART3 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL3 3 /* UART3 on board */ +#define CONFIG_CONS_INDEX 3 + +#define CONFIG_BAUDRATE 115200 +#define CFG_PBSIZE 256 + +#endif /* CFG_PRINTF */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LOADADDR 0x80008000 + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#ifdef CFG_NAND + +/*----------------------------------------------------------------------- + * Board NAND Info. + */ + + +#define CFG_NAND_K9F1G08R0A /* Micron 16-bit 256MB chip large page NAND chip*/ +#define NAND_16BIT + +/* NAND is partitioned: + * 0x00000000 - 0x0007FFFF Booting Image + * 0x00080000 - 0x000BFFFF U-Boot Image + * 0x000C0000 - 0x000FFFFF U-Boot Env Data (X-loader doesn't care) + * 0x00100000 - 0x002FFFFF Kernel Image + * 0x00300000 - 0x08000000 depends on application + */ +#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */ +#define NAND_UBOOT_END 0x00C0000 /* Giving a space of 2 blocks = 256KB */ +#define NAND_BLOCK_SIZE 0x20000 + +#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) +#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) +#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) +#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) + +#ifdef NAND_16BIT +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0) +#define READ_NAND(adr) \ + (*(volatile u16 *)GPMC_NAND_DATA_0) +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) + +#else /* to support 8-bit NAND devices */ +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d;} while(0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d;} while(0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_DATA_0 = d;} while(0) +#define READ_NAND(adr) \ + (*(volatile u8 *)GPMC_NAND_DATA_0); +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) + +#endif + +#define NAND_CTL_CLRALE(adr) +#define NAND_CTL_SETALE(adr) +#define NAND_CTL_CLRCLE(adr) +#define NAND_CTL_SETCLE(adr) +#define NAND_DISABLE_CE() +#define NAND_ENABLE_CE() + +#else +/*----------------------------------------------------------------------- + * Board oneNAND Info. + */ +#define CFG_SYNC_BURST_READ 1 + +/* OneNAND is partitioned: + * 0x0000000 - 0x0080000 X-Loader + * 0x0080000 - 0x00c0000 U-boot Image + * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care) + * 0x00e0000 - 0x0120000 Kernel Image + * 0x0120000 - 0x4000000 depends on application + */ + +#define ONENAND_START_BLOCK 4 +#define ONENAND_END_BLOCK 6 +#define ONENAND_PAGE_SIZE 2048 /* 2KB */ +#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ + +#endif /* oneNAND */ +#endif /* __CONFIG_H */ + diff --git a/include/configs/omap3430sdp.h b/include/configs/omap3430sdp.h new file mode 100644 index 0000000..ad880ed --- /dev/null +++ b/include/configs/omap3430sdp.h @@ -0,0 +1,213 @@ +/* + * (C) Copyright 2006 + * Texas Instruments + * Richard Woodruff + * + * X-Loader Configuation settings for the TI OMAP SDP3430 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* serial printf facility takes about 3.5K */ +#define CFG_PRINTF +//#undef CFG_PRINTF + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_3430SDP 1 /* working with SDP */ +//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ + +/* Enable the below macro if MMC boot support is required */ +//#define CONFIG_MMC 1 +#if defined(CONFIG_MMC) + #define CFG_CMD_MMC 1 + #define CFG_CMD_FAT 1 +#endif + +#include /* get chip and board defs */ + +/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ +//#define CFG_UDELAY + +/* Clock Defines */ +#define V_OSCK 19200000 /* Clock output from T2 */ + +#if (V_OSCK > 19200000) +#define V_SCLK (V_OSCK >> 1) +#else +#define V_SCLK V_OSCK +#endif + +//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ +#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */ + +/* Memory type */ +#define CFG_3430SDRAM_DDR 1 + +/* The actual register values are defined in u-boot- mem.h */ +/* SDRAM Bank Allocation method */ +//#define SDRC_B_R_C 1 +//#define SDRC_B1_R_B0_C 1 +#define SDRC_R_B_C 1 + +/* Boot type */ +#define CFG_NAND 1 +//#define CFG_ONENAND 1 + +# define NAND_BASE_ADR NAND_BASE /* NAND flash */ +# define ONENAND_BASE ONENAND_MAP /* OneNand flash */ + +#ifdef CFG_NAND +#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M +#define OMAP34XX_GPMC_CS0_MAP NAND_BASE_ADR +#else +#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M +#define OMAP34XX_GPMC_CS0_MAP ONENAND_BASE +#define ONENAND_ADDR ONENAND_BASE /* physical address of OneNAND at CS0*/ +#endif + +#ifdef CFG_PRINTF + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (48000000) +#define CFG_NS16550_COM1 OMAP34XX_UART1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* UART1 on 3430SDP */ +#define CONFIG_CONS_INDEX 1 + +#define CONFIG_BAUDRATE 115200 +#define CFG_PBSIZE 256 + +#endif /* CFG_PRINTF */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LOADADDR 0x80008000 + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#ifdef CFG_NAND + +/*----------------------------------------------------------------------- + * Board NAND Info. + */ + + +#define CFG_NAND_K9F1G08R0A /* Samsung 8-bit 128MB chip large page NAND chip*/ +#define NAND_8BIT + +/* NAND is partitioned: + * 0x00000000 - 0x0007FFFF Booting Image + * 0x00080000 - 0x000BFFFF U-Boot Image + * 0x000C0000 - 0x000FFFFF U-Boot Env Data (X-loader doesn't care) + * 0x00100000 - 0x002FFFFF Kernel Image + * 0x00300000 - 0x08000000 depends on application + */ +#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */ +#define NAND_UBOOT_END 0x00C0000 /* Giving a space of 2 blocks = 256KB */ +#define NAND_BLOCK_SIZE 0x20000 + +#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) +#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) +#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) +#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) + +#ifdef NAND_16BIT +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0) +#define READ_NAND(adr) \ + (*(volatile u16 *)GPMC_NAND_DATA_0) +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) + +#else /* to support 8-bit NAND devices */ +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d;} while(0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d;} while(0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_DATA_0 = d;} while(0) +#define READ_NAND(adr) \ + (*(volatile u8 *)GPMC_NAND_DATA_0); +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) + +#endif + +#define NAND_CTL_CLRALE(adr) +#define NAND_CTL_SETALE(adr) +#define NAND_CTL_CLRCLE(adr) +#define NAND_CTL_SETCLE(adr) +#define NAND_DISABLE_CE() +#define NAND_ENABLE_CE() + +#else +/*----------------------------------------------------------------------- + * Board oneNAND Info. + */ +#define CFG_SYNC_BURST_READ 1 + +/* OneNAND is partitioned: + * 0x0000000 - 0x0080000 X-Loader + * 0x0080000 - 0x00c0000 U-boot Image + * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care) + * 0x00e0000 - 0x0120000 Kernel Image + * 0x0120000 - 0x4000000 depends on application + */ + +#define ONENAND_START_BLOCK 4 +#define ONENAND_END_BLOCK 6 +#define ONENAND_PAGE_SIZE 2048 /* 2KB */ +#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ + +#endif /* oneNAND */ +#endif /* __CONFIG_H */ + diff --git a/include/configs/omap3530beagle.h b/include/configs/omap3530beagle.h new file mode 100644 index 0000000..5625417 --- /dev/null +++ b/include/configs/omap3530beagle.h @@ -0,0 +1,205 @@ +/* + * (C) Copyright 2006 + * Texas Instruments + * Richard Woodruff + * + * X-Loader Configuation settings for the TI OMAP SDP3430 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* serial printf facility takes about 3.5K */ +#define CFG_PRINTF +//#undef CFG_PRINTF + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ + +#define CONFIG_BEAGLE_REV2 1 + +/* Enable the below macro if MMC boot support is required */ +#define CONFIG_MMC 1 +#if defined(CONFIG_MMC) + #define CFG_CMD_MMC 1 + #define CFG_CMD_FAT 1 + #define CFG_I2C_SPEED 100000 + #define CFG_I2C_SLAVE 1 + #define CFG_I2C_BUS 0 + #define CFG_I2C_BUS_SELECT 1 + #define CONFIG_DRIVER_OMAP34XX_I2C 1 +#endif + +#include /* get chip and board defs */ + +/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ +//#define CFG_UDELAY + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ + +#if (V_OSCK > 19200000) +#define V_SCLK (V_OSCK >> 1) +#else +#define V_SCLK V_OSCK +#endif + +//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ +#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */ + +/* Memory type */ +#define CFG_3430SDRAM_DDR 1 + +/* The actual register values are defined in u-boot- mem.h */ +/* SDRAM Bank Allocation method */ +//#define SDRC_B_R_C 1 +//#define SDRC_B1_R_B0_C 1 +#define SDRC_R_B_C 1 + +#define NAND_BASE_ADR NAND_BASE +#define ONENAND_BASE ONENAND_MAP +#define ONENAND_ADDR ONENAND_BASE + +#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M + +#ifdef CFG_PRINTF + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE -4 +#define CFG_NS16550_CLK 48000000 +#define CFG_NS16550_COM3 OMAP34XX_UART3 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 3 /* use UART3 */ +#define CONFIG_CONS_INDEX 3 + +#define CONFIG_BAUDRATE 115200 +#define CFG_PBSIZE 256 + +#endif /* CFG_PRINTF */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LOADADDR 0x80008000 + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Board NAND Info. + */ + + +#define CFG_NAND_K9F1G08R0A +#define NAND_16BIT + +/* NAND is partitioned: + * 0x00000000 - 0x0007FFFF Booting Image + * 0x00080000 - 0x000BFFFF U-Boot Image + * 0x000C0000 - 0x000FFFFF U-Boot Env Data (X-loader doesn't care) + * 0x00100000 - 0x002FFFFF Kernel Image + * 0x00300000 - 0x08000000 depends on application + */ +#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */ +#define NAND_UBOOT_END 0x0160000 /* Giving a space of 2 blocks = 256KB */ +#define NAND_BLOCK_SIZE 0x20000 + +#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) +#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) +#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) +#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) + +#ifdef NAND_16BIT +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0) +#define READ_NAND(adr) \ + (*(volatile u16 *)GPMC_NAND_DATA_0) +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) + +#else /* to support 8-bit NAND devices */ +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0) +#define READ_NAND(adr) \ + (*(volatile u8 *)GPMC_NAND_DATA_0); +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) + +#endif + +#define NAND_CTL_CLRALE(adr) +#define NAND_CTL_SETALE(adr) +#define NAND_CTL_CLRCLE(adr) +#define NAND_CTL_SETCLE(adr) +#define NAND_DISABLE_CE() +#define NAND_ENABLE_CE() + +/*----------------------------------------------------------------------- + * Board oneNAND Info. + */ +#define CFG_SYNC_BURST_READ 1 + +/* OneNAND is partitioned: + * 0x0000000 - 0x0080000 X-Loader + * 0x0080000 - 0x00c0000 U-boot Image + * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care) + * 0x00e0000 - 0x0120000 Kernel Image + * 0x0120000 - 0x4000000 depends on application + */ + +#define ONENAND_START_BLOCK 4 +#define ONENAND_END_BLOCK 6 +#define ONENAND_PAGE_SIZE 2048 /* 2KB */ +#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ + +#endif /* __CONFIG_H */ + diff --git a/include/configs/omap3530gta04.h b/include/configs/omap3530gta04.h new file mode 100644 index 0000000..3e6ef21 --- /dev/null +++ b/include/configs/omap3530gta04.h @@ -0,0 +1,216 @@ +/* + * (C) Copyright 2006 + * Texas Instruments + * Richard Woodruff + * + * X-Loader Configuation settings for the TI OMAP SDP3430 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* configure for GTA04 with DM3730 */ +#define CONFIG_OMAP36XX 1 /* or 36XX (DM3730) */ +#define PRCM_CLK_CFG2_400MHZ 1 + +/* serial printf facility takes about 3.5K */ +#define CFG_PRINTF +//#undef CFG_PRINTF + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +//#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ + +#define CONFIG_BEAGLE_REV2 1 + +/* Enable the below macro if MMC boot support is required */ +//#define CONFIG_MMC 1 +#if defined(CONFIG_MMC) + #define CFG_CMD_MMC 1 + #define CFG_CMD_FAT 1 + #define CFG_I2C_SPEED 100000 + #define CFG_I2C_SLAVE 1 + #define CFG_I2C_BUS 0 + #define CFG_I2C_BUS_SELECT 1 + #define CONFIG_DRIVER_OMAP34XX_I2C 1 +#endif + +#include /* get chip and board defs */ + +/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ +//#define CFG_UDELAY + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ + +#if (V_OSCK > 19200000) +#define V_SCLK (V_OSCK >> 1) +#else +#define V_SCLK V_OSCK +#endif + +//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ +#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */ + +/* Memory type */ +#define CFG_3430SDRAM_DDR 1 + +/* The actual register values are defined in u-boot- mem.h */ +/* SDRAM Bank Allocation method */ +//#define SDRC_B_R_C 1 +//#define SDRC_B1_R_B0_C 1 +#define SDRC_R_B_C 1 + +/* Enable the below macro if NAND boot support is required */ +//#define CONFIG_NAND 1 + +#define NAND_BASE_ADR NAND_BASE +#define ONENAND_BASE ONENAND_MAP +#define ONENAND_ADDR ONENAND_BASE + +#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M + +#ifdef CFG_PRINTF + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE -4 +#define CFG_NS16550_CLK 48000000 +#define CFG_NS16550_COM3 OMAP34XX_UART3 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 3 /* use UART3 */ +#define CONFIG_CONS_INDEX 3 + +#define CONFIG_BAUDRATE 115200 +#define CFG_PBSIZE 256 + +#endif /* CFG_PRINTF */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LOADADDR 0x80008000 + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#if defined(CONFIG_NAND) + +/*----------------------------------------------------------------------- + * Board NAND Info. + */ + + +#define CFG_NAND_K9F1G08R0A +#define NAND_16BIT + +/* NAND is partitioned: + * 0x00000000 - 0x0007FFFF Booting Image + * 0x00080000 - 0x000BFFFF U-Boot Image + * 0x000C0000 - 0x000FFFFF U-Boot Env Data (X-loader doesn't care) + * 0x00100000 - 0x002FFFFF Kernel Image + * 0x00300000 - 0x08000000 depends on application + */ +#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */ +#define NAND_UBOOT_END 0x0160000 /* Giving a space of 2 blocks = 256KB */ +#define NAND_BLOCK_SIZE 0x20000 + +#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) +#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) +#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) +#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) + +#ifdef NAND_16BIT +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0) +#define READ_NAND(adr) \ + (*(volatile u16 *)GPMC_NAND_DATA_0) +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) + +#else /* to support 8-bit NAND devices */ +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0) +#define READ_NAND(adr) \ + (*(volatile u8 *)GPMC_NAND_DATA_0); +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) + +#endif + +#define NAND_CTL_CLRALE(adr) +#define NAND_CTL_SETALE(adr) +#define NAND_CTL_CLRCLE(adr) +#define NAND_CTL_SETCLE(adr) +#define NAND_DISABLE_CE() +#define NAND_ENABLE_CE() + +/*----------------------------------------------------------------------- + * Board oneNAND Info. + */ +#define CFG_SYNC_BURST_READ 1 + +/* OneNAND is partitioned: + * 0x0000000 - 0x0080000 X-Loader + * 0x0080000 - 0x00c0000 U-boot Image + * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care) + * 0x00e0000 - 0x0120000 Kernel Image + * 0x0120000 - 0x4000000 depends on application + */ + +#define ONENAND_START_BLOCK 4 +#define ONENAND_END_BLOCK 6 +#define ONENAND_PAGE_SIZE 2048 /* 2KB */ +#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ + +#endif + +#endif /* __CONFIG_H */ + diff --git a/include/configs/omap3evm.h b/include/configs/omap3evm.h new file mode 100644 index 0000000..10e48ba --- /dev/null +++ b/include/configs/omap3evm.h @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2007 Mistral Solutions Pvt Ltd. + * + * X-Loader Configuation settings for the OMAP3EVM board. + * + * Derived from /include/configs/omap3430sdp.h + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* serial printf facility takes about 3.5K */ +#define CFG_PRINTF +//#undef CFG_PRINTF + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +//#define CONFIG_3430SDP 1 /* working with SDP */ +//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ + +#define CONFIG_OMAP3EVM 1 /* working with EVM */ + +/* Enable the below macro if MMC boot support is required */ +#define CONFIG_MMC 1 +#if defined(CONFIG_MMC) + #define CFG_CMD_MMC 1 + #define CFG_CMD_FAT 1 + #define CFG_I2C_SPEED 100000 + #define CFG_I2C_SLAVE 1 + #define CFG_I2C_BUS 0 + #define CFG_I2C_BUS_SELECT 1 + #define CONFIG_DRIVER_OMAP34XX_I2C 1 +#endif + +#include /* get chip and board defs */ + +/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ +//#define CFG_UDELAY + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ + +#if (V_OSCK > 19200000) +#define V_SCLK (V_OSCK >> 1) +#else +#define V_SCLK V_OSCK +#endif + +//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ +#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */ + +/* Memory type */ +#define CFG_3430SDRAM_DDR 1 + +/* The actual register values are defined in u-boot- mem.h */ +/* SDRAM Bank Allocation method */ +//#define SDRC_B_R_C 1 +//#define SDRC_B1_R_B0_C 1 +#define SDRC_R_B_C 1 + + +# define NAND_BASE_ADR NAND_BASE /* NAND flash */ +# define ONENAND_BASE ONENAND_MAP /* OneNand flash */ + +#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M +#define ONENAND_ADDR ONENAND_BASE /* physical address of OneNAND at CS0*/ + +#ifdef CFG_PRINTF + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (48000000) +#define CFG_NS16550_COM1 OMAP34XX_UART1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* UART1 on OMAP3EVM */ +#define CONFIG_CONS_INDEX 1 + +#define CONFIG_BAUDRATE 115200 +#define CFG_PBSIZE 256 + +#endif /* CFG_PRINTF */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LOADADDR 0x80008000 + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Board NAND Info. + */ + + +#define CFG_NAND_K9F1G08R0A /* Samsung 8-bit 128MB chip large page NAND chip*/ +#define NAND_16BIT + +/* NAND is partitioned: + * 0x00000000 - 0x0007FFFF Booting Image + * 0x00080000 - 0x0023FFFF U-Boot Image + * 0x00240000 - 0x0027FFFF U-Boot Env Data (X-loader doesn't care) + * 0x00280000 - 0x0077FFFF Kernel Image + * 0x00780000 - 0x08000000 depends on application + */ +#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */ +#define NAND_UBOOT_END 0x0240000 /* Giving a space of 2 blocks = 256KB */ +#define NAND_BLOCK_SIZE 0x20000 + +#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) +#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) +#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) +#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) + +#ifdef NAND_16BIT +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0) +#define READ_NAND(adr) \ + (*(volatile u16 *)GPMC_NAND_DATA_0) +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) + +#else /* to support 8-bit NAND devices */ +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d;} while(0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d;} while(0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_DATA_0 = d;} while(0) +#define READ_NAND(adr) \ + (*(volatile u8 *)GPMC_NAND_DATA_0); +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) + +#endif + +#define NAND_CTL_CLRALE(adr) +#define NAND_CTL_SETALE(adr) +#define NAND_CTL_CLRCLE(adr) +#define NAND_CTL_SETCLE(adr) +#define NAND_DISABLE_CE() +#define NAND_ENABLE_CE() + +/*----------------------------------------------------------------------- + * Board oneNAND Info. + */ +#define CFG_SYNC_BURST_READ 1 + +/* OneNAND is partitioned: + * 0x0000000 - 0x0080000 X-Loader + * 0x0080000 - 0x0240000 U-boot Image + * 0x0240000 - 0x0280000 U-Boot Env Data (X-loader doesn't care) + * 0x0280000 - 0x0780000 Kernel Image + * 0x0780000 - 0x8000000 depends on application + */ + +#define ONENAND_START_BLOCK 4 +#define ONENAND_END_BLOCK 18 +#define ONENAND_PAGE_SIZE 2048 /* 2KB */ +#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ + +#endif /* __CONFIG_H */ + diff --git a/include/configs/omap4430panda.h b/include/configs/omap4430panda.h new file mode 100644 index 0000000..74e2f42 --- /dev/null +++ b/include/configs/omap4430panda.h @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2006 + * Texas Instruments + * Richard Woodruff + * + * X-Loader Configuation settings for the TI OMAP SDP3430 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* serial printf facility takes about 3.5K */ +#define CFG_PRINTF +//#undef CFG_PRINTF + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA9 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP44XX 1 /* which is a 34XX */ +#define CONFIG_OMAP4430 1 /* which is in a 3430 */ +#define CONFIG_4430PANDA 1 /* working with SDP */ + +/* Keep Default @ 33MHz at boot loader level + * On Phoenix board vlotage needs to be bumped up + * before scaling the MPU up + */ +#define CONFIG_MPU_600 1 +#define CORE_190MHZ 1 +/* Enable the below macro if MMC boot support is required */ +#define CONFIG_MMC 1 +#if defined(CONFIG_MMC) + /* To Enable MMC boot for OMAP4430 Panda */ + //#define CONFIG_MMC1 1 + /* To Enable EMMC boot for OMAP4430 Panda */ + #define CONFIG_MMC2 1 + #define CFG_CMD_MMC 1 + #define CFG_CMD_FAT 1 +#endif + +#include /* get chip and board defs */ + +/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ +//#define CFG_UDELAY + +/* Clock Defines */ +#define V_OSCK 19200000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + +/* Memory type */ +#define CFG_4430SDRAM_DDR 1 + +#ifdef CFG_PRINTF + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (48000000) +#define CFG_NS16550_COM3 OMAP44XX_UART3 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* UART1 on 3430SDP */ +#define CONFIG_CONS_INDEX 3 + +#define CONFIG_BAUDRATE 115200 +#define CFG_PBSIZE 256 + +#endif /* CFG_PRINTF */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LOADADDR 0x80e80000 + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CFG_ENV_SIZE 0x100 +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#endif /* __CONFIG_H */ + diff --git a/include/configs/overo.h b/include/configs/overo.h new file mode 100644 index 0000000..70e3683 --- /dev/null +++ b/include/configs/overo.h @@ -0,0 +1,205 @@ +/* + * (C) Copyright 2006 + * Texas Instruments + * Richard Woodruff + * + * X-Loader Configuation settings for the overo board. + * + * Derived from /include/configs/omap3evm.h + * Steve Sakoman + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* serial printf facility takes about 3.5K */ +#define CFG_PRINTF +//#undef CFG_PRINTF + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OVERO 1 /* working with overo */ + +/* Enable the below macro if MMC boot support is required */ +#define CONFIG_MMC 1 +#if defined(CONFIG_MMC) + #define CFG_CMD_MMC 1 + #define CFG_CMD_FAT 1 + #define CFG_I2C_SPEED 100000 + #define CFG_I2C_SLAVE 1 + #define CFG_I2C_BUS 0 + #define CFG_I2C_BUS_SELECT 1 + #define CONFIG_DRIVER_OMAP34XX_I2C 1 +#endif + +#include /* get chip and board defs */ + +/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ +//#define CFG_UDELAY + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ + +#if (V_OSCK > 19200000) +#define V_SCLK (V_OSCK >> 1) +#else +#define V_SCLK V_OSCK +#endif + +//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ +#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */ + +/* Memory type */ +#define CFG_3430SDRAM_DDR 1 + +/* The actual register values are defined in u-boot- mem.h */ +/* SDRAM Bank Allocation method */ +//#define SDRC_B_R_C 1 +//#define SDRC_B1_R_B0_C 1 +#define SDRC_R_B_C 1 + +#define NAND_BASE_ADR NAND_BASE +#define ONENAND_BASE ONENAND_MAP +#define ONENAND_ADDR ONENAND_BASE + +#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M + +#ifdef CFG_PRINTF + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE -4 +#define CFG_NS16550_CLK 48000000 +#define CFG_NS16550_COM3 OMAP34XX_UART3 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 3 /* use UART3 */ +#define CONFIG_CONS_INDEX 3 + +#define CONFIG_BAUDRATE 115200 +#define CFG_PBSIZE 256 + +#endif /* CFG_PRINTF */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LOADADDR 0x80008000 + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Board NAND Info. + */ + +#define CFG_NAND_K9F1G08R0A +#define NAND_16BIT + +/* NAND is partitioned: + * 0x00000000 - 0x0007FFFF Booting Image + * 0x00080000 - 0x0023FFFF U-Boot Image + * 0x00240000 - 0x0027FFFF U-Boot Env Data (X-loader doesn't care) + * 0x00280000 - 0x0077FFFF Kernel Image + * 0x00780000 - 0x08000000 depends on application + */ +#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */ +#define NAND_UBOOT_END 0x0240000 /* Giving a space of 2 blocks = 256KB */ +#define NAND_BLOCK_SIZE 0x20000 + +#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) +#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) +#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) +#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) + +#ifdef NAND_16BIT +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0) +#define READ_NAND(adr) \ + (*(volatile u16 *)GPMC_NAND_DATA_0) +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) + +#else /* to support 8-bit NAND devices */ +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0) +#define READ_NAND(adr) \ + (*(volatile u8 *)GPMC_NAND_DATA_0); +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) + +#endif + +#define NAND_CTL_CLRALE(adr) +#define NAND_CTL_SETALE(adr) +#define NAND_CTL_CLRCLE(adr) +#define NAND_CTL_SETCLE(adr) +#define NAND_DISABLE_CE() +#define NAND_ENABLE_CE() + +/*----------------------------------------------------------------------- + * Board oneNAND Info. + */ +#define CFG_SYNC_BURST_READ 1 + +/* OneNAND is partitioned: + * 0x0000000 - 0x0080000 X-Loader + * 0x0080000 - 0x0240000 U-boot Image + * 0x0240000 - 0x0280000 U-Boot Env Data (X-loader doesn't care) + * 0x0280000 - 0x0780000 Kernel Image + * 0x0780000 - 0x8000000 depends on application + */ + +#define ONENAND_START_BLOCK 4 +#define ONENAND_END_BLOCK 18 +#define ONENAND_PAGE_SIZE 2048 /* 2KB */ +#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ + +#endif /* __CONFIG_H */ + diff --git a/include/fat.h b/include/fat.h new file mode 100644 index 0000000..4f70981 --- /dev/null +++ b/include/fat.h @@ -0,0 +1,215 @@ +/* + * R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg + * + * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6 + * 2003-03-10 - kharris@nexus-tech.net - ported to u-boot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _FAT_H_ +#define _FAT_H_ + +#include + +#define CONFIG_SUPPORT_VFAT + +#define SECTOR_SIZE FS_BLOCK_SIZE + +#define FS_BLOCK_SIZE 512 + +#if FS_BLOCK_SIZE != SECTOR_SIZE +#error FS_BLOCK_SIZE != SECTOR_SIZE - This code needs to be fixed! +#endif + +#define MAX_CLUSTSIZE 65536 +#define DIRENTSPERBLOCK (FS_BLOCK_SIZE/sizeof(dir_entry)) +#define DIRENTSPERCLUST ((mydata->clust_size*SECTOR_SIZE)/sizeof(dir_entry)) + +#define FATBUFBLOCKS 6 +#define FATBUFSIZE (FS_BLOCK_SIZE*FATBUFBLOCKS) +#define FAT12BUFSIZE ((FATBUFSIZE*2)/3) +#define FAT16BUFSIZE (FATBUFSIZE/2) +#define FAT32BUFSIZE (FATBUFSIZE/4) + + +/* Filesystem identifiers */ +#define FAT12_SIGN "FAT12 " +#define FAT16_SIGN "FAT16 " +#define FAT32_SIGN "FAT32 " +#define SIGNLEN 8 + +/* File attributes */ +#define ATTR_RO 1 +#define ATTR_HIDDEN 2 +#define ATTR_SYS 4 +#define ATTR_VOLUME 8 +#define ATTR_DIR 16 +#define ATTR_ARCH 32 + +#define ATTR_VFAT (ATTR_RO | ATTR_HIDDEN | ATTR_SYS | ATTR_VOLUME) + +#define DELETED_FLAG ((char)0xe5) /* Marks deleted files when in name[0] */ +#define aRING 0x05 /* Used to represent 'å' in name[0] */ + +/* Indicates that the entry is the last long entry in a set of long + * dir entries + */ +#define LAST_LONG_ENTRY_MASK 0x40 + +/* Flags telling whether we should read a file or list a directory */ +#define LS_NO 0 +#define LS_YES 1 +#define LS_DIR 1 +#define LS_ROOT 2 + +#ifdef DEBUG +#define FAT_DPRINT(args...) printf(args) +#else +#define FAT_DPRINT(args...) +#endif +#define FAT_ERROR(args...) printf(args) + +#define ISDIRDELIM(c) ((c) == '/' || (c) == '\\') + +#define FSTYPE_NONE (-1) + +#if defined(__linux__) && defined(__KERNEL__) +#define FAT2CPU16 le16_to_cpu +#define FAT2CPU32 le32_to_cpu +#else +#if __LITTLE_ENDIAN +#define FAT2CPU16(x) (x) +#define FAT2CPU32(x) (x) +#else +#define FAT2CPU16(x) ((((x) & 0x00ff) << 8) | (((x) & 0xff00) >> 8)) +#define FAT2CPU32(x) ((((x) & 0x000000ff) << 24) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0xff000000) >> 24)) +#endif +#endif + +#define TOLOWER(c) if((c) >= 'A' && (c) <= 'Z'){(c)+=('a' - 'A');} +#define START(dent) (FAT2CPU16((dent)->start) \ + + (mydata->fatsize != 32 ? 0 : \ + (FAT2CPU16((dent)->starthi) << 16))) + + +typedef struct boot_sector { + __u8 ignored[3]; /* Bootstrap code */ + char system_id[8]; /* Name of fs */ + __u8 sector_size[2]; /* Bytes/sector */ + __u8 cluster_size; /* Sectors/cluster */ + __u16 reserved; /* Number of reserved sectors */ + __u8 fats; /* Number of FATs */ + __u8 dir_entries[2]; /* Number of root directory entries */ + __u8 sectors[2]; /* Number of sectors */ + __u8 media; /* Media code */ + __u16 fat_length; /* Sectors/FAT */ + __u16 secs_track; /* Sectors/track */ + __u16 heads; /* Number of heads */ + __u32 hidden; /* Number of hidden sectors */ + __u32 total_sect; /* Number of sectors (if sectors == 0) */ + + /* FAT32 only */ + __u32 fat32_length; /* Sectors/FAT */ + __u16 flags; /* Bit 8: fat mirroring, low 4: active fat */ + __u8 version[2]; /* Filesystem version */ + __u32 root_cluster; /* First cluster in root directory */ + __u16 info_sector; /* Filesystem info sector */ + __u16 backup_boot; /* Backup boot sector */ + __u16 reserved2[6]; /* Unused */ +} boot_sector; + +typedef struct volume_info +{ + __u8 drive_number; /* BIOS drive number */ + __u8 reserved; /* Unused */ + __u8 ext_boot_sign; /* 0x29 if fields below exist (DOS 3.3+) */ + __u8 volume_id[4]; /* Volume ID number */ + char volume_label[11]; /* Volume label */ + char fs_type[8]; /* Typically FAT12, FAT16, or FAT32 */ + /* Boot code comes next, all but 2 bytes to fill up sector */ + /* Boot sign comes last, 2 bytes */ +} volume_info; + +typedef struct dir_entry { + char name[8],ext[3]; /* Name and extension */ + __u8 attr; /* Attribute bits */ + __u8 lcase; /* Case for base and extension */ + __u8 ctime_ms; /* Creation time, milliseconds */ + __u16 ctime; /* Creation time */ + __u16 cdate; /* Creation date */ + __u16 adate; /* Last access date */ + __u16 starthi; /* High 16 bits of cluster in FAT32 */ + __u16 time,date,start;/* Time, date and first cluster */ + __u32 size; /* File size in bytes */ +} dir_entry; + +typedef struct dir_slot { + __u8 id; /* Sequence number for slot */ + __u8 name0_4[10]; /* First 5 characters in name */ + __u8 attr; /* Attribute byte */ + __u8 reserved; /* Unused */ + __u8 alias_checksum;/* Checksum for 8.3 alias */ + __u8 name5_10[12]; /* 6 more characters in name */ + __u16 start; /* Unused */ + __u8 name11_12[4]; /* Last 2 characters in name */ +} dir_slot; + +/* Private filesystem parameters */ +typedef struct { + int fatsize; /* Size of FAT in bits */ + __u16 fatlength; /* Length of FAT in sectors */ + __u16 fat_sect; /* Starting sector of the FAT */ + __u16 rootdir_sect; /* Start sector of root directory */ + __u16 clust_size; /* Size of clusters in sectors */ + short data_begin; /* The sector of the first cluster, can be negative */ + __u32 fatbuf[FATBUFSIZE]; /* Current FAT buffer */ + int fatbufnum; /* Used by get_fatent, init to -1 */ +} fsdata; + +typedef int (file_detectfs_func)(void); +typedef int (file_ls_func)(const char *dir); +typedef long (file_read_func)(const char *filename, void *buffer, + unsigned long maxsize); + +struct filesystem { + file_detectfs_func *detect; + file_ls_func *ls; + file_read_func *read; + const char name[12]; +}; + +/* FAT tables */ +file_detectfs_func file_fat_detectfs; +file_ls_func file_fat_ls; +file_read_func file_fat_read; + +/* Currently this doesn't check if the dir exists or is valid... */ +int file_cd(const char *path); +int file_fat_detectfs(void); +int file_fat_ls(const char *dir); +long file_fat_read(const char *filename, void *buffer, unsigned long maxsize); +const char *file_getfsname(int idx); +int fat_register_device(block_dev_desc_t *dev_desc, int part_no); + +#endif /* _FAT_H_ */ diff --git a/include/i2c.h b/include/i2c.h new file mode 100644 index 0000000..a51c164 --- /dev/null +++ b/include/i2c.h @@ -0,0 +1,151 @@ +/* + * (C) Copyright 2001 + * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * The original I2C interface was + * (C) 2000 by Paolo Scaffardi (arsenio@tin.it) + * AIRVENT SAM s.p.a - RIMINI(ITALY) + * but has been changed substantially. + */ + +#ifndef _I2C_H_ +#define _I2C_H_ + +/* + * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING + * + * The implementation MUST NOT use static or global variables if the + * I2C routines are used to read SDRAM configuration information + * because this is done before the memories are initialized. Limited + * use of stack-based variables are OK (the initial stack size is + * limited). + * + * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING + */ + +/* + * Configuration items. + */ +#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ + +#if defined(CONFIG_I2C_MULTI_BUS) +#define CFG_MAX_I2C_BUS 2 +#define I2C_GET_BUS() i2c_get_bus_num() +#define I2C_SET_BUS(a) i2c_set_bus_num(a) +#else +#define CFG_MAX_I2C_BUS 1 +#define I2C_GET_BUS() 0 +#define I2C_SET_BUS(a) +#endif + +/* define the I2C bus number for RTC and DTT if not already done */ +#if !defined(CFG_RTC_BUS_NUM) +#define CFG_RTC_BUS_NUM 0 +#endif +#if !defined(CFG_DTT_BUS_NUM) +#define CFG_DTT_BUS_NUM 0 +#endif +#if !defined(CFG_SPD_BUS_NUM) +#define CFG_SPD_BUS_NUM 0 +#endif + +/* + * Initialization, must be called once on start up, may be called + * repeatedly to change the speed and slave addresses. + */ +void i2c_init(int speed, int slaveaddr); +#ifdef CFG_I2C_INIT_BOARD +void i2c_init_board(void); +#endif + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ +int i2c_probe(uchar chip); + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); + +/* + * Utility routines to read/write registers. + */ +uchar i2c_reg_read (uchar chip, uchar reg); +void i2c_reg_write(uchar chip, uchar reg, uchar val); + +/* + * Functions for setting the current I2C bus and its speed + */ + +/* + * i2c_set_bus_num: + * + * Change the active I2C bus. Subsequent read/write calls will + * go to this one. + * + * bus - bus index, zero based + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_num(unsigned int bus); + +/* + * i2c_get_bus_num: + * + * Returns index of currently active I2C bus. Zero-based. + */ + +unsigned int i2c_get_bus_num(void); + +/* + * i2c_set_bus_speed: + * + * Change the speed of the active I2C bus + * + * speed - bus speed in Hz + * + * Returns: 0 on success, not 0 on failure + * + */ +int i2c_set_bus_speed(unsigned int); + +/* + * i2c_get_bus_speed: + * + * Returns speed of currently active I2C bus in Hz + */ + +unsigned int i2c_get_bus_speed(void); + +#endif /* _I2C_H_ */ diff --git a/include/ide.h b/include/ide.h new file mode 100644 index 0000000..dfef32f --- /dev/null +++ b/include/ide.h @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IDE_H +#define _IDE_H + +#define IDE_BUS(dev) (dev >> 1) + +#ifdef CONFIG_IDE_LED + +/* + * LED Port + */ +#define LED_PORT ((uchar *)(PER8_BASE + 0x3000)) +#define LED_IDE1 0x01 +#define LED_IDE2 0x02 +#define DEVICE_LED(d) ((d & 2) | ((d & 2) == 0)) /* depends on bit positions! */ + +#endif /* CONFIG_IDE_LED */ + +#ifdef CFG_64BIT_LBA +typedef uint64_t lbaint_t; +#else +typedef ulong lbaint_t; +#endif + +/* + * Function Prototypes + */ + +void ide_init (void); +ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer); +ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer); + +#endif /* _IDE_H */ diff --git a/include/linux/byteorder/big_endian.h b/include/linux/byteorder/big_endian.h new file mode 100644 index 0000000..19b0c86 --- /dev/null +++ b/include/linux/byteorder/big_endian.h @@ -0,0 +1,69 @@ +#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H +#define _LINUX_BYTEORDER_BIG_ENDIAN_H + +#ifndef __BIG_ENDIAN +#define __BIG_ENDIAN 4321 +#endif +#ifndef __BIG_ENDIAN_BITFIELD +#define __BIG_ENDIAN_BITFIELD +#endif +#define __BYTE_ORDER __BIG_ENDIAN + +#include + +#define __constant_htonl(x) ((__u32)(x)) +#define __constant_ntohl(x) ((__u32)(x)) +#define __constant_htons(x) ((__u16)(x)) +#define __constant_ntohs(x) ((__u16)(x)) +#define __constant_cpu_to_le64(x) ___swab64((x)) +#define __constant_le64_to_cpu(x) ___swab64((x)) +#define __constant_cpu_to_le32(x) ___swab32((x)) +#define __constant_le32_to_cpu(x) ___swab32((x)) +#define __constant_cpu_to_le16(x) ___swab16((x)) +#define __constant_le16_to_cpu(x) ___swab16((x)) +#define __constant_cpu_to_be64(x) ((__u64)(x)) +#define __constant_be64_to_cpu(x) ((__u64)(x)) +#define __constant_cpu_to_be32(x) ((__u32)(x)) +#define __constant_be32_to_cpu(x) ((__u32)(x)) +#define __constant_cpu_to_be16(x) ((__u16)(x)) +#define __constant_be16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_le64(x) __swab64((x)) +#define __le64_to_cpu(x) __swab64((x)) +#define __cpu_to_le32(x) __swab32((x)) +#define __le32_to_cpu(x) __swab32((x)) +#define __cpu_to_le16(x) __swab16((x)) +#define __le16_to_cpu(x) __swab16((x)) +#define __cpu_to_be64(x) ((__u64)(x)) +#define __be64_to_cpu(x) ((__u64)(x)) +#define __cpu_to_be32(x) ((__u32)(x)) +#define __be32_to_cpu(x) ((__u32)(x)) +#define __cpu_to_be16(x) ((__u16)(x)) +#define __be16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_le64p(x) __swab64p((x)) +#define __le64_to_cpup(x) __swab64p((x)) +#define __cpu_to_le32p(x) __swab32p((x)) +#define __le32_to_cpup(x) __swab32p((x)) +#define __cpu_to_le16p(x) __swab16p((x)) +#define __le16_to_cpup(x) __swab16p((x)) +#define __cpu_to_be64p(x) (*(__u64*)(x)) +#define __be64_to_cpup(x) (*(__u64*)(x)) +#define __cpu_to_be32p(x) (*(__u32*)(x)) +#define __be32_to_cpup(x) (*(__u32*)(x)) +#define __cpu_to_be16p(x) (*(__u16*)(x)) +#define __be16_to_cpup(x) (*(__u16*)(x)) +#define __cpu_to_le64s(x) __swab64s((x)) +#define __le64_to_cpus(x) __swab64s((x)) +#define __cpu_to_le32s(x) __swab32s((x)) +#define __le32_to_cpus(x) __swab32s((x)) +#define __cpu_to_le16s(x) __swab16s((x)) +#define __le16_to_cpus(x) __swab16s((x)) +#define __cpu_to_be64s(x) do {} while (0) +#define __be64_to_cpus(x) do {} while (0) +#define __cpu_to_be32s(x) do {} while (0) +#define __be32_to_cpus(x) do {} while (0) +#define __cpu_to_be16s(x) do {} while (0) +#define __be16_to_cpus(x) do {} while (0) + +#include + +#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */ diff --git a/include/linux/byteorder/generic.h b/include/linux/byteorder/generic.h new file mode 100644 index 0000000..cff850f --- /dev/null +++ b/include/linux/byteorder/generic.h @@ -0,0 +1,180 @@ +#ifndef _LINUX_BYTEORDER_GENERIC_H +#define _LINUX_BYTEORDER_GENERIC_H + +/* + * linux/byteorder_generic.h + * Generic Byte-reordering support + * + * Francois-Rene Rideau 19970707 + * gathered all the good ideas from all asm-foo/byteorder.h into one file, + * cleaned them up. + * I hope it is compliant with non-GCC compilers. + * I decided to put __BYTEORDER_HAS_U64__ in byteorder.h, + * because I wasn't sure it would be ok to put it in types.h + * Upgraded it to 2.1.43 + * Francois-Rene Rideau 19971012 + * Upgraded it to 2.1.57 + * to please Linus T., replaced huge #ifdef's between little/big endian + * by nestedly #include'd files. + * Francois-Rene Rideau 19971205 + * Made it to 2.1.71; now a facelift: + * Put files under include/linux/byteorder/ + * Split swab from generic support. + * + * TODO: + * = Regular kernel maintainers could also replace all these manual + * byteswap macros that remain, disseminated among drivers, + * after some grep or the sources... + * = Linus might want to rename all these macros and files to fit his taste, + * to fit his personal naming scheme. + * = it seems that a few drivers would also appreciate + * nybble swapping support... + * = every architecture could add their byteswap macro in asm/byteorder.h + * see how some architectures already do (i386, alpha, ppc, etc) + * = cpu_to_beXX and beXX_to_cpu might some day need to be well + * distinguished throughout the kernel. This is not the case currently, + * since little endian, big endian, and pdp endian machines needn't it. + * But this might be the case for, say, a port of Linux to 20/21 bit + * architectures (and F21 Linux addict around?). + */ + +/* + * The following macros are to be defined by : + * + * Conversion of long and short int between network and host format + * ntohl(__u32 x) + * ntohs(__u16 x) + * htonl(__u32 x) + * htons(__u16 x) + * It seems that some programs (which? where? or perhaps a standard? POSIX?) + * might like the above to be functions, not macros (why?). + * if that's true, then detect them, and take measures. + * Anyway, the measure is: define only ___ntohl as a macro instead, + * and in a separate file, have + * unsigned long inline ntohl(x){return ___ntohl(x);} + * + * The same for constant arguments + * __constant_ntohl(__u32 x) + * __constant_ntohs(__u16 x) + * __constant_htonl(__u32 x) + * __constant_htons(__u16 x) + * + * Conversion of XX-bit integers (16- 32- or 64-) + * between native CPU format and little/big endian format + * 64-bit stuff only defined for proper architectures + * cpu_to_[bl]eXX(__uXX x) + * [bl]eXX_to_cpu(__uXX x) + * + * The same, but takes a pointer to the value to convert + * cpu_to_[bl]eXXp(__uXX x) + * [bl]eXX_to_cpup(__uXX x) + * + * The same, but change in situ + * cpu_to_[bl]eXXs(__uXX x) + * [bl]eXX_to_cpus(__uXX x) + * + * See asm-foo/byteorder.h for examples of how to provide + * architecture-optimized versions + * + */ + + +#if defined(__KERNEL__) +/* + * inside the kernel, we can use nicknames; + * outside of it, we must avoid POSIX namespace pollution... + */ +#define cpu_to_le64 __cpu_to_le64 +#define le64_to_cpu __le64_to_cpu +#define cpu_to_le32 __cpu_to_le32 +#define le32_to_cpu __le32_to_cpu +#define cpu_to_le16 __cpu_to_le16 +#define le16_to_cpu __le16_to_cpu +#define cpu_to_be64 __cpu_to_be64 +#define be64_to_cpu __be64_to_cpu +#define cpu_to_be32 __cpu_to_be32 +#define be32_to_cpu __be32_to_cpu +#define cpu_to_be16 __cpu_to_be16 +#define be16_to_cpu __be16_to_cpu +#define cpu_to_le64p __cpu_to_le64p +#define le64_to_cpup __le64_to_cpup +#define cpu_to_le32p __cpu_to_le32p +#define le32_to_cpup __le32_to_cpup +#define cpu_to_le16p __cpu_to_le16p +#define le16_to_cpup __le16_to_cpup +#define cpu_to_be64p __cpu_to_be64p +#define be64_to_cpup __be64_to_cpup +#define cpu_to_be32p __cpu_to_be32p +#define be32_to_cpup __be32_to_cpup +#define cpu_to_be16p __cpu_to_be16p +#define be16_to_cpup __be16_to_cpup +#define cpu_to_le64s __cpu_to_le64s +#define le64_to_cpus __le64_to_cpus +#define cpu_to_le32s __cpu_to_le32s +#define le32_to_cpus __le32_to_cpus +#define cpu_to_le16s __cpu_to_le16s +#define le16_to_cpus __le16_to_cpus +#define cpu_to_be64s __cpu_to_be64s +#define be64_to_cpus __be64_to_cpus +#define cpu_to_be32s __cpu_to_be32s +#define be32_to_cpus __be32_to_cpus +#define cpu_to_be16s __cpu_to_be16s +#define be16_to_cpus __be16_to_cpus +#endif + + +/* + * Handle ntohl and suches. These have various compatibility + * issues - like we want to give the prototype even though we + * also have a macro for them in case some strange program + * wants to take the address of the thing or something.. + * + * Note that these used to return a "long" in libc5, even though + * long is often 64-bit these days.. Thus the casts. + * + * They have to be macros in order to do the constant folding + * correctly - if the argument passed into a inline function + * it is no longer constant according to gcc.. + */ + +#undef ntohl +#undef ntohs +#undef htonl +#undef htons + +/* + * Do the prototypes. Somebody might want to take the + * address or some such sick thing.. + */ +#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2) +extern __u32 ntohl(__u32); +extern __u32 htonl(__u32); +#else +extern unsigned long int ntohl(unsigned long int); +extern unsigned long int htonl(unsigned long int); +#endif +extern unsigned short int ntohs(unsigned short int); +extern unsigned short int htons(unsigned short int); + + +#if defined(__GNUC__) && (__GNUC__ >= 2) + +#define ___htonl(x) __cpu_to_be32(x) +#define ___htons(x) __cpu_to_be16(x) +#define ___ntohl(x) __be32_to_cpu(x) +#define ___ntohs(x) __be16_to_cpu(x) + +#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2) +#define htonl(x) ___htonl(x) +#define ntohl(x) ___ntohl(x) +#else +#define htonl(x) ((unsigned long)___htonl(x)) +#define ntohl(x) ((unsigned long)___ntohl(x)) +#endif +#define htons(x) ___htons(x) +#define ntohs(x) ___ntohs(x) + +#endif /* OPTIMIZE */ + + +#endif /* _LINUX_BYTEORDER_GENERIC_H */ diff --git a/include/linux/byteorder/little_endian.h b/include/linux/byteorder/little_endian.h new file mode 100644 index 0000000..a46f3ec --- /dev/null +++ b/include/linux/byteorder/little_endian.h @@ -0,0 +1,69 @@ +#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H +#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H + +#ifndef __LITTLE_ENDIAN +#define __LITTLE_ENDIAN 1234 +#endif +#ifndef __LITTLE_ENDIAN_BITFIELD +#define __LITTLE_ENDIAN_BITFIELD +#endif +#define __BYTE_ORDER __LITTLE_ENDIAN + +#include + +#define __constant_htonl(x) ___constant_swab32((x)) +#define __constant_ntohl(x) ___constant_swab32((x)) +#define __constant_htons(x) ___constant_swab16((x)) +#define __constant_ntohs(x) ___constant_swab16((x)) +#define __constant_cpu_to_le64(x) ((__u64)(x)) +#define __constant_le64_to_cpu(x) ((__u64)(x)) +#define __constant_cpu_to_le32(x) ((__u32)(x)) +#define __constant_le32_to_cpu(x) ((__u32)(x)) +#define __constant_cpu_to_le16(x) ((__u16)(x)) +#define __constant_le16_to_cpu(x) ((__u16)(x)) +#define __constant_cpu_to_be64(x) ___constant_swab64((x)) +#define __constant_be64_to_cpu(x) ___constant_swab64((x)) +#define __constant_cpu_to_be32(x) ___constant_swab32((x)) +#define __constant_be32_to_cpu(x) ___constant_swab32((x)) +#define __constant_cpu_to_be16(x) ___constant_swab16((x)) +#define __constant_be16_to_cpu(x) ___constant_swab16((x)) +#define __cpu_to_le64(x) ((__u64)(x)) +#define __le64_to_cpu(x) ((__u64)(x)) +#define __cpu_to_le32(x) ((__u32)(x)) +#define __le32_to_cpu(x) ((__u32)(x)) +#define __cpu_to_le16(x) ((__u16)(x)) +#define __le16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_be64(x) __swab64((x)) +#define __be64_to_cpu(x) __swab64((x)) +#define __cpu_to_be32(x) __swab32((x)) +#define __be32_to_cpu(x) __swab32((x)) +#define __cpu_to_be16(x) __swab16((x)) +#define __be16_to_cpu(x) __swab16((x)) +#define __cpu_to_le64p(x) (*(__u64*)(x)) +#define __le64_to_cpup(x) (*(__u64*)(x)) +#define __cpu_to_le32p(x) (*(__u32*)(x)) +#define __le32_to_cpup(x) (*(__u32*)(x)) +#define __cpu_to_le16p(x) (*(__u16*)(x)) +#define __le16_to_cpup(x) (*(__u16*)(x)) +#define __cpu_to_be64p(x) __swab64p((x)) +#define __be64_to_cpup(x) __swab64p((x)) +#define __cpu_to_be32p(x) __swab32p((x)) +#define __be32_to_cpup(x) __swab32p((x)) +#define __cpu_to_be16p(x) __swab16p((x)) +#define __be16_to_cpup(x) __swab16p((x)) +#define __cpu_to_le64s(x) do {} while (0) +#define __le64_to_cpus(x) do {} while (0) +#define __cpu_to_le32s(x) do {} while (0) +#define __le32_to_cpus(x) do {} while (0) +#define __cpu_to_le16s(x) do {} while (0) +#define __le16_to_cpus(x) do {} while (0) +#define __cpu_to_be64s(x) __swab64s((x)) +#define __be64_to_cpus(x) __swab64s((x)) +#define __cpu_to_be32s(x) __swab32s((x)) +#define __be32_to_cpus(x) __swab32s((x)) +#define __cpu_to_be16s(x) __swab16s((x)) +#define __be16_to_cpus(x) __swab16s((x)) + +#include + +#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */ diff --git a/include/linux/byteorder/swab.h b/include/linux/byteorder/swab.h new file mode 100644 index 0000000..b1d570e --- /dev/null +++ b/include/linux/byteorder/swab.h @@ -0,0 +1,158 @@ +#ifndef _LINUX_BYTEORDER_SWAB_H +#define _LINUX_BYTEORDER_SWAB_H + +/* + * linux/byteorder/swab.h + * Byte-swapping, independently from CPU endianness + * swabXX[ps]?(foo) + * + * Francois-Rene Rideau 19971205 + * separated swab functions from cpu_to_XX, + * to clean up support for bizarre-endian architectures. + * + * See asm-i386/byteorder.h and suches for examples of how to provide + * architecture-dependent optimized versions + * + */ + +/* casts are necessary for constants, because we never know how for sure + * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. + */ +#define ___swab16(x) \ + ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8) )) +#define ___swab32(x) \ + ((__u32)( \ + (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x) & (__u32)0xff000000UL) >> 24) )) +#define ___swab64(x) \ + ((__u64)( \ + (__u64)(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \ + (__u64)(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \ + (__u64)(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \ + (__u64)(((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \ + (__u64)(((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \ + (__u64)(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ + (__u64)(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \ + (__u64)(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56) )) + +/* + * provide defaults when no architecture-specific optimization is detected + */ +#ifndef __arch__swab16 +# define __arch__swab16(x) ___swab16(x) +#endif +#ifndef __arch__swab32 +# define __arch__swab32(x) ___swab32(x) +#endif +#ifndef __arch__swab64 +# define __arch__swab64(x) ___swab64(x) +#endif + +#ifndef __arch__swab16p +# define __arch__swab16p(x) __swab16(*(x)) +#endif +#ifndef __arch__swab32p +# define __arch__swab32p(x) __swab32(*(x)) +#endif +#ifndef __arch__swab64p +# define __arch__swab64p(x) __swab64(*(x)) +#endif + +#ifndef __arch__swab16s +# define __arch__swab16s(x) do { *(x) = __swab16p((x)); } while (0) +#endif +#ifndef __arch__swab32s +# define __arch__swab32s(x) do { *(x) = __swab32p((x)); } while (0) +#endif +#ifndef __arch__swab64s +# define __arch__swab64s(x) do { *(x) = __swab64p((x)); } while (0) +#endif + + +/* + * Allow constant folding + */ +#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) +# define __swab16(x) \ +(__builtin_constant_p((__u16)(x)) ? \ + ___swab16((x)) : \ + __fswab16((x))) +# define __swab32(x) \ +(__builtin_constant_p((__u32)(x)) ? \ + ___swab32((x)) : \ + __fswab32((x))) +# define __swab64(x) \ +(__builtin_constant_p((__u64)(x)) ? \ + ___swab64((x)) : \ + __fswab64((x))) +#else +# define __swab16(x) __fswab16(x) +# define __swab32(x) __fswab32(x) +# define __swab64(x) __fswab64(x) +#endif /* OPTIMIZE */ + + +static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x) +{ + return __arch__swab16(x); +} +static __inline__ __u16 __swab16p(__u16 *x) +{ + return __arch__swab16p(x); +} +static __inline__ void __swab16s(__u16 *addr) +{ + __arch__swab16s(addr); +} + +static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x) +{ + return __arch__swab32(x); +} +static __inline__ __u32 __swab32p(__u32 *x) +{ + return __arch__swab32p(x); +} +static __inline__ void __swab32s(__u32 *addr) +{ + __arch__swab32s(addr); +} + +#ifdef __BYTEORDER_HAS_U64__ +static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x) +{ +# ifdef __SWAB_64_THRU_32__ + __u32 h = x >> 32; + __u32 l = x & ((1ULL<<32)-1); + return (((__u64)__swab32(l)) << 32) | ((__u64)(__swab32(h))); +# else + return __arch__swab64(x); +# endif +} +static __inline__ __u64 __swab64p(__u64 *x) +{ + return __arch__swab64p(x); +} +static __inline__ void __swab64s(__u64 *addr) +{ + __arch__swab64s(addr); +} +#endif /* __BYTEORDER_HAS_U64__ */ + +#if defined(__KERNEL__) +#define swab16 __swab16 +#define swab32 __swab32 +#define swab64 __swab64 +#define swab16p __swab16p +#define swab32p __swab32p +#define swab64p __swab64p +#define swab16s __swab16s +#define swab32s __swab32s +#define swab64s __swab64s +#endif + +#endif /* _LINUX_BYTEORDER_SWAB_H */ diff --git a/include/linux/config.h b/include/linux/config.h new file mode 100644 index 0000000..a0194cb --- /dev/null +++ b/include/linux/config.h @@ -0,0 +1,6 @@ +#ifndef _LINUX_CONFIG_H +#define _LINUX_CONFIG_H + +/* #include */ + +#endif diff --git a/include/linux/posix_types.h b/include/linux/posix_types.h new file mode 100644 index 0000000..bd37e1f --- /dev/null +++ b/include/linux/posix_types.h @@ -0,0 +1,48 @@ +#ifndef _LINUX_POSIX_TYPES_H +#define _LINUX_POSIX_TYPES_H + +#include + +/* + * This allows for 1024 file descriptors: if NR_OPEN is ever grown + * beyond that you'll have to change this too. But 1024 fd's seem to be + * enough even for such "real" unices like OSF/1, so hopefully this is + * one limit that doesn't have to be changed [again]. + * + * Note that POSIX wants the FD_CLEAR(fd,fdsetp) defines to be in + * (and thus ) - but this is a more logical + * place for them. Solved by having dummy defines in . + */ + +/* + * Those macros may have been defined in . But we always + * use the ones here. + */ +#undef __NFDBITS +#define __NFDBITS (8 * sizeof(unsigned long)) + +#undef __FD_SETSIZE +#define __FD_SETSIZE 1024 + +#undef __FDSET_LONGS +#define __FDSET_LONGS (__FD_SETSIZE/__NFDBITS) + +#undef __FDELT +#define __FDELT(d) ((d) / __NFDBITS) + +#undef __FDMASK +#define __FDMASK(d) (1UL << ((d) % __NFDBITS)) + +typedef struct { + unsigned long fds_bits [__FDSET_LONGS]; +} __kernel_fd_set; + +/* Type of a signal handler. */ +typedef void (*__kernel_sighandler_t)(int); + +/* Type of a SYSV IPC key. */ +typedef int __kernel_key_t; + +#include + +#endif /* _LINUX_POSIX_TYPES_H */ diff --git a/include/linux/stat.h b/include/linux/stat.h new file mode 100644 index 0000000..f9422cb --- /dev/null +++ b/include/linux/stat.h @@ -0,0 +1,132 @@ +#ifndef _LINUX_STAT_H +#define _LINUX_STAT_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define S_IFMT 00170000 /* type of file */ +#define S_IFSOCK 0140000 /* named socket */ +#define S_IFLNK 0120000 /* symbolic link */ +#define S_IFREG 0100000 /* regular */ +#define S_IFBLK 0060000 /* block special */ +#define S_IFDIR 0040000 /* directory */ +#define S_IFCHR 0020000 /* character special */ +#define S_IFIFO 0010000 /* fifo */ +#define S_ISUID 0004000 /* set user id on execution */ +#define S_ISGID 0002000 /* set group id on execution */ +#define S_ISVTX 0001000 /* save swapped text even after use */ + +#define S_ISLNK(m) (((m) & S_IFMT) == S_IFLNK) +#define S_ISREG(m) (((m) & S_IFMT) == S_IFREG) +#define S_ISDIR(m) (((m) & S_IFMT) == S_IFDIR) +#define S_ISCHR(m) (((m) & S_IFMT) == S_IFCHR) +#define S_ISBLK(m) (((m) & S_IFMT) == S_IFBLK) +#define S_ISFIFO(m) (((m) & S_IFMT) == S_IFIFO) +#define S_ISSOCK(m) (((m) & S_IFMT) == S_IFSOCK) + +#define S_IRWXU 00700 /* rwx for owner */ +#define S_IRUSR 00400 /* read permission for owner */ +#define S_IWUSR 00200 /* write permission for owner */ +#define S_IXUSR 00100 /* execute/search permission for owner */ + +#define S_IRWXG 00070 /* rwx for group */ +#define S_IRGRP 00040 /* read permission for group */ +#define S_IWGRP 00020 /* write permission for group */ +#define S_IXGRP 00010 /* execute/search permission for group */ + +#define S_IRWXO 00007 /* rwx for other */ +#define S_IROTH 00004 /* read permission for other */ +#define S_IWOTH 00002 /* read permission for other */ +#define S_IXOTH 00001 /* execute/search permission for other */ + +#ifdef __PPC__ + +struct stat { + dev_t st_dev; /* file system id */ + ino_t st_ino; /* file id */ + mode_t st_mode; /* ownership/protection */ + nlink_t st_nlink; /* number of links */ + uid_t st_uid; /* user id */ + gid_t st_gid; /* group id */ + dev_t st_rdev; + off_t st_size; /* file size in # of bytes */ + unsigned long st_blksize; /* block size */ + unsigned long st_blocks; /* file size in # of blocks */ + unsigned long st_atime; /* time file was last accessed */ + unsigned long __unused1; + unsigned long st_mtime; /* time file was last modified */ + unsigned long __unused2; + unsigned long st_ctime; /* time file status was last changed */ + unsigned long __unused3; + unsigned long __unused4; + unsigned long __unused5; +}; + +#endif /* __PPC__ */ + +#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__) + +struct stat { + unsigned short st_dev; + unsigned short __pad1; + unsigned long st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned short st_rdev; + unsigned short __pad2; + unsigned long st_size; + unsigned long st_blksize; + unsigned long st_blocks; + unsigned long st_atime; + unsigned long __unused1; + unsigned long st_mtime; + unsigned long __unused2; + unsigned long st_ctime; + unsigned long __unused3; + unsigned long __unused4; + unsigned long __unused5; +}; + +#endif /* __ARM__ */ + +#if defined (__MIPS__) + +struct stat { + dev_t st_dev; + long st_pad1[3]; + ino_t st_ino; + mode_t st_mode; + nlink_t st_nlink; + uid_t st_uid; + gid_t st_gid; + dev_t st_rdev; + long st_pad2[2]; + off_t st_size; + long st_pad3; + /* + * Actually this should be timestruc_t st_atime, st_mtime and st_ctime + * but we don't have it under Linux. + */ + time_t st_atime; + long reserved0; + time_t st_mtime; + long reserved1; + time_t st_ctime; + long reserved2; + long st_blksize; + long st_blocks; + long st_pad4[14]; +}; + +#endif /* __MIPS__ */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/linux/stddef.h b/include/linux/stddef.h new file mode 100644 index 0000000..81e34c2 --- /dev/null +++ b/include/linux/stddef.h @@ -0,0 +1,18 @@ +#ifndef _LINUX_STDDEF_H +#define _LINUX_STDDEF_H + +#undef NULL +#if defined(__cplusplus) +#define NULL 0 +#else +#define NULL ((void *)0) +#endif + +#ifndef _SIZE_T +#include +#endif + +#undef offsetof +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) + +#endif diff --git a/include/linux/time.h b/include/linux/time.h new file mode 100644 index 0000000..bf12b99 --- /dev/null +++ b/include/linux/time.h @@ -0,0 +1,158 @@ +#ifndef _LINUX_TIME_H +#define _LINUX_TIME_H + +#include + +#define _DEFUN(a,b,c) a(c) +#define _CONST const +#define _AND , + +#define _REENT_ONLY + +#define SECSPERMIN 60L +#define MINSPERHOUR 60L +#define HOURSPERDAY 24L +#define SECSPERHOUR (SECSPERMIN * MINSPERHOUR) +#define SECSPERDAY (SECSPERHOUR * HOURSPERDAY) +#define DAYSPERWEEK 7 +#define MONSPERYEAR 12 + +#define YEAR_BASE 1900 +#define EPOCH_YEAR 1970 +#define EPOCH_WDAY 4 + +#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0) + + +/* Used by other time functions. */ +struct tm { + int tm_sec; /* Seconds. [0-60] (1 leap second) */ + int tm_min; /* Minutes. [0-59] */ + int tm_hour; /* Hours. [0-23] */ + int tm_mday; /* Day. [1-31] */ + int tm_mon; /* Month. [0-11] */ + int tm_year; /* Year - 1900. */ + int tm_wday; /* Day of week. [0-6] */ + int tm_yday; /* Days in year.[0-365] */ + int tm_isdst; /* DST. [-1/0/1]*/ + +# ifdef __USE_BSD + long int tm_gmtoff; /* Seconds east of UTC. */ + __const char *tm_zone; /* Timezone abbreviation. */ +# else + long int __tm_gmtoff; /* Seconds east of UTC. */ + __const char *__tm_zone; /* Timezone abbreviation. */ +# endif +}; + +static inline char * +_DEFUN (asctime_r, (tim_p, result), + _CONST struct tm *tim_p _AND + char *result) +{ + static _CONST char day_name[7][3] = { + "Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat" + }; + static _CONST char mon_name[12][3] = { + "Jan", "Feb", "Mar", "Apr", "May", "Jun", + "Jul", "Aug", "Sep", "Oct", "Nov", "Dec" + }; + + sprintf (result, "%.3s %.3s %.2d %.2d:%.2d:%.2d %d\n", + day_name[tim_p->tm_wday], + mon_name[tim_p->tm_mon], + tim_p->tm_mday, tim_p->tm_hour, tim_p->tm_min, + tim_p->tm_sec, 1900 + tim_p->tm_year); + return result; +} + +static inline struct tm * +_DEFUN (localtime_r, (tim_p, res), + _CONST time_t * tim_p _AND + struct tm *res) +{ + static _CONST int mon_lengths[2][MONSPERYEAR] = { + {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}, + {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31} + } ; + + static _CONST int year_lengths[2] = { + 365, + 366 + } ; + + long days, rem; + int y; + int yleap; + _CONST int *ip; + + days = ((long) *tim_p) / SECSPERDAY; + rem = ((long) *tim_p) % SECSPERDAY; + while (rem < 0) + { + rem += SECSPERDAY; + --days; + } + while (rem >= SECSPERDAY) + { + rem -= SECSPERDAY; + ++days; + } + + /* compute hour, min, and sec */ + res->tm_hour = (int) (rem / SECSPERHOUR); + rem %= SECSPERHOUR; + res->tm_min = (int) (rem / SECSPERMIN); + res->tm_sec = (int) (rem % SECSPERMIN); + + /* compute day of week */ + if ((res->tm_wday = ((EPOCH_WDAY + days) % DAYSPERWEEK)) < 0) + res->tm_wday += DAYSPERWEEK; + + /* compute year & day of year */ + y = EPOCH_YEAR; + if (days >= 0) + { + for (;;) + { + yleap = isleap(y); + if (days < year_lengths[yleap]) + break; + y++; + days -= year_lengths[yleap]; + } + } + else + { + do + { + --y; + yleap = isleap(y); + days += year_lengths[yleap]; + } while (days < 0); + } + + res->tm_year = y - YEAR_BASE; + res->tm_yday = days; + ip = mon_lengths[yleap]; + for (res->tm_mon = 0; days >= ip[res->tm_mon]; ++res->tm_mon) + days -= ip[res->tm_mon]; + res->tm_mday = days + 1; + + /* set daylight saving time flag */ + res->tm_isdst = -1; + + return (res); +} + +static inline char * +_DEFUN (ctime_r, (tim_p, result), + _CONST time_t * tim_p _AND + char * result) + +{ + struct tm tm; + return asctime_r (localtime_r (tim_p, &tm), result); +} + +#endif diff --git a/include/linux/types.h b/include/linux/types.h new file mode 100644 index 0000000..df4808f --- /dev/null +++ b/include/linux/types.h @@ -0,0 +1,130 @@ +#ifndef _LINUX_TYPES_H +#define _LINUX_TYPES_H + +#ifdef __KERNEL__ +#include +#endif + +#include +#include + +#ifndef __KERNEL_STRICT_NAMES + +typedef __kernel_fd_set fd_set; +typedef __kernel_dev_t dev_t; +typedef __kernel_ino_t ino_t; +typedef __kernel_mode_t mode_t; +typedef __kernel_nlink_t nlink_t; +typedef __kernel_off_t off_t; +typedef __kernel_pid_t pid_t; +typedef __kernel_daddr_t daddr_t; +typedef __kernel_key_t key_t; +typedef __kernel_suseconds_t suseconds_t; + +#ifdef __KERNEL__ +typedef __kernel_uid32_t uid_t; +typedef __kernel_gid32_t gid_t; +typedef __kernel_uid16_t uid16_t; +typedef __kernel_gid16_t gid16_t; + +#ifdef CONFIG_UID16 +/* This is defined by include/asm-{arch}/posix_types.h */ +typedef __kernel_old_uid_t old_uid_t; +typedef __kernel_old_gid_t old_gid_t; +#endif /* CONFIG_UID16 */ + +/* libc5 includes this file to define uid_t, thus uid_t can never change + * when it is included by non-kernel code + */ +#else +typedef __kernel_uid_t uid_t; +typedef __kernel_gid_t gid_t; +#endif /* __KERNEL__ */ + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __kernel_loff_t loff_t; +#endif + +/* + * The following typedefs are also protected by individual ifdefs for + * historical reasons: + */ +#ifndef _SIZE_T +#define _SIZE_T +typedef __kernel_size_t size_t; +#endif + +#ifndef _SSIZE_T +#define _SSIZE_T +typedef __kernel_ssize_t ssize_t; +#endif + +#ifndef _PTRDIFF_T +#define _PTRDIFF_T +typedef __kernel_ptrdiff_t ptrdiff_t; +#endif + +#ifndef _TIME_T +#define _TIME_T +typedef __kernel_time_t time_t; +#endif + +#ifndef _CLOCK_T +#define _CLOCK_T +typedef __kernel_clock_t clock_t; +#endif + +#ifndef _CADDR_T +#define _CADDR_T +typedef __kernel_caddr_t caddr_t; +#endif + +/* bsd */ +typedef unsigned char u_char; +typedef unsigned short u_short; +typedef unsigned int u_int; +typedef unsigned long u_long; + +/* sysv */ +typedef unsigned char unchar; +typedef unsigned short ushort; +typedef unsigned int uint; +typedef unsigned long ulong; + +#ifndef __BIT_TYPES_DEFINED__ +#define __BIT_TYPES_DEFINED__ + +typedef __u8 u_int8_t; +typedef __s8 int8_t; +typedef __u16 u_int16_t; +typedef __s16 int16_t; +typedef __u32 u_int32_t; +typedef __s32 int32_t; + +#endif /* !(__BIT_TYPES_DEFINED__) */ + +typedef __u8 uint8_t; +typedef __u16 uint16_t; +typedef __u32 uint32_t; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __u64 uint64_t; +typedef __u64 u_int64_t; +typedef __s64 int64_t; +#endif + +#endif /* __KERNEL_STRICT_NAMES */ + +/* + * Below are truly Linux-specific types that should never collide with + * any application/library that wants linux/types.h. + */ + +struct ustat { + __kernel_daddr_t f_tfree; + __kernel_ino_t f_tinode; + char f_fname[6]; + char f_fpack[6]; +}; + +#endif /* _LINUX_TYPES_H */ diff --git a/include/malloc.h b/include/malloc.h new file mode 100644 index 0000000..47154b0 --- /dev/null +++ b/include/malloc.h @@ -0,0 +1,942 @@ +/* + A version of malloc/free/realloc written by Doug Lea and released to the + public domain. Send questions/comments/complaints/performance data + to dl@cs.oswego.edu + +* VERSION 2.6.6 Sun Mar 5 19:10:03 2000 Doug Lea (dl at gee) + + Note: There may be an updated version of this malloc obtainable at + ftp://g.oswego.edu/pub/misc/malloc.c + Check before installing! + +* Why use this malloc? + + This is not the fastest, most space-conserving, most portable, or + most tunable malloc ever written. However it is among the fastest + while also being among the most space-conserving, portable and tunable. + Consistent balance across these factors results in a good general-purpose + allocator. For a high-level description, see + http://g.oswego.edu/dl/html/malloc.html + +* Synopsis of public routines + + (Much fuller descriptions are contained in the program documentation below.) + + malloc(size_t n); + Return a pointer to a newly allocated chunk of at least n bytes, or null + if no space is available. + free(Void_t* p); + Release the chunk of memory pointed to by p, or no effect if p is null. + realloc(Void_t* p, size_t n); + Return a pointer to a chunk of size n that contains the same data + as does chunk p up to the minimum of (n, p's size) bytes, or null + if no space is available. The returned pointer may or may not be + the same as p. If p is null, equivalent to malloc. Unless the + #define REALLOC_ZERO_BYTES_FREES below is set, realloc with a + size argument of zero (re)allocates a minimum-sized chunk. + memalign(size_t alignment, size_t n); + Return a pointer to a newly allocated chunk of n bytes, aligned + in accord with the alignment argument, which must be a power of + two. + valloc(size_t n); + Equivalent to memalign(pagesize, n), where pagesize is the page + size of the system (or as near to this as can be figured out from + all the includes/defines below.) + pvalloc(size_t n); + Equivalent to valloc(minimum-page-that-holds(n)), that is, + round up n to nearest pagesize. + calloc(size_t unit, size_t quantity); + Returns a pointer to quantity * unit bytes, with all locations + set to zero. + cfree(Void_t* p); + Equivalent to free(p). + malloc_trim(size_t pad); + Release all but pad bytes of freed top-most memory back + to the system. Return 1 if successful, else 0. + malloc_usable_size(Void_t* p); + Report the number usable allocated bytes associated with allocated + chunk p. This may or may not report more bytes than were requested, + due to alignment and minimum size constraints. + malloc_stats(); + Prints brief summary statistics on stderr. + mallinfo() + Returns (by copy) a struct containing various summary statistics. + mallopt(int parameter_number, int parameter_value) + Changes one of the tunable parameters described below. Returns + 1 if successful in changing the parameter, else 0. + +* Vital statistics: + + Alignment: 8-byte + 8 byte alignment is currently hardwired into the design. This + seems to suffice for all current machines and C compilers. + + Assumed pointer representation: 4 or 8 bytes + Code for 8-byte pointers is untested by me but has worked + reliably by Wolfram Gloger, who contributed most of the + changes supporting this. + + Assumed size_t representation: 4 or 8 bytes + Note that size_t is allowed to be 4 bytes even if pointers are 8. + + Minimum overhead per allocated chunk: 4 or 8 bytes + Each malloced chunk has a hidden overhead of 4 bytes holding size + and status information. + + Minimum allocated size: 4-byte ptrs: 16 bytes (including 4 overhead) + 8-byte ptrs: 24/32 bytes (including, 4/8 overhead) + + When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte + ptrs but 4 byte size) or 24 (for 8/8) additional bytes are + needed; 4 (8) for a trailing size field + and 8 (16) bytes for free list pointers. Thus, the minimum + allocatable size is 16/24/32 bytes. + + Even a request for zero bytes (i.e., malloc(0)) returns a + pointer to something of the minimum allocatable size. + + Maximum allocated size: 4-byte size_t: 2^31 - 8 bytes + 8-byte size_t: 2^63 - 16 bytes + + It is assumed that (possibly signed) size_t bit values suffice to + represent chunk sizes. `Possibly signed' is due to the fact + that `size_t' may be defined on a system as either a signed or + an unsigned type. To be conservative, values that would appear + as negative numbers are avoided. + Requests for sizes with a negative sign bit when the request + size is treaded as a long will return null. + + Maximum overhead wastage per allocated chunk: normally 15 bytes + + Alignnment demands, plus the minimum allocatable size restriction + make the normal worst-case wastage 15 bytes (i.e., up to 15 + more bytes will be allocated than were requested in malloc), with + two exceptions: + 1. Because requests for zero bytes allocate non-zero space, + the worst case wastage for a request of zero bytes is 24 bytes. + 2. For requests >= mmap_threshold that are serviced via + mmap(), the worst case wastage is 8 bytes plus the remainder + from a system page (the minimal mmap unit); typically 4096 bytes. + +* Limitations + + Here are some features that are NOT currently supported + + * No user-definable hooks for callbacks and the like. + * No automated mechanism for fully checking that all accesses + to malloced memory stay within their bounds. + * No support for compaction. + +* Synopsis of compile-time options: + + People have reported using previous versions of this malloc on all + versions of Unix, sometimes by tweaking some of the defines + below. It has been tested most extensively on Solaris and + Linux. It is also reported to work on WIN32 platforms. + People have also reported adapting this malloc for use in + stand-alone embedded systems. + + The implementation is in straight, hand-tuned ANSI C. Among other + consequences, it uses a lot of macros. Because of this, to be at + all usable, this code should be compiled using an optimizing compiler + (for example gcc -O2) that can simplify expressions and control + paths. + + __STD_C (default: derived from C compiler defines) + Nonzero if using ANSI-standard C compiler, a C++ compiler, or + a C compiler sufficiently close to ANSI to get away with it. + DEBUG (default: NOT defined) + Define to enable debugging. Adds fairly extensive assertion-based + checking to help track down memory errors, but noticeably slows down + execution. + REALLOC_ZERO_BYTES_FREES (default: NOT defined) + Define this if you think that realloc(p, 0) should be equivalent + to free(p). Otherwise, since malloc returns a unique pointer for + malloc(0), so does realloc(p, 0). + HAVE_MEMCPY (default: defined) + Define if you are not otherwise using ANSI STD C, but still + have memcpy and memset in your C library and want to use them. + Otherwise, simple internal versions are supplied. + USE_MEMCPY (default: 1 if HAVE_MEMCPY is defined, 0 otherwise) + Define as 1 if you want the C library versions of memset and + memcpy called in realloc and calloc (otherwise macro versions are used). + At least on some platforms, the simple macro versions usually + outperform libc versions. + HAVE_MMAP (default: defined as 1) + Define to non-zero to optionally make malloc() use mmap() to + allocate very large blocks. + HAVE_MREMAP (default: defined as 0 unless Linux libc set) + Define to non-zero to optionally make realloc() use mremap() to + reallocate very large blocks. + malloc_getpagesize (default: derived from system #includes) + Either a constant or routine call returning the system page size. + HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined) + Optionally define if you are on a system with a /usr/include/malloc.h + that declares struct mallinfo. It is not at all necessary to + define this even if you do, but will ensure consistency. + INTERNAL_SIZE_T (default: size_t) + Define to a 32-bit type (probably `unsigned int') if you are on a + 64-bit machine, yet do not want or need to allow malloc requests of + greater than 2^31 to be handled. This saves space, especially for + very small chunks. + INTERNAL_LINUX_C_LIB (default: NOT defined) + Defined only when compiled as part of Linux libc. + Also note that there is some odd internal name-mangling via defines + (for example, internally, `malloc' is named `mALLOc') needed + when compiling in this case. These look funny but don't otherwise + affect anything. + WIN32 (default: undefined) + Define this on MS win (95, nt) platforms to compile in sbrk emulation. + LACKS_UNISTD_H (default: undefined if not WIN32) + Define this if your system does not have a . + LACKS_SYS_PARAM_H (default: undefined if not WIN32) + Define this if your system does not have a . + MORECORE (default: sbrk) + The name of the routine to call to obtain more memory from the system. + MORECORE_FAILURE (default: -1) + The value returned upon failure of MORECORE. + MORECORE_CLEARS (default 1) + True (1) if the routine mapped to MORECORE zeroes out memory (which + holds for sbrk). + DEFAULT_TRIM_THRESHOLD + DEFAULT_TOP_PAD + DEFAULT_MMAP_THRESHOLD + DEFAULT_MMAP_MAX + Default values of tunable parameters (described in detail below) + controlling interaction with host system routines (sbrk, mmap, etc). + These values may also be changed dynamically via mallopt(). The + preset defaults are those that give best performance for typical + programs/systems. + USE_DL_PREFIX (default: undefined) + Prefix all public routines with the string 'dl'. Useful to + quickly avoid procedure declaration conflicts and linker symbol + conflicts with existing memory allocation routines. + + +*/ + + + + +/* Preliminaries */ + +#ifndef __STD_C +#ifdef __STDC__ +#define __STD_C 1 +#else +#if __cplusplus +#define __STD_C 1 +#else +#define __STD_C 0 +#endif /*__cplusplus*/ +#endif /*__STDC__*/ +#endif /*__STD_C*/ + +#ifndef Void_t +#if (__STD_C || defined(WIN32)) +#define Void_t void +#else +#define Void_t char +#endif +#endif /*Void_t*/ + +#if __STD_C +#include /* for size_t */ +#else +#include +#endif /* __STD_C */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if 0 /* not for U-Boot */ +#include /* needed for malloc_stats */ +#endif + + +/* + Compile-time options +*/ + + +/* + Debugging: + + Because freed chunks may be overwritten with link fields, this + malloc will often die when freed memory is overwritten by user + programs. This can be very effective (albeit in an annoying way) + in helping track down dangling pointers. + + If you compile with -DDEBUG, a number of assertion checks are + enabled that will catch more memory errors. You probably won't be + able to make much sense of the actual assertion errors, but they + should help you locate incorrectly overwritten memory. The + checking is fairly extensive, and will slow down execution + noticeably. Calling malloc_stats or mallinfo with DEBUG set will + attempt to check every non-mmapped allocated and free chunk in the + course of computing the summmaries. (By nature, mmapped regions + cannot be checked very much automatically.) + + Setting DEBUG may also be helpful if you are trying to modify + this code. The assertions in the check routines spell out in more + detail the assumptions and invariants underlying the algorithms. + +*/ + +#ifdef DEBUG +/* #include */ +#define assert(x) ((void)0) +#else +#define assert(x) ((void)0) +#endif + + +/* + INTERNAL_SIZE_T is the word-size used for internal bookkeeping + of chunk sizes. On a 64-bit machine, you can reduce malloc + overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int' + at the expense of not being able to handle requests greater than + 2^31. This limitation is hardly ever a concern; you are encouraged + to set this. However, the default version is the same as size_t. +*/ + +#ifndef INTERNAL_SIZE_T +#define INTERNAL_SIZE_T size_t +#endif + +/* + REALLOC_ZERO_BYTES_FREES should be set if a call to + realloc with zero bytes should be the same as a call to free. + Some people think it should. Otherwise, since this malloc + returns a unique pointer for malloc(0), so does realloc(p, 0). +*/ + + +/* #define REALLOC_ZERO_BYTES_FREES */ + + +/* + WIN32 causes an emulation of sbrk to be compiled in + mmap-based options are not currently supported in WIN32. +*/ + +/* #define WIN32 */ +#ifdef WIN32 +#define MORECORE wsbrk +#define HAVE_MMAP 0 + +#define LACKS_UNISTD_H +#define LACKS_SYS_PARAM_H + +/* + Include 'windows.h' to get the necessary declarations for the + Microsoft Visual C++ data structures and routines used in the 'sbrk' + emulation. + + Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft + Visual C++ header files are included. +*/ +#define WIN32_LEAN_AND_MEAN +#include +#endif + + +/* + HAVE_MEMCPY should be defined if you are not otherwise using + ANSI STD C, but still have memcpy and memset in your C library + and want to use them in calloc and realloc. Otherwise simple + macro versions are defined here. + + USE_MEMCPY should be defined as 1 if you actually want to + have memset and memcpy called. People report that the macro + versions are often enough faster than libc versions on many + systems that it is better to use them. + +*/ + +#define HAVE_MEMCPY + +#ifndef USE_MEMCPY +#ifdef HAVE_MEMCPY +#define USE_MEMCPY 1 +#else +#define USE_MEMCPY 0 +#endif +#endif + +#if (__STD_C || defined(HAVE_MEMCPY)) + +#if __STD_C +void* memset(void*, int, size_t); +void* memcpy(void*, const void*, size_t); +#else +#ifdef WIN32 +/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */ +/* 'windows.h' */ +#else +Void_t* memset(); +Void_t* memcpy(); +#endif +#endif +#endif + +#if USE_MEMCPY + +/* The following macros are only invoked with (2n+1)-multiples of + INTERNAL_SIZE_T units, with a positive integer n. This is exploited + for fast inline execution when n is small. */ + +#define MALLOC_ZERO(charp, nbytes) \ +do { \ + INTERNAL_SIZE_T mzsz = (nbytes); \ + if(mzsz <= 9*sizeof(mzsz)) { \ + INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp); \ + if(mzsz >= 5*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; \ + if(mzsz >= 7*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; \ + if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; }}} \ + *mz++ = 0; \ + *mz++ = 0; \ + *mz = 0; \ + } else memset((charp), 0, mzsz); \ +} while(0) + +#define MALLOC_COPY(dest,src,nbytes) \ +do { \ + INTERNAL_SIZE_T mcsz = (nbytes); \ + if(mcsz <= 9*sizeof(mcsz)) { \ + INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src); \ + INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest); \ + if(mcsz >= 5*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + if(mcsz >= 7*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; }}} \ + *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + *mcdst = *mcsrc ; \ + } else memcpy(dest, src, mcsz); \ +} while(0) + +#else /* !USE_MEMCPY */ + +/* Use Duff's device for good zeroing/copying performance. */ + +#define MALLOC_ZERO(charp, nbytes) \ +do { \ + INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp); \ + long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ + if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ + switch (mctmp) { \ + case 0: for(;;) { *mzp++ = 0; \ + case 7: *mzp++ = 0; \ + case 6: *mzp++ = 0; \ + case 5: *mzp++ = 0; \ + case 4: *mzp++ = 0; \ + case 3: *mzp++ = 0; \ + case 2: *mzp++ = 0; \ + case 1: *mzp++ = 0; if(mcn <= 0) break; mcn--; } \ + } \ +} while(0) + +#define MALLOC_COPY(dest,src,nbytes) \ +do { \ + INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src; \ + INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest; \ + long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ + if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ + switch (mctmp) { \ + case 0: for(;;) { *mcdst++ = *mcsrc++; \ + case 7: *mcdst++ = *mcsrc++; \ + case 6: *mcdst++ = *mcsrc++; \ + case 5: *mcdst++ = *mcsrc++; \ + case 4: *mcdst++ = *mcsrc++; \ + case 3: *mcdst++ = *mcsrc++; \ + case 2: *mcdst++ = *mcsrc++; \ + case 1: *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; } \ + } \ +} while(0) + +#endif + + +/* + Define HAVE_MMAP to optionally make malloc() use mmap() to + allocate very large blocks. These will be returned to the + operating system immediately after a free(). +*/ + +/*** +#ifndef HAVE_MMAP +#define HAVE_MMAP 1 +#endif +***/ +#undef HAVE_MMAP /* Not available for U-Boot */ + +/* + Define HAVE_MREMAP to make realloc() use mremap() to re-allocate + large blocks. This is currently only possible on Linux with + kernel versions newer than 1.3.77. +*/ + +/*** +#ifndef HAVE_MREMAP +#ifdef INTERNAL_LINUX_C_LIB +#define HAVE_MREMAP 1 +#else +#define HAVE_MREMAP 0 +#endif +#endif +***/ +#undef HAVE_MREMAP /* Not available for U-Boot */ + +#if HAVE_MMAP + +#include +#include +#include + +#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON) +#define MAP_ANONYMOUS MAP_ANON +#endif + +#endif /* HAVE_MMAP */ + +/* + Access to system page size. To the extent possible, this malloc + manages memory from the system in page-size units. + + The following mechanics for getpagesize were adapted from + bsd/gnu getpagesize.h +*/ + +#define LACKS_UNISTD_H /* Shortcut for U-Boot */ +#define malloc_getpagesize 4096 + +#ifndef LACKS_UNISTD_H +# include +#endif + +#ifndef malloc_getpagesize +# ifdef _SC_PAGESIZE /* some SVR4 systems omit an underscore */ +# ifndef _SC_PAGE_SIZE +# define _SC_PAGE_SIZE _SC_PAGESIZE +# endif +# endif +# ifdef _SC_PAGE_SIZE +# define malloc_getpagesize sysconf(_SC_PAGE_SIZE) +# else +# if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE) + extern size_t getpagesize(); +# define malloc_getpagesize getpagesize() +# else +# ifdef WIN32 +# define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */ +# else +# ifndef LACKS_SYS_PARAM_H +# include +# endif +# ifdef EXEC_PAGESIZE +# define malloc_getpagesize EXEC_PAGESIZE +# else +# ifdef NBPG +# ifndef CLSIZE +# define malloc_getpagesize NBPG +# else +# define malloc_getpagesize (NBPG * CLSIZE) +# endif +# else +# ifdef NBPC +# define malloc_getpagesize NBPC +# else +# ifdef PAGESIZE +# define malloc_getpagesize PAGESIZE +# else +# define malloc_getpagesize (4096) /* just guess */ +# endif +# endif +# endif +# endif +# endif +# endif +# endif +#endif + + +/* + + This version of malloc supports the standard SVID/XPG mallinfo + routine that returns a struct containing the same kind of + information you can get from malloc_stats. It should work on + any SVID/XPG compliant system that has a /usr/include/malloc.h + defining struct mallinfo. (If you'd like to install such a thing + yourself, cut out the preliminary declarations as described above + and below and save them in a malloc.h file. But there's no + compelling reason to bother to do this.) + + The main declaration needed is the mallinfo struct that is returned + (by-copy) by mallinfo(). The SVID/XPG malloinfo struct contains a + bunch of fields, most of which are not even meaningful in this + version of malloc. Some of these fields are are instead filled by + mallinfo() with other numbers that might possibly be of interest. + + HAVE_USR_INCLUDE_MALLOC_H should be set if you have a + /usr/include/malloc.h file that includes a declaration of struct + mallinfo. If so, it is included; else an SVID2/XPG2 compliant + version is declared below. These must be precisely the same for + mallinfo() to work. + +*/ + +/* #define HAVE_USR_INCLUDE_MALLOC_H */ + +#if HAVE_USR_INCLUDE_MALLOC_H +#include "/usr/include/malloc.h" +#else + +/* SVID2/XPG mallinfo structure */ + +struct mallinfo { + int arena; /* total space allocated from system */ + int ordblks; /* number of non-inuse chunks */ + int smblks; /* unused -- always zero */ + int hblks; /* number of mmapped regions */ + int hblkhd; /* total space in mmapped regions */ + int usmblks; /* unused -- always zero */ + int fsmblks; /* unused -- always zero */ + int uordblks; /* total allocated space */ + int fordblks; /* total non-inuse space */ + int keepcost; /* top-most, releasable (via malloc_trim) space */ +}; + +/* SVID2/XPG mallopt options */ + +#define M_MXFAST 1 /* UNUSED in this malloc */ +#define M_NLBLKS 2 /* UNUSED in this malloc */ +#define M_GRAIN 3 /* UNUSED in this malloc */ +#define M_KEEP 4 /* UNUSED in this malloc */ + +#endif + +/* mallopt options that actually do something */ + +#define M_TRIM_THRESHOLD -1 +#define M_TOP_PAD -2 +#define M_MMAP_THRESHOLD -3 +#define M_MMAP_MAX -4 + + +#ifndef DEFAULT_TRIM_THRESHOLD +#define DEFAULT_TRIM_THRESHOLD (128 * 1024) +#endif + +/* + M_TRIM_THRESHOLD is the maximum amount of unused top-most memory + to keep before releasing via malloc_trim in free(). + + Automatic trimming is mainly useful in long-lived programs. + Because trimming via sbrk can be slow on some systems, and can + sometimes be wasteful (in cases where programs immediately + afterward allocate more large chunks) the value should be high + enough so that your overall system performance would improve by + releasing. + + The trim threshold and the mmap control parameters (see below) + can be traded off with one another. Trimming and mmapping are + two different ways of releasing unused memory back to the + system. Between these two, it is often possible to keep + system-level demands of a long-lived program down to a bare + minimum. For example, in one test suite of sessions measuring + the XF86 X server on Linux, using a trim threshold of 128K and a + mmap threshold of 192K led to near-minimal long term resource + consumption. + + If you are using this malloc in a long-lived program, it should + pay to experiment with these values. As a rough guide, you + might set to a value close to the average size of a process + (program) running on your system. Releasing this much memory + would allow such a process to run in memory. Generally, it's + worth it to tune for trimming rather tham memory mapping when a + program undergoes phases where several large chunks are + allocated and released in ways that can reuse each other's + storage, perhaps mixed with phases where there are no such + chunks at all. And in well-behaved long-lived programs, + controlling release of large blocks via trimming versus mapping + is usually faster. + + However, in most programs, these parameters serve mainly as + protection against the system-level effects of carrying around + massive amounts of unneeded memory. Since frequent calls to + sbrk, mmap, and munmap otherwise degrade performance, the default + parameters are set to relatively high values that serve only as + safeguards. + + The default trim value is high enough to cause trimming only in + fairly extreme (by current memory consumption standards) cases. + It must be greater than page size to have any useful effect. To + disable trimming completely, you can set to (unsigned long)(-1); + + +*/ + + +#ifndef DEFAULT_TOP_PAD +#define DEFAULT_TOP_PAD (0) +#endif + +/* + M_TOP_PAD is the amount of extra `padding' space to allocate or + retain whenever sbrk is called. It is used in two ways internally: + + * When sbrk is called to extend the top of the arena to satisfy + a new malloc request, this much padding is added to the sbrk + request. + + * When malloc_trim is called automatically from free(), + it is used as the `pad' argument. + + In both cases, the actual amount of padding is rounded + so that the end of the arena is always a system page boundary. + + The main reason for using padding is to avoid calling sbrk so + often. Having even a small pad greatly reduces the likelihood + that nearly every malloc request during program start-up (or + after trimming) will invoke sbrk, which needlessly wastes + time. + + Automatic rounding-up to page-size units is normally sufficient + to avoid measurable overhead, so the default is 0. However, in + systems where sbrk is relatively slow, it can pay to increase + this value, at the expense of carrying around more memory than + the program needs. + +*/ + + +#ifndef DEFAULT_MMAP_THRESHOLD +#define DEFAULT_MMAP_THRESHOLD (128 * 1024) +#endif + +/* + + M_MMAP_THRESHOLD is the request size threshold for using mmap() + to service a request. Requests of at least this size that cannot + be allocated using already-existing space will be serviced via mmap. + (If enough normal freed space already exists it is used instead.) + + Using mmap segregates relatively large chunks of memory so that + they can be individually obtained and released from the host + system. A request serviced through mmap is never reused by any + other request (at least not directly; the system may just so + happen to remap successive requests to the same locations). + + Segregating space in this way has the benefit that mmapped space + can ALWAYS be individually released back to the system, which + helps keep the system level memory demands of a long-lived + program low. Mapped memory can never become `locked' between + other chunks, as can happen with normally allocated chunks, which + menas that even trimming via malloc_trim would not release them. + + However, it has the disadvantages that: + + 1. The space cannot be reclaimed, consolidated, and then + used to service later requests, as happens with normal chunks. + 2. It can lead to more wastage because of mmap page alignment + requirements + 3. It causes malloc performance to be more dependent on host + system memory management support routines which may vary in + implementation quality and may impose arbitrary + limitations. Generally, servicing a request via normal + malloc steps is faster than going through a system's mmap. + + All together, these considerations should lead you to use mmap + only for relatively large requests. + + +*/ + + +#ifndef DEFAULT_MMAP_MAX +#if HAVE_MMAP +#define DEFAULT_MMAP_MAX (64) +#else +#define DEFAULT_MMAP_MAX (0) +#endif +#endif + +/* + M_MMAP_MAX is the maximum number of requests to simultaneously + service using mmap. This parameter exists because: + + 1. Some systems have a limited number of internal tables for + use by mmap. + 2. In most systems, overreliance on mmap can degrade overall + performance. + 3. If a program allocates many large regions, it is probably + better off using normal sbrk-based allocation routines that + can reclaim and reallocate normal heap memory. Using a + small value allows transition into this mode after the + first few allocations. + + Setting to 0 disables all use of mmap. If HAVE_MMAP is not set, + the default value is 0, and attempts to set it to non-zero values + in mallopt will fail. +*/ + + +/* + USE_DL_PREFIX will prefix all public routines with the string 'dl'. + Useful to quickly avoid procedure declaration conflicts and linker + symbol conflicts with existing memory allocation routines. + +*/ + +/* #define USE_DL_PREFIX */ + + +/* + + Special defines for linux libc + + Except when compiled using these special defines for Linux libc + using weak aliases, this malloc is NOT designed to work in + multithreaded applications. No semaphores or other concurrency + control are provided to ensure that multiple malloc or free calls + don't run at the same time, which could be disasterous. A single + semaphore could be used across malloc, realloc, and free (which is + essentially the effect of the linux weak alias approach). It would + be hard to obtain finer granularity. + +*/ + + +#ifdef INTERNAL_LINUX_C_LIB + +#if __STD_C + +Void_t * __default_morecore_init (ptrdiff_t); +Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init; + +#else + +Void_t * __default_morecore_init (); +Void_t *(*__morecore)() = __default_morecore_init; + +#endif + +#define MORECORE (*__morecore) +#define MORECORE_FAILURE 0 +#define MORECORE_CLEARS 1 + +#else /* INTERNAL_LINUX_C_LIB */ + +#if __STD_C +extern Void_t* sbrk(ptrdiff_t); +#else +extern Void_t* sbrk(); +#endif + +#ifndef MORECORE +#define MORECORE sbrk +#endif + +#ifndef MORECORE_FAILURE +#define MORECORE_FAILURE -1 +#endif + +#ifndef MORECORE_CLEARS +#define MORECORE_CLEARS 1 +#endif + +#endif /* INTERNAL_LINUX_C_LIB */ + +#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__) + +#define cALLOc __libc_calloc +#define fREe __libc_free +#define mALLOc __libc_malloc +#define mEMALIGn __libc_memalign +#define rEALLOc __libc_realloc +#define vALLOc __libc_valloc +#define pvALLOc __libc_pvalloc +#define mALLINFo __libc_mallinfo +#define mALLOPt __libc_mallopt + +#pragma weak calloc = __libc_calloc +#pragma weak free = __libc_free +#pragma weak cfree = __libc_free +#pragma weak malloc = __libc_malloc +#pragma weak memalign = __libc_memalign +#pragma weak realloc = __libc_realloc +#pragma weak valloc = __libc_valloc +#pragma weak pvalloc = __libc_pvalloc +#pragma weak mallinfo = __libc_mallinfo +#pragma weak mallopt = __libc_mallopt + +#else + +#ifdef USE_DL_PREFIX +#define cALLOc dlcalloc +#define fREe dlfree +#define mALLOc dlmalloc +#define mEMALIGn dlmemalign +#define rEALLOc dlrealloc +#define vALLOc dlvalloc +#define pvALLOc dlpvalloc +#define mALLINFo dlmallinfo +#define mALLOPt dlmallopt +#else /* USE_DL_PREFIX */ +#define cALLOc calloc +#define fREe free +#define mALLOc malloc +#define mEMALIGn memalign +#define rEALLOc realloc +#define vALLOc valloc +#define pvALLOc pvalloc +#define mALLINFo mallinfo +#define mALLOPt mallopt +#endif /* USE_DL_PREFIX */ + +#endif + +/* Public routines */ + +#if __STD_C + +Void_t* mALLOc(size_t); +void fREe(Void_t*); +Void_t* rEALLOc(Void_t*, size_t); +Void_t* mEMALIGn(size_t, size_t); +Void_t* vALLOc(size_t); +Void_t* pvALLOc(size_t); +Void_t* cALLOc(size_t, size_t); +void cfree(Void_t*); +int malloc_trim(size_t); +size_t malloc_usable_size(Void_t*); +void malloc_stats(void); +int mALLOPt(int, int); +struct mallinfo mALLINFo(void); +#else +Void_t* mALLOc(); +void fREe(); +Void_t* rEALLOc(); +Void_t* mEMALIGn(); +Void_t* vALLOc(); +Void_t* pvALLOc(); +Void_t* cALLOc(); +void cfree(); +int malloc_trim(); +size_t malloc_usable_size(); +void malloc_stats(); +int mALLOPt(); +struct mallinfo mALLINFo(); +#endif + + +#ifdef __cplusplus +}; /* end of extern "C" */ +#endif diff --git a/include/mmc.h b/include/mmc.h new file mode 100644 index 0000000..19c76fe --- /dev/null +++ b/include/mmc.h @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _MMC_H_ +#define _MMC_H_ +#include + +/* MMC command numbers */ +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_APP_CMD 55 + +/* SD Card command numbers */ +#define SD_CMD_SEND_RELATIVE_ADDR 3 +#define SD_CMD_SWITCH 6 +#define SD_CMD_SEND_IF_COND 8 + +#define SD_CMD_APP_SET_BUS_WIDTH 6 +#define SD_CMD_APP_SEND_OP_COND 41 + +int mmc_init(int verbose); +int mmc_read(ulong src, uchar *dst, int size); +int mmc_write(uchar *src, ulong dst, int size); +int mmc2info(ulong addr); + +#endif /* _MMC_H_ */ diff --git a/include/ns16550.h b/include/ns16550.h new file mode 100644 index 0000000..36d2d40 --- /dev/null +++ b/include/ns16550.h @@ -0,0 +1,130 @@ +/* + *This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * NS16550 Serial Port + * originally from linux source (arch/ppc/boot/ns16550.h) + * modified slightly to + * have addresses as offsets from CFG_ISA_BASE + * added a few more definitions + * added prototypes for ns16550.c + * reduced no of com ports to 2 + * modifications (c) Rob Taylor, Flying Pig Systems. 2000. + */ + +#if (CFG_NS16550_REG_SIZE == 1) +struct NS16550 { + unsigned char rbr; /* 0 */ + unsigned char ier; /* 1 */ + unsigned char fcr; /* 2 */ + unsigned char lcr; /* 3 */ + unsigned char mcr; /* 4 */ + unsigned char lsr; /* 5 */ + unsigned char msr; /* 6 */ + unsigned char scr; /* 7 */ +} __attribute__ ((packed)); +#elif (CFG_NS16550_REG_SIZE == 2) +struct NS16550 { + unsigned short rbr; /* 0 */ + unsigned short ier; /* 1 */ + unsigned short fcr; /* 2 */ + unsigned short lcr; /* 3 */ + unsigned short mcr; /* 4 */ + unsigned short lsr; /* 5 */ + unsigned short msr; /* 6 */ + unsigned short scr; /* 7 */ +} __attribute__ ((packed)); +#elif (CFG_NS16550_REG_SIZE == 4) +struct NS16550 { + unsigned long rbr; /* 0 */ + unsigned long ier; /* 1 */ + unsigned long fcr; /* 2 */ + unsigned long lcr; /* 3 */ + unsigned long mcr; /* 4 */ + unsigned long lsr; /* 5 */ + unsigned long msr; /* 6 */ + unsigned long scr; /* 7 */ +} __attribute__ ((packed)); +#elif (CFG_NS16550_REG_SIZE == -4) +struct NS16550 { + unsigned char rbr; /* 0 */ + int pad1:24; + unsigned char ier; /* 1 */ + int pad2:24; + unsigned char fcr; /* 2 */ + int pad3:24; + unsigned char lcr; /* 3 */ + int pad4:24; + unsigned char mcr; /* 4 */ + int pad5:24; + unsigned char lsr; /* 5 */ + int pad6:24; + unsigned char msr; /* 6 */ + int pad7:24; + unsigned char scr; /* 7 */ + int pad8:24; +#if defined(CONFIG_OMAP) + unsigned char mdr1; /* mode select reset TL16C750*/ +#endif +#ifdef CONFIG_OMAP1510 + int pad9:24; + unsigned long pad[10]; + unsigned char osc_12m_sel; + int pad10:24; +#endif +} __attribute__ ((packed)); +#else +#error "Please define NS16550 registers size." +#endif + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +typedef volatile struct NS16550 *NS16550_t; + +#define FCR_FIFO_EN 0x01 /* Fifo enable */ +#define FCR_RXSR 0x02 /* Receiver soft reset */ +#define FCR_TXSR 0x04 /* Transmitter soft reset */ + +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_DMA_EN 0x04 +#define MCR_TX_DFR 0x08 + +#define LCR_WLS_MSK 0x03 /* character length slect mask */ +#define LCR_WLS_5 0x00 /* 5 bit character length */ +#define LCR_WLS_6 0x01 /* 6 bit character length */ +#define LCR_WLS_7 0x02 /* 7 bit character length */ +#define LCR_WLS_8 0x03 /* 8 bit character length */ +#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define LCR_PEN 0x08 /* Parity eneble */ +#define LCR_EPS 0x10 /* Even Parity Select */ +#define LCR_STKP 0x20 /* Stick Parity */ +#define LCR_SBRK 0x40 /* Set Break */ +#define LCR_BKSE 0x80 /* Bank select enable */ + +#define LSR_DR 0x01 /* Data ready */ +#define LSR_OE 0x02 /* Overrun */ +#define LSR_PE 0x04 /* Parity error */ +#define LSR_FE 0x08 /* Framing error */ +#define LSR_BI 0x10 /* Break */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define LSR_TEMT 0x40 /* Xmitter empty */ +#define LSR_ERR 0x80 /* Error */ + +#ifdef CONFIG_OMAP1510 +#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */ +#endif + +/* useful defaults for LCR */ +#define LCR_8N1 0x03 + +void NS16550_init (NS16550_t com_port, int baud_divisor); +void NS16550_putc (NS16550_t com_port, char c); +char NS16550_getc (NS16550_t com_port); +int NS16550_tstc (NS16550_t com_port); +void NS16550_reinit (NS16550_t com_port, int baud_divisor); diff --git a/include/part.h b/include/part.h new file mode 100644 index 0000000..318aa3c --- /dev/null +++ b/include/part.h @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _PART_H +#define _PART_H +#include + +typedef struct block_dev_desc { + int if_type; /* type of the interface */ + int dev; /* device number */ + unsigned char part_type; /* partition type */ + unsigned char target; /* target SCSI ID */ + unsigned char lun; /* target LUN */ + unsigned char type; /* device type */ + unsigned char removable; /* removable device */ +#ifdef CONFIG_LBA48 + unsigned char lba48; /* device can use 48bit addr (ATA/ATAPI v7) */ +#endif + lbaint_t lba; /* number of blocks */ + unsigned long blksz; /* block size */ + unsigned char vendor [40+1]; /* IDE model, SCSI Vendor */ + unsigned char product[20+1]; /* IDE Serial no, SCSI product */ + unsigned char revision[8+1]; /* firmware revision */ + unsigned long (*block_read)(int dev, + unsigned long start, + lbaint_t blkcnt, + unsigned long *buffer); +}block_dev_desc_t; + +/* Interface types: */ +#define IF_TYPE_UNKNOWN 0 +#define IF_TYPE_IDE 1 +#define IF_TYPE_SCSI 2 +#define IF_TYPE_ATAPI 3 +#define IF_TYPE_USB 4 +#define IF_TYPE_DOC 5 +#define IF_TYPE_MMC 6 + +/* Part types */ +#define PART_TYPE_UNKNOWN 0x00 +#define PART_TYPE_MAC 0x01 +#define PART_TYPE_DOS 0x02 +#define PART_TYPE_ISO 0x03 +#define PART_TYPE_AMIGA 0x04 + +/* + * Type string for U-Boot bootable partitions + */ +#define BOOT_PART_TYPE "U-Boot" /* primary boot partition type */ +#define BOOT_PART_COMP "PPCBoot" /* PPCBoot compatibility type */ + +/* device types */ +#define DEV_TYPE_UNKNOWN 0xff /* not connected */ +#define DEV_TYPE_HARDDISK 0x00 /* harddisk */ +#define DEV_TYPE_TAPE 0x01 /* Tape */ +#define DEV_TYPE_CDROM 0x05 /* CD-ROM */ +#define DEV_TYPE_OPDISK 0x07 /* optical disk */ + +typedef struct disk_partition { + ulong start; /* # of first block in partition */ + ulong size; /* number of blocks in partition */ + ulong blksz; /* block size in bytes */ + uchar name[32]; /* partition name */ + uchar type[32]; /* string type description */ +} disk_partition_t; + +/* disk/part.c */ +int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); +void print_part (block_dev_desc_t *dev_desc); +void init_part (block_dev_desc_t *dev_desc); +void dev_print(block_dev_desc_t *dev_desc); + + +#ifdef CONFIG_MAC_PARTITION +/* disk/part_mac.c */ +int get_partition_info_mac (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); +void print_part_mac (block_dev_desc_t *dev_desc); +int test_part_mac (block_dev_desc_t *dev_desc); +#endif + +#ifdef CONFIG_DOS_PARTITION +/* disk/part_dos.c */ +int get_partition_info_dos (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); +void print_part_dos (block_dev_desc_t *dev_desc); +int test_part_dos (block_dev_desc_t *dev_desc); +#endif + +#ifdef CONFIG_ISO_PARTITION +/* disk/part_iso.c */ +int get_partition_info_iso (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); +void print_part_iso (block_dev_desc_t *dev_desc); +int test_part_iso (block_dev_desc_t *dev_desc); +#endif + +#ifdef CONFIG_AMIGA_PARTITION +/* disk/part_amiga.c */ +int get_partition_info_amiga (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); +void print_part_amiga (block_dev_desc_t *dev_desc); +int test_part_amiga (block_dev_desc_t *dev_desc); +#endif + +#endif /* _PART_H */ diff --git a/lib/Makefile b/lib/Makefile new file mode 100644 index 0000000..32b3798 --- /dev/null +++ b/lib/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2004 Texas Instruments +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(ARCH).a + +SOBJS = _udivsi3.o _umodsi3.o + +COBJS = board.o ecc.o printf.o div0.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/lib/_udivsi3.S b/lib/_udivsi3.S new file mode 100644 index 0000000..2cdcd48 --- /dev/null +++ b/lib/_udivsi3.S @@ -0,0 +1,77 @@ +/* # 1 "libgcc1.S" */ +@ libgcc1 routines for ARM cpu. +@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) +dividend .req r0 +divisor .req r1 +result .req r2 +curbit .req r3 +/* ip .req r12 */ +/* sp .req r13 */ +/* lr .req r14 */ +/* pc .req r15 */ + .text + .globl __udivsi3 + .type __udivsi3 ,function + .align 0 + __udivsi3 : + cmp divisor, #0 + beq Ldiv0 + mov curbit, #1 + mov result, #0 + cmp dividend, divisor + bcc Lgot_result +Loop1: + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. + cmp divisor, #0x10000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #4 + movcc curbit, curbit, lsl #4 + bcc Loop1 +Lbignum: + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. + cmp divisor, #0x80000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #1 + movcc curbit, curbit, lsl #1 + bcc Lbignum +Loop3: + @ Test for possible subtractions, and note which bits + @ are done in the result. On the final pass, this may subtract + @ too much from the dividend, but the result will be ok, since the + @ "bit" will have been shifted out at the bottom. + cmp dividend, divisor + subcs dividend, dividend, divisor + orrcs result, result, curbit + cmp dividend, divisor, lsr #1 + subcs dividend, dividend, divisor, lsr #1 + orrcs result, result, curbit, lsr #1 + cmp dividend, divisor, lsr #2 + subcs dividend, dividend, divisor, lsr #2 + orrcs result, result, curbit, lsr #2 + cmp dividend, divisor, lsr #3 + subcs dividend, dividend, divisor, lsr #3 + orrcs result, result, curbit, lsr #3 + cmp dividend, #0 @ Early termination? + movnes curbit, curbit, lsr #4 @ No, any more bits to do? + movne divisor, divisor, lsr #4 + bne Loop3 +Lgot_result: + mov r0, result + mov pc, lr +Ldiv0: + str lr, [sp, #-4]! + bl __div0 (PLT) + mov r0, #0 @ about as wrong as it could be + ldmia sp!, {pc} + .size __udivsi3 , . - __udivsi3 +/* # 235 "libgcc1.S" */ +/* # 320 "libgcc1.S" */ +/* # 421 "libgcc1.S" */ +/* # 433 "libgcc1.S" */ +/* # 456 "libgcc1.S" */ +/* # 500 "libgcc1.S" */ +/* # 580 "libgcc1.S" */ diff --git a/lib/_umodsi3.S b/lib/_umodsi3.S new file mode 100644 index 0000000..e4aebe8 --- /dev/null +++ b/lib/_umodsi3.S @@ -0,0 +1,88 @@ +/* # 1 "libgcc1.S" */ +@ libgcc1 routines for ARM cpu. +@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) +/* # 145 "libgcc1.S" */ +dividend .req r0 +divisor .req r1 +overdone .req r2 +curbit .req r3 +/* ip .req r12 */ +/* sp .req r13 */ +/* lr .req r14 */ +/* pc .req r15 */ + .text + .globl __umodsi3 + .type __umodsi3 ,function + .align 0 + __umodsi3 : + cmp divisor, #0 + beq Ldiv0 + mov curbit, #1 + cmp dividend, divisor + movcc pc, lr +Loop1: + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. + cmp divisor, #0x10000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #4 + movcc curbit, curbit, lsl #4 + bcc Loop1 +Lbignum: + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. + cmp divisor, #0x80000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #1 + movcc curbit, curbit, lsl #1 + bcc Lbignum +Loop3: + @ Test for possible subtractions. On the final pass, this may + @ subtract too much from the dividend, so keep track of which + @ subtractions are done, we can fix them up afterwards... + mov overdone, #0 + cmp dividend, divisor + subcs dividend, dividend, divisor + cmp dividend, divisor, lsr #1 + subcs dividend, dividend, divisor, lsr #1 + orrcs overdone, overdone, curbit, ror #1 + cmp dividend, divisor, lsr #2 + subcs dividend, dividend, divisor, lsr #2 + orrcs overdone, overdone, curbit, ror #2 + cmp dividend, divisor, lsr #3 + subcs dividend, dividend, divisor, lsr #3 + orrcs overdone, overdone, curbit, ror #3 + mov ip, curbit + cmp dividend, #0 @ Early termination? + movnes curbit, curbit, lsr #4 @ No, any more bits to do? + movne divisor, divisor, lsr #4 + bne Loop3 + @ Any subtractions that we should not have done will be recorded in + @ the top three bits of "overdone". Exactly which were not needed + @ are governed by the position of the bit, stored in ip. + @ If we terminated early, because dividend became zero, + @ then none of the below will match, since the bit in ip will not be + @ in the bottom nibble. + ands overdone, overdone, #0xe0000000 + moveq pc, lr @ No fixups needed + tst overdone, ip, ror #3 + addne dividend, dividend, divisor, lsr #3 + tst overdone, ip, ror #2 + addne dividend, dividend, divisor, lsr #2 + tst overdone, ip, ror #1 + addne dividend, dividend, divisor, lsr #1 + mov pc, lr +Ldiv0: + str lr, [sp, #-4]! + bl __div0 (PLT) + mov r0, #0 @ about as wrong as it could be + ldmia sp!, {pc} + .size __umodsi3 , . - __umodsi3 +/* # 320 "libgcc1.S" */ +/* # 421 "libgcc1.S" */ +/* # 433 "libgcc1.S" */ +/* # 456 "libgcc1.S" */ +/* # 500 "libgcc1.S" */ +/* # 580 "libgcc1.S" */ diff --git a/lib/board.c b/lib/board.c new file mode 100644 index 0000000..fc6e86b --- /dev/null +++ b/lib/board.c @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2005 Texas Instruments. + * + * (C) Copyright 2004 + * Jian Zhang, Texas Instruments, jzhang@ti.com. + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +const char version_string[] = + "Texas Instruments X-Loader 1.4.4ss modified for GTA04 (" __DATE__ " - " __TIME__ ")"; + +int print_info(void) +{ +#ifdef CFG_PRINTF + printf("\n\n%s\n", version_string); +#endif + return 0; +} + +static int init_func_i2c (void) +{ +#ifdef CONFIG_MMC +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); +#endif +#endif + return 0; +} + +typedef int (init_fnc_t) (void); + +init_fnc_t *init_sequence[] = { + cpu_init, /* basic cpu dependent setup */ + board_init, /* basic board dependent setup */ +#ifdef CFG_NS16550_SERIAL + serial_init, /* serial communications setup */ +#endif + print_info, + nand_init, /* board specific nand init */ +#ifdef CONFIG_MMC +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + init_func_i2c, +#endif +#endif + NULL, +}; + +void start_armboot (void) +{ + init_fnc_t **init_fnc_ptr; + int i, size; + uchar *buf; + int *first_instruction; + block_dev_desc_t *dev_desc = NULL; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + if ((*init_fnc_ptr)() != 0) { + hang (); + } + } + + misc_init_r(); + + buf = (uchar*) CFG_LOADADDR; + *(int *)buf = 0xffffffff; + +#ifdef CONFIG_MMC + /* first try mmc */ + if (mmc_init(1)) { + size = file_fat_read("u-boot.bin", buf, 0); + if (size > 0) { +#ifdef CFG_PRINTF + printf("Loading u-boot.bin (%i bytes) from mmc/sd\n", size); +#endif + buf += size; + } + } +#endif + +#ifdef CONFIG_NAND + + if (buf == (uchar *)CFG_LOADADDR) { + /* if no u-boot on mmc, try onenand or nand, depending upon sysboot */ + if (get_mem_type() == GPMC_ONENAND){ +#ifdef CFG_ONENAND +#ifdef CFG_PRINTF + printf("Loading u-boot.bin from onenand\n"); +#endif + for (i = ONENAND_START_BLOCK; i < ONENAND_END_BLOCK; i++){ + if (!onenand_read_block(buf, i)) + buf += ONENAND_BLOCK_SIZE; + } +#endif + } else if (get_mem_type() == GPMC_NAND){ +#ifdef CFG_NAND_K9F1G08R0A +#ifdef CFG_PRINTF + printf("Loading u-boot.bin from nand\n"); +#endif + for (i = NAND_UBOOT_START; i < NAND_UBOOT_END; i+= NAND_BLOCK_SIZE){ + if (!nand_read_block(buf, i)) + buf += NAND_BLOCK_SIZE; /* advance buf ptr */ + } +#endif + } + } +#endif + + /* if u-boot not found on mmc or + * nand read result is erased data + * then serial boot + */ + first_instruction = (int *)CFG_LOADADDR; + if((buf == (uchar *)CFG_LOADADDR) || (*first_instruction == 0xffffffff)) { + extern int do_load_serial_bin (ulong offset, int baudrate); + printf("u-boot.bin not found or blank nand contents - attempting serial boot . . .\n"); + do_load_serial_bin(CFG_LOADADDR, 115200); + } + + /* go run U-Boot and never return */ + ((init_fnc_t *)CFG_LOADADDR)(); + + /* should never come here */ +} + +void hang (void) +{ + /* call board specific hang function */ + board_hang(); + + /* if board_hang() returns, hang here */ +#ifdef CFG_PRINTF + printf("X-Loader hangs\n"); +#endif + for (;;); +} diff --git a/lib/div0.c b/lib/div0.c new file mode 100644 index 0000000..6267bf1 --- /dev/null +++ b/lib/div0.c @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Replacement (=dummy) for GNU/Linux division-by zero handler */ +void __div0 (void) +{ + extern void hang (void); + + hang(); +} diff --git a/lib/ecc.c b/lib/ecc.c new file mode 100644 index 0000000..28fc40d --- /dev/null +++ b/lib/ecc.c @@ -0,0 +1,250 @@ +/* + * (C) Copyright 2000 Texas Instruments + * + * This file os based on the following u-boot file: + * common/cmd_nand.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * Pre-calculated 256-way 1 byte column parity + */ +static const u_char nand_ecc_precalc_table[] = { + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 +}; + + +/* + * Creates non-inverted ECC code from line parity + */ +static void nand_trans_result(u_char reg2, u_char reg3, + u_char *ecc_code) +{ + u_char a, b, i, tmp1, tmp2; + + /* Initialize variables */ + a = b = 0x80; + tmp1 = tmp2 = 0; + + /* Calculate first ECC byte */ + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + a >>= 1; + } + + /* Calculate second ECC byte */ + b = 0x80; + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + a >>= 1; + } + + /* Store two of the ECC bytes */ + ecc_code[0] = tmp1; + ecc_code[1] = tmp2; +} + +/* + * Calculate 3 byte ECC code for 256 byte block + */ +/* ECC Calculation is different between NAND and NAND Legacy code + * in U-Boot. If NAND_LEGACY is enabled in u-boot it should be + * enabled in the config file in x-loader also + */ +#ifdef NAND_LEGACY +void nand_calculate_ecc (const u_char *dat, u_char *ecc_code) +{ + u_char idx, reg1, reg3; + int j; + + /* Initialize variables */ + reg1 = reg3 = 0; + ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; + + /* Build up column parity */ + for(j = 0; j < 256; j++) { + + /* Get CP0 - CP5 from table */ + idx = nand_ecc_precalc_table[dat[j]]; + reg1 ^= idx; + + /* All bit XOR = 1 ? */ + if (idx & 0x40) { + reg3 ^= (u_char) j; + } + } + + /* Create non-inverted ECC code from line parity */ + nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code); + + /* Calculate final ECC code */ + ecc_code[0] = ~ecc_code[0]; + ecc_code[1] = ~ecc_code[1]; + ecc_code[2] = ((~reg1) << 2) | 0x03; +} +#else +void nand_calculate_ecc (const u_char *dat, u_char *ecc_code) +{ + u_char idx, reg1, reg2, reg3; + int j; + + /* Initialize variables */ + reg1 = reg2 = reg3 = 0; + ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; + + /* Build up column parity */ + for(j = 0; j < 256; j++) { + + /* Get CP0 - CP5 from table */ + idx = nand_ecc_precalc_table[dat[j]]; + reg1 ^= (idx & 0x3f); + + /* All bit XOR = 1 ? */ + if (idx & 0x40) { + reg3 ^= (u_char) j; + reg2 ^= ~((u_char) j); + } + } + + /* Create non-inverted ECC code from line parity */ + nand_trans_result(reg2, reg3, ecc_code); + + /* Calculate final ECC code */ + ecc_code[0] = ~ecc_code[0]; + ecc_code[1] = ~ecc_code[1]; + ecc_code[2] = ((~reg1) << 2) | 0x03; +} +#endif +/* + * Detect and correct a 1 bit error for 256 byte block + */ +int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + u_char a, b, c, d1, d2, d3, add, bit, i; + + /* Do error detection */ + d1 = calc_ecc[0] ^ read_ecc[0]; + d2 = calc_ecc[1] ^ read_ecc[1]; + d3 = calc_ecc[2] ^ read_ecc[2]; + + if ((d1 | d2 | d3) == 0) { + /* No errors */ + return 0; + } + else { + a = (d1 ^ (d1 >> 1)) & 0x55; + b = (d2 ^ (d2 >> 1)) & 0x55; + c = (d3 ^ (d3 >> 1)) & 0x54; + + /* Found and will correct single bit error in the data */ + if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { + c = 0x80; + add = 0; + a = 0x80; + for (i=0; i<4; i++) { + if (d1 & c) + add |= a; + c >>= 2; + a >>= 1; + } + c = 0x80; + for (i=0; i<4; i++) { + if (d2 & c) + add |= a; + c >>= 2; + a >>= 1; + } + bit = 0; + b = 0x04; + c = 0x80; + for (i=0; i<3; i++) { + if (d3 & c) + bit |= b; + c >>= 2; + b >>= 1; + } + b = 0x01; + a = dat[add]; + a ^= (b << bit); + dat[add] = a; + return 1; + } + else { + i = 0; + while (d1) { + if (d1 & 0x01) + ++i; + d1 >>= 1; + } + while (d2) { + if (d2 & 0x01) + ++i; + d2 >>= 1; + } + while (d3) { + if (d3 & 0x01) + ++i; + d3 >>= 1; + } + if (i == 1) { + /* ECC Code Error Correction */ + read_ecc[0] = calc_ecc[0]; + read_ecc[1] = calc_ecc[1]; + read_ecc[2] = calc_ecc[2]; + return 2; + } + else { + /* Uncorrectable Error */ + return -1; + } + } + } + + /* Should never happen */ + return -1; +} + diff --git a/lib/printf.c b/lib/printf.c new file mode 100644 index 0000000..91d22fc --- /dev/null +++ b/lib/printf.c @@ -0,0 +1,304 @@ +/* + * (C) Copyright 2004 Texas Instruments + * + * Based on the following file: + * linux/lib/vsprintf.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */ +/* + * Wirzenius wrote this portably, Torvalds fucked it up :-) + */ + +#include +#include + +#ifdef CFG_PRINTF + +/* we use this so that we can do without the ctype library */ +#define is_digit(c) ((c) >= '0' && (c) <= '9') + +size_t strnlen(const char * s, size_t count) +{ + const char *sc; + + for (sc = s; count-- && *sc != '\0'; ++sc) + /* nothing */; + return sc - s; +} + +static int skip_atoi(const char **s) +{ + int i=0; + + while (is_digit(**s)) + i = i*10 + *((*s)++) - '0'; + return i; +} + +#define ZEROPAD 1 /* pad with zero */ +#define SIGN 2 /* unsigned/signed long */ +#define PLUS 4 /* show plus */ +#define SPACE 8 /* space if plus */ +#define LEFT 16 /* left justified */ +#define SPECIAL 32 /* 0x */ +#define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ + +#define do_div(n,base) ({ \ +int __res; \ +__res = ((unsigned long) n) % (unsigned) base; \ +n = ((unsigned long) n) / (unsigned) base; \ +__res; }) + +static char * number(char * str, long num, int base, int size, int precision + ,int type) +{ + char c,sign,tmp[66]; + const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; + int i; + + if (type & LARGE) + digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; + if (type & LEFT) + type &= ~ZEROPAD; + if (base < 2 || base > 36) + return 0; + c = (type & ZEROPAD) ? '0' : ' '; + sign = 0; + if (type & SIGN) { + if (num < 0) { + sign = '-'; + num = -num; + size--; + } else if (type & PLUS) { + sign = '+'; + size--; + } else if (type & SPACE) { + sign = ' '; + size--; + } + } + if (type & SPECIAL) { + if (base == 16) + size -= 2; + else if (base == 8) + size--; + } + i = 0; + if (num == 0) + tmp[i++]='0'; + else while (num != 0) + tmp[i++] = digits[do_div(num,base)]; + if (i > precision) + precision = i; + size -= precision; + if (!(type&(ZEROPAD+LEFT))) + while(size-->0) + *str++ = ' '; + if (sign) + *str++ = sign; + if (type & SPECIAL) { + if (base==8) + *str++ = '0'; + else if (base==16) { + *str++ = '0'; + *str++ = digits[33]; + } + } + if (!(type & LEFT)) + while (size-- > 0) + *str++ = c; + while (i < precision--) + *str++ = '0'; + while (i-- > 0) + *str++ = tmp[i]; + while (size-- > 0) + *str++ = ' '; + return str; +} + + +static int vsprintf(char *buf, const char *fmt, va_list args) +{ + int len; + unsigned long num; + int i, base; + char * str; + const char *s; + + int flags; /* flags to number() */ + + int field_width; /* width of output field */ + int precision; /* min. # of digits for integers; max + number of chars for from string */ + int qualifier; /* 'h', 'l', or 'L' for integer fields */ + + for (str=buf ; *fmt ; ++fmt) { + if (*fmt != '%') { + *str++ = *fmt; + continue; + } + + /* process flags */ + flags = 0; + repeat: + ++fmt; /* this also skips first '%' */ + switch (*fmt) { + case '-': flags |= LEFT; goto repeat; + case '+': flags |= PLUS; goto repeat; + case ' ': flags |= SPACE; goto repeat; + case '#': flags |= SPECIAL; goto repeat; + case '0': flags |= ZEROPAD; goto repeat; + } + + /* get field width */ + field_width = -1; + if (is_digit(*fmt)) + field_width = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + field_width = va_arg(args, int); + if (field_width < 0) { + field_width = -field_width; + flags |= LEFT; + } + } + + /* get the precision */ + precision = -1; + if (*fmt == '.') { + ++fmt; + if (is_digit(*fmt)) + precision = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + precision = va_arg(args, int); + } + if (precision < 0) + precision = 0; + } + + /* get the conversion qualifier */ + qualifier = -1; + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') { + qualifier = *fmt; + ++fmt; + } + + /* default base */ + base = 10; + + switch (*fmt) { + case 'c': + if (!(flags & LEFT)) + while (--field_width > 0) + *str++ = ' '; + *str++ = (unsigned char) va_arg(args, int); + while (--field_width > 0) + *str++ = ' '; + continue; + + case 's': + s = va_arg(args, char *); + if (!s) + s = ""; + + len = strnlen(s, precision); + + if (!(flags & LEFT)) + while (len < field_width--) + *str++ = ' '; + for (i = 0; i < len; ++i) + *str++ = *s++; + while (len < field_width--) + *str++ = ' '; + continue; + + case 'p': + if (field_width == -1) { + field_width = 2*sizeof(void *); + flags |= ZEROPAD; + } + str = number(str, + (unsigned long) va_arg(args, void *), 16, + field_width, precision, flags); + continue; + + + case 'n': + if (qualifier == 'l') { + long * ip = va_arg(args, long *); + *ip = (str - buf); + } else { + int * ip = va_arg(args, int *); + *ip = (str - buf); + } + continue; + + case '%': + *str++ = '%'; + continue; + + /* integer number formats - set up the flags and "break" */ + case 'o': + base = 8; + break; + + case 'X': + flags |= LARGE; + case 'x': + base = 16; + break; + + case 'd': + case 'i': + flags |= SIGN; + case 'u': + break; + + default: + *str++ = '%'; + if (*fmt) + *str++ = *fmt; + else + --fmt; + continue; + } + if (qualifier == 'l') + num = va_arg(args, unsigned long); + else if (qualifier == 'h') { + num = (unsigned short) va_arg(args, int); + if (flags & SIGN) + num = (short) num; + } else if (flags & SIGN) + num = va_arg(args, int); + else + num = va_arg(args, unsigned int); + str = number(str, num, base, field_width, precision, flags); + } + *str = '\0'; + return str-buf; +} + +void serial_printf (const char *fmt, ...) +{ + va_list args; + uint i; + char printbuffer[CFG_PBSIZE]; + + va_start (args, fmt); + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + i = vsprintf (printbuffer, fmt, args); + va_end (args); + + /* Print the string */ + serial_puts (printbuffer); +} +#endif diff --git a/mkconfig b/mkconfig new file mode 100755 index 0000000..54c5268 --- /dev/null +++ b/mkconfig @@ -0,0 +1,63 @@ +#!/bin/sh -e + +# Script to create header files and links to configure +# X-Loader for a specific board. +# +# Parameters: Target Architecture CPU Board +# +# (C) 2004 Texas Instruments +# (C) 2002 DENX Software Engineering, Wolfgang Denk +# + +APPEND=no # Default: Create new config file + +while [ $# -gt 0 ] ; do + case "$1" in + --) shift ; break ;; + -a) shift ; APPEND=yes ;; + *) break ;; + esac +done + +[ $# -lt 4 ] && exit 1 +[ $# -gt 5 ] && exit 1 + +echo "Configuring for $1 board..." + +# +# Create link to architecture specific headers +# +if [ "$SRCTREE" != "$OBJTREE" ] ; then + mkdir -p ${OBJTREE}/include + cd ${OBJTREE}/include + mkdir -p asm + rm -f asm/arch + ln -s ${SRCTREE}/include/asm/arch-$3 asm/arch +else + cd ./include + rm -f asm/arch + ln -s arch-$3 asm/arch +fi + +# +# Create include file for Make +# +echo "ARCH = $2" > config.mk +echo "CPU = $3" >> config.mk +echo "BOARD = $4" >> config.mk + +[ "$5" ] && echo "VENDOR = $5" >> config.mk + +# +# Create board specific header file +# +if [ "$APPEND" = "yes" ] # Append to existing config file +then + echo >> config.h +else + > config.h # Create new config file +fi +echo "/* Automatically generated - do not edit */" >>config.h +echo "#include " >>config.h + +exit 0 diff --git a/rules.mk b/rules.mk new file mode 100644 index 0000000..107f2a3 --- /dev/null +++ b/rules.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +_depend: $(obj).depend + +$(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(SRCS) + @rm -f $@ + @for f in $(SRCS); do \ + g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \ + $(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \ + done + +######################################################################### diff --git a/scripts/mkoneboot.sh b/scripts/mkoneboot.sh new file mode 100644 index 0000000..f0862a5 --- /dev/null +++ b/scripts/mkoneboot.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +IMAGE1=x-load.bin.ift +IMAGE2=x-load-signed.ift +TMP=oneloader +PAGESIZE=2048 + +size=`ls -la $IMAGE1 | awk -F' ' '{ printf $5}'` +let remain=$PAGESIZE-$size +dd if=/dev/zero of=$IMAGE2 bs=1 count=512 +#dd if=/dev/zero of=zerofile bs=$remain count=1 > /dev/null 2> /dev/null +cat $IMAGE1>>$IMAGE2 + +rm -f $IMAGE1 + +echo "Create $IMAGE2 completed..." diff --git a/scripts/signGP.c b/scripts/signGP.c new file mode 100644 index 0000000..963a937 --- /dev/null +++ b/scripts/signGP.c @@ -0,0 +1,300 @@ +/** + * signGP.c - Read the x-load.bin file and write out the x-load.bin.ift file + * + * The signed image is the original pre-pended with the size of the image + * and the load address. If not entered on command line, file name is + * assumed to be x-load.bin in current directory and load address is + * 0x40200800. + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 of + * the License as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + +#undef CH_WITH_CHRAM +struct chsettings { + __u32 section_key; + __u8 valid; + __u8 version; + __u16 reserved; + __u32 flags; +} __attribute__ ((__packed__)); + +/* __u32 cm_clksel_core; + __u32 reserved1; + __u32 cm_autoidle_dpll_mpu; + __u32 cm_clksel_dpll_mpu; + __u32 cm_div_m2_dpll_mpu; + __u32 cm_autoidle_dpll_core; + __u32 cm_clksel_dpll_core; + __u32 cm_div_m2_dpll_core; + __u32 cm_div_m3_dpll_core; + __u32 cm_div_m4_dpll_core; + __u32 cm_div_m5_dpll_core; + __u32 cm_div_m6_dpll_core; + __u32 cm_div_m7_dpll_core; + __u32 cm_autoidle_dpll_per; + __u32 cm_clksel_dpll_per; + __u32 cm_div_m2_dpll_per; + __u32 cm_div_m3_dpll_per; + __u32 cm_div_m4_dpll_per; + __u32 cm_div_m5_dpll_per; + __u32 cm_div_m6_dpll_per; + __u32 cm_div_m7_dpll_per; + __u32 cm_autoidle_dpll_usb; + __u32 cm_clksel_dpll_usb; + __u32 cm_div_m2_dpll_usb; +}*/ + +struct gp_header { + __u32 size; + __u32 load_addr; +} __attribute__ ((__packed__)); + +struct ch_toc { + __u32 section_offset; + __u32 section_size; + __u8 unused[12]; + __u8 section_name[12]; +} __attribute__ ((__packed__)); + +struct chram { + /* CHRAM */ + __u32 section_key_chr; + __u8 section_disable_chr; + __u8 pad_chr[3]; + /* EMIF1 */ + __u32 config_emif1; + __u32 refresh_emif1; + __u32 tim1_emif1; + __u32 tim2_emif1; + __u32 tim3_emif1; + __u32 pwrControl_emif1; + __u32 phy_cntr1_emif1; + __u32 phy_cntr2_emif1; + __u8 modereg1_emif1; + __u8 modereg2_emif1; + __u8 modereg3_emif1; + __u8 pad_emif1; + /* EMIF2 */ + __u32 config_emif2; + __u32 refresh_emif2; + __u32 tim1_emif2; + __u32 tim2_emif2; + __u32 tim3_emif2; + __u32 pwrControl_emif2; + __u32 phy_cntr1_emif2; + __u32 phy_cntr2_emif2; + __u8 modereg1_emif2; + __u8 modereg2_emif2; + __u8 modereg3_emif2; + __u8 pad_emif2; + + __u32 dmm_lisa_map; + __u8 flags; + __u8 pad[3]; +} __attribute__ ((__packed__)); + + +struct ch_chsettings_chram { + struct ch_toc toc_chsettings; + struct ch_toc toc_chram; + struct ch_toc toc_terminator; + struct chsettings section_chsettings; + struct chram section_chram; + __u8 padding1[512 - + (sizeof(struct ch_toc) * 3 + + sizeof(struct chsettings) + sizeof(struct chram))]; + /* struct gp_header gpheader; */ +} __attribute__ ((__packed__)); + +struct ch_chsettings_nochram { + struct ch_toc toc_chsettings; + struct ch_toc toc_terminator; + struct chsettings section_chsettings; + __u8 padding1[512 - + (sizeof(struct ch_toc) * 2 + + sizeof(struct chsettings))]; + /* struct gp_header gpheader; */ +} __attribute__ ((__packed__)); + + +#ifdef CH_WITH_CHRAM +static const struct ch_chsettings_chram config_header = { + /* CHSETTINGS TOC */ + {sizeof(struct ch_toc) * 4, + sizeof(struct chsettings), + "", + {"CHSETTINGS"} + }, + /* CHRAM TOC */ + {sizeof(struct ch_toc) * 4 + sizeof(struct chsettings), + sizeof(struct chram), + "", + {"CHRAM"} + }, + /* toc terminator */ + {0xFFFFFFFF, + 0xFFFFFFFF, + {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF}, + {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF} + }, + /* CHSETTINGS section */ + { + 0xC0C0C0C1, + 0, + 1, + 0, + 0}, + /* CHRAM section */ + { + 0xc0c0c0c2, + 0x01, + {0x00, 0x00, 0x00}, + + /* EMIF1 */ + 0x80800eb2, + 0x00000010, + 0x110d1624, + 0x3058161b, + 0x030060b2, + 0x00000200, + 0x901ff416, + 0x00000000, + 0x23, + 0x01, + 0x02, + 0x00, + + /* EMIF2 */ + 0x80800eb2, + 0x000002ba, + 0x110d1624, + 0x3058161b, + 0x03006542, + 0x00000200, + 0x901ff416, + 0x00000000, + 0x23, + 0x01, + 0x02, + 0x00, + + /* LISA map */ + 0x80700100, + 0x05, + {0x00, 0x00, 0x00}, + }, + "" +}; +#else +static struct ch_chsettings_nochram config_header + __attribute__((section(".config_header"))) = { + /* CHSETTINGS TOC */ + {(sizeof(struct ch_toc)) * 2, + sizeof(struct chsettings), + "", + {"CHSETTINGS"} + }, + /* toc terminator */ + {0xFFFFFFFF, + 0xFFFFFFFF, + {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF}, + {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF} + }, + /* CHSETTINGS section */ + { + 0xC0C0C0C1, + 0, + 1, + 0, + 0}, + "" +}; +#endif + + +int main(int argc, char *argv[]) +{ + int i; + char ifname[FILENAME_MAX], ofname[FILENAME_MAX], ch; + FILE *ifile, *ofile; + unsigned long loadaddr, len; + struct stat sinfo; + + + /* Default to x-load.bin and 0x40200800. */ + strcpy(ifname, "x-load.bin"); + loadaddr = 0x40200800; + + if ((argc == 2) || (argc == 3)) + strcpy(ifname, argv[1]); + + if (argc == 3) + loadaddr = strtoul(argv[2], NULL, 16); + + /* Form the output file name. */ + strcpy(ofname, ifname); + strcat(ofname, ".ift"); + + /* Open the input file. */ + ifile = fopen(ifname, "rb"); + if (ifile == NULL) { + printf("Cannot open %s\n", ifname); + return 1; + } + + /* Get file length. */ + stat(ifname, &sinfo); + len = sinfo.st_size; + + /* Open the output file and write it. */ + ofile = fopen(ofname, "wb"); + if (ofile == NULL) { + printf("Cannot open %s\n", ofname); + fclose(ifile); + return 1; + } + + /* Pad 1 sector of zeroes. */ +#if 0 + ch = 0x00; + for (i = 0; i < 0x200; i++) + fwrite(&ch, 1, 1, ofile); +#endif + + fwrite(&config_header, 1, 512, ofile); + fwrite(&len, 1, 4, ofile); + fwrite(&loadaddr, 1, 4, ofile); + for (i = 0; i < len; i++) { + fread(&ch, 1, 1, ifile); + fwrite(&ch, 1, 1, ofile); + } + + fclose(ifile); + fclose(ofile); + + return 0; +} diff --git a/x-loader/Makefile b/x-loader/Makefile deleted file mode 100644 index 27fe4b5..0000000 --- a/x-loader/Makefile +++ /dev/null @@ -1,271 +0,0 @@ -# -# (C) Copyright 2004-2006, Texas Instruments, -# Jian Zhang -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -HOSTARCH := $(shell uname -m | \ - sed -e s/i.86/i386/ \ - -e s/sun4u/sparc64/ \ - -e s/arm.*/arm/ \ - -e s/sa110/arm/ \ - -e s/powerpc/ppc/ \ - -e s/macppc/ppc/) - -HOSTOS := $(shell uname -s | tr A-Z a-z | \ - sed -e 's/\(cygwin\).*/cygwin/') - -export HOSTARCH - -# Deal with colliding definitions from tcsh etc. -VENDOR= - -######################################################################### -# -# X-loader build supports producing a object files to the separate external -# directory. Two use cases are supported: -# -# 1) Add O= to the make command line -# 'make O=/tmp/build all' -# -# 2) Set environement variable BUILD_DIR to point to the desired location -# 'export BUILD_DIR=/tmp/build' -# 'make' -# -# Command line 'O=' setting overrides BUILD_DIR environent variable. -# -# When none of the above methods is used the local build is performed and -# the object files are placed in the source directory. -# - -ifdef O -ifeq ("$(origin O)", "command line") -BUILD_DIR := $(O) -endif -endif - -ifneq ($(BUILD_DIR),) -saved-output := $(BUILD_DIR) - -# Attempt to create a output directory. -$(shell [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR}) - -# Verify if it was successful. -BUILD_DIR := $(shell cd $(BUILD_DIR) && /bin/pwd) -$(if $(BUILD_DIR),,$(error output directory "$(saved-output)" does not exist)) -endif # ifneq ($(BUILD_DIR),) - -OBJTREE := $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR)) -SRCTREE := $(CURDIR) -TOPDIR := $(SRCTREE) -LNDIR := $(OBJTREE) -export TOPDIR SRCTREE OBJTREE - -MKCONFIG := $(SRCTREE)/mkconfig -export MKCONFIG - -ifneq ($(OBJTREE),$(SRCTREE)) -REMOTE_BUILD := 1 -export REMOTE_BUILD -endif - -# $(obj) and (src) are defined in config.mk but here in main Makefile -# we also need them before config.mk is included which is the case for -# some targets like unconfig, clean, clobber, distclean, etc. -ifneq ($(OBJTREE),$(SRCTREE)) -obj := $(OBJTREE)/ -src := $(SRCTREE)/ -else -obj := -src := -endif -export obj src - -# Make sure CDPATH settings don't interfere -unexport CDPATH - -######################################################################### - -ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk)) -# load ARCH, BOARD, and CPU configuration -include $(obj)include/config.mk -export ARCH CPU BOARD VENDOR -# load other configuration -include $(TOPDIR)/config.mk - -ifndef CROSS_COMPILE -CROSS_COMPILE = arm-none-linux-gnueabi- -#CROSS_COMPILE = arm-linux- -export CROSS_COMPILE -endif - -######################################################################### -# X-LOAD objects....order is important (i.e. start must be first) - -OBJS = cpu/$(CPU)/start.o - -OBJS := $(addprefix $(obj),$(OBJS)) - -LIBS += board/$(BOARDDIR)/lib$(BOARD).a -LIBS += cpu/$(CPU)/lib$(CPU).a -LIBS += lib/lib$(ARCH).a -LIBS += fs/fat/libfat.a -LIBS += disk/libdisk.a -LIBS += drivers/libdrivers.a -LIBS += common/libcommon.a - -LIBS := $(addprefix $(obj),$(sort $(LIBS))) -.PHONY : $(LIBS) - -# Add GCC lib -PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc - -SUBDIRS = - -__OBJS := $(subst $(obj),,$(OBJS)) -__LIBS := $(subst $(obj),,$(LIBS)) - -######################################################################### -######################################################################### - -ALL = $(obj)x-load.bin $(obj)System.map - -all: $(ALL) - -ift: $(ALL) $(obj)x-load.bin.ift - -$(obj)x-load.bin.ift: $(obj)signGP $(obj)System.map $(obj)x-load.bin - TEXT_BASE=`grep -w _start $(obj)System.map|cut -d ' ' -f1` - $(obj)./signGP $(obj)x-load.bin $(TEXT_BASE) - cp $(obj)x-load.bin.ift $(obj)MLO - -$(obj)x-load.bin: $(obj)x-load - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(obj)x-load: $(OBJS) $(LIBS) $(LDSCRIPT) - UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ - --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ - -Map x-load.map -o x-load - -$(OBJS): - $(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@)) - -$(LIBS): - $(MAKE) -C $(dir $(subst $(obj),,$@)) - -$(obj)System.map: $(obj)x-load - @$(NM) $< | \ - grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ - sort > $(obj)System.map - -oneboot: $(obj)x-load.bin - scripts/mkoneboot.sh - -$(obj)signGP: scripts/signGP.c - gcc -Wall -g -O3 -o $(obj)signGP $< - -######################################################################### -else -all $(obj)x-load $(obj)x-load.bin oneboot depend dep $(obj)System.map: - @echo "System not configured - see README" >&2 - @ exit 1 -endif - -######################################################################### - -unconfig: - rm -f $(obj)include/config.h $(obj)include/config.mk - -#======================================================================== -# ARM -#======================================================================== -######################################################################### -## OMAP2 (ARM1136) Systems -######################################################################### - -omap2420h4_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 - -omap2430sdp_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm1136 omap2430sdp - -######################################################################### -## OMAP3 (ARM-CortexA8) Systems -######################################################################### -omap3430sdp_config : unconfig - @$(MKCONFIG) $(@:_config=) arm omap3 omap3430sdp - -omap3430labrador_config : unconfig - @$(MKCONFIG) $(@:_config=) arm omap3 omap3430labrador - -omap3evm_config : unconfig - @$(MKCONFIG) $(@:_config=) arm omap3 omap3evm - -overo_config : unconfig - @$(MKCONFIG) $(@:_config=) arm omap3 overo - -omap3530beagle_config : unconfig - @$(MKCONFIG) $(@:_config=) arm omap3 omap3530beagle - -omap3530gta04_config : unconfig - @$(MKCONFIG) $(@:_config=) arm omap3 omap3530gta04 - -######################################################################### -## OMAP4 (ARM-CortexA9) Systems -######################################################################### -omap4430panda_config : unconfig - @./mkconfig $(@:_config=) arm omap4 omap4430panda - -######################################################################### - -clean: - find $(OBJTREE) -type f \ - \( -name 'core' -o -name '*.bak' -o -name '*~' \ - -o -name '*.o' -o -name '*.a' \) -print \ - | xargs rm -f - -clobber: clean - find $(OBJTREE) -type f \ - \( -name .depend -o -name '*.srec' -o -name '*.bin' \) \ - -print \ - | xargs rm -f - rm -f $(OBJS) $(obj)*.bak $(obj)tags $(obj)TAGS - rm -fr $(obj)*.*~ - rm -f $(obj)x-load $(obj)x-load.map $(ALL) $(obj)x-load.bin.ift $(obj)signGP $(obj)MLO - rm -f $(obj)include/asm/proc $(obj)include/asm/arch - -ifeq ($(OBJTREE),$(SRCTREE)) -mrproper \ -distclean: clobber unconfig -else -mrproper \ -distclean: clobber unconfig - rm -rf $(obj)* -endif - -backup: - F=`basename $(TOPDIR)` ; cd .. ; \ - gtar --force-local -zcvf `date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F - -######################################################################### diff --git a/x-loader/README b/x-loader/README deleted file mode 100644 index d7b16dd..0000000 --- a/x-loader/README +++ /dev/null @@ -1,142 +0,0 @@ -# -# (C) Copyright 2004-2006 Texas Instruments -# -# Some cut/paste from U-Boot README -# (C) Copyright 2000 - 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -Summary: -======== - -This directory contains the source code for X-Loader, an initial program -loader for Embedded boards based on OMAP processors. X-Loader can be -signed by Texas Instruments IFT and installed to Nand flash to achieve -Nand booting. - - -Status: -======= - -The support for Texas Instruments H4 board (OMAP2420) has been implemented -and tested. (Nov 2004) -The support for Texas Instruments 2430SDP board (OMAP2430) has been implemented -and tested. (Jul 2006) -The support for Texas Instruments 3430SDP board (OMAP3430) has been implemented -and tested. (Dec 2006) - - -Support for other OMAP boards can be added. - - -Directory Hierarchy: -==================== - -- board Board dependent files -- cpu CPU specific files -- drivers Commonly used device drivers -- lib Libraries - -- cpu/arm926ejs Files specific to ARM 926 CPUs -- cpu/arm1136 Files specific to ARM 1136 CPUs -- cpu/omap3 Files specific to ARM CortexA8 CPU - - -- board/omap2420h4 - Files specific to OMAP 2420 H4 boards -- board/omap2430sdp - Files specific to OMAP 2430 2430sdp boards -- board/omap3430sdp - Files specific to OMAP 3420sdp boards - - -Software Configuration: -======================= - -Configuration is usually done using C preprocessor defines. Configuration -depends on the combination of board and CPU type; all such information is -kept in a configuration file "include/configs/.h". - -Example: For a OMAP4 PandaBoard, all configuration settings are in -"include/configs/omap4430panda.h" - -For all supported boards there are ready-to-use default -configurations available; just type "make _config". - -Example: For a OMAP4 PandaBoard, type: - - cd x-load - make omap4430panda_config - -After a board has been configured, type "make" to build it supposing the -needed cross tools are in your path. - - -Image Format: -============= - -X-Loader expects OS boot loader (e.g. U-Boot) in Nand flash using -JFFS2 style ECC. - - -Prepare Booting Nand Flash: -=========================== - -After you have built x-load.bin for your board, you need to do the -followings to get it into Nand flash: - -1. Use Texas Instruments IFT to sign x-load.bin. This results in a -signed image called x-load.bin.ift. -2. Use Texas Instruments FlashPrep to generate a .out file using -FlashWriterNand and specifying 0 as nand target address. -3. Use Texas instrumnets Code Composer Studio to run the .out file -which flashes x-load.bin.ift to Nand flash. - -Next you need to get your OS boot loader to Nand at the address your -X-Loader expects. For the H3 example, you can use U-Boot to flash U-Boot. -You can't use FlashWriterNand because it uses ROM code ECC style. - -Implemenation notes: -==================== -H4 support NAND flash booting -2430sdp & 3430sdp support OneNAND booting - - - - - - - - - - - - - - - - - - - - - - diff --git a/x-loader/README-GTA04 b/x-loader/README-GTA04 deleted file mode 100644 index db2431c..0000000 --- a/x-loader/README-GTA04 +++ /dev/null @@ -1,46 +0,0 @@ -This X-loader has been modified for the http://www.GTA04.org board: - -* added Micron MCP detection -* added board revision detection -* added GTA04 notice to greeting -* added memory write check when loading u-boot.bin - from SD card to detect SDRAM failures -* added more Macros to compile either x-loader, MLO and - serial loader from the same sources - -For compiling the different variants, modify these files - -1. X-Loader -a) include/configs/omap3530gta04.h -//#define CONFIG_MMC 1 -#define CONFIG_NAND 1 - -b) board/omap3530gta04/config.mk -TEXT_BASE = 0x40200800 - -2. MLO -a) include/configs/omap3530gta04.h -#define CONFIG_MMC 1 -#define CONFIG_NAND 1 - -b) board/omap3530gta04/config.mk -TEXT_BASE = 0x40200800 - -3. Serial Loader -a) include/configs/omap3530gta04.h -//#define CONFIG_MMC 1 -//#define CONFIG_NAND 1 - -b) board/omap3530gta04/config.mk -TEXT_BASE = 0x40200800 - - -Compile: -make omap3530gta04_config - - -Result file: -X-Loader: x-load.bin.ift -MLO: rename x-load.bin.ift to MLO -Serial Loader: send x-load.bin through pserial tool - diff --git a/x-loader/arm_config.mk b/x-loader/arm_config.mk deleted file mode 100644 index 73d9625..0000000 --- a/x-loader/arm_config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2000-2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ diff --git a/x-loader/board/omap2420h4/Makefile b/x-loader/board/omap2420h4/Makefile deleted file mode 100644 index e6f7629..0000000 --- a/x-loader/board/omap2420h4/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap2420h4.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap2420h4/config.mk b/x-loader/board/omap2420h4/config.mk deleted file mode 100644 index 1c770f3..0000000 --- a/x-loader/board/omap2420h4/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2004 -# Texas Instruments, -# -# TI H4 board with OMAP2420 (ARM1136) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 -# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) ES2 will be configurable -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -# CONFIG_PARTIAL_SRAM must be defined to use this. -TEXT_BASE = 0x80e80000 - -# Used with full SRAM boot. -# This is either with a GP system or a signed boot image. -# easiest, and safest way to go if you can. -# Comment out //CONFIG_PARTIAL_SRAM for this one. -# -#TEXT_BASE = 0x40280000 - diff --git a/x-loader/board/omap2420h4/omap2420h4.c b/x-loader/board/omap2420h4/omap2420h4.c deleted file mode 100644 index ef81b49..0000000 --- a/x-loader/board/omap2420h4/omap2420h4.c +++ /dev/null @@ -1,598 +0,0 @@ -/* - * Copyright (C) 2005 Texas Instruments. - * Jian Zhang - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include - -#include -#include -#include - -static void wait_for_command_complete(unsigned int wd_base); -static void watchdog_init(void); -static void peripheral_enable(void); -static void muxSetupUART1(void); -static u32 get_cpu_rev(void); - - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - return 0; -} - -#ifdef CFG_SDRAM_DDR -void -config_sdram_ddr(u32 rev) -{ - /* ball D11, mode 0 */ - __raw_writeb(0x08, 0x48000032); - - /* SDRC_CS0 Configuration */ - if (rev == CPU_2420_2422_ES1) { - __raw_writel(H4_2422_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING); - } else { - __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - } - - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - - /* - * CS0 SDRC Mode Register - * Burst length = 4 - DDR memory - * Serial mode - * CAS latency = 3 - */ - __raw_writel(0x00000032, SDRC_MR_0); - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00000002, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00000002, SDRC_DLLB_CTRL); - } else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x - } - -} -#endif // CFG_SDRAM_DDR - - -#ifdef CFG_SDRAM_COMBO -void -config_sdram_combo(u32 rev) -{ - - u32 dllctrl=0; - - /* ball C12, mode 0 */ - __raw_writeb(0x00, 0x480000a1); - /* ball D11, mode 0 */ - __raw_writeb(0x00, 0x48000032); - /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */ - __raw_writeb(0x00, 0x480000a3); - - /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */ - __raw_writel(0x00000012, SDRC_SYSCONFIG); - delay(200000); - __raw_writel(0x00000010, SDRC_SYSCONFIG); - - /* SDRCTriState: no Tris */ - /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - - /* CS0 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX9: 1x8Mbx32 */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* CS0 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0); - - /* CS1 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX9: 1x8Mbx32 */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1); - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_1); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - /* CS1 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_1); - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - if (rev == CPU_242X_ES1) - dllctrl = (BIT0|BIT3); - else - dllctrl = BIT0; - - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLA_CTRL); - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */ - } - else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ? - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x - } -} - -#endif // CFG_SDRAM_COMBO - -#ifdef CFG_SDRAM_SDR -void -config_sdram_sdr(u32 rev) -{ - u32 dllctrl=0; - - /* ball D11, mode 0 */ - __raw_writeb(0x00, 0x48000032); - - __raw_writel(0x00000012, SDRC_SYSCONFIG); - delay(200000); - __raw_writel(0x00000010, SDRC_SYSCONFIG); - - /* Chip-level shared interface management */ - /* SDRCTriState: no Tris */ - /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ - /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */ - if (rev == CPU_2420_2422_ES1) - __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING); - else - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - /* CS0 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX14: 32Mbx32 */ - __raw_writel(H4_2420_SDRC_MDCFG_0_SDR, SDRC_MCFG_0); /* diff from combo case */ - __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* CS0 SDRC Mode Register */ - /* Burst length = 2 - SDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2420_SDRC_MR_0_SDR, SDRC_MR_0); /* diff from combo case */ - - /* SDRC DLLA control register */ - /* Enable DLL, Load counter with 115 (middle of range) */ - /* Delay is 90 degrees */ - - if (rev == CPU_242X_ES1) - dllctrl = (BIT0|BIT3); - else - dllctrl = BIT0; - - if (rev == CPU_2420_2422_ES1) { - __raw_writel(0x00007306, SDRC_DLLA_CTRL); - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */ - } - else { - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x - } - -} -#endif // CFG_SDRAM_SDR - -#ifdef CFG_SDRAM_STACKED -void -config_sdram_stacked(u32 rev) -{ - - /* Pin Muxing for SDRC */ - __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */ - __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */ - __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */ - __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */ - - /* configure sdrc 32 bit for COMBO ddr sdram */ - __raw_writel(0x00000010, SDRC_SYSCONFIG); /* no idle ack and RESET enable */ - delay(200000); - __raw_writel(0x00000010, SDRC_SYSCONFIG); /* smart idle mode */ - - /* SDRC_SHARING */ - /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */ - //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - __raw_writel(0x00004900, SDRC_SHARING); - - /* SDRC_CS0 Configuration */ - /* None for ES2.1 */ - - /* SDRC_CS1 Configuration */ - __raw_writel(0x00000000, SDRC_CS_CFG); /* Remap CS1 to 0x80000000 */ - - /* Disable power down of CKE */ - __raw_writel(0x00000085, SDRC_POWER); - - __raw_writel(0x01A02019, SDRC_MCFG_1); /* SDRC_MCFG1 */ - __raw_writel(0x0003DD03, SDRC_RFR_CTRL1); /* SDRC_RFR_CTRL1 */ - __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1); /* SDRC_ACTIM_CTRLA0 */ - __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1); /* SDRC_ACTIM_CTRLB0 */ - - /*Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_1); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - /* CS0 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(0x00000032, SDRC_MR_1); - __raw_writel(0x00000020, SDRC_EMR2_1); /* weak-strength driver */ - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); - } - else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x - } -} -#endif // CFG_SDRAM_STACKED - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ -int s_init(int skip) -{ - u32 rev; - - rev = get_cpu_rev(); - - watchdog_init(); - muxSetupUART1(); - delay(100); - - /*DPLL out = 2x DPLL --> core clock */ - __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); - - /*DPLL into low power bypass (others off) */ - __raw_writel(0x00000001, CM_CLKEN_PLL); - - /*MPU core clock = Core /2 = 300 */ - __raw_writel(MPU_DIV, CM_CLKSEL_MPU); - - /*DSPif=200, DSPif=100, IVA=200 */ - __raw_writel(DSP_DIV, CM_CLKSEL_DSP); - - /*GFX clock (L3/2) 50MHz */ - __raw_writel(GFX_DIV, CM_CLKSEL_GFX); - - /*L3=100, L4=100, DisplaySS=50 Vlync=96Mhz,ssi=100, usb=50 */ - __raw_writel(BUS_DIV, CM_CLKSEL1_CORE); - - /*12MHz apll src, 12/(1+1)*50=300 */ - __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); - - /*Valid the configuration */ - __raw_writel(0x00000001, PRCM_CLKCFG_CTRL); - delay(1000); - - /*Enable DPLL=300, 96MHz APLL locked. */ - __raw_writel(0x0000000F, CM_CLKEN_PLL); - delay(200000); - -#ifdef CFG_SDRAM_DDR - config_sdram_ddr(rev); -#elif defined(CFG_SDRAM_COMBO) - config_sdram_combo(rev); -#elif defined(CFG_SDRAM_SDR) - config_sdram_sdr(rev); -#elif defined(CFG_SDRAM_STACKED) - config_sdram_stacked(rev); -#else -#error SDRAM type not supported -#endif - - delay(20000); - peripheral_enable(); - return(0); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - return(0); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -static void watchdog_init(void) -{ -#define GP (BIT8|BIT9) - - /* There are 4 watch dogs. 1 secure, and 3 general purpose. - * I would expect that the ROM takes care of the secure one, - * but we will try also. Of the 3 GP ones, 1 can reset us - * directly, the other 2 only generate MPU interrupts. - */ - __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR); - -#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/ - __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR); - wait_for_command_complete(WD3_BASE); - __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR); - - __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR); - wait_for_command_complete(WD4_BASE); - __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR); -#endif - -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -static void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base+WWPS); - } while (pending); -} - - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init (void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -static void peripheral_enable(void) -{ - unsigned int v, if_clks=0, func_clks=0; - - /* Enable GP2 timer.*/ - if_clks |= BIT4; - func_clks |= BIT4; - v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */ - __raw_writel(v, CM_CLKSEL2_CORE); - __raw_writel(0x1, CM_CLKSEL_WKUP); - -#ifdef CFG_NS16550 - /* Enable UART1 clock */ - func_clks |= BIT21; - if_clks |= BIT21; -#endif - v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ - __raw_writel(v,CM_ICLKEN1_CORE ); - v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN1_CORE); - delay(1000); - -#ifndef KERNEL_UPDATED - { -#define V1 0xffffffff -#define V2 0x00000007 - - __raw_writel(V1, CM_FCLKEN1_CORE); - __raw_writel(V2, CM_FCLKEN2_CORE); - __raw_writel(V1, CM_ICLKEN1_CORE); - __raw_writel(V1, CM_ICLKEN2_CORE); - } -#endif - -} - -/* Pin Muxing registers used for UART1 */ -#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5) -#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6) -#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7) -#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8) -/**************************************** - * Routine: muxSetupUART1 (ostboot) - * Description: Set up uart1 muxing - *****************************************/ -static void muxSetupUART1(void) -{ - volatile unsigned char *MuxConfigReg; - - /* UART1_CTS pin configuration, PIN = D21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_RTS pin configuration, PIN = H21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_TX pin configuration, PIN = L20 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ - - /* UART1_RX pin configuration, PIN = T21 */ - MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX; - *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ -} - -int nand_init(void) -{ - u32 rev; - - rev = get_cpu_rev(); - - - /* GPMC pin muxing */ - (*(volatile int*)0x48000070) &= 0x000000FF; - (*(volatile int*)0x48000074) &= 0x00000000; - (*(volatile int*)0x48000078) &= 0x00000000; - (*(volatile int*)0x4800007C) &= 0x00000000; - (*(volatile int*)0x48000080) &= 0xFF000000; - - /* GPMC_IO_DIR */ - (*(volatile int*)0x4800008C) = 0x19000000; - - /* GPMC Configuration */ - (*(volatile int*)0x6800A010) = 0x0000000A; - while (((*(volatile int *)0x6800A014) & 0x00000001) == 0); - - (*(volatile int*)0x6800A050) = 0x00000001; - (*(volatile int*)0x6800A060) = 0x00001800; - (*(volatile int*)0x6800A064) = 0x00141400; - (*(volatile int*)0x6800A068) = 0x00141400; - (*(volatile int*)0x6800A06C) = 0x0F010F01; - (*(volatile int*)0x6800A070) = 0x010C1414; - (*(volatile int*)0x6800A074) = 0x00000A80; - (*(volatile int*)0x6800A078) = 0x00000C44; //base 0x04000000 - - (*(volatile int*)0x6800A0A8) = 0x00000000; - delay(1000); -#ifdef CFG_SDRAM_STACKED - (*(volatile int*)0x6800A090) = 0x00011000; -#else - (*(volatile int*)0x6800A090) = 0x00011200; -#endif - (*(volatile int*)0x6800A094) = 0x001f1f00; - (*(volatile int*)0x6800A098) = 0x00080802; - (*(volatile int*)0x6800A09C) = 0x1C091C09; - (*(volatile int*)0x6800A0A0) = 0x031A1F1F; - (*(volatile int*)0x6800A0A4) = 0x000003C2; - (*(volatile int*)0x6800A0A8) = 0x00000F48; - - if (rev != CPU_2420_2422_ES1) - (*(volatile int*)0x6800A040) = 0x1FF0; // es2.x - - if (nand_chip()){ - printf("Unsupported Chip!\n"); - return 1; - } - return 0; -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 v; - v = __raw_readl(TAP_IDCODE_REG); - v = v >> 28; - return(v+1); /* currently 2422 and 2420 match up */ -} - -/* optionally do something like blinking LED */ -void board_hang (void) -{} - - - diff --git a/x-loader/board/omap2420h4/platform.S b/x-loader/board/omap2420h4/platform.S deleted file mode 100644 index 5cc37e5..0000000 --- a/x-loader/board/omap2420h4/platform.S +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#ifdef CONFIG_PARTIAL_SRAM - -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = PRCM_CLKCFG_CTRL - addr of valid reg - * R1 = CM_CLKEN_PLL - addr dpll ctlr reg - * R2 = dpll value - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - ******************************************************************************/ -.global go_to_speed - go_to_speed: - sub sp, sp, #0x4 /* get some stack space */ - str r4, [sp] /* save r4's value */ - - /* move into fast relock bypass */ - ldr r8, pll_ctl_add - mov r4, #0x2 - str r4, [r8] - ldr r4, pll_stat -block: - ldr r8, [r4] /* wait for bypass to take effect */ - and r8, r8, #0x3 - cmp r8, #0x1 - bne block - - /* set new dpll dividers _after_ in bypass */ - ldr r4, pll_div_add - ldr r8, pll_div_val - str r8, [r4] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r4, cfg3_0_addr - ldr r8, cfg3_0_val - str r8, [r4] - ldr r4, cfg4_0_addr - ldr r8, cfg4_0_val - str r8, [r4] - ldr r4, cfg1_0_addr - ldr r8, [r4] - orr r8, r8, #0x3 /* up gpmc divider */ - str r8, [r4] - - /* setup to 2x loop though code. The first loop pre-loads the - * icache, the 2nd commits the prcm config, and locks the dpll - */ - mov r4, #0x1000 /* spin spin spin */ - mov r8, #0x4 /* first pass condition & set registers */ - cmp r8, #0x4 -2: - ldrne r8, [r3] /* DPLL lock check */ - and r8, r8, #0x7 - cmp r8, #0x2 - beq 4f -3: - subeq r8, r8, #0x1 - streq r8, [r0] /* commit dividers (2nd time) */ - nop -lloop1: - sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop1 - mov r4, #0x40000 - cmp r8, #0x1 - nop - streq r2, [r1] /* lock dpll (2nd time) */ - nop -lloop2: - sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop2 - mov r4, #0x40000 - cmp r8, #0x1 - nop - ldreq r8, [r3] /* get lock condition for dpll */ - cmp r8, #0x4 /* first time though? */ - bne 2b - moveq r8, #0x2 /* set to dpll check condition. */ - beq 3b /* if condition not true branch */ -4: - ldr r4, [sp] - add sp, sp, #0x4 /* return stack space */ - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -cfg3_0_addr: - .word GPMC_CONFIG3_0 -cfg3_0_val: - .word SMNAND_GPMC_CONFIG3 -cfg4_0_addr: - .word GPMC_CONFIG4_0 -cfg4_0_val: - .word SMNAND_GPMC_CONFIG4 -cfg1_0_addr: - .word GPMC_CONFIG1_0 -pll_ctl_add: - .word CM_CLKEN_PLL -pll_stat: - .word CM_IDLEST_CKGEN -pll_div_add: - .word CM_CLKSEL1_PLL -pll_div_val: - .word DPLL_VAL /* DPLL setting (300MHz default) */ -#endif - -.globl platformsetup -platformsetup: - mov r3, r0 /* save skip information */ -#ifdef CONFIG_APTIX - ldr r0, REG_SDRC_MCFG_0 - ldr r1, VAL_SDRC_MCFG_0 - str r1, [r0] - ldr r0, REG_SDRC_MR_0 - ldr r1, VAL_SDRC_MR_0 - str r1, [r0] - /* a ddr needs emr1 set here */ - ldr r0, REG_SDRC_SHARING - ldr r1, VAL_SDRC_SHARING - str r1, [r0] - ldr r0, REG_SDRC_RFR_CTRL_0 - ldr r1, VAL_SDRC_RFR_CTRL_0 - str r1, [r0] - - /* little delay after init */ - mov r2, #0x1800 -1: - subs r2, r2, #0x1 - bne 1b -#endif -#ifdef CONFIG_PARTIAL_SRAM - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - mov r0, r3 /* pass skip info to s_init */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ -#endif - - /* map interrupt controller */ - ldr r0, VAL_INTH_SETUP - mcr p15, 0, r0, c15, c2, 4 - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -VAL_INTH_SETUP: - .word PERIFERAL_PORT_BASE -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - - - - - - diff --git a/x-loader/board/omap2420h4/x-load.lds b/x-loader/board/omap2420h4/x-load.lds deleted file mode 100644 index f664ca7..0000000 --- a/x-loader/board/omap2420h4/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm1136/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/x-loader/board/omap2430sdp/Makefile b/x-loader/board/omap2430sdp/Makefile deleted file mode 100644 index b6c984c..0000000 --- a/x-loader/board/omap2430sdp/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap2430sdp.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap2430sdp/config.mk b/x-loader/board/omap2430sdp/config.mk deleted file mode 100644 index 7bc5078..0000000 --- a/x-loader/board/omap2430sdp/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2004 -# Texas Instruments, -# -# TI H4 board with OMAP2420 (ARM1136) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 -# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) ES2 will be configurable -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# 2430 h4 has same mem configuration as h4. - -# For use with external or internal boots. -# CONFIG_PARTIAL_SRAM must be defined to use this. -TEXT_BASE = 0x80e80000 - -# Used with full SRAM boot. -# This is either with a GP system or a signed boot image. -# easiest, and safest way to go if you can. -# Comment out //CONFIG_PARTIAL_SRAM for this one. -# -#TEXT_BASE = 0x40280000 - diff --git a/x-loader/board/omap2430sdp/omap2430sdp.c b/x-loader/board/omap2430sdp/omap2430sdp.c deleted file mode 100644 index f2a7b42..0000000 --- a/x-loader/board/omap2430sdp/omap2430sdp.c +++ /dev/null @@ -1,746 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Texas Instruments, - * Jian Zhang - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include - -static void wait_for_command_complete(unsigned int wd_base); -static void watchdog_init(void); -static void peripheral_enable(void); -static void muxSetupAll(void); -static u32 get_cpu_rev(void); -static u32 get_device_type(void); -static void prcm_init(void); - - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - return 0; -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 v; - v = __raw_readl(TAP_IDCODE_REG); - v = v >> 28; - return(v+1); /* currently 2422 and 2420 match up */ -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return(mode >>= 8); -} - -/************************************************************* - * Helper function to wait for the status of a register - *************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return(1); - if (i==bound) - return(0); - } while (1); -} - -/************************************************************* - * Support for multiple type of memory types - *************************************************************/ -#ifdef CFG_SDRAM_DDR -void -config_sdram_ddr(u32 rev) -{ - /* ball D11, mode 0 */ - __raw_writeb(0x08, 0x48000032); - - /* SDRC_CS0 Configuration */ - __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - - /* - * CS0 SDRC Mode Register - * Burst length = 4 - DDR memory - * Serial mode - * CAS latency = 3 - */ - __raw_writel(0x00000032, SDRC_MR_0); - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x - -} -#endif // CFG_SDRAM_DDR - -#ifdef CFG_SDRAM_COMBO -void -config_sdram_combo(u32 rev) -{ - - u32 dllctrl=0; - - /* ball C12, mode 0 */ - __raw_writeb(0x00, 0x480000a1); - /* ball D11, mode 0 */ - __raw_writeb(0x00, 0x48000032); - /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */ - __raw_writeb(0x00, 0x480000a3); - - /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */ - __raw_writel(0x00000012, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */ - __raw_writel(0x00000000, SDRC_SYSCONFIG); - - /* SDRCTriState: no Tris */ - /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ - if (rev == CPU_2420_2422_ES1) - __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING); - else - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - - /* CS0 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX9: 1x8Mbx32 */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - - /* This is reqd only for ES1 */ - if (rev == CPU_242X_ES1) - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - delay(5000); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* CS0 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0); - - /* CS1 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX9: 1x8Mbx32 */ - __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1); - /* This is reqd only for ES1 */ - if (rev == CPU_242X_ES1) - __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, 0x680090d8); - __raw_writel(CMD_PRECHARGE, 0x680090d8); - __raw_writel(CMD_AUTOREFRESH, 0x680090d8); - __raw_writel(CMD_AUTOREFRESH, 0x680090d8); - - /* CS1 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2422_SDRC_MR_0_DDR, 0x680090b4); - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - - if (rev == CPU_242X_ES1) - dllctrl = (BIT0|BIT3); - else - dllctrl = BIT0; - - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLA_CTRL); - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */ - } - else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x - // __raw_writel(0x00009808, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ? - __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x - //__raw_writel(0x00009808, SDRC_DLLB_CTRL); // ES2.x - } -} - -#endif // CFG_SDRAM_COMBO - -#ifdef CFG_2430SDRAM_DDR -void -config_2430sdram_ddr(u32 rev) -{ - u32 dllstat, dllctrl; - - __raw_writel(0x00000012, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */ - __raw_writel(0x00000000, SDRC_SYSCONFIG); - - /* Chip-level shared interface management */ - /* SDRCTriState: no Tris */ - /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */ - /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */ - __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - /* CS0 SDRC Memory Configuration, */ - /* DDR-SDRAM, External SDRAM is x32bit, */ - /* Configure to MUX14: 32Mbx32 */ - __raw_writel(SDP_2430_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(SDP_2430_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - - __raw_writel(H4_2420_SDRC_RFR_CTRL, SDRC_RFR_CTRL); - - /* Manual Command sequence */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - delay(5000); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* CS0 SDRC Mode Register */ - /* Burst length = 2 - SDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(H4_2420_SDRC_MR_0_DDR, SDRC_MR_0); - - /* Set up SDRC DLL values for 2430 DDR */ - dllctrl = (SDP_2430_SDRC_DLLAB_CTRL & ~BIT2); /* set target ctrl val */ - __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set lock mode */ - __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set lock mode */ - delay(0x1000); /* time to track to center */ - dllstat = __raw_readl(SDRC_DLLA_STATUS) & 0xFF00; /* get status */ - dllctrl = (dllctrl & 0x00FF) | dllstat | BIT2; /* build unlock value */ - __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set unlock mode */ - __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set unlock mode */ -} -#endif // CFG_2430SDRAM_DDR - -#ifdef CFG_SDRAM_STACKED -void -config_sdram_stacked(u32 rev) -{ - - /* Pin Muxing for SDRC */ - __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */ - __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */ - __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */ - __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */ - - /* configure sdrc 32 bit for COMBO ddr sdram */ - __raw_writel(0x00000010, SDRC_SYSCONFIG); /* no idle ack and RESET enable */ - delay(200000); - __raw_writel(0x00000010, SDRC_SYSCONFIG); /* smart idle mode */ - - /* SDRC_SHARING */ - /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */ - //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING); - - __raw_writel(0x00004900, SDRC_SHARING); - - /* SDRC_CS0 Configuration */ - /* None for ES2.1 */ - - /* SDRC_CS1 Configuration */ - __raw_writel(0x00000000, SDRC_CS_CFG); /* Remap CS1 to 0x80000000 */ - - /* Disable power down of CKE */ - __raw_writel(0x00000085, SDRC_POWER); - - __raw_writel(0x01A02019, SDRC_MCFG_1); /* SDRC_MCFG1 */ - __raw_writel(0x0003DD03, SDRC_RFR_CTRL1); /* SDRC_RFR_CTRL1 */ - __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1); /* SDRC_ACTIM_CTRLA0 */ - __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1); /* SDRC_ACTIM_CTRLB0 */ - - /*Manual Command sequence */ - __raw_writel(0x00000000, 0x680090D8); - __raw_writel(0x00000001, 0x680090D8); - __raw_writel(0x00000002, 0x680090D8); - __raw_writel(0x00000002, 0x680090D8); - - /* CS0 SDRC Mode Register */ - /* Burst length = 4 - DDR memory */ - /* Serial mode */ - /* CAS latency = 3 */ - __raw_writel(0x00000032, 0x680090B4); - __raw_writel(0x00000020, 0x680090BC); /* weak-strength driver */ - - /* SDRC DLLA control register */ - /* Delay is 90 degrees */ - if (rev == CPU_2420_2422_ES1) { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00007302, SDRC_DLLA_CTRL); - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00007302, SDRC_DLLB_CTRL); - } - else { - /* Enable DLL, Load counter with 115 (middle of range) */ - __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x - /* Enable DLL, Load counter with 128 (middle of range) */ - __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x - } -} -#endif // CFG_SDRAM_STACKED - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(u32 *shift) -{ -#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ -#define GPT_CTR OMAP24XX_GPT2+TCRR /* read counter address */ - u32 start, cstart, cend, cdiff, val; - unsigned int v, if_clks=0, func_clks=0 ; - - - - if(__raw_readl(PRCM_CLKSRC_CTRL) & BIT7){ /* if currently /2 */ - *shift = 1; - }else{ - *shift = 0; - } - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* mask for sys_clk use */ - __raw_writel(val, CM_CLKSEL2_CORE); /* timer2 source to sys_clk */ - __raw_writel(BIT4, CM_ICLKEN1_CORE); /* timer2 interface clock on */ - __raw_writel(BIT4, CM_FCLKEN1_CORE); /* timer2 function clock on */ - /* Enable GP2 timer.*/ - if_clks |= BIT4; - func_clks |= BIT4; - v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ - __raw_writel(v,CM_ICLKEN1_CORE ); - v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN1_CORE); - __raw_writel(0, OMAP24XX_GPT2+TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP24XX_GPT2+TCLR); /* enable clock */ - /* enable 32kHz source */ /* enabled out of reset */ - /* determine sys_clk via gauging */ - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles*/ - while(__raw_readl(S32K_CR) < start); /* dead loop till start time */ - cstart = __raw_readl(GPT_CTR); /* get start sys_clk count */ - while(__raw_readl(S32K_CR) < (start+20)); /* wait for 40 cycles */ - cend = __raw_readl(GPT_CTR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - /* based on number of ticks assign speed */ - if(cdiff > (19000 >> *shift)) - return(S38_4M); - else if (cdiff > (15200 >> *shift)) - return(S26M); - else if (cdiff > (13000 >> *shift)) - return(S24M); - else if (cdiff > (9000 >> *shift)) - return(S19_2M); - else if (cdiff > (7600 >> *shift)) - return(S13M); - else - return(S12M); -} - -/********************************************************************************* - * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default). - * -- called from SRAM - *********************************************************************************/ -void -prcm_init() -{ - u32 div, speed, val, div_by_2; - - val = __raw_readl(PRCM_CLKSRC_CTRL) & ~(BIT1 | BIT0); -#if defined(OMAP2430_SQUARE_CLOCK_INPUT) - __raw_writel(val, PRCM_CLKSRC_CTRL); -#else - __raw_writel((val | BIT0), PRCM_CLKSRC_CTRL); -#endif - speed = get_osc_clk_speed(&div_by_2); - if((speed > S19_2M) && (!div_by_2)){ /* if fast && /2 off, enable it */ - val = ~(BIT6|BIT7) & __raw_readl(PRCM_CLKSRC_CTRL); - val |= (0x2 << 6); /* divide by 2 if (24,26,38.4) -> (12/13/19.2) */ - __raw_writel(val, PRCM_CLKSRC_CTRL); - } - - __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */ - __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */ - __raw_writel(0, CM_ICLKEN1_CORE); - __raw_writel(0, CM_ICLKEN2_CORE); - - /*DPLL into low power bypass (others off) */ - __raw_writel(0x00000001, CM_CLKEN_PLL); - - __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */ - __raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */ - __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */ - __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */ - __raw_writel(MDM_DIV, CM_CLKSEL_MDM); /* set mdm dividers */ - - div = BUS_DIV; - __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/SSi dividers */ - delay(1000); - - /*13MHz apll src, PRCM 'x' DPLL rate */ - __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); - - /*Valid the configuration */ - __raw_writel(0x00000001, PRCM_CLKCFG_CTRL); - delay(1000); - - /* set up APLLS_CLKIN per crystal */ - if (speed > S19_2M) - speed >>= 1; /* if fast shift to /2 range */ - val = (0x2 << 23); /* default to 13Mhz for 2430c */ - if (speed == S12M) - val = (0x3 << 23); - else if (speed == S19_2M) - val = (0x0 << 23); - val |= (~(BIT23|BIT24|BIT25) & __raw_readl(CM_CLKSEL1_PLL)); - __raw_writel(val, CM_CLKSEL1_PLL); - - __raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */ - wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);/* wait for apll lock */ - - delay(200000); -} - -void SEC_generic(void) -{ -/* Permission values for registers -Full fledged permissions to all */ -#define UNLOCK_1 0xFFFFFFFF -#define UNLOCK_2 0x00000000 -#define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT)*/ - __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x68); /* REQ_INFO_PERMISSION_1 L*/ - __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ - __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ - __raw_writel(UNLOCK_2, PM_RT_APE_BASE_ADDR_ARM + 0x60); /* ADDR_MATCH_1 L*/ - - - __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ - - __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ - __raw_writel(UNLOCK_2, PM_OCM_RAM_BASE_ADDR_ARM + 0x80); /* ADDR_MATCH_2 L*/ - - /* IVA Changes */ - __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ - __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for general use. - ***********************************************************/ -void try_unlock_sram(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - mode = get_device_type(); - - if ((mode == GP_DEVICE) || (mode == HS_DEVICE) || (mode == EMU_DEVICE) - || (mode == TST_DEVICE)) { - /* Secure or Emulation device - HS/E/T */ - SEC_generic(); - } - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -int s_init(int skip) -{ - u32 rev; - - rev = get_cpu_rev(); - - watchdog_init(); - try_unlock_sram(); - muxSetupAll(); - delay(100); - prcm_init(); - -#ifdef CFG_SDRAM_DDR - config_sdram_ddr(rev); -#elif defined(CFG_SDRAM_COMBO) - config_sdram_combo(rev); -#elif defined(CFG_2430SDRAM_DDR) - config_2430sdram_ddr(rev); -#elif defined(CFG_SDRAM_STACKED) - config_sdram_stacked(rev); -#else -#error SDRAM type not supported -#endif - - delay(20000); - peripheral_enable(); - return(0); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - return(0); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -static void watchdog_init(void) -{ -#define GP (BIT8|BIT9) - - /* There are 4 watch dogs. 1 secure, and 3 general purpose. - * I would expect that the ROM takes care of the secure one, - * but we will try also. Of the 3 GP ones, 1 can reset us - * directly, the other 2 only generate MPU interrupts. - */ - __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR); - -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -static void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base+WWPS); - } while (pending); -} - - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init (void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -static void peripheral_enable(void) -{ - unsigned int v, if_clks=0, if_clks2 = 0, func_clks=0, func_clks2 = 0; - - /* Enable GP2 timer.*/ - if_clks |= BIT4; - func_clks |= BIT4; - v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP24XX_GPT2 */ - __raw_writel(v, CM_CLKSEL2_CORE); - __raw_writel(0x1, CM_CLKSEL_WKUP); - -#ifdef CFG_NS16550 - /* Enable UART1 clock */ - func_clks |= BIT21; - if_clks |= BIT21; -#endif - v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ - __raw_writel(v,CM_ICLKEN1_CORE ); - v = __raw_readl(CM_ICLKEN2_CORE) | if_clks2; /* Interface clocks on */ - __raw_writel(v, CM_ICLKEN2_CORE); - v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN1_CORE); - v = __raw_readl(CM_FCLKEN2_CORE) | func_clks2; /* Functional Clocks on */ - __raw_writel(v, CM_FCLKEN2_CORE); - delay(1000); - -} - -/* Do pin muxing for all the devices used in X-Loader */ -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writeb(VALUE, OMAP24XX_CTRL_BASE + OFFSET); -static void muxSetupAll(void) -{ - /* UART 1*/ - MUX_VAL(0x00B1, 0x1B) /* uart1_cts- EN, HI, 3, ->gpio_32 */ - MUX_VAL(0x00B2, 0x1B) /* uart1_rts- EN, HI, 3, ->gpio_8 */ - MUX_VAL(0x00B3, 0x1B) /* uart1_tx- EN, HI, 3, ->gpio_9 */ - MUX_VAL(0x00B4, 0x1B) /* uart1_rx- EN, HI, 3, ->gpio_10 */ - MUX_VAL(0x0107, 0x01) /* ssi1_dat_tx- Dis, 1, ->uart1_tx */ - MUX_VAL(0x0108, 0x01) /* ssi1_flag_tx- Dis, 1, ->uart1_rts */ - MUX_VAL(0x0109, 0x01) /* ssi1_rdy_tx- Dis, 1, ->uart1_cts */ - MUX_VAL(0x010A, 0x01) /* ssi1_dat_rx- Dis, 1, ->uart1_rx */ - - /* Mux settings for SDRC */ - MUX_VAL(0x0054, 0x1B) /* sdrc_a14 - EN, HI, 3, ->gpio_0 */ - MUX_VAL(0x0055, 0x1B) /* sdrc_a13 - EN, HI, 3, ->gpio_1 */ - MUX_VAL(0x0056, 0x00) /* sdrc_a12 - Dis, 0 */ - MUX_VAL(0x0046, 0x00) /* sdrc_ncs1 - Dis, 0 */ - MUX_VAL(0x0048, 0x00) /* sdrc_cke1 - Dis, 0 */ - /* GPMC */ - MUX_VAL(0x0030, 0x00) /* gpmc_clk - Dis, 0 */ - MUX_VAL(0x0032, 0x00) /* gpmc_ncs1- Dis, 0 */ - MUX_VAL(0x0033, 0x00) /* gpmc_ncs2- Dis, 0 */ - MUX_VAL(0x0034, 0x03) /* gpmc_ncs3- Dis, 3, ->gpio_24 */ - MUX_VAL(0x0035, 0x03) /* gpmc_ncs4- Dis, 3, ->gpio_25 */ - MUX_VAL(0x0036, 0x00) /* gpmc_ncs5- Dis, 0 */ - MUX_VAL(0x0037, 0x03) /* gpmc_ncs6- Dis, 3, ->gpio_27 */ - MUX_VAL(0x0038, 0x00) /* gpmc_ncs7- Dis, 0 */ - MUX_VAL(0x0040, 0x18) /* gpmc_wait1- Dis, 0 */ - MUX_VAL(0x0041, 0x18) /* gpmc_wait2- Dis, 0 */ - MUX_VAL(0x0042, 0x1B) /* gpmc_wait3- EN, HI, 3, ->gpio_35 */ - MUX_VAL(0x0085, 0x1B) /* gpmc_a10- EN, HI, 3, ->gpio_3 */ -} - -int nand_init(void) -{ - u32 rev; - - /* GPMC Configuration */ - rev = get_cpu_rev(); - - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ -#ifdef CFG_NAND - __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ -#endif - - /* Set the GPMC Vals . For NAND boot on 2430SDP, NAND is mapped at CS0 - * , NOR at CS1 and MPDB at CS5. And oneNAND boot, we map oneNAND at CS0. - * We configure only GPMC CS0 with required values. Configiring other devices - * at other CS in done in u-boot anyway. So we don't have to bother doing it here. - */ - __raw_writel(0, GPMC_CONFIG7_0); - sdelay(1000); - -#ifdef CFG_NAND - __raw_writel( SMNAND_GPMC_CONFIG1, GPMC_CONFIG1_0); - __raw_writel( SMNAND_GPMC_CONFIG2, GPMC_CONFIG2_0); - __raw_writel( SMNAND_GPMC_CONFIG3, GPMC_CONFIG3_0); - __raw_writel( SMNAND_GPMC_CONFIG4, GPMC_CONFIG4_0); - __raw_writel( SMNAND_GPMC_CONFIG5, GPMC_CONFIG5_0); - __raw_writel( SMNAND_GPMC_CONFIG6, GPMC_CONFIG6_0); - -#else /* CFG_ONENAND */ - __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1_0); - __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2_0); - __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3_0); - __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4_0); - __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5_0); - __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6_0); -#endif - - /* Enable the GPMC Mapping */ - __raw_writel(( ((OMAP24XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((OMAP24XX_GPMC_CS0_MAP>>24) & 0x3F) | - (1<<6) ), GPMC_CONFIG7_0); - sdelay(2000); -#ifdef CFG_NAND - if (nand_chip()){ -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } -#else - if (onenand_chip()){ -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } - -#endif - return 0; -} - -/* optionally do something like blinking LED */ -void board_hang (void) -{ while (0) {};} diff --git a/x-loader/board/omap2430sdp/platform.S b/x-loader/board/omap2430sdp/platform.S deleted file mode 100644 index f221d7e..0000000 --- a/x-loader/board/omap2430sdp/platform.S +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2005 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = PRCM_CLKCFG_CTRL - addr of valid reg - * R1 = CM_CLKEN_PLL - addr dpll ctlr reg - * R2 = dpll value - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - ******************************************************************************/ -.global go_to_speed - go_to_speed: - sub sp, sp, #0x4 /* get some stack space */ - str r4, [sp] /* save r4's value */ - - /* move into fast relock bypass */ - ldr r8, pll_ctl_add - mov r4, #0x2 - str r4, [r8] - ldr r4, pll_stat -block: - ldr r8, [r4] /* wait for bypass to take effect */ - and r8, r8, #0x3 - cmp r8, #0x1 - bne block - - /* set new dpll dividers _after_ in bypass */ - ldr r4, pll_div_add - ldr r8, pll_div_val - str r8, [r4] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r4, flash_cfg3_addr - ldr r8, flash_cfg3_val - str r8, [r4] - ldr r4, flash_cfg4_addr - ldr r8, flash_cfg4_val - str r8, [r4] - ldr r4, flash_cfg1_addr - ldr r8, [r4] - orr r8, r8, #0x3 /* up gpmc divider */ - str r8, [r4] - - /* setup to 2x loop though code. The first loop pre-loads the - * icache, the 2nd commits the prcm config, and locks the dpll - */ - mov r4, #0x1000 /* spin spin spin */ - mov r8, #0x4 /* first pass condition & set registers */ - cmp r8, #0x4 -2: - ldrne r8, [r3] /* DPLL lock check */ - and r8, r8, #0x7 - cmp r8, #0x2 - beq 4f -3: - subeq r8, r8, #0x1 - streq r8, [r0] /* commit dividers (2nd time) */ - nop -lloop1: - sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop1 - mov r4, #0x40000 - cmp r8, #0x1 - nop - streq r2, [r1] /* lock dpll (2nd time) */ - nop -lloop2: - sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ - nop - cmp r4, #0x0 - bne lloop2 - mov r4, #0x40000 - cmp r8, #0x1 - nop - ldreq r8, [r3] /* get lock condition for dpll */ - cmp r8, #0x4 /* first time though? */ - bne 2b - moveq r8, #0x2 /* set to dpll check condition. */ - beq 3b /* if condition not true branch */ -4: - ldr r4, [sp] - add sp, sp, #0x4 /* return stack space */ - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -#ifdef CFG_ONENAND -flash_cfg3_addr: - .word GPMC_CONFIG3_0 -flash_cfg3_val: - .word ONENAND_GPMC_CONFIG3 -flash_cfg4_addr: - .word GPMC_CONFIG4_0 -flash_cfg4_val: - .word ONENAND_GPMC_CONFIG4 -flash_cfg1_addr: - .word GPMC_CONFIG1_0 -#else -flash_cfg3_addr: - .word GPMC_CONFIG3_0 -flash_cfg3_val: - .word SMNAND_GPMC_CONFIG3 -flash_cfg4_addr: - .word GPMC_CONFIG4_0 -flash_cfg4_val: - .word SMNAND_GPMC_CONFIG4 -flash_cfg1_addr: - .word GPMC_CONFIG1_0 -#endif -pll_ctl_add: - .word CM_CLKEN_PLL -pll_stat: - .word CM_IDLEST_CKGEN -pll_div_add: - .word CM_CLKSEL1_PLL -pll_div_val: - .word DPLL_VAL /* DPLL setting (300MHz default) */ - -.globl platformsetup -platformsetup: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* map interrupt controller */ - ldr r0, VAL_INTH_SETUP - mcr p15, 0, r0, c15, c2, 4 - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -VAL_INTH_SETUP: - .word PERIFERAL_PORT_BASE -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - diff --git a/x-loader/board/omap2430sdp/x-load.lds b/x-loader/board/omap2430sdp/x-load.lds deleted file mode 100644 index f12e8f8..0000000 --- a/x-loader/board/omap2430sdp/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004-2005 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/arm1136/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/x-loader/board/omap3430labrador/Makefile b/x-loader/board/omap3430labrador/Makefile deleted file mode 100644 index d54b666..0000000 --- a/x-loader/board/omap3430labrador/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap3430sdp.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap3430labrador/config.mk b/x-loader/board/omap3430labrador/config.mk deleted file mode 100644 index d6ad6c5..0000000 --- a/x-loader/board/omap3430labrador/config.mk +++ /dev/null @@ -1,22 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, -# -# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# SDP3430 has 1 bank of 32MB or 128MB mDDR-SDRAM on CS0 -# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000'0000 (bank1) - re-mappable below CS1 - -# For use if you want X-Loader to relocate from SRAM to DDR -#TEXT_BASE = 0x80e80000 - -# For XIP in 64K of SRAM or debug (GP device has it all availabe) -# SRAM 40200000-4020FFFF base -# initial stack at 0x4020fffc used in s_init (below xloader). -# The run time stack is (above xloader, 2k below) -# If any globals exist there needs to be room for them also -TEXT_BASE = 0x40208800 diff --git a/x-loader/board/omap3430labrador/omap3430sdp.c b/x-loader/board/omap3430labrador/omap3430sdp.c deleted file mode 100644 index 89d9ff1..0000000 --- a/x-loader/board/omap3430labrador/omap3430sdp.c +++ /dev/null @@ -1,753 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, - * Jian Zhang - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -typedef struct dpll_param dpll_param; - -#define MAX_SIL_INDEX 3 - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param * get_mpu_dpll_param(void); -extern dpll_param * get_iva_dpll_param(void); -extern dpll_param * get_core_dpll_param(void); -extern dpll_param * get_per_dpll_param(void); - -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - return 0; -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return(mode >>= 8); -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 cpuid=0; - /* On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate - * between ES2.0 and ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); - if((cpuid & 0xf) == 0x0) - return CPU_3430_ES1; - else - return CPU_3430_ES2; - -} - -/****************************************** - * cpu_is_3410(void) - returns true for 3410 - ******************************************/ -u32 cpu_is_3410(void) -{ - int status; - if(get_cpu_rev() < CPU_3430_ES2) { - return 0; - } else { - /* read scalability status and return 1 for 3410*/ - status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); - /* Check whether MPU frequency is set to 266 MHz which - * is nominal for 3410. If yes return true else false - */ - if (((status >> 8) & 0x3) == 0x2) - return 1; - else - return 0; - } -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return (1); - if (i == bound) - return (0); - } while (1); -} - -#ifdef CFG_3430SDRAM_DDR -/********************************************************************* - * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. - *********************************************************************/ -void config_3430sdram_ddr(void) -{ - /* reset sdrc controller */ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); - __raw_writel(0, SDRC_SYSCONFIG); - - /* setup sdrc to ball mux */ - __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); - - /* set mdcfg */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - - /* set timing */ - __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL); - - /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - delay(5000); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* set mr0 */ - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); - - /* set up dll */ - __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); - delay(0x2000); /* give time to lock */ - -} -#endif // CFG_3430SDRAM_DDR - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(void) -{ - u32 start, cstart, cend, cdiff, val; - - val = __raw_readl(PRM_CLKSRC_CTRL); - /* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~BIT7)) | BIT6; - __raw_writel(val, PRM_CLKSRC_CTRL); - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; - __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ - - /* Enable I and F Clocks for GPT1 */ - val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; - __raw_writel(val, CM_ICLKEN_WKUP); - val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; - __raw_writel(val, CM_FCLKEN_WKUP); - - __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ - /* enable 32kHz source *//* enabled out of reset */ - /* determine sys_clk via gauging */ - - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ - while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ - cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ - while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ - cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - - /* based on number of ticks assign speed */ - if (cdiff > 19000) - return (S38_4M); - else if (cdiff > 15200) - return (S26M); - else if (cdiff > 13000) - return (S24M); - else if (cdiff > 9000) - return (S19_2M); - else if (cdiff > 7600) - return (S13M); - else - return (S12M); -} - -/****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * -- input oscillator clock frequency. - * - *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) -{ - if(osc_clk == S38_4M) - *sys_clkin_sel= 4; - else if(osc_clk == S26M) - *sys_clkin_sel = 3; - else if(osc_clk == S19_2M) - *sys_clkin_sel = 2; - else if(osc_clk == S13M) - *sys_clkin_sel = 1; - else if(osc_clk == S12M) - *sys_clkin_sel = 0; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 osc_clk=0, sys_clkin_sel; - dpll_param *dpll_param_p; - u32 clk_index, sil_index; - - /* Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ - - /* If the input clock is greater than 19.2M always divide/2 */ - if(sys_clkin_sel > 2) { - sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */ - clk_index = sys_clkin_sel/2; - } else { - sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */ - clk_index = sys_clkin_sel; - } - - sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ - - /* The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - if(cpu_is_3410()) - sil_index = 2; - else { - if(get_cpu_rev() == CPU_3430_ES1) - sil_index = 0; - else if(get_cpu_rev() == CPU_3430_ES2) - sil_index = 1; - } - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address of Core DPLL param table*/ - dpll_param_p = (dpll_param *)get_core_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; - /* CORE DPLL */ - /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); - /* For 3430 ES1.0 Errata 1.50, default value directly doesnt - work. write another value and then default value. */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ - sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ - sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb ES1 only */ - sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ - sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to PER DPLL param table*/ - dpll_param_p = (dpll_param *)get_per_dpll_param(); - /* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; - /* PER DPLL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ - sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to MPU DPLL param table*/ - dpll_param_p = (dpll_param *)get_mpu_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; - /* MPU DPLL (unlocked already) */ - sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address to IVA DPLL param table*/ - dpll_param_p = (dpll_param *)get_iva_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; - /* IVA DPLL (set to 12*20=240MHz) */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); - sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ - sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ - sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); - - /* Set up GPTimers to sys_clk source only */ - sr32(CM_CLKSEL_PER, 0, 8, 0xff); - sr32(CM_CLKSEL_WKUP, 0, 1, 1); - - delay(5000); -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock(void) -{ - /* Permission values for registers -Full fledged permissions to all */ - #define UNLOCK_1 0xFFFFFFFF - #define UNLOCK_2 0x00000000 - #define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT)*/ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T*/ - mode = get_device_type(); - if (mode == GP_DEVICE) { - secure_unlock(); - } - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -void s_init(void) -{ - watchdog_init(); -#ifdef CONFIG_3430_AS_3410 - /* setup the scalability control register for - * 3430 to work in 3410 mode - */ - __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP); -#endif - try_unlock_memory(); - set_muxconf_regs(); - delay(100); - prcm_init(); - per_clocks_enable(); - config_3430sdram_ddr(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - return(0); -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is - * either taken care of by ROM (HS/EMU) or not accessible (GP). - * We need to take care of WD2-MPU or take a PRCM reset. WD3 - * should not be running and does not generate a PRCM reset. - */ - sr32(CM_FCLKEN_WKUP, 5, 1, 1); - sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init (void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void per_clocks_enable(void) -{ - /* Enable GP2 timer. */ - sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ - -#ifdef CFG_NS16550 -////#ifdef CONFIG_SERIAL3 - sr32(CM_FCLKEN_PER, 11, 1, 0x1); - sr32(CM_ICLKEN_PER, 11, 1, 0x1); -////#else - /* Enable UART1 clocks */ - sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); - sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); -////#endif -#endif - delay(1000); -} - -/* Set MUX for UART, GPMC, SDRC, GPIO */ - -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - /*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4 lab*/\ - MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5 lab*/\ - MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*sys_ndmareq1 lab*/\ - MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_IO_DIR lab*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1 lab*/\ - MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ - MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ - MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ - MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ - MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ - MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ - MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ - MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ - MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/ -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} - -/********************************************************** - * Routine: nand+_init - * Description: Set up nand for nand and jffs2 commands - *********************************************************/ -int nand_init(void) -{ - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ -#ifdef CFG_NAND - __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ -#endif - - /* setup CS0 for Micron NAND, leave other CS's to u-boot */ - __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); - delay(1000); - -#ifdef CFG_NAND - __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - -#else /* CFG_ONENAND */ - __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); -#endif - - /* Enable the GPMC Mapping */ - __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((OMAP34XX_GPMC_CS0_MAP>>24) & 0x3F) | - (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - -#ifdef CFG_NAND - if (nand_chip()){ -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } -#else - if (onenand_chip()){ -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } -#endif - return 0; -} - -/* optionally do something like blinking LED */ -void board_hang (void) -{ while (0) {};} diff --git a/x-loader/board/omap3430labrador/platform.S b/x-loader/board/omap3430labrador/platform.S deleted file mode 100644 index 5869270..0000000 --- a/x-loader/board/omap3430labrador/platform.S +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE,0x07,0x05,0x01 -/* ES2 */ -.word 0x0FA,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D,0x0C,0x03,0x01 -/* ES2 */ -.word 0x1F4,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179,0x12,0x04,0x01 -/* ES2 */ -.word 0x271,0x17,0x03,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D,0x19,0x03,0x01 -/* ES2 */ -.word 0x0FA,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA,0x32,0x03,0x01 -/* ES2 */ -.word 0x271,0x2F,0x03,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D,0x05,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA,0x0C,0x03,0x01 -/* ES2 */ -.word 0x168,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082,0x09,0x07,0x01 -/* ES2 */ -.word 0x0E1,0x0B,0x06,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D,0x0C,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F,0x30,0x03,0x01 -/* ES2 */ -.word 0x0E1,0x17,0x06,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -/* Core DPLL targets for L3 at 166 & L133 */ -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 -/* ES2 */ -.word M_12,N_12,FSEL_12,M2_12 -/* 3410 */ -.word M_12,N_12,FSEL_12,M2_12 - -/* 13MHz */ -/* ES1 */ -.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 -/* ES2 */ -.word M_13,N_13,FSEL_13,M2_13 -/* 3410 */ -.word M_13,N_13,FSEL_13,M2_13 - -/* 19.2MHz */ -/* ES1 */ -.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 -/* ES2 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 -/* 3410 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 - -/* 26MHz */ -/* ES1 */ -.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 -/* ES2 */ -.word M_26,N_26,FSEL_26,M2_26 -/* 3410 */ -.word M_26,N_26,FSEL_26,M2_26 - -/* 38.4MHz */ -/* ES1 */ -.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 -/* ES2 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 -/* 3410 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8,0x05,0x07,0x09 - -/* 13MHz */ -.word 0x1B0,0x0C,0x03,0x09 - -/* 19.2MHz */ -.word 0xE1,0x09,0x07,0x09 - -/* 26MHz */ -.word 0xD8,0x0C,0x07,0x09 - -/* 38.4MHz */ -.word 0xE1,0x13,0x07,0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/omap3430labrador/x-load.lds b/x-loader/board/omap3430labrador/x-load.lds deleted file mode 100644 index 9402f74..0000000 --- a/x-loader/board/omap3430labrador/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * November 2006 - Changed to support 3430sdp device - * Copyright (c) 2004-2006 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/omap3/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/x-loader/board/omap3430sdp/Makefile b/x-loader/board/omap3430sdp/Makefile deleted file mode 100644 index d54b666..0000000 --- a/x-loader/board/omap3430sdp/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap3430sdp.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap3430sdp/config.mk b/x-loader/board/omap3430sdp/config.mk deleted file mode 100644 index d6ad6c5..0000000 --- a/x-loader/board/omap3430sdp/config.mk +++ /dev/null @@ -1,22 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, -# -# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# SDP3430 has 1 bank of 32MB or 128MB mDDR-SDRAM on CS0 -# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 -# Physical Address: -# 8000'0000 (bank0) -# A000'0000 (bank1) - re-mappable below CS1 - -# For use if you want X-Loader to relocate from SRAM to DDR -#TEXT_BASE = 0x80e80000 - -# For XIP in 64K of SRAM or debug (GP device has it all availabe) -# SRAM 40200000-4020FFFF base -# initial stack at 0x4020fffc used in s_init (below xloader). -# The run time stack is (above xloader, 2k below) -# If any globals exist there needs to be room for them also -TEXT_BASE = 0x40208800 diff --git a/x-loader/board/omap3430sdp/omap3430sdp.c b/x-loader/board/omap3430sdp/omap3430sdp.c deleted file mode 100644 index 6ed62bc..0000000 --- a/x-loader/board/omap3430sdp/omap3430sdp.c +++ /dev/null @@ -1,779 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * Jian Zhang - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -typedef struct dpll_param dpll_param; - -#define MAX_SIL_INDEX 3 - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param * get_mpu_dpll_param(); -extern dpll_param * get_iva_dpll_param(); -extern dpll_param * get_core_dpll_param(); -extern dpll_param * get_per_dpll_param(); - -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - return 0; -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return(mode >>= 8); -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 cpuid=0; - /* On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate - * between ES2.0 and ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); - if((cpuid & 0xf) == 0x0) - return CPU_3430_ES1; - else - return CPU_3430_ES2; - -} - -/****************************************** - * cpu_is_3410(void) - returns true for 3410 - ******************************************/ -u32 cpu_is_3410(void) -{ - int status; - if(get_cpu_rev() < CPU_3430_ES2) { - return 0; - } else { - /* read scalability status and return 1 for 3410*/ - status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); - /* Check whether MPU frequency is set to 266 MHz which - * is nominal for 3410. If yes return true else false - */ - if (((status >> 8) & 0x3) == 0x2) - return 1; - else - return 0; - } -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return (1); - if (i == bound) - return (0); - } while (1); -} - -#ifdef CFG_3430SDRAM_DDR -/********************************************************************* - * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. - *********************************************************************/ -void config_3430sdram_ddr(void) -{ - /* reset sdrc controller */ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); - __raw_writel(0, SDRC_SYSCONFIG); - - /* setup sdrc to ball mux */ - __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); - - /* set mdcfg */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - - /* set timing */ - __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL); - - /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - delay(5000); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* set mr0 */ - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); - - /* set up dll */ - __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); - delay(0x2000); /* give time to lock */ - -} -#endif // CFG_3430SDRAM_DDR - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(void) -{ - u32 start, cstart, cend, cdiff, val; - - val = __raw_readl(PRM_CLKSRC_CTRL); - /* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~BIT7)) | BIT6; - __raw_writel(val, PRM_CLKSRC_CTRL); - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; - __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ - - /* Enable I and F Clocks for GPT1 */ - val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; - __raw_writel(val, CM_ICLKEN_WKUP); - val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; - __raw_writel(val, CM_FCLKEN_WKUP); - - __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ - /* enable 32kHz source *//* enabled out of reset */ - /* determine sys_clk via gauging */ - - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ - while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ - cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ - while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ - cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - - /* based on number of ticks assign speed */ - if (cdiff > 19000) - return (S38_4M); - else if (cdiff > 15200) - return (S26M); - else if (cdiff > 13000) - return (S24M); - else if (cdiff > 9000) - return (S19_2M); - else if (cdiff > 7600) - return (S13M); - else - return (S12M); -} - -/****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * -- input oscillator clock frequency. - * - *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) -{ - if(osc_clk == S38_4M) - *sys_clkin_sel= 4; - else if(osc_clk == S26M) - *sys_clkin_sel = 3; - else if(osc_clk == S19_2M) - *sys_clkin_sel = 2; - else if(osc_clk == S13M) - *sys_clkin_sel = 1; - else if(osc_clk == S12M) - *sys_clkin_sel = 0; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 osc_clk=0, sys_clkin_sel; - dpll_param *dpll_param_p; - u32 clk_index, sil_index; - - /* Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ - - /* If the input clock is greater than 19.2M always divide/2 */ - if(sys_clkin_sel > 2) { - sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */ - clk_index = sys_clkin_sel/2; - } else { - sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */ - clk_index = sys_clkin_sel; - } - - /* The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - if(cpu_is_3410()) - sil_index = 2; - else { - if(get_cpu_rev() == CPU_3430_ES1) - sil_index = 0; - else if(get_cpu_rev() == CPU_3430_ES2) - sil_index = 1; - } - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address of Core DPLL param table*/ - dpll_param_p = (dpll_param *)get_core_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; - /* CORE DPLL */ - /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ - sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ - sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ - sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to PER DPLL param table*/ - dpll_param_p = (dpll_param *)get_per_dpll_param(); - /* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; - /* PER DPLL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ - sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to MPU DPLL param table*/ - dpll_param_p = (dpll_param *)get_mpu_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; - /* MPU DPLL (unlocked already) */ - sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address to IVA DPLL param table*/ - dpll_param_p = (dpll_param *)get_iva_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; - /* IVA DPLL (set to 12*20=240MHz) */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); - sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ - sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ - sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); - - /* Set up GPTimers to sys_clk source only */ - sr32(CM_CLKSEL_PER, 0, 8, 0xff); - sr32(CM_CLKSEL_WKUP, 0, 1, 1); - - delay(5000); -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock(void) -{ - /* Permission values for registers -Full fledged permissions to all */ - #define UNLOCK_1 0xFFFFFFFF - #define UNLOCK_2 0x00000000 - #define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT)*/ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T*/ - mode = get_device_type(); - if (mode == GP_DEVICE) { - secure_unlock(); - } - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -void s_init(void) -{ - watchdog_init(); -#ifdef CONFIG_3430_AS_3410 - /* setup the scalability control register for - * 3430 to work in 3410 mode - */ - __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP); -#endif - try_unlock_memory(); - set_muxconf_regs(); - delay(100); - prcm_init(); - per_clocks_enable(); - config_3430sdram_ddr(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - return(0); -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is - * either taken care of by ROM (HS/EMU) or not accessible (GP). - * We need to take care of WD2-MPU or take a PRCM reset. WD3 - * should not be running and does not generate a PRCM reset. - */ - sr32(CM_FCLKEN_WKUP, 5, 1, 1); - sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init (void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void per_clocks_enable(void) -{ - /* Enable GP2 timer. */ - sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ - -#ifdef CFG_NS16550 - /* Enable UART1 clocks */ - sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); - sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); -#endif - delay(1000); -} - -/* Set MUX for UART, GPMC, SDRC, GPIO */ - -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\ - MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\ - MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\ - MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ - MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ - MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ - MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ - MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ - MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ - MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ - MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/ - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} - -/********************************************************** - * Routine: nand+_init - * Description: Set up nand for nand and jffs2 commands - *********************************************************/ -int nand_init(void) -{ - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ -#ifdef CFG_NAND - __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ -#endif - - /* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0 - * , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0. - * We configure only GPMC CS0 with required values. Configiring other devices - * at other CS in done in u-boot anyway. So we don't have to bother doing it here. - */ - __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); - delay(1000); - -#ifdef CFG_NAND - __raw_writel( SMNAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel( SMNAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel( SMNAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel( SMNAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel( SMNAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel( SMNAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - -#else /* CFG_ONENAND */ - __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); -#endif - - /* Enable the GPMC Mapping */ - __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((OMAP34XX_GPMC_CS0_MAP>>24) & 0x3F) | - (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); -#if defined(CFG_NAND) - if (nand_chip()){ -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } -#elif defined(CFG_ONENAND) - if (onenand_chip()){ -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } -#endif - return 0; -} - -#ifdef CFG_CMD_FAT -typedef int (mmc_boot_addr) (void); -int mmc_boot(void) -{ - long size, i; - unsigned long offset = CFG_LOADADDR; - unsigned long count; - char buf[12]; - block_dev_desc_t *dev_desc = NULL; - int dev = 0; - int part = 1; - char *ep; - unsigned char ret = 0; - - printf("Starting X-loader on MMC \n"); - - ret = mmc_init(1); - if(ret == 0){ - printf("\n MMC init failed \n"); - return 0; - } - - dev_desc = mmc_get_dev(0); - fat_register_device(dev_desc, 1); - size = file_fat_read("u-boot.bin", (unsigned char *)offset, 0); - if (size == -1) { - return 0; - } - printf("\n%ld Bytes Read from MMC \n", size); - - printf("Starting OS Bootloader from MMC...\n"); - - ((mmc_boot_addr *) CFG_LOADADDR) (); - - return 0; -} -#endif - -/* optionally do something like blinking LED */ -void board_hang (void) -{ while (0) {};} diff --git a/x-loader/board/omap3430sdp/platform.S b/x-loader/board/omap3430sdp/platform.S deleted file mode 100644 index 5869270..0000000 --- a/x-loader/board/omap3430sdp/platform.S +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE,0x07,0x05,0x01 -/* ES2 */ -.word 0x0FA,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D,0x0C,0x03,0x01 -/* ES2 */ -.word 0x1F4,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179,0x12,0x04,0x01 -/* ES2 */ -.word 0x271,0x17,0x03,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D,0x19,0x03,0x01 -/* ES2 */ -.word 0x0FA,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA,0x32,0x03,0x01 -/* ES2 */ -.word 0x271,0x2F,0x03,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D,0x05,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA,0x0C,0x03,0x01 -/* ES2 */ -.word 0x168,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082,0x09,0x07,0x01 -/* ES2 */ -.word 0x0E1,0x0B,0x06,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D,0x0C,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F,0x30,0x03,0x01 -/* ES2 */ -.word 0x0E1,0x17,0x06,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -/* Core DPLL targets for L3 at 166 & L133 */ -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 -/* ES2 */ -.word M_12,N_12,FSEL_12,M2_12 -/* 3410 */ -.word M_12,N_12,FSEL_12,M2_12 - -/* 13MHz */ -/* ES1 */ -.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 -/* ES2 */ -.word M_13,N_13,FSEL_13,M2_13 -/* 3410 */ -.word M_13,N_13,FSEL_13,M2_13 - -/* 19.2MHz */ -/* ES1 */ -.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 -/* ES2 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 -/* 3410 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 - -/* 26MHz */ -/* ES1 */ -.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 -/* ES2 */ -.word M_26,N_26,FSEL_26,M2_26 -/* 3410 */ -.word M_26,N_26,FSEL_26,M2_26 - -/* 38.4MHz */ -/* ES1 */ -.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 -/* ES2 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 -/* 3410 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8,0x05,0x07,0x09 - -/* 13MHz */ -.word 0x1B0,0x0C,0x03,0x09 - -/* 19.2MHz */ -.word 0xE1,0x09,0x07,0x09 - -/* 26MHz */ -.word 0xD8,0x0C,0x07,0x09 - -/* 38.4MHz */ -.word 0xE1,0x13,0x07,0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/omap3430sdp/x-load.lds b/x-loader/board/omap3430sdp/x-load.lds deleted file mode 100644 index 9402f74..0000000 --- a/x-loader/board/omap3430sdp/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * November 2006 - Changed to support 3430sdp device - * Copyright (c) 2004-2006 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/omap3/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/x-loader/board/omap3530beagle/Makefile b/x-loader/board/omap3530beagle/Makefile deleted file mode 100644 index b7b51ce..0000000 --- a/x-loader/board/omap3530beagle/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap3530beagle.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap3530beagle/config.mk b/x-loader/board/omap3530beagle/config.mk deleted file mode 100644 index f271b14..0000000 --- a/x-loader/board/omap3530beagle/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, -# -# Beagle board uses TI OMAP3530 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Beagle has 1 bank of 128MB mPOP-SDRAM on CS0 -# Physical Address: -# 8000'0000 (bank0) - -# For use if you want X-Loader to relocate from SRAM to DDR -#TEXT_BASE = 0x80e80000 - -# For XIP in 64K of SRAM or debug (GP device has it all availabe) -# SRAM 40200000-4020FFFF base -# initial stack at 0x4020fffc used in s_init (below xloader). -# The run time stack is (above xloader, 2k below) -# If any globals exist there needs to be room for them also -TEXT_BASE = 0x40200800 diff --git a/x-loader/board/omap3530beagle/omap3530beagle.c b/x-loader/board/omap3530beagle/omap3530beagle.c deleted file mode 100644 index 073e35a..0000000 --- a/x-loader/board/omap3530beagle/omap3530beagle.c +++ /dev/null @@ -1,1081 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * Jian Zhang - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* params for XM */ -#define CORE_DPLL_PARAM_M2 0x09 -#define CORE_DPLL_PARAM_M 0x360 -#define CORE_DPLL_PARAM_N 0xC - -/* BeagleBoard revisions */ -#define REVISION_AXBX 0x7 -#define REVISION_CX 0x6 -#define REVISION_C4 0x5 -#define REVISION_XM 0x0 - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -typedef struct dpll_param dpll_param; - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param *get_mpu_dpll_param(); -extern dpll_param *get_iva_dpll_param(); -extern dpll_param *get_core_dpll_param(); -extern dpll_param *get_per_dpll_param(); - -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v)) - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -void udelay (unsigned long usecs) { - delay(usecs); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init(void) -{ - return 0; -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return mode >>= 8; -} - -/************************************************ - * get_sysboot_value(void) - return SYS_BOOT[4:0] - ************************************************/ -u32 get_sysboot_value(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK); - return mode; -} - -/************************************************************* - * Routine: get_mem_type(void) - returns the kind of memory connected - * to GPMC that we are trying to boot form. Uses SYS BOOT settings. - *************************************************************/ -u32 get_mem_type(void) -{ - - if (beagle_revision() == REVISION_XM) - return GPMC_NONE; - - u32 mem_type = get_sysboot_value(); - switch (mem_type) { - case 0: - case 2: - case 4: - case 16: - case 22: - return GPMC_ONENAND; - - case 1: - case 12: - case 15: - case 21: - case 27: - return GPMC_NAND; - - case 3: - case 6: - return MMC_ONENAND; - - case 8: - case 11: - case 14: - case 20: - case 26: - return GPMC_MDOC; - - case 17: - case 18: - case 24: - return MMC_NAND; - - case 7: - case 10: - case 13: - case 19: - case 25: - default: - return GPMC_NOR; - } -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 cpuid = 0; - /* On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate - * between ES2.0 and ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); - if ((cpuid & 0xf) == 0x0) - return CPU_3430_ES1; - else - return CPU_3430_ES2; - -} - -/****************************************** - * cpu_is_3410(void) - returns true for 3410 - ******************************************/ -u32 cpu_is_3410(void) -{ - int status; - if (get_cpu_rev() < CPU_3430_ES2) { - return 0; - } else { - /* read scalability status and return 1 for 3410*/ - status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); - /* Check whether MPU frequency is set to 266 MHz which - * is nominal for 3410. If yes return true else false - */ - if (((status >> 8) & 0x3) == 0x2) - return 1; - else - return 0; - } -} - -/****************************************** - * beagle_identify - * Description: Detect if we are running on a Beagle revision Ax/Bx, - * C1/2/3, C4 or D. This can be done by reading - * the level of GPIO173, GPIO172 and GPIO171. This should - * result in - * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx - * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3 - * GPIO173, GPIO172, GPIO171: 1 0 1 => C4 - * GPIO173, GPIO172, GPIO171: 0 0 0 => XM - ******************************************/ -int beagle_revision(void) -{ - int rev; - - omap_request_gpio(171); - omap_request_gpio(172); - omap_request_gpio(173); - omap_set_gpio_direction(171, 1); - omap_set_gpio_direction(172, 1); - omap_set_gpio_direction(173, 1); - - rev = omap_get_gpio_datain(173) << 2 | - omap_get_gpio_datain(172) << 1 | - omap_get_gpio_datain(171); - omap_free_gpio(171); - omap_free_gpio(172); - omap_free_gpio(173); - - return rev; -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return 1; - if (i == bound) - return 0; - } while (1); -} - -#ifdef CFG_3430SDRAM_DDR - -#define MICRON_DDR 0 -#define NUMONYX_MCP 1 -int identify_xm_ddr() -{ - int mfr, id; - - __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((NAND_BASE_ADR>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - nand_readid(&mfr, &id); - if (mfr == 0) - return MICRON_DDR; - if ((mfr == 0x20) && (id == 0xba)) - return NUMONYX_MCP; -} -/********************************************************************* - * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. - *********************************************************************/ -void config_3430sdram_ddr(void) -{ - /* reset sdrc controller */ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); - __raw_writel(0, SDRC_SYSCONFIG); - - /* setup sdrc to ball mux */ - __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); - - switch(beagle_revision()) { - case REVISION_C4: - if (identify_xm_ddr() == NUMONYX_MCP) { - __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1); - __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - } else { - __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - } - break; - case REVISION_XM: - if (identify_xm_ddr() == MICRON_DDR) { - __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1); - } else { - __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1); - __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - } - break; - default: - __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - } - - __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER); - - /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_NOP, SDRC_MANUAL_1); - - delay(5000); - - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); - - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - /* set mr0 */ - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1); - - /* set up dll */ - __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); - delay(0x2000); /* give time to lock */ - -} -#endif /* CFG_3430SDRAM_DDR */ - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(void) -{ - u32 start, cstart, cend, cdiff, cdiv, val; - - val = __raw_readl(PRM_CLKSRC_CTRL); - - if (val & SYSCLKDIV_2) - cdiv = 2; - else - cdiv = 1; - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; - __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ - - /* Enable I and F Clocks for GPT1 */ - val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; - __raw_writel(val, CM_ICLKEN_WKUP); - val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; - __raw_writel(val, CM_FCLKEN_WKUP); - - __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ - /* enable 32kHz source */ - /* enabled out of reset */ - /* determine sys_clk via gauging */ - - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ - while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */ - cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ - while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */ - cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - cdiff *= cdiv; - - /* based on number of ticks assign speed */ - if (cdiff > 19000) - return S38_4M; - else if (cdiff > 15200) - return S26M; - else if (cdiff > 13000) - return S24M; - else if (cdiff > 9000) - return S19_2M; - else if (cdiff > 7600) - return S13M; - else - return S12M; -} - -/****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * -- input oscillator clock frequency. - * - *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) -{ - if (osc_clk == S38_4M) - *sys_clkin_sel = 4; - else if (osc_clk == S26M) - *sys_clkin_sel = 3; - else if (osc_clk == S19_2M) - *sys_clkin_sel = 2; - else if (osc_clk == S13M) - *sys_clkin_sel = 1; - else if (osc_clk == S12M) - *sys_clkin_sel = 0; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 osc_clk = 0, sys_clkin_sel; - dpll_param *dpll_param_p; - u32 clk_index, sil_index; - - /* Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ - - /* If the input clock is greater than 19.2M always divide/2 */ - if (sys_clkin_sel > 2) { - sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */ - clk_index = sys_clkin_sel / 2; - } else { - sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */ - clk_index = sys_clkin_sel; - } - - sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ - - /* The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - sil_index = get_cpu_rev() - 1; - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address of Core DPLL param table */ - dpll_param_p = (dpll_param *) get_core_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - /* CORE DPLL */ - /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); - - /* For 3430 ES1.0 Errata 1.50, default value directly doesnt - work. write another value and then default value. */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ - sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ - sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ - sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to PER DPLL param table */ - dpll_param_p = (dpll_param *) get_per_dpll_param(); - /* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; - /* PER DPLL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - - if (beagle_revision() == REVISION_XM) { - sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */ - } else { - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ - } - - sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to MPU DPLL param table */ - dpll_param_p = (dpll_param *) get_mpu_dpll_param(); - - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - - /* MPU DPLL (unlocked already) */ - sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address to IVA DPLL param table */ - dpll_param_p = (dpll_param *) get_iva_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - /* IVA DPLL (set to 12*20=240MHz) */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); - sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ - sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ - sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); - - /* Set up GPTimers to sys_clk source only */ - sr32(CM_CLKSEL_PER, 0, 8, 0xff); - sr32(CM_CLKSEL_WKUP, 0, 1, 1); - - delay(5000); -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock(void) -{ - /* Permission values for registers -Full fledged permissions to all */ -#define UNLOCK_1 0xFFFFFFFF -#define UNLOCK_2 0x00000000 -#define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT) */ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T */ - mode = get_device_type(); - if (mode == GP_DEVICE) - secure_unlock(); - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -void s_init(void) -{ - watchdog_init(); -#ifdef CONFIG_3430_AS_3410 - /* setup the scalability control register for - * 3430 to work in 3410 mode - */ - __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP); -#endif - try_unlock_memory(); - set_muxconf_regs(); - delay(100); - per_clocks_enable(); - prcm_init(); - config_3430sdram_ddr(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r(void) -{ - int rev; - - rev = beagle_revision(); - switch (rev) { - case REVISION_AXBX: - printf("Beagle Rev Ax/Bx\n"); - break; - case REVISION_CX: - printf("Beagle Rev C1/C2/C3\n"); - break; - case REVISION_C4: - if (identify_xm_ddr() == NUMONYX_MCP) - printf("Beagle Rev C4 from Special Computing\n"); - else - printf("Beagle Rev C4\n"); - break; - case REVISION_XM: - printf("Beagle xM Rev A\n"); - break; - default: - printf("Beagle unknown 0x%02x\n", rev); - } - - return 0; -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is - * either taken care of by ROM (HS/EMU) or not accessible (GP). - * We need to take care of WD2-MPU or take a PRCM reset. WD3 - * should not be running and does not generate a PRCM reset. - */ - sr32(CM_FCLKEN_WKUP, 5, 1, 1); - sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init(void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void per_clocks_enable(void) -{ - /* Enable GP2 timer. */ - sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ - -#ifdef CFG_NS16550 - /* UART1 clocks */ - sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); - sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); - - /* UART 3 Clocks */ - sr32(CM_FCLKEN_PER, 11, 1, 0x1); - sr32(CM_ICLKEN_PER, 11, 1, 0x1); - -#endif - -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - /* Turn on all 3 I2C clocks */ - sr32(CM_FCLKEN1_CORE, 15, 3, 0x7); - sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */ -#endif - - /* Enable the ICLK for 32K Sync Timer as its used in udelay */ - sr32(CM_ICLKEN_WKUP, 2, 1, 0x1); - - sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON); - sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON); - sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON); - sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON); - sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON); - sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON); - sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON); - sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON); - sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON); - sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON); - sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON); - sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON); - - /* Enable GPIO 5 & GPIO 6 clocks */ - sr32(CM_FCLKEN_PER, 17, 2, 0x3); - sr32(CM_ICLKEN_PER, 17, 2, 0x3); - - delay(1000); -} - -/* Set MUX for UART, GPMC, SDRC, GPIO */ - -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*GPMC_nCS6*/\ - MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPIO_61*/\ - MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPIO_65*/\ - MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ - MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ - MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ - MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\ - MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ - MUX_VAL(CP(McSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\ - MUX_VAL(CP(McSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\ - MUX_VAL(CP(McSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\ - MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ - MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ - MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ - MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29 */\ - MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ - MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/ - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} - -/********************************************************** - * Routine: nand+_init - * Description: Set up nand for nand and jffs2 commands - *********************************************************/ - -int nand_init(void) -{ - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ - - /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0. - * We configure only GPMC CS0 with required values. Configiring other devices - * at other CS is done in u-boot. So we don't have to bother doing it here. - */ - __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); - delay(1000); - -#ifdef CFG_NAND_K9F1G08R0A - if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) { - __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((NAND_BASE_ADR>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (nand_chip()) { -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } - } -#endif - -#ifdef CFG_ONENAND - if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) { - __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((ONENAND_BASE>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (onenand_chip()) { -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } - } -#endif - return 0; -} - -#define DEBUG_LED1 149 /* gpio */ -#define DEBUG_LED2 150 /* gpio */ - -void blinkLEDs() -{ - void *p; - - /* Alternately turn the LEDs on and off */ - p = (unsigned long *)OMAP34XX_GPIO5_BASE; - while (1) { - /* turn LED1 on and LED2 off */ - *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED1 % 32); - *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED2 % 32); - - /* delay for a while */ - delay(1000); - - /* turn LED1 off and LED2 on */ - *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED1 % 32); - *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED2 % 32); - - /* delay for a while */ - delay(1000); - } -} - -/* optionally do something like blinking LED */ -void board_hang(void) -{ - while (1) - blinkLEDs(); -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void raise(void) -{ -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void abort(void) -{ -} diff --git a/x-loader/board/omap3530beagle/platform.S b/x-loader/board/omap3530beagle/platform.S deleted file mode 100644 index 5869270..0000000 --- a/x-loader/board/omap3530beagle/platform.S +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE,0x07,0x05,0x01 -/* ES2 */ -.word 0x0FA,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D,0x0C,0x03,0x01 -/* ES2 */ -.word 0x1F4,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179,0x12,0x04,0x01 -/* ES2 */ -.word 0x271,0x17,0x03,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D,0x19,0x03,0x01 -/* ES2 */ -.word 0x0FA,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA,0x32,0x03,0x01 -/* ES2 */ -.word 0x271,0x2F,0x03,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D,0x05,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA,0x0C,0x03,0x01 -/* ES2 */ -.word 0x168,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082,0x09,0x07,0x01 -/* ES2 */ -.word 0x0E1,0x0B,0x06,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D,0x0C,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F,0x30,0x03,0x01 -/* ES2 */ -.word 0x0E1,0x17,0x06,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -/* Core DPLL targets for L3 at 166 & L133 */ -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 -/* ES2 */ -.word M_12,N_12,FSEL_12,M2_12 -/* 3410 */ -.word M_12,N_12,FSEL_12,M2_12 - -/* 13MHz */ -/* ES1 */ -.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 -/* ES2 */ -.word M_13,N_13,FSEL_13,M2_13 -/* 3410 */ -.word M_13,N_13,FSEL_13,M2_13 - -/* 19.2MHz */ -/* ES1 */ -.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 -/* ES2 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 -/* 3410 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 - -/* 26MHz */ -/* ES1 */ -.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 -/* ES2 */ -.word M_26,N_26,FSEL_26,M2_26 -/* 3410 */ -.word M_26,N_26,FSEL_26,M2_26 - -/* 38.4MHz */ -/* ES1 */ -.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 -/* ES2 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 -/* 3410 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8,0x05,0x07,0x09 - -/* 13MHz */ -.word 0x1B0,0x0C,0x03,0x09 - -/* 19.2MHz */ -.word 0xE1,0x09,0x07,0x09 - -/* 26MHz */ -.word 0xD8,0x0C,0x07,0x09 - -/* 38.4MHz */ -.word 0xE1,0x13,0x07,0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/omap3530beagle/platform.S_old b/x-loader/board/omap3530beagle/platform.S_old deleted file mode 100644 index 8368487..0000000 --- a/x-loader/board/omap3530beagle/platform.S_old +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE -.word 0x07 -.word 0x05 -.word 0x01 -/* ES2 */ -.word 0x0FA -.word 0x05 -.word 0x07 -.word 0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D -.word 0x0C -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x1F4 -.word 0x0C -.word 0x03 -.word 0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179 -.word 0x12 -.word 0x04 -.word 0x01 -/* ES2 */ -.word 0x271 -.word 0x17 -.word 0x03 -.word 0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D -.word 0x19 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0FA -.word 0x0C -.word 0x07 -.word 0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA -.word 0x32 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x271 -.word 0x2F -.word 0x03 -.word 0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D -.word 0x05 -.word 0x07 -.word 0x01 -/* ES2 */ -.word 0x0B4 -.word 0x05 -.word 0x07 -.word 0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA -.word 0x0C -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x168 -.word 0x0C -.word 0x03 -.word 0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082 -.word 0x09 -.word 0x07 -.word 0x01 -/* ES2 */ -.word 0x0E1 -.word 0x0B -.word 0x06 -.word 0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D -.word 0x0C -.word 0x07 -.word 0x01 -/* ES2 */ -.word 0x0B4 -.word 0x0C -.word 0x07 -.word 0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F -.word 0x30 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0E1 -.word 0x17 -.word 0x06 -.word 0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x19F -.word 0x0E -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0A6 -.word 0x05 -.word 0x07 -.word 0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x1B2 -.word 0x10 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x14C -.word 0x0C -.word 0x03 -.word 0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x19F -.word 0x17 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x19F -.word 0x17 -.word 0x03 -.word 0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x1B2 -.word 0x21 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0A6 -.word 0x0C -.word 0x07 -.word 0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x19F -.word 0x2F -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x19F -.word 0x2F -.word 0x03 -.word 0x01 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8 -.word 0x05 -.word 0x07 -.word 0x09 - -/* 13MHz */ -.word 0x1B0 -.word 0x0C -.word 0x03 -.word 0x09 - -/* 19.2MHz */ -.word 0xE1 -.word 0x09 -.word 0x07 -.word 0x09 - -/* 26MHz */ -.word 0xD8 -.word 0x0C -.word 0x07 -.word 0x09 - -/* 38.4MHz */ -.word 0xE1 -.word 0x13 -.word 0x07 -.word 0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/omap3530beagle/x-load.lds b/x-loader/board/omap3530beagle/x-load.lds deleted file mode 100644 index 9402f74..0000000 --- a/x-loader/board/omap3530beagle/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * November 2006 - Changed to support 3430sdp device - * Copyright (c) 2004-2006 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/omap3/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/x-loader/board/omap3530gta04/Makefile b/x-loader/board/omap3530gta04/Makefile deleted file mode 100644 index 436d974..0000000 --- a/x-loader/board/omap3530gta04/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap3530gta04.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap3530gta04/config.mk b/x-loader/board/omap3530gta04/config.mk deleted file mode 100644 index 01eafc1..0000000 --- a/x-loader/board/omap3530gta04/config.mk +++ /dev/null @@ -1,23 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, -# -# Beagle board uses TI OMAP3530 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Beagle has 1 bank of 128MB mPOP-SDRAM on CS0 -# Physical Address: -# 8000'0000 (bank0) - -# For use if you want X-Loader to relocate from SRAM to DDR -#TEXT_BASE = 0x80e80000 - -# if you want X-Loader to load to RAM through peripheral boot -#TEXT_BASE = 0x40200000 # for serial loader - -# For XIP in 64K of SRAM or debug (GP device has it all availabe) -# SRAM 40200000-4020FFFF base -# initial stack at 0x4020fffc used in s_init (below xloader). -# The run time stack is (above xloader, 2k below) -# If any globals exist there needs to be room for them also -TEXT_BASE = 0x40208800 diff --git a/x-loader/board/omap3530gta04/omap3530gta04.c b/x-loader/board/omap3530gta04/omap3530gta04.c deleted file mode 100644 index 04f310d..0000000 --- a/x-loader/board/omap3530gta04/omap3530gta04.c +++ /dev/null @@ -1,1279 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * Jian Zhang - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* params for 37XX */ -#define CORE_DPLL_PARAM_M2 0x09 -#define CORE_DPLL_PARAM_M 0x360 -#define CORE_DPLL_PARAM_N 0xC - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -typedef struct dpll_param dpll_param; - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param *get_mpu_dpll_param(void); -extern dpll_param *get_iva_dpll_param(void); -extern dpll_param *get_core_dpll_param(void); -extern dpll_param *get_per_dpll_param(void); - -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v)) - -static char *rev_s[CPU_3XX_MAX_REV] = { - "1.0", - "2.0", - "2.1", - "3.0", - "3.1", - "UNKNOWN", - "UNKNOWN", - "3.1.2"}; - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -void udelay (unsigned long usecs) { - delay(usecs); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init(void) -{ - /* - use code like this to early enable USB charging! - so that the board boots with no battery but USB power - - if i2c does not work at this position, - try to move this code to gta04_revision() - - I2C_SET_BUS(0); - data = 0x01; - i2c_write(0x4B, 0x29, 1, &data, 1); - data = 0x0c; - i2c_write(0x4B, 0x2b, 1, &data, 1); - i2c_read(0x4B, 0x2a, 1, &data, 1); - -*/ - -#if 0 /* no - does not work as expected */ - - /* - For charging using USB, the software must enable the USB automatic - charge by forcing the BOOT_BCI[1] BCIAUTOUSB bit to 1. When the USB - charger is plugged in, the software detects the type of device - (USB charger or carkit charger). The software must set the POWER_CTRL[5] - OTG_EN bit to 1 at least 50 ms before forcing the BCIMFSTS4[2] USBFASTMCHG - bit to 1. - */ - - u8 data; - int i; - - I2C_SET_BUS(0); - - /* enable access to BCIIREF1 */ - data = 0xE7; - i2c_write(0x4A, 0x85, 1, &data, 1); // write BCIMFKEY - - /* set charging current = 852mA */ - data = 0xFF; - i2c_write(0x4A, 0x9B, 1, &data, 1); // write BCIIREF1 - - /* forcing the field BCIAUTOUSB (BOOT_BCI[1]) to 1 */ - i2c_read(0x4B, 0x3D, 1, &data, 1); // read BOOT_BCI - data |= 0x33; // CONFIG_DONE | BCIAUTOWEN | BCIAUTOUSB | BCIAUTOAC - i2c_write(0x4B, 0x3D, 1, &data, 1); // write BOOT_BCI - - /* Enabling interfacing with usb through OCP */ - i2c_read(0x48, 0xFE, 1, &data, 1); // read BOOT_BCI - data |= 0x01; // PHY_DPLL_CLK - i2c_write(0x48, 0xFE, 1, &data, 1); // write BOOT_BCI - - do { - udelay(10); - i2c_read(0x48, 0xFE, 1, &data, 1); // read PHY_CLK_CTRL_STS - } while (!(data & 0x01)); /* loop until PHY DPLL is locked */ - - /* OTG_EN (POWER_CTRL[5]) to 1 */ - data = 0x20; - i2c_write(0x48, 0xAD, 1, &data, 1); // write POWER_CTRL_SET - - for(i=0; i<50; i++) - udelay(1000); - - /* forcing USBFASTMCHG(BCIMFSTS4[2]) to 1 */ - i2c_read(0x4A, 0x84, 1, &data, 1); // read BCIMFSTS4 - data |= 0x04; // USBFASTMCHG - i2c_write(0x4A, 0x84, 1, &data, 1); // write BCIMFSTS4 - -#endif - return 0; -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return mode >>= 8; -} - -/************************************************ - * get_sysboot_value(void) - return SYS_BOOT[4:0] - ************************************************/ -u32 get_sysboot_value(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK); - return mode; -} - -/************************************************************* - * Routine: get_mem_type(void) - returns the kind of memory connected - * to GPMC that we are trying to boot form. Uses SYS BOOT settings. - *************************************************************/ -u32 get_mem_type(void) -{ - u32 mem_type = get_sysboot_value(); - switch (mem_type) { - case 0: - case 2: - case 4: - case 16: - case 22: - return GPMC_ONENAND; - - case 1: - case 12: - case 15: - case 21: - case 27: - return GPMC_NAND; - - case 3: - case 6: - return MMC_ONENAND; - - case 8: - case 11: - case 14: - case 20: - case 26: - return GPMC_MDOC; - - case 17: - case 18: - case 24: - return MMC_NAND; - - case 7: - case 10: - case 13: - case 19: - case 25: - default: - return GPMC_NOR; - } -} - -/****************************************** - * get_cpu_type(void) - extract cpu info - ******************************************/ -u32 get_cpu_type(void) -{ - return __raw_readl(CONTROL_OMAP_STATUS); -} - -/****************************************** - * get_cpu_id(void) - extract cpu id - * returns 0 for ES1.0, cpuid otherwise - ******************************************/ -u32 get_cpu_id(void) -{ - u32 cpuid = 0; - - /* - * On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate between ES1.0 and > ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid)); - if ((cpuid & 0xf) == 0x0) { - return 0; - } else { - /* Decode the IDs on > ES1.0 */ - cpuid = __raw_readl(CONTROL_IDCODE); - } - - return cpuid; -} - -/****************************************** - * get_cpu_family(void) - extract cpu info - ******************************************/ -u32 get_cpu_family(void) -{ - u16 hawkeye; - u32 cpu_family; - u32 cpuid = get_cpu_id(); - - if (cpuid == 0) - return CPU_OMAP34XX; - - hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff; - switch (hawkeye) { - case HAWKEYE_OMAP34XX: - cpu_family = CPU_OMAP34XX; - break; - case HAWKEYE_AM35XX: - cpu_family = CPU_AM35XX; - break; - case HAWKEYE_OMAP36XX: - cpu_family = CPU_OMAP36XX; - break; - default: - cpu_family = CPU_OMAP34XX; - } - - return cpu_family; -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 cpuid = 0; - /* On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate - * between ES2.0 and ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); - if ((cpuid & 0xf) == 0x0) - return CPU_3430_ES1; - else - return CPU_3430_ES2; - -} - -/****************************************** - * Print CPU information - ******************************************/ -int print_cpuinfo (void) -{ - char *cpu_family_s, *cpu_s, *sec_s; - - switch (get_cpu_family()) { - case CPU_OMAP34XX: - cpu_family_s = "OMAP"; - switch (get_cpu_type()) { - case OMAP3503: - cpu_s = "3503"; - break; - case OMAP3515: - cpu_s = "3515"; - break; - case OMAP3525: - cpu_s = "3525"; - break; - case OMAP3530: - cpu_s = "3530"; - break; - default: - cpu_s = "35XX"; - break; - } - break; - case CPU_AM35XX: - cpu_family_s = "AM"; - switch (get_cpu_type()) { - case AM3505: - cpu_s = "3505"; - break; - case AM3517: - cpu_s = "3517"; - break; - default: - cpu_s = "35XX"; - break; - } - break; - case CPU_OMAP36XX: - cpu_family_s = "OMAP"; - switch (get_cpu_type()) { - case OMAP3730: - cpu_s = "3630/3730"; - break; - default: - cpu_s = "36XX/37XX"; - break; - } - break; - default: - cpu_family_s = "OMAP"; - cpu_s = "35XX"; - } - - switch (get_device_type()) { - case TST_DEVICE: - sec_s = "TST"; - break; - case EMU_DEVICE: - sec_s = "EMU"; - break; - case HS_DEVICE: - sec_s = "HS"; - break; - case GP_DEVICE: - sec_s = "GP"; - break; - default: - sec_s = "?"; - } - - printf("%s%s-%s ES%s\n", - cpu_family_s, cpu_s, sec_s, rev_s[get_cpu_rev()]); - - return 0; -} - -/****************************************** - * cpu_is_3410(void) - returns true for 3410 - ******************************************/ -u32 cpu_is_3410(void) -{ - int status; - if (get_cpu_rev() < CPU_3430_ES2) { - return 0; - } else { - /* read scalability status and return 1 for 3410*/ - status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); - /* Check whether MPU frequency is set to 266 MHz which - * is nominal for 3410. If yes return true else false - */ - if (((status >> 8) & 0x3) == 0x2) - return 1; - else - return 0; - } -} - -int gta04_revision(void) -{ - int rev; - static char revision[8] = { /* revision table defined by pull-down R305, R306, R307 */ - 9, - 6, - 7, - 3, - 8, - 4, - 5, - 2 - }; - omap_request_gpio(171); - omap_request_gpio(172); - omap_request_gpio(173); - omap_set_gpio_direction(171, 1); - omap_set_gpio_direction(172, 1); - omap_set_gpio_direction(173, 1); - - rev = omap_get_gpio_datain(173) << 2 | - omap_get_gpio_datain(172) << 1 | - omap_get_gpio_datain(171) << 0; - omap_free_gpio(171); - omap_free_gpio(172); - omap_free_gpio(173); - - return revision[rev]; /* 000 means GTA04A2 */ -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return 1; - if (i == bound) - return 0; - } while (1); -} - -#ifdef CFG_3430SDRAM_DDR - -#define MICRON_DDR 0 -#define NUMONYX_MCP 1 -#define MICRON_MCP 2 - -int identify_xm_ddr(void) -{ -#ifdef CONFIG_NAND - - int mfr, id; - extern int nand_readid(int *mfr, int *id); - - __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((NAND_BASE_ADR>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - nand_readid(&mfr, &id); - if (mfr == 0) - return MICRON_DDR; - if ((mfr == 0x20) && (id == 0xba)) - return NUMONYX_MCP; - if ((mfr == 0x2c) && (id == 0xbc)) - return MICRON_MCP; -#endif - return 0; -} - -/********************************************************************* - * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. - *********************************************************************/ -void config_3430sdram_ddr(void) -{ - /* reset sdrc controller */ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); - __raw_writel(0, SDRC_SYSCONFIG); - - /* setup sdrc to ball mux */ - __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); - - // FIXME: can we not only read the chip maker but also bus clock speed and bank size??? - - switch (identify_xm_ddr()) { - case NUMONYX_MCP: - // should not be used on GTA04 - __raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1); - __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - break; - case MICRON_MCP: - // big Micron - __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1); - break; - case MICRON_DDR: - default: - // small micron - __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - break; - } - - __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER); - - /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_NOP, SDRC_MANUAL_1); - - delay(5000); - - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); - - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - /* set mr0 */ - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1); - - /* set up dll */ - __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); - delay(0x2000); /* give time to lock */ - -} -#endif /* CFG_3430SDRAM_DDR */ - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(void) -{ - u32 start, cstart, cend, cdiff, cdiv, val; - - val = __raw_readl(PRM_CLKSRC_CTRL); - - if (val & SYSCLKDIV_2) - cdiv = 2; - else - cdiv = 1; - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; - __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ - - /* Enable I and F Clocks for GPT1 */ - val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; - __raw_writel(val, CM_ICLKEN_WKUP); - val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; - __raw_writel(val, CM_FCLKEN_WKUP); - - __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ - /* enable 32kHz source */ - /* enabled out of reset */ - /* determine sys_clk via gauging */ - - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ - while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */ - cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ - while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */ - cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - cdiff *= cdiv; - - /* based on number of ticks assign speed */ - if (cdiff > 19000) - return S38_4M; - else if (cdiff > 15200) - return S26M; - else if (cdiff > 13000) - return S24M; - else if (cdiff > 9000) - return S19_2M; - else if (cdiff > 7600) - return S13M; - else - return S12M; -} - -/****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * -- input oscillator clock frequency. - * - *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) -{ - if (osc_clk == S38_4M) - *sys_clkin_sel = 4; - else if (osc_clk == S26M) - *sys_clkin_sel = 3; - else if (osc_clk == S19_2M) - *sys_clkin_sel = 2; - else if (osc_clk == S13M) - *sys_clkin_sel = 1; - else if (osc_clk == S12M) - *sys_clkin_sel = 0; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 osc_clk = 0, sys_clkin_sel; - dpll_param *dpll_param_p; - u32 clk_index, sil_index; - - /* Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ - - /* If the input clock is greater than 19.2M always divide/2 */ - if (sys_clkin_sel > 2) { - sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */ - clk_index = sys_clkin_sel / 2; - } else { - sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */ - clk_index = sys_clkin_sel; - } - - sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ - - /* The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - sil_index = get_cpu_rev() - 1; - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address of Core DPLL param table */ - dpll_param_p = (dpll_param *) get_core_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - /* CORE DPLL */ - /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); - - /* For 3430 ES1.0 Errata 1.50, default value directly doesnt - work. write another value and then default value. */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ - sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ - sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ - sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to PER DPLL param table */ - dpll_param_p = (dpll_param *) get_per_dpll_param(); - /* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; - /* PER DPLL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - - if (get_cpu_family() == CPU_OMAP36XX) { - sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */ - } else { - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ - } - - sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to MPU DPLL param table */ - dpll_param_p = (dpll_param *) get_mpu_dpll_param(); - - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - - /* MPU DPLL (unlocked already) */ - sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address to IVA DPLL param table */ - dpll_param_p = (dpll_param *) get_iva_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - /* IVA DPLL (set to 12*20=240MHz) */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); - sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ - sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ - sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); - - /* Set up GPTimers to sys_clk source only */ - sr32(CM_CLKSEL_PER, 0, 8, 0xff); - sr32(CM_CLKSEL_WKUP, 0, 1, 1); - - delay(5000); -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock(void) -{ - /* Permission values for registers -Full fledged permissions to all */ -#define UNLOCK_1 0xFFFFFFFF -#define UNLOCK_2 0x00000000 -#define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT) */ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T */ - mode = get_device_type(); - if (mode == GP_DEVICE) - secure_unlock(); - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -void s_init(void) -{ - watchdog_init(); -#ifdef CONFIG_3430_AS_3410 - /* setup the scalability control register for - * 3430 to work in 3410 mode - */ - __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP); -#endif - try_unlock_memory(); - set_muxconf_regs(); - delay(100); - per_clocks_enable(); - prcm_init(); - config_3430sdram_ddr(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r(void) -{ - int rev; - print_cpuinfo(); - rev = gta04_revision(); - printf("Board detected: GTA04A%d\n", rev); - switch (identify_xm_ddr()) { - case NUMONYX_MCP: printf("Memory: Numonyx MCP 512MB/bank\n"); break; - case MICRON_MCP: printf("Memory: Micron MCP 256MB/bank\n"); break; - case MICRON_DDR: printf("Memory: Micron DDR 128MB/bank\n"); break; - default: printf("Memory: unknown 128MB/bank\n"); break; - } - return 0; -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is - * either taken care of by ROM (HS/EMU) or not accessible (GP). - * We need to take care of WD2-MPU or take a PRCM reset. WD3 - * should not be running and does not generate a PRCM reset. - */ - sr32(CM_FCLKEN_WKUP, 5, 1, 1); - sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init(void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void per_clocks_enable(void) -{ - /* Enable GP2 timer. */ - sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ - -#ifdef CFG_NS16550 - /* UART1 clocks */ - sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); - sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); - - /* UART 3 Clocks */ - sr32(CM_FCLKEN_PER, 11, 1, 0x1); - sr32(CM_ICLKEN_PER, 11, 1, 0x1); - -#endif - -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - /* Turn on all 3 I2C clocks */ - sr32(CM_FCLKEN1_CORE, 15, 3, 0x7); - sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */ -#endif - - /* Enable the ICLK for 32K Sync Timer as its used in udelay */ - sr32(CM_ICLKEN_WKUP, 2, 1, 0x1); - - sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON); - sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON); - sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON); - sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON); - sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON); - sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON); - sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON); - sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON); - sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON); - sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON); - sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON); - sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON); - - /* Enable GPIO 5 & GPIO 6 clocks */ - sr32(CM_FCLKEN_PER, 17, 2, 0x3); - sr32(CM_ICLKEN_PER, 17, 2, 0x3); - - delay(1000); -} - -/* Set MUX for UART, GPMC, SDRC, GPIO */ - -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ -MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M4)) /*GPMC_nCS6=gpio_57=gpt11_pwm*/\ - MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPIO_61*/\ - MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPIO_65*/\ - MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ - MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ - MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ - MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\ - MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ -MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M4)) /*UART3_CTS_RCTX */\ -MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M4)) /*UART3_RTS_SD */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ - MUX_VAL(CP(McSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\ - MUX_VAL(CP(McSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\ - MUX_VAL(CP(McSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\ - MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M4)) /*GPIO_186*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ -MUX_VAL(CP(ETK_CTL), (IEN | PTU | DIS | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ - MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ - MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29 */\ - MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ - MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/ - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -#if 1 // enable backlight as first boot indication - MUX_VAL(CP(GPMC_nCS6), (IEN | PTU | EN | M4)); /*GPMC_nCS6=gpio_57=gpt11_pwm*/ -#endif -} - -/********************************************************** - * Routine: nand+_init - * Description: Set up nand for nand and jffs2 commands - *********************************************************/ - -int nand_init(void) -{ -#ifdef CONFIG_NAND - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ - - /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0. - * We configure only GPMC CS0 with required values. Configiring other devices - * at other CS is done in u-boot. So we don't have to bother doing it here. - */ - __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); - delay(1000); - -#ifdef CFG_NAND_K9F1G08R0A - if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) { - __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((NAND_BASE_ADR>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (nand_chip()) { -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } - } -#endif - -#ifdef CFG_ONENAND - if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) { - __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((ONENAND_BASE>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (onenand_chip()) { -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } - } -#endif -#endif - return 0; -} - -// 57 for backlight - -#define DEBUG_LED1 149 /* gpio */ -// #define DEBUG_LED2 150 /* gpio */ - -void blinkLEDs(void) -{ - void *p; - - /* Alternately turn the LEDs on and off */ - p = (unsigned long *)OMAP34XX_GPIO5_BASE; - while (1) { - /* turn LED1 on and LED2 off */ - *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED1 % 32); -#ifdef DEBUG_LED2 - *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED2 % 32); -#endif - /* delay for a while */ - delay(1000); - - /* turn LED1 off and LED2 on */ - *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED1 % 32); -#ifdef DEBUG_LED2 - *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED2 % 32); -#endif - /* delay for a while */ - delay(1000); - } -} - -/* optionally do something like blinking LED */ -void board_hang(void) -{ - while (1) - blinkLEDs(); -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void raise(void) -{ -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void abort(void) -{ -} diff --git a/x-loader/board/omap3530gta04/platform.S b/x-loader/board/omap3530gta04/platform.S deleted file mode 100644 index 5869270..0000000 --- a/x-loader/board/omap3530gta04/platform.S +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE,0x07,0x05,0x01 -/* ES2 */ -.word 0x0FA,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D,0x0C,0x03,0x01 -/* ES2 */ -.word 0x1F4,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179,0x12,0x04,0x01 -/* ES2 */ -.word 0x271,0x17,0x03,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D,0x19,0x03,0x01 -/* ES2 */ -.word 0x0FA,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA,0x32,0x03,0x01 -/* ES2 */ -.word 0x271,0x2F,0x03,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D,0x05,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA,0x0C,0x03,0x01 -/* ES2 */ -.word 0x168,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082,0x09,0x07,0x01 -/* ES2 */ -.word 0x0E1,0x0B,0x06,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D,0x0C,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F,0x30,0x03,0x01 -/* ES2 */ -.word 0x0E1,0x17,0x06,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -/* Core DPLL targets for L3 at 166 & L133 */ -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 -/* ES2 */ -.word M_12,N_12,FSEL_12,M2_12 -/* 3410 */ -.word M_12,N_12,FSEL_12,M2_12 - -/* 13MHz */ -/* ES1 */ -.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 -/* ES2 */ -.word M_13,N_13,FSEL_13,M2_13 -/* 3410 */ -.word M_13,N_13,FSEL_13,M2_13 - -/* 19.2MHz */ -/* ES1 */ -.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 -/* ES2 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 -/* 3410 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 - -/* 26MHz */ -/* ES1 */ -.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 -/* ES2 */ -.word M_26,N_26,FSEL_26,M2_26 -/* 3410 */ -.word M_26,N_26,FSEL_26,M2_26 - -/* 38.4MHz */ -/* ES1 */ -.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 -/* ES2 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 -/* 3410 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8,0x05,0x07,0x09 - -/* 13MHz */ -.word 0x1B0,0x0C,0x03,0x09 - -/* 19.2MHz */ -.word 0xE1,0x09,0x07,0x09 - -/* 26MHz */ -.word 0xD8,0x0C,0x07,0x09 - -/* 38.4MHz */ -.word 0xE1,0x13,0x07,0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/omap3evm/Makefile b/x-loader/board/omap3evm/Makefile deleted file mode 100644 index d83f45e..0000000 --- a/x-loader/board/omap3evm/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap3evm.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap3evm/config.mk b/x-loader/board/omap3evm/config.mk deleted file mode 100644 index a45ec22..0000000 --- a/x-loader/board/omap3evm/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# (C) Copyright 2006 -# Texas Instruments, -# -# OMAP3EVM board uses OMAP3430 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments# -# -# OMAP3EVM has 1 bank of 128MB mPOP-SDRAM on CS0 -# Physical Address: -# 8000'0000 (bank0) - -# For use if you want X-Loader to relocate from SRAM to DDR -#TEXT_BASE = 0x80e80000 - -# For XIP in 64K of SRAM or debug (GP device has it all availabe) -# SRAM 40200000-4020FFFF base -# initial stack at 0x4020fffc used in s_init (below xloader). -# The run time stack is (above xloader, 2k below) -# If any globals exist there needs to be room for them also -TEXT_BASE = 0x40200800 diff --git a/x-loader/board/omap3evm/omap3evm.c b/x-loader/board/omap3evm/omap3evm.c deleted file mode 100644 index 16c1f70..0000000 --- a/x-loader/board/omap3evm/omap3evm.c +++ /dev/null @@ -1,814 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * Jian Zhang - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -typedef struct dpll_param dpll_param; - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param * get_mpu_dpll_param(); -extern dpll_param * get_iva_dpll_param(); -extern dpll_param * get_core_dpll_param(); -extern dpll_param * get_per_dpll_param(); - -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -void udelay (unsigned long usecs) { - delay(usecs); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init (void) -{ - return 0; -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return(mode >>= 8); -} - -/************************************************ - * get_sysboot_value(void) - return SYS_BOOT[4:0] - ************************************************/ -u32 get_sysboot_value(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK); - return mode; -} -/************************************************************* - * Routine: get_mem_type(void) - returns the kind of memory connected - * to GPMC that we are trying to boot form. Uses SYS BOOT settings. - *************************************************************/ -u32 get_mem_type(void) -{ - u32 mem_type = get_sysboot_value(); - switch (mem_type){ - case 0: - case 2: - case 4: - case 16: - case 22: return GPMC_ONENAND; - - case 1: - case 12: - case 15: - case 21: - case 27: return GPMC_NAND; - - case 3: - case 6: return MMC_ONENAND; - - case 8: - case 11: - case 14: - case 20: - case 26: return GPMC_MDOC; - - case 17: - case 18: - case 24: return MMC_NAND; - - case 7: - case 10: - case 13: - case 19: - case 25: - default: return GPMC_NOR; - } -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 cpuid=0; - /* On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate - * between ES2.0 and ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); - if((cpuid & 0xf) == 0x0) - return CPU_3430_ES1; - else - return CPU_3430_ES2; - -} - -/****************************************** - * cpu_is_3410(void) - returns true for 3410 - ******************************************/ -u32 cpu_is_3410(void) -{ - int status; - if(get_cpu_rev() < CPU_3430_ES2) { - return 0; - } else { - /* read scalability status and return 1 for 3410*/ - status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); - /* Check whether MPU frequency is set to 266 MHz which - * is nominal for 3410. If yes return true else false - */ - if (((status >> 8) & 0x3) == 0x2) - return 1; - else - return 0; - } -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return (1); - if (i == bound) - return (0); - } while (1); -} - -#ifdef CFG_3430SDRAM_DDR -/********************************************************************* - * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. - *********************************************************************/ -void config_3430sdram_ddr(void) -{ - /* reset sdrc controller */ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); - __raw_writel(0, SDRC_SYSCONFIG); - - /* setup sdrc to ball mux */ - __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); - - /* set mdcfg */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - - /* set timing */ - if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){ - __raw_writel(INFINEON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(INFINEON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - } - if ((get_mem_type() == GPMC_NAND) ||(get_mem_type() == MMC_NAND)){ - __raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); - } - - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER); - - /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - delay(5000); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - - /* set mr0 */ - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); - - /* set up dll */ - __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); - delay(0x2000); /* give time to lock */ - -} -#endif // CFG_3430SDRAM_DDR - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(void) -{ - u32 start, cstart, cend, cdiff, val; - - val = __raw_readl(PRM_CLKSRC_CTRL); - /* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~BIT7)) | BIT6; - __raw_writel(val, PRM_CLKSRC_CTRL); - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; - __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ - - /* Enable I and F Clocks for GPT1 */ - val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; - __raw_writel(val, CM_ICLKEN_WKUP); - val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; - __raw_writel(val, CM_FCLKEN_WKUP); - - __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ - /* enable 32kHz source *//* enabled out of reset */ - /* determine sys_clk via gauging */ - - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ - while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ - cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ - while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ - cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - - /* based on number of ticks assign speed */ - if (cdiff > 19000) - return (S38_4M); - else if (cdiff > 15200) - return (S26M); - else if (cdiff > 13000) - return (S24M); - else if (cdiff > 9000) - return (S19_2M); - else if (cdiff > 7600) - return (S13M); - else - return (S12M); -} - -/****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * -- input oscillator clock frequency. - * - *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) -{ - if(osc_clk == S38_4M) - *sys_clkin_sel= 4; - else if(osc_clk == S26M) - *sys_clkin_sel = 3; - else if(osc_clk == S19_2M) - *sys_clkin_sel = 2; - else if(osc_clk == S13M) - *sys_clkin_sel = 1; - else if(osc_clk == S12M) - *sys_clkin_sel = 0; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 osc_clk=0, sys_clkin_sel; - dpll_param *dpll_param_p; - u32 clk_index, sil_index; - - /* Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ - - /* If the input clock is greater than 19.2M always divide/2 */ - if(sys_clkin_sel > 2) { - sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */ - clk_index = sys_clkin_sel/2; - } else { - sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */ - clk_index = sys_clkin_sel; - } - - /* The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - sil_index = get_cpu_rev() - 1; - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address of Core DPLL param table*/ - dpll_param_p = (dpll_param *)get_core_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 2*clk_index + sil_index; - /* CORE DPLL */ - /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ - sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ - sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ - sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to PER DPLL param table*/ - dpll_param_p = (dpll_param *)get_per_dpll_param(); - /* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; - /* PER DPLL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ - sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to MPU DPLL param table*/ - dpll_param_p = (dpll_param *)get_mpu_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 2*clk_index + sil_index; - /* MPU DPLL (unlocked already) */ - sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address to IVA DPLL param table*/ - dpll_param_p = (dpll_param *)get_iva_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 2*clk_index + sil_index; - /* IVA DPLL (set to 12*20=240MHz) */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); - sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ - sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ - sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); - - /* Set up GPTimers to sys_clk source only */ - sr32(CM_CLKSEL_PER, 0, 8, 0xff); - sr32(CM_CLKSEL_WKUP, 0, 1, 1); - - delay(5000); -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock(void) -{ - /* Permission values for registers -Full fledged permissions to all */ - #define UNLOCK_1 0xFFFFFFFF - #define UNLOCK_2 0x00000000 - #define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT)*/ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T*/ - mode = get_device_type(); - if (mode == GP_DEVICE) { - secure_unlock(); - } - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -void s_init(void) -{ - watchdog_init(); -#ifdef CONFIG_3430_AS_3410 - /* setup the scalability control register for - * 3430 to work in 3410 mode - */ - __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP); -#endif - try_unlock_memory(); - set_muxconf_regs(); - delay(100); - prcm_init(); - per_clocks_enable(); - config_3430sdram_ddr(); -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r (void) -{ - return(0); -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is - * either taken care of by ROM (HS/EMU) or not accessible (GP). - * We need to take care of WD2-MPU or take a PRCM reset. WD3 - * should not be running and does not generate a PRCM reset. - */ - sr32(CM_FCLKEN_WKUP, 5, 1, 1); - sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init (void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void per_clocks_enable(void) -{ - /* Enable GP2 timer. */ - sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ - -#ifdef CFG_NS16550 - /* Enable UART1 clocks */ - sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); - sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); -#endif - delay(1000); -} - -/* Set MUX for UART, GPMC, SDRC, GPIO */ - -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\ - MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\ - MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\ - MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ - MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ - MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ - MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ - MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ - MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ - MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ - MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/ - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} - -/********************************************************** - * Routine: nand+_init - * Description: Set up nand for nand and jffs2 commands - *********************************************************/ - -int nand_init(void) -{ - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ - - /* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0 - * , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0. - * We configure only GPMC CS0 with required values. Configiring other devices - * at other CS in done in u-boot anyway. So we don't have to bother doing it here. - */ - __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); - delay(1000); - - if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)){ - __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((NAND_BASE_ADR>>24) & 0x3F) | - (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (nand_chip()){ -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } - - } - - if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){ - __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((ONENAND_BASE>>24) & 0x3F) | - (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (onenand_chip()){ -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } - } - return 0; -} - -/* optionally do something like blinking LED */ -void board_hang (void) -{ while (0) {};} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void raise(void) -{ -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void abort(void) -{ -} diff --git a/x-loader/board/omap3evm/platform.S b/x-loader/board/omap3evm/platform.S deleted file mode 100644 index 8368487..0000000 --- a/x-loader/board/omap3evm/platform.S +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE -.word 0x07 -.word 0x05 -.word 0x01 -/* ES2 */ -.word 0x0FA -.word 0x05 -.word 0x07 -.word 0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D -.word 0x0C -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x1F4 -.word 0x0C -.word 0x03 -.word 0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179 -.word 0x12 -.word 0x04 -.word 0x01 -/* ES2 */ -.word 0x271 -.word 0x17 -.word 0x03 -.word 0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D -.word 0x19 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0FA -.word 0x0C -.word 0x07 -.word 0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA -.word 0x32 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x271 -.word 0x2F -.word 0x03 -.word 0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D -.word 0x05 -.word 0x07 -.word 0x01 -/* ES2 */ -.word 0x0B4 -.word 0x05 -.word 0x07 -.word 0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA -.word 0x0C -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x168 -.word 0x0C -.word 0x03 -.word 0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082 -.word 0x09 -.word 0x07 -.word 0x01 -/* ES2 */ -.word 0x0E1 -.word 0x0B -.word 0x06 -.word 0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D -.word 0x0C -.word 0x07 -.word 0x01 -/* ES2 */ -.word 0x0B4 -.word 0x0C -.word 0x07 -.word 0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F -.word 0x30 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0E1 -.word 0x17 -.word 0x06 -.word 0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x19F -.word 0x0E -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0A6 -.word 0x05 -.word 0x07 -.word 0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x1B2 -.word 0x10 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x14C -.word 0x0C -.word 0x03 -.word 0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x19F -.word 0x17 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x19F -.word 0x17 -.word 0x03 -.word 0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x1B2 -.word 0x21 -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x0A6 -.word 0x0C -.word 0x07 -.word 0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x19F -.word 0x2F -.word 0x03 -.word 0x01 -/* ES2 */ -.word 0x19F -.word 0x2F -.word 0x03 -.word 0x01 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8 -.word 0x05 -.word 0x07 -.word 0x09 - -/* 13MHz */ -.word 0x1B0 -.word 0x0C -.word 0x03 -.word 0x09 - -/* 19.2MHz */ -.word 0xE1 -.word 0x09 -.word 0x07 -.word 0x09 - -/* 26MHz */ -.word 0xD8 -.word 0x0C -.word 0x07 -.word 0x09 - -/* 38.4MHz */ -.word 0xE1 -.word 0x13 -.word 0x07 -.word 0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/omap3evm/x-load.lds b/x-loader/board/omap3evm/x-load.lds deleted file mode 100644 index 5f352d3..0000000 --- a/x-loader/board/omap3evm/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * November 2006 - Changed to support 3430sdp device - * Copyright (c) 2004-2006 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/omap3/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/x-loader/board/omap4430panda/Makefile b/x-loader/board/omap4430panda/Makefile deleted file mode 100644 index 6b6f9be..0000000 --- a/x-loader/board/omap4430panda/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -# -# (C) Copyright 2009 -# Texas Instruments, -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := omap4430panda.o clock.o syslib.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/omap4430panda/clock.c b/x-loader/board/omap4430panda/clock.c deleted file mode 100644 index 792e5d6..0000000 --- a/x-loader/board/omap4430panda/clock.c +++ /dev/null @@ -1,804 +0,0 @@ -/* - * (C) Copyright 2009 - * Texas Instruments, - * Richard Woodruff - * Rajendra Nayak - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define CONFIG_OMAP4_SDC 1 - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int m2; - unsigned int m3; - unsigned int m4; - unsigned int m5; - unsigned int m6; - unsigned int m7; -}; - -/* Tables having M,N,M2 et al values for different sys_clk speeds - * This table is generated only for OPP100 - * The tables are organized as follows: - * Rows : 1 - 12M, 2 - 13M, 3 - 16.8M, 4 - 19.2M, 5 - 26M, 6 - 27M, 7 - 38.4M - */ - -/* MPU parameters */ -struct dpll_param mpu_dpll_param[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values */ -#ifdef CONFIG_MPU_600 - /* RUN MPU @ 600 MHz */ - {0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, -#elif CONFIG_MPU_1000 - {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, -#else - {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, -#endif -}; - -/* IVA parameters */ -struct dpll_param iva_dpll_param[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values */ -#ifdef CONFIG_OMAP4_SDC - {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}, -#else - {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}, -#endif -}; - -/* CORE parameters */ -struct dpll_param core_dpll_param[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values - DDR@200MHz*/ - {0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05}, -}; - -/* CORE parameters - ES2.1 */ -struct dpll_param core_dpll_param_ddr400[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values - DDR@400MHz*/ - {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}, -}; - -/* CORE parameters for L3 at 190 MHz - For ES1 only*/ -struct dpll_param core_dpll_param_l3_190[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values */ -#ifdef CONFIG_OMAP4_SDC -#ifdef CORE_190MHZ - {0x1f0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}, -#else /* Default CORE @166MHz */ - {0x1b0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}, -#endif -#else - {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x08}, -#endif -}; - -/* PER parameters */ -struct dpll_param per_dpll_param[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values */ -#if 0 - /* SDC settings */ - {0x0a, 0x00, 0x04, 0x03, 0x06, 0x05, 0x02, 0x03}, -#endif - {0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05}, -}; - -/* ABE parameters */ -struct dpll_param abe_dpll_param[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values */ -#ifdef CONFIG_OMAP4_SDC - {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0}, -#else - {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0}, -#endif -}; - -/* USB parameters */ -struct dpll_param usb_dpll_param[7] = { - /* 12M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 13M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 16.8M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 19.2M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 26M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 27M values */ - {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - /* 38.4M values */ -#ifdef CONFIG_OMAP4_SDC - {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, -#else - {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, -#endif -}; - -typedef struct dpll_param dpll_param; - -static void configure_mpu_dpll(u32 clk_index) -{ - dpll_param *dpll_param_p; - - /* Unlock the MPU dpll */ - sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY); - - /* Program MPU DPLL */ - dpll_param_p = &mpu_dpll_param[clk_index]; - - sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */ - - /* Set M,N,M2 values */ - sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param_p->n); - sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M2_DPLL_MPU, 8, 1, 0x1); - - /* Lock the mpu dpll */ - sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_LOCK | 0x10); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_MPU, LDELAY); - - return; -} - -static void configure_iva_dpll(u32 clk_index) -{ - dpll_param *dpll_param_p; - - /* Unlock the IVA dpll */ - sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_IVA, LDELAY); - - /* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */ - sr32(CM_BYPCLK_DPLL_IVA, 0, 2, 0x1); - - /* Program IVA DPLL */ - dpll_param_p = &iva_dpll_param[clk_index]; - - sr32(CM_AUTOIDLE_DPLL_IVA, 0, 3, 0x0); /* Disable DPLL autoidle */ - - /* Set M,N,M4,M5 */ - sr32(CM_CLKSEL_DPLL_IVA, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_IVA, 0, 7, dpll_param_p->n); - sr32(CM_DIV_M4_DPLL_IVA, 0, 5, dpll_param_p->m4); - sr32(CM_DIV_M4_DPLL_IVA, 8, 1, 0x1); - sr32(CM_DIV_M5_DPLL_IVA, 0, 5, dpll_param_p->m5); - sr32(CM_DIV_M5_DPLL_IVA, 8, 1, 0x1); - - /* Lock the iva dpll */ - sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_LOCK); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_IVA, LDELAY); - - return; -} - -static void configure_per_dpll(u32 clk_index) -{ - dpll_param *dpll_param_p; - - /* Unlock the PER dpll */ - sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_PER, LDELAY); - - /* Program PER DPLL */ - dpll_param_p = &per_dpll_param[clk_index]; - - /* Disable autoidle */ - sr32(CM_AUTOIDLE_DPLL_PER, 0, 3, 0x0); - - sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param_p->n); - sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param_p->m3); - sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param_p->m4); - sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param_p->m5); - sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6); - sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7); - -// if(omap_revision() == OMAP4430_ES1_0) -// { - /* Do this only on ES1.0 */ - sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1); - sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1); - sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1); - sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1); - sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1); - sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1); -// } - - /* Lock the per dpll */ - sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_PER, LDELAY); - - return; -} - -static void configure_abe_dpll(u32 clk_index) -{ - dpll_param *dpll_param_p; - - /* Select sys_clk as ref clk for ABE dpll */ - sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0); - - /* Enable slimbus and pad clocks */ - sr32(CM_CLKSEL_ABE, 0, 32, 0x500); - - /* Unlock the ABE dpll */ - sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY); - - /* Program ABE DPLL */ - dpll_param_p = &abe_dpll_param[clk_index]; - - /* Disable autoidle */ - sr32(CM_AUTOIDLE_DPLL_ABE, 0, 3, 0x0); - - sr32(CM_CLKSEL_DPLL_ABE, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_ABE, 0, 6, dpll_param_p->n); - - /* Force DPLL CLKOUTHIF to stay enabled */ - sr32(CM_DIV_M2_DPLL_ABE, 0, 32, 0x500); - sr32(CM_DIV_M2_DPLL_ABE, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M2_DPLL_ABE, 8, 1, 0x1); - /* Force DPLL CLKOUTHIF to stay enabled */ - sr32(CM_DIV_M3_DPLL_ABE, 0, 32, 0x100); - sr32(CM_DIV_M3_DPLL_ABE, 0, 5, dpll_param_p->m3); - sr32(CM_DIV_M3_DPLL_ABE, 8, 1, 0x1); - - /* Lock the abe dpll */ - sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_LOCK); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_ABE, LDELAY); - - return; -} - -static void configure_usb_dpll(u32 clk_index) -{ - dpll_param *dpll_param_p; - - /* Select the 60Mhz clock 480/8 = 60*/ - sr32(CM_CLKSEL_USB_60MHz, 0, 32, 0x1); - - /* Unlock the USB dpll */ - sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_USB, LDELAY); - - /* Program USB DPLL */ - dpll_param_p = &usb_dpll_param[clk_index]; - - /* Disable autoidle */ - sr32(CM_AUTOIDLE_DPLL_USB, 0, 3, 0x0); - - sr32(CM_CLKSEL_DPLL_USB, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_USB, 0, 6, dpll_param_p->n); - - /* Force DPLL CLKOUT to stay active */ - sr32(CM_DIV_M2_DPLL_USB, 0, 32, 0x100); - sr32(CM_DIV_M2_DPLL_USB, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M2_DPLL_USB, 8, 1, 0x1); - sr32(CM_CLKDCOLDO_DPLL_USB, 8, 1, 0x1); - - /* Lock the usb dpll */ - sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_LOCK); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_USB, LDELAY); - - /* force enable the CLKDCOLDO clock */ - sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100); - - return; -} - -static void configure_core_dpll(clk_index) -{ - dpll_param *dpll_param_p; - - /* Get the sysclk speed from cm_sys_clksel - * Set it to 38.4 MHz, in case ROM code is bypassed - */ - if (!clk_index) - return; - - /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */ - sr32(CM_CLKSEL_CORE, 0, 32, 0x110); - - /* Unlock the CORE dpll */ - sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY); - - /* Program Core DPLL */ - if(omap_revision() == OMAP4430_ES1_0) - dpll_param_p = &core_dpll_param_l3_190[clk_index]; - else if(omap_revision() == OMAP4430_ES2_0) - dpll_param_p = &core_dpll_param[clk_index]; - else if(omap_revision() == OMAP4430_ES2_1) - dpll_param_p = &core_dpll_param_ddr400[clk_index]; - - /* Disable autoidle */ - sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0); - - sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n); - sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3); - sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4); - sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5); - sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6); - sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7); - - if(omap_revision() == OMAP4430_ES1_0) - { - /* Do this only on ES1.0 */ - sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); - } - - - /* Lock the core dpll */ - sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); - - return; -} - - -void configure_core_dpll_no_lock(void) -{ - dpll_param *dpll_param_p; - u32 clk_index; - - /* Get the sysclk speed from cm_sys_clksel - * Set it to 38.4 MHz, in case ROM code is bypassed - */ - __raw_writel(0x7,CM_SYS_CLKSEL); - clk_index = 7; - - clk_index = clk_index - 1; - /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */ - sr32(CM_CLKSEL_CORE, 0, 32, 0x110); - - /* Unlock the CORE dpll */ - sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY); - - /* Program Core DPLL */ - if(omap_revision() == OMAP4430_ES1_0) - dpll_param_p = &core_dpll_param_l3_190[clk_index]; - else if(omap_revision() == OMAP4430_ES2_0) - dpll_param_p = &core_dpll_param[clk_index]; - else if(omap_revision() == OMAP4430_ES2_1) - dpll_param_p = &core_dpll_param_ddr400[clk_index]; - - /* Disable autoidle */ - sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0); - - sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m); - sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n); - sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2); - sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3); - sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4); - sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5); - sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6); - sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7); - -// if(omap_revision() == OMAP4430_ES1_0) -// { - /* Do this only on ES1.0 */ - sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); - sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); -// } - - return; -} - -void lock_core_dpll(void) -{ - /* Lock the core dpll */ - sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK); - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); - - return; -} - -void lock_core_dpll_shadow(void) -{ - dpll_param *dpll_param_p; - /* Lock the core dpll using freq update method */ - *(volatile int*)0x4A004120 = 10; //(CM_CLKMODE_DPLL_CORE) - - if(omap_revision() == OMAP4430_ES1_0) - dpll_param_p = &core_dpll_param_l3_190[6]; - else if(omap_revision() == OMAP4430_ES2_0) - dpll_param_p = &core_dpll_param[6]; - else if(omap_revision() == OMAP4430_ES2_1) - dpll_param_p = &core_dpll_param_ddr400[6]; - - /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1, - * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1 - */ - *(volatile int*)0x4A004260 = 0x70D | (dpll_param_p->m2 << 11); - - /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */ - while( ( (*(volatile int*)0x4A004260) & 0x1) == 0x1 ); - - /* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */ - wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); - //lock_core_dpll(); - - return; -} - -static void enable_all_clocks(void) -{ - volatile int regvalue = 0; - - /* Enable Ducati clocks */ - sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1); - sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2); - - wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY); - - /* Enable ivahd and sl2 clocks */ - sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1); - sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1); - sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2); - - wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY); - - /* wait for ivahd to become accessible */ - //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY); - /* wait for sl2 to become accessible */ - //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY); - - /* Enable Tesla clocks */ - sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1); - sr32(DSP_CLKSTCTRL, 0, 32, 0x2); - - wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY); - - /* wait for tesla to become accessible */ - //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY); - - /* TODO: Some hack needed by MM: Clean this */ - #if 0 /* Doesn't work on some Zebu */ - *(volatile int*)0x4a306910 = 0x00000003; - *(volatile int*)0x550809a0 = 0x00000001; - *(volatile int*)0x55080a20 = 0x00000007; - #endif - - /* ABE clocks */ - sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3); - sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY); - sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY); - sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY); - sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY); - sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY); - sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY); - sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY); - sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY); - sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY); - sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY); - sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY); - sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY); - sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY); - /* Disable sleep transitions */ - sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0); - - /* L4PER clocks */ - sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2); - sr32(CM_L4PER_DMTIMER10_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER10_CLKCTRL, LDELAY); - sr32(CM_L4PER_DMTIMER11_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER11_CLKCTRL, LDELAY); - sr32(CM_L4PER_DMTIMER2_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER2_CLKCTRL, LDELAY); - sr32(CM_L4PER_DMTIMER3_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER3_CLKCTRL, LDELAY); - sr32(CM_L4PER_DMTIMER4_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER4_CLKCTRL, LDELAY); - sr32(CM_L4PER_DMTIMER9_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY); - - /* GPIO clocks */ - sr32(CM_L4PER_GPIO2_CLKCTRL, 0 ,32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY); - sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY); - - sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2); - - /* I2C clocks */ - sr32(CM_L4PER_I2C1_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C1_CLKCTRL, LDELAY); - sr32(CM_L4PER_I2C2_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C2_CLKCTRL, LDELAY); - sr32(CM_L4PER_I2C3_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C3_CLKCTRL, LDELAY); - sr32(CM_L4PER_I2C4_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C4_CLKCTRL, LDELAY); - - sr32(CM_L4PER_MCBSP4_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCBSP4_CLKCTRL, LDELAY); - - /* MCSPI clocks */ - sr32(CM_L4PER_MCSPI1_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI1_CLKCTRL, LDELAY); - sr32(CM_L4PER_MCSPI2_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI2_CLKCTRL, LDELAY); - sr32(CM_L4PER_MCSPI3_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI3_CLKCTRL, LDELAY); - sr32(CM_L4PER_MCSPI4_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI4_CLKCTRL, LDELAY); - - /* MMC clocks */ - sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2); - sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC1_CLKCTRL, LDELAY); - sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2); - sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC2_CLKCTRL, LDELAY); - sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY); - sr32(CM_L4PER_MMCSD4_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD4_CLKCTRL, LDELAY); - sr32(CM_L4PER_MMCSD5_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_MMCSD5_CLKCTRL, LDELAY); - - /* UART clocks */ - sr32(CM_L4PER_UART1_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART1_CLKCTRL, LDELAY); - sr32(CM_L4PER_UART2_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART2_CLKCTRL, LDELAY); - sr32(CM_L4PER_UART3_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART3_CLKCTRL, LDELAY); - sr32(CM_L4PER_UART4_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART4_CLKCTRL, LDELAY); - - /* WKUP clocks */ - sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY); - sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002); - wait_on_value(BIT17|BIT16, 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY); - - sr32(CM_WKUP_KEYBOARD_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_WKUP_KEYBOARD_CLKCTRL, LDELAY); - - sr32(CM_SDMA_CLKSTCTRL, 0, 32, 0x0); - sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x3); - sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_1_CLKCTRL, LDELAY); - sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_2_CLKCTRL, LDELAY); - sr32(CM_D2D_CLKSTCTRL, 0, 32, 0x3); - sr32(CM_L3_2_GPMC_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L3_2_GPMC_CLKCTRL, LDELAY); - sr32(CM_L3INSTR_L3_3_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_3_CLKCTRL, LDELAY); - sr32(CM_L3INSTR_L3_INSTR_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_INSTR_CLKCTRL, LDELAY); - sr32(CM_L3INSTR_OCP_WP1_CLKCTRL, 0, 32, 0x1); - wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_OCP_WP1_CLKCTRL, LDELAY); - - /* WDT clocks */ - sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2); - wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY); - - /* Enable Camera clocks */ - sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3); - sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY); - sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY); - sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0); - - /* Enable DSS clocks */ - /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */ - *(volatile int*)0x4A307100 = 0x7; //DSS_PRM - sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2); - sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY); - sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY); - /* Check for DSS Clocks */ - while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00) - /* Set HW_AUTO transition mode */ - sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3); - - /* Enable SGX clocks */ - sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2); - sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY); - /* Check for SGX FCLK and ICLK */ - while ( (*(volatile int*)0x4A009200) != 0x302 ); - //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0); - /* Enable hsi/unipro/usb clocks */ - sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY); - sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY); - sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY); - sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY); - sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1); - //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY); - sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2); - //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY); - /* enable the 32K, 48M optional clocks and enable the module */ - sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301); - //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY); - return; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 clk_index; - - /* Get the sysclk speed from cm_sys_clksel - * Set the CM_SYS_CLKSEL in case ROM code has not set - */ - __raw_writel(0x7,CM_SYS_CLKSEL); - clk_index = readl(CM_SYS_CLKSEL); - if (!clk_index) - return; /* Sys clk uninitialized */ - /* Core DPLL is locked using FREQ update method */ - /* configure_core_dpll(clk_index - 1); */ - - /* Configure all DPLL's at 100% OPP */ - configure_mpu_dpll(clk_index - 1); - configure_iva_dpll(clk_index - 1); - configure_per_dpll(clk_index - 1); - configure_abe_dpll(clk_index - 1); - configure_usb_dpll(clk_index - 1); - -#ifdef CONFIG_OMAP4_SDC - /* Enable all clocks */ - enable_all_clocks(); -#endif - - return; -} diff --git a/x-loader/board/omap4430panda/config.mk b/x-loader/board/omap4430panda/config.mk deleted file mode 100644 index 01173eb..0000000 --- a/x-loader/board/omap4430panda/config.mk +++ /dev/null @@ -1,21 +0,0 @@ -# -# (C) Copyright 2006-2009 -# Texas Instruments, -# -# SDP4430 board uses ARM-CortexA9 cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -TEXT_BASE = 0x40304350 - - -# Handy to get symbols to debug ROM version. -#TEXT_BASE = 0x0 -#TEXT_BASE = 0x08000000 -#TEXT_BASE = 0x04000000 diff --git a/x-loader/board/omap4430panda/omap4430panda.c b/x-loader/board/omap4430panda/omap4430panda.c deleted file mode 100644 index 5695733..0000000 --- a/x-loader/board/omap4430panda/omap4430panda.c +++ /dev/null @@ -1,1235 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) -#include -#endif - -/* EMIF and DMM registers */ -#define EMIF1_BASE 0x4c000000 -#define EMIF2_BASE 0x4d000000 -#define DMM_BASE 0x4e000000 -/* EMIF */ -#define EMIF_MOD_ID_REV 0x0000 -#define EMIF_STATUS 0x0004 -#define EMIF_SDRAM_CONFIG 0x0008 -#define EMIF_LPDDR2_NVM_CONFIG 0x000C -#define EMIF_SDRAM_REF_CTRL 0x0010 -#define EMIF_SDRAM_REF_CTRL_SHDW 0x0014 -#define EMIF_SDRAM_TIM_1 0x0018 -#define EMIF_SDRAM_TIM_1_SHDW 0x001C -#define EMIF_SDRAM_TIM_2 0x0020 -#define EMIF_SDRAM_TIM_2_SHDW 0x0024 -#define EMIF_SDRAM_TIM_3 0x0028 -#define EMIF_SDRAM_TIM_3_SHDW 0x002C -#define EMIF_LPDDR2_NVM_TIM 0x0030 -#define EMIF_LPDDR2_NVM_TIM_SHDW 0x0034 -#define EMIF_PWR_MGMT_CTRL 0x0038 -#define EMIF_PWR_MGMT_CTRL_SHDW 0x003C -#define EMIF_LPDDR2_MODE_REG_DATA 0x0040 -#define EMIF_LPDDR2_MODE_REG_CFG 0x0050 -#define EMIF_L3_CONFIG 0x0054 -#define EMIF_L3_CFG_VAL_1 0x0058 -#define EMIF_L3_CFG_VAL_2 0x005C -#define IODFT_TLGC 0x0060 -#define EMIF_PERF_CNT_1 0x0080 -#define EMIF_PERF_CNT_2 0x0084 -#define EMIF_PERF_CNT_CFG 0x0088 -#define EMIF_PERF_CNT_SEL 0x008C -#define EMIF_PERF_CNT_TIM 0x0090 -#define EMIF_READ_IDLE_CTRL 0x0098 -#define EMIF_READ_IDLE_CTRL_SHDW 0x009c -#define EMIF_ZQ_CONFIG 0x00C8 -#define EMIF_DDR_PHY_CTRL_1 0x00E4 -#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00E8 -#define EMIF_DDR_PHY_CTRL_2 0x00EC - -#define DMM_LISA_MAP_0 0x0040 -#define DMM_LISA_MAP_1 0x0044 -#define DMM_LISA_MAP_2 0x0048 -#define DMM_LISA_MAP_3 0x004C - -#define MR0_ADDR 0 -#define MR1_ADDR 1 -#define MR2_ADDR 2 -#define MR4_ADDR 4 -#define MR10_ADDR 10 -#define MR16_ADDR 16 -#define REF_EN 0x40000000 -/* defines for MR1 */ -#define MR1_BL4 2 -#define MR1_BL8 3 -#define MR1_BL16 4 - -#define MR1_BT_SEQ 0 -#define BT_INT 1 - -#define MR1_WC 0 -#define MR1_NWC 1 - -#define MR1_NWR3 1 -#define MR1_NWR4 2 -#define MR1_NWR5 3 -#define MR1_NWR6 4 -#define MR1_NWR7 5 -#define MR1_NWR8 6 - -#define MR1_VALUE (MR1_NWR3 << 5) | (MR1_WC << 4) | (MR1_BT_SEQ << 3) \ - | (MR1_BL8 << 0) - -/* defines for MR2 */ -#define MR2_RL3_WL1 1 -#define MR2_RL4_WL2 2 -#define MR2_RL5_WL2 3 -#define MR2_RL6_WL3 4 - -/* defines for MR10 */ -#define MR10_ZQINIT 0xFF -#define MR10_ZQRESET 0xC3 -#define MR10_ZQCL 0xAB -#define MR10_ZQCS 0x56 - - -/* TODO: FREQ update method is not working so shadow registers programming - * is just for same of completeness. This would be safer if auto - * trasnitions are working - */ -#define FREQ_UPDATE_EMIF -/* EMIF Needs to be configured@19.2 MHz and shadow registers - * should be programmed for new OPP. - */ -/* Elpida 2x2Gbit */ -#define SDRAM_CONFIG_INIT 0x80800EB1 -#define DDR_PHY_CTRL_1_INIT 0x849FFFF5 -#define READ_IDLE_CTRL 0x000501FF -#define PWR_MGMT_CTRL 0x4000000f -#define PWR_MGMT_CTRL_OPP100 0x4000000f -#define ZQ_CONFIG 0x500b3215 - -#define CS1_MR(mr) ((mr) | 0x80000000) -struct ddr_regs{ - u32 tim1; - u32 tim2; - u32 tim3; - u32 phy_ctrl_1; - u32 ref_ctrl; - u32 config_init; - u32 config_final; - u32 zq_config; - u8 mr1; - u8 mr2; -}; -const struct ddr_regs ddr_regs_380_mhz = { - .tim1 = 0x10cb061a, - .tim2 = 0x20350d52, - .tim3 = 0x00b1431f, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x000005ca, - .config_init = 0x80000eb1, - .config_final = 0x80001ab1, - .zq_config = 0x500b3215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -/* - * Unused timings - but we may need them later - * Keep them commented - */ -#if 0 -const struct ddr_regs ddr_regs_400_mhz = { - .tim1 = 0x10eb065a, - .tim2 = 0x20370dd2, - .tim3 = 0x00b1c33f, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x00000618, - .config_init = 0x80000eb1, - .config_final = 0x80001ab1, - .zq_config = 0x500b3215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -const struct ddr_regs ddr_regs_200_mhz = { - .tim1 = 0x08648309, - .tim2 = 0x101b06ca, - .tim3 = 0x0048a19f, - .phy_ctrl_1 = 0x849FF405, - .ref_ctrl = 0x0000030c, - .config_init = 0x80000eb1, - .config_final = 0x80000eb1, - .zq_config = 0x500b3215, - .mr1 = 0x23, - .mr2 = 0x1 -}; -#endif - -const struct ddr_regs ddr_regs_200_mhz_2cs = { - .tim1 = 0x08648309, - .tim2 = 0x101b06ca, - .tim3 = 0x0048a19f, - .phy_ctrl_1 = 0x849FF405, - .ref_ctrl = 0x0000030c, - .config_init = 0x80000eb9, - .config_final = 0x80000eb9, - .zq_config = 0xD00b3215, - .mr1 = 0x23, - .mr2 = 0x1 -}; - -const struct ddr_regs ddr_regs_400_mhz_2cs = { - /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/ - .tim1 = 0x10eb0662, - .tim2 = 0x20370dd2, - .tim3 = 0x00b1c33f, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x00000618, - .config_init = 0x80000eb9, - .config_final = 0x80001ab9, - .zq_config = 0xD00b3215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b" : "=r" (loops) : "0"(loops)); -} - - -void big_delay(unsigned int count) -{ - int i; - for (i=0; iconfig_init; - - /* PHY control values */ - *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = DDR_PHY_CTRL_1_INIT; - *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1_SHDW)= ddr_regs->phy_ctrl_1; - - /* - * EMIF_READ_IDLE_CTRL - */ - *(volatile int*)(base + EMIF_READ_IDLE_CTRL) = READ_IDLE_CTRL; - *(volatile int*)(base + EMIF_READ_IDLE_CTRL_SHDW) = READ_IDLE_CTRL; - - /* - * EMIF_SDRAM_TIM_1 - */ - *(volatile int*)(base + EMIF_SDRAM_TIM_1) = ddr_regs->tim1; - *(volatile int*)(base + EMIF_SDRAM_TIM_1_SHDW) = ddr_regs->tim1; - - /* - * EMIF_SDRAM_TIM_2 - */ - *(volatile int*)(base + EMIF_SDRAM_TIM_2) = ddr_regs->tim2; - *(volatile int*)(base + EMIF_SDRAM_TIM_2_SHDW) = ddr_regs->tim2; - - /* - * EMIF_SDRAM_TIM_3 - */ - *(volatile int*)(base + EMIF_SDRAM_TIM_3) = ddr_regs->tim3; - *(volatile int*)(base + EMIF_SDRAM_TIM_3_SHDW) = ddr_regs->tim3; - - *(volatile int*)(base + EMIF_ZQ_CONFIG) = ddr_regs->zq_config; - /* - * EMIF_PWR_MGMT_CTRL - */ - //*(volatile int*)(base + EMIF_PWR_MGMT_CTRL) = PWR_MGMT_CTRL; - //*(volatile int*)(base + EMIF_PWR_MGMT_CTRL_SHDW) = PWR_MGMT_CTRL_OPP100; - /* - * poll MR0 register (DAI bit) - * REG_CS[31] = 0 -- Mode register command to CS0 - * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW - * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW - */ - - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = MR0_ADDR; - do { - reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA); - } while ((reg_value & 0x1) != 0); - - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR0_ADDR); - do { - reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA); - } while ((reg_value & 0x1) != 0); - - - /* set MR10 register */ - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR10_ADDR; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR10_ADDR); - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT; - - /* wait for tZQINIT=1us */ - delay(10); - - /* set MR1 register */ - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR1_ADDR; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR1_ADDR); - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1; - - - /* set MR2 register RL=6 for OPP100 */ - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR2_ADDR; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR2_ADDR); - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2; - - /* Set SDRAM CONFIG register again here with final RL-WL value */ - *(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config_final; - *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = ddr_regs->phy_ctrl_1; - - /* - * EMIF_SDRAM_REF_CTRL - * refresh rate = DDR_CLK / reg_refresh_rate - * 3.9 uS = (400MHz) / reg_refresh_rate - */ - *(volatile int*)(base + EMIF_SDRAM_REF_CTRL) = ddr_regs->ref_ctrl; - *(volatile int*)(base + EMIF_SDRAM_REF_CTRL_SHDW) = ddr_regs->ref_ctrl; - - /* set MR16 register */ - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR16_ADDR | REF_EN; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0; - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = - CS1_MR(MR16_ADDR | REF_EN); - *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0; - /* LPDDR2 init complete */ - -} -/***************************************** - * Routine: ddr_init - * Description: Configure DDR - * EMIF1 -- CS0 -- DDR1 (256 MB) - * EMIF2 -- CS0 -- DDR2 (256 MB) - *****************************************/ -static void ddr_init(void) -{ - unsigned int base_addr, rev; - rev = omap_revision(); - - if (rev == OMAP4430_ES1_0) - { - /* Configurte the Control Module DDRIO device */ - __raw_writel(0x1c1c1c1c, 0x4A100638); - __raw_writel(0x1c1c1c1c, 0x4A10063c); - __raw_writel(0x1c1c1c1c, 0x4A100640); - __raw_writel(0x1c1c1c1c, 0x4A100648); - __raw_writel(0x1c1c1c1c, 0x4A10064c); - __raw_writel(0x1c1c1c1c, 0x4A100650); - /* LPDDR2IO set to NMOS PTV */ - __raw_writel(0x00ffc000, 0x4A100704); - } else if (rev == OMAP4430_ES2_0) { - __raw_writel(0x9e9e9e9e, 0x4A100638); - __raw_writel(0x9e9e9e9e, 0x4A10063c); - __raw_writel(0x9e9e9e9e, 0x4A100640); - __raw_writel(0x9e9e9e9e, 0x4A100648); - __raw_writel(0x9e9e9e9e, 0x4A10064c); - __raw_writel(0x9e9e9e9e, 0x4A100650); - /* LPDDR2IO set to NMOS PTV */ - __raw_writel(0x00ffc000, 0x4A100704); - } - - /* - * DMM Configuration - */ - - /* Both EMIFs 128 byte interleaved*/ - if (rev == OMAP4430_ES1_0) - *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80540300; - else - *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80640300; - - /* EMIF2 only at 0x90000000 */ - //*(volatile int*)(DMM_BASE + DMM_LISA_MAP_1) = 0x90400200; - - *(volatile int*)(DMM_BASE + DMM_LISA_MAP_2) = 0x00000000; - *(volatile int*)(DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100; - - /* DDR needs to be initialised @ 19.2 MHz - * So put core DPLL in bypass mode - * Configure the Core DPLL but don't lock it - */ - configure_core_dpll_no_lock(); - - /* No IDLE: BUG in SDC */ - //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); - //while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); - *(volatile int*)(EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; - *(volatile int*)(EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; - - base_addr = EMIF1_BASE; - emif_config(base_addr); - - /* Configure EMIF24D */ - base_addr = EMIF2_BASE; - emif_config(base_addr); - /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */ - lock_core_dpll_shadow(); - /* TODO: SDC needs few hacks to get DDR freq update working */ - - /* Set DLL_OVERRIDE = 0 */ - *(volatile int*)CM_DLL_CTRL = 0x0; - - delay(200); - - /* Check for DDR PHY ready for EMIF1 & EMIF2 */ - while((((*(volatile int*)(EMIF1_BASE + EMIF_STATUS))&(0x04)) != 0x04) \ - || (((*(volatile int*)(EMIF2_BASE + EMIF_STATUS))&(0x04)) != 0x04)); - - /* Reprogram the DDR PYHY Control register */ - /* PHY control values */ - - sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1); - sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1); - - /* Put the Core Subsystem PD to ON State */ - - /* No IDLE: BUG in SDC */ - //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); - //while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); - *(volatile int*)(EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; - *(volatile int*)(EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; - - /* SYSTEM BUG: - * In n a specific situation, the OCP interface between the DMM and - * EMIF may hang. - * 1. A TILER port is used to perform 2D burst writes of - * width 1 and height 8 - * 2. ELLAn port is used to perform reads - * 3. All accesses are routed to the same EMIF controller - * - * Work around to avoid this issue REG_SYS_THRESH_MAX value should - * be kept higher than default 0x7. As per recommondation 0x0A will - * be used for better performance with REG_LL_THRESH_MAX = 0x00 - */ - if (rev == OMAP4430_ES1_0) { - *(volatile int*)(EMIF1_BASE + EMIF_L3_CONFIG) = 0x0A0000FF; - *(volatile int*)(EMIF2_BASE + EMIF_L3_CONFIG) = 0x0A0000FF; - } - - /* - * DMM : DMM_LISA_MAP_0(Section_0) - * [31:24] SYS_ADDR 0x80 - * [22:20] SYS_SIZE 0x7 - 2Gb - * [19:18] SDRC_INTLDMM 0x1 - 128 byte - * [17:16] SDRC_ADDRSPC 0x0 - * [9:8] SDRC_MAP 0x3 - * [7:0] SDRC_ADDR 0X0 - */ - reset_phy(EMIF1_BASE); - reset_phy(EMIF2_BASE); - - *((volatile int *)0x80000000) = 0; - *((volatile int *)0x80000080) = 0; - //*((volatile int *)0x90000000) = 0; -} -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init(void) -{ - return 0; -} - -/************************************************************* - * Routine: get_mem_type(void) - returns the kind of memory connected - * to GPMC that we are trying to boot form. Uses SYS BOOT settings. - *************************************************************/ -u32 get_mem_type(void) -{ - /* no nand, so return GPMC_NONE */ - return GPMC_NONE; -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock_mem(void) -{ - /* Permission values for registers -Full fledged permissions to all */ - #define UNLOCK_1 0xFFFFFFFF - #define UNLOCK_2 0x00000000 - #define UNLOCK_3 0x0000FFFF - - /* Protection Module Register Target APE (PM_RT)*/ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP/EMU(special) type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T*/ - return; -} - - -#if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000) -static scale_vcores(void) -{ - unsigned int rev = omap_revision(); - /* For VC bypass only VCOREx_CGF_FORCE is necessary and - * VCOREx_CFG_VOLTAGE changes can be discarded - */ - /* PRM_VC_CFG_I2C_MODE */ - *(volatile int*)(0x4A307BA8) = 0x0; - /* PRM_VC_CFG_I2C_CLK */ - *(volatile int*)(0x4A307BAC) = 0x6026; - - /* set VCORE1 force VSEL */ - /* PRM_VC_VAL_BYPASS) */ - if(rev == OMAP4430_ES1_0) - *(volatile int*)(0x4A307BA0) = 0x3B5512; - else - *(volatile int*)(0x4A307BA0) = 0x3A5512; - - *(volatile int*)(0x4A307BA0) |= 0x1000000; - while((*(volatile int*)(0x4A307BA0)) & 0x1000000); - - /* PRM_IRQSTATUS_MPU */ - *(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010); - - - /* FIXME: set VCORE2 force VSEL, Check the reset value */ - /* PRM_VC_VAL_BYPASS) */ - if(rev == OMAP4430_ES1_0) - *(volatile int*)(0x4A307BA0) = 0x315B12; - else - *(volatile int*)(0x4A307BA0) = 0x295B12; - *(volatile int*)(0x4A307BA0) |= 0x1000000; - while((*(volatile int*)(0x4A307BA0)) & 0x1000000); - - /* PRM_IRQSTATUS_MPU */ - *(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010); - - /*/set VCORE3 force VSEL */ - /* PRM_VC_VAL_BYPASS */ - if(rev == OMAP4430_ES1_0) - *(volatile int*)(0x4A307BA0) = 0x316112; - else if (rev == OMAP4430_ES2_0) - *(volatile int*)(0x4A307BA0) = 0x296112; - else if (rev == OMAP4430_ES2_1) - *(volatile int*)(0x4A307BA0) = 0x2A6112; - *(volatile int*)(0x4A307BA0) |= 0x1000000; - while((*(volatile int*)(0x4A307BA0)) & 0x1000000); - - /* PRM_IRQSTATUS_MPU */ - *(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010); - -} -#endif - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called path is with SRAM stack. - **********************************************************/ - -void s_init(void) -{ - unsigned int rev = omap_revision(); - - set_muxconf_regs(); - delay(100); - - /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ - /* Currently SMI in Kernel on ES2 devices seems to have an isse - * Once that is resolved, we can postpone this config to kernel - */ - //setup_auxcr(get_device_type(), external_boot); - - ddr_init(); - -/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ -#if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000) - scale_vcores(); -#endif - prcm_init(); - - if(rev != OMAP4430_ES1_0) { - if (__raw_readl(0x4805D138) & (1<<22)) { - sr32(0x4A30a31C, 8, 1, 0x1); /* enable software ioreq */ - sr32(0x4A30a31C, 1, 2, 0x0); /* set for sys_clk (38.4MHz) */ - sr32(0x4A30a31C, 16, 4, 0x1); /* set divisor to 2 */ - sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */ - sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ - } - else { - sr32(0x4A30a314, 8, 1, 0x1); /* enable software ioreq */ - sr32(0x4A30a314, 1, 2, 0x2); /* set for PER_DPLL */ - sr32(0x4A30a314, 16, 4, 0xf); /* set divisor to 16 */ - sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */ - sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ - } - } - -} - -/******************************************************* - * Routine: misc_init_r - * Description: Init ethernet (done here so udelay works) - ********************************************************/ -int misc_init_r(void) -{ - return 0; -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/******************************************************************* - * Routine:ether_init - * Description: take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. - ******************************************************************/ - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init(void) -{ - return 0; -} - -#define OMAP44XX_WKUP_CTRL_BASE 0x4A31E000 -#if 1 -#define M0_SAFE M0 -#define M1_SAFE M1 -#define M2_SAFE M2 -#define M4_SAFE M4 -#define M7_SAFE M7 -#define M3_SAFE M3 -#define M5_SAFE M5 -#define M6_SAFE M6 -#else -#define M0_SAFE M7 -#define M1_SAFE M7 -#define M2_SAFE M7 -#define M4_SAFE M7 -#define M7_SAFE M7 -#define M3_SAFE M7 -#define M5_SAFE M7 -#define M6_SAFE M7 -#endif -#define MV(OFFSET, VALUE)\ - __raw_writew((VALUE), OMAP44XX_CTRL_BASE + (OFFSET)); -#define MV1(OFFSET, VALUE)\ - __raw_writew((VALUE), OMAP44XX_WKUP_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -#define WK(x) (CONTROL_WKUP_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ - -#define MUX_DEFAULT_OMAP4() \ - MV(CP(GPMC_AD0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \ - MV(CP(GPMC_AD1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \ - MV(CP(GPMC_AD2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat2 */ \ - MV(CP(GPMC_AD3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat3 */ \ - MV(CP(GPMC_AD4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat4 */ \ - MV(CP(GPMC_AD5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat5 */ \ - MV(CP(GPMC_AD6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat6 */ \ - MV(CP(GPMC_AD7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat7 */ \ - MV(CP(GPMC_AD8) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_32 */ \ - MV(CP(GPMC_AD9) , ( PTU | IEN | M3)) /* gpio_33 */ \ - MV(CP(GPMC_AD10) , ( PTU | IEN | M3)) /* gpio_34 */ \ - MV(CP(GPMC_AD11) , ( PTU | IEN | M3)) /* gpio_35 */ \ - MV(CP(GPMC_AD12) , ( PTU | IEN | M3)) /* gpio_36 */ \ - MV(CP(GPMC_AD13) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_37 */ \ - MV(CP(GPMC_AD14) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_38 */ \ - MV(CP(GPMC_AD15) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \ - MV(CP(GPMC_A16) , ( M3)) /* gpio_40 */ \ - MV(CP(GPMC_A17) , ( PTD | M3)) /* gpio_41 */ \ - MV(CP(GPMC_A18) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row6 */ \ - MV(CP(GPMC_A19) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \ - MV(CP(GPMC_A20) , ( IEN | M3)) /* gpio_44 */ \ - MV(CP(GPMC_A21) , ( M3)) /* gpio_45 */ \ - MV(CP(GPMC_A22) , ( M3)) /* gpio_46 */ \ - MV(CP(GPMC_A23) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \ - MV(CP(GPMC_A24) , ( PTD | M3)) /* gpio_48 */ \ - MV(CP(GPMC_A25) , ( PTD | M3)) /* gpio_49 */ \ - MV(CP(GPMC_NCS0) , ( M3)) /* gpio_50 */ \ - MV(CP(GPMC_NCS1) , ( IEN | M3)) /* gpio_51 */ \ - MV(CP(GPMC_NCS2) , ( IEN | M3)) /* gpio_52 */ \ - MV(CP(GPMC_NCS3) , ( IEN | M3)) /* gpio_53 */ \ - MV(CP(GPMC_NWP) , ( M3)) /* gpio_54 */ \ - MV(CP(GPMC_CLK) , ( PTD | M3)) /* gpio_55 */ \ - MV(CP(GPMC_NADV_ALE) , ( M3)) /* gpio_56 */ \ - MV(CP(GPMC_NOE) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)) /* sdmmc2_clk */ \ - MV(CP(GPMC_NWE) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_cmd */ \ - MV(CP(GPMC_NBE0_CLE) , ( M3)) /* gpio_59 */ \ - MV(CP(GPMC_NBE1) , ( PTD | M3)) /* gpio_60 */ \ - MV(CP(GPMC_WAIT0) , ( PTU | IEN | M3)) /* gpio_61 */ \ - MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_62 */ \ - MV(CP(C2C_DATA11) , ( PTD | M3)) /* gpio_100 */ \ - MV(CP(C2C_DATA12) , ( PTD | IEN | M3)) /* gpio_101 */ \ - MV(CP(C2C_DATA13) , ( PTD | M3)) /* gpio_102 */ \ - MV(CP(C2C_DATA14) , ( M1)) /* dsi2_te0 */ \ - MV(CP(C2C_DATA15) , ( PTD | M3)) /* gpio_104 */ \ - MV(CP(HDMI_HPD) , ( M0)) /* hdmi_hpd */ \ - MV(CP(HDMI_CEC) , ( M0)) /* hdmi_cec */ \ - MV(CP(HDMI_DDC_SCL) , ( PTU | M0)) /* hdmi_ddc_scl */ \ - MV(CP(HDMI_DDC_SDA) , ( PTU | IEN | M0)) /* hdmi_ddc_sda */ \ - MV(CP(CSI21_DX0) , ( IEN | M0)) /* csi21_dx0 */ \ - MV(CP(CSI21_DY0) , ( IEN | M0)) /* csi21_dy0 */ \ - MV(CP(CSI21_DX1) , ( IEN | M0)) /* csi21_dx1 */ \ - MV(CP(CSI21_DY1) , ( IEN | M0)) /* csi21_dy1 */ \ - MV(CP(CSI21_DX2) , ( IEN | M0)) /* csi21_dx2 */ \ - MV(CP(CSI21_DY2) , ( IEN | M0)) /* csi21_dy2 */ \ - MV(CP(CSI21_DX3) , ( PTD | M7)) /* csi21_dx3 */ \ - MV(CP(CSI21_DY3) , ( PTD | M7)) /* csi21_dy3 */ \ - MV(CP(CSI21_DX4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7)) /* csi21_dx4 */ \ - MV(CP(CSI21_DY4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7)) /* csi21_dy4 */ \ - MV(CP(CSI22_DX0) , ( IEN | M0)) /* csi22_dx0 */ \ - MV(CP(CSI22_DY0) , ( IEN | M0)) /* csi22_dy0 */ \ - MV(CP(CSI22_DX1) , ( IEN | M0)) /* csi22_dx1 */ \ - MV(CP(CSI22_DY1) , ( IEN | M0)) /* csi22_dy1 */ \ - MV(CP(CAM_SHUTTER) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \ - MV(CP(CAM_STROBE) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \ - MV(CP(CAM_GLOBALRESET) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \ - MV(CP(USBB1_ULPITLL_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \ - MV(CP(USBB1_ULPITLL_STP) , ( OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \ - MV(CP(USBB1_ULPITLL_DIR) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \ - MV(CP(USBB1_ULPITLL_NXT) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \ - MV(CP(USBB1_ULPITLL_DAT0) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \ - MV(CP(USBB1_ULPITLL_DAT1) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \ - MV(CP(USBB1_ULPITLL_DAT2) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \ - MV(CP(USBB1_ULPITLL_DAT3) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \ - MV(CP(USBB1_ULPITLL_DAT4) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \ - MV(CP(USBB1_ULPITLL_DAT5) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \ - MV(CP(USBB1_ULPITLL_DAT6) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \ - MV(CP(USBB1_ULPITLL_DAT7) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat7 */ \ - MV(CP(USBB1_HSIC_DATA) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_data */ \ - MV(CP(USBB1_HSIC_STROBE) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_strobe */ \ - MV(CP(USBC1_ICUSB_DP) , ( IEN | M0)) /* usbc1_icusb_dp */ \ - MV(CP(USBC1_ICUSB_DM) , ( IEN | M0)) /* usbc1_icusb_dm */ \ - MV(CP(SDMMC1_CLK) , ( PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc1_clk */ \ - MV(CP(SDMMC1_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_cmd */ \ - MV(CP(SDMMC1_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat0 */ \ - MV(CP(SDMMC1_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat1 */ \ - MV(CP(SDMMC1_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat2 */ \ - MV(CP(SDMMC1_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat3 */ \ - MV(CP(SDMMC1_DAT4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat4 */ \ - MV(CP(SDMMC1_DAT5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat5 */ \ - MV(CP(SDMMC1_DAT6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat6 */ \ - MV(CP(SDMMC1_DAT7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat7 */ \ - MV(CP(ABE_MCBSP2_CLKX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_clkx */ \ - MV(CP(ABE_MCBSP2_DR) , ( IEN | OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dr */ \ - MV(CP(ABE_MCBSP2_DX) , ( OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dx */ \ - MV(CP(ABE_MCBSP2_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_fsx */ \ - MV(CP(ABE_MCBSP1_CLKX) , ( IEN | M1)) /* abe_slimbus1_clock */ \ - MV(CP(ABE_MCBSP1_DR) , ( IEN | M1)) /* abe_slimbus1_data */ \ - MV(CP(ABE_MCBSP1_DX) , ( OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp1_dx */ \ - MV(CP(ABE_MCBSP1_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp1_fsx */ \ - MV(CP(ABE_PDM_UL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_ul_data */ \ - MV(CP(ABE_PDM_DL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_dl_data */ \ - MV(CP(ABE_PDM_FRAME) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_frame */ \ - MV(CP(ABE_PDM_LB_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_lb_clk */ \ - MV(CP(ABE_CLKS) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_clks */ \ - MV(CP(ABE_DMIC_CLK1) , ( M0)) /* abe_dmic_clk1 */ \ - MV(CP(ABE_DMIC_DIN1) , ( IEN | M0)) /* abe_dmic_din1 */ \ - MV(CP(ABE_DMIC_DIN2) , ( IEN | M0)) /* abe_dmic_din2 */ \ - MV(CP(ABE_DMIC_DIN3) , ( IEN | M0)) /* abe_dmic_din3 */ \ - MV(CP(UART2_CTS) , ( PTU | IEN | M0)) /* uart2_cts */ \ - MV(CP(UART2_RTS) , ( M0)) /* uart2_rts */ \ - MV(CP(UART2_RX) , ( PTU | IEN | M0)) /* uart2_rx */ \ - MV(CP(UART2_TX) , ( M0)) /* uart2_tx */ \ - MV(CP(HDQ_SIO) , ( M3)) /* gpio_127 */ \ - MV(CP(I2C1_SCL) , ( PTU | IEN | M0)) /* i2c1_scl */ \ - MV(CP(I2C1_SDA) , ( PTU | IEN | M0)) /* i2c1_sda */ \ - MV(CP(I2C2_SCL) , ( PTU | IEN | M0)) /* i2c2_scl */ \ - MV(CP(I2C2_SDA) , ( PTU | IEN | M0)) /* i2c2_sda */ \ - MV(CP(I2C3_SCL) , ( PTU | IEN | M0)) /* i2c3_scl */ \ - MV(CP(I2C3_SDA) , ( PTU | IEN | M0)) /* i2c3_sda */ \ - MV(CP(I2C4_SCL) , ( PTU | IEN | M0)) /* i2c4_scl */ \ - MV(CP(I2C4_SDA) , ( PTU | IEN | M0)) /* i2c4_sda */ \ - MV(CP(MCSPI1_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_clk */ \ - MV(CP(MCSPI1_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_somi */ \ - MV(CP(MCSPI1_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_simo */ \ - MV(CP(MCSPI1_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_cs0 */ \ - MV(CP(MCSPI1_CS1) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* mcspi1_cs1 */ \ - MV(CP(MCSPI1_CS2) , ( PTU | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_139 */ \ - MV(CP(MCSPI1_CS3) , ( PTU | IEN | M3)) /* gpio_140 */ \ - MV(CP(UART3_CTS_RCTX) , ( PTU | IEN | M0)) /* uart3_tx */ \ - MV(CP(UART3_RTS_SD) , ( M0)) /* uart3_rts_sd */ \ - MV(CP(UART3_RX_IRRX) , ( IEN | M0)) /* uart3_rx */ \ - MV(CP(UART3_TX_IRTX) , ( M0)) /* uart3_tx */ \ - MV(CP(SDMMC5_CLK) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc5_clk */ \ - MV(CP(SDMMC5_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_cmd */ \ - MV(CP(SDMMC5_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat0 */ \ - MV(CP(SDMMC5_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat1 */ \ - MV(CP(SDMMC5_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat2 */ \ - MV(CP(SDMMC5_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat3 */ \ - MV(CP(MCSPI4_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_clk */ \ - MV(CP(MCSPI4_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_simo */ \ - MV(CP(MCSPI4_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_somi */ \ - MV(CP(MCSPI4_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \ - MV(CP(UART4_RX) , ( IEN | M0)) /* uart4_rx */ \ - MV(CP(UART4_TX) , ( M0)) /* uart4_tx */ \ - MV(CP(USBB2_ULPITLL_CLK) , ( IEN | M3)) /* gpio_157 */ \ - MV(CP(USBB2_ULPITLL_STP) , ( IEN | M5)) /* dispc2_data23 */ \ - MV(CP(USBB2_ULPITLL_DIR) , ( IEN | M5)) /* dispc2_data22 */ \ - MV(CP(USBB2_ULPITLL_NXT) , ( IEN | M5)) /* dispc2_data21 */ \ - MV(CP(USBB2_ULPITLL_DAT0) , ( IEN | M5)) /* dispc2_data20 */ \ - MV(CP(USBB2_ULPITLL_DAT1) , ( IEN | M5)) /* dispc2_data19 */ \ - MV(CP(USBB2_ULPITLL_DAT2) , ( IEN | M5)) /* dispc2_data18 */ \ - MV(CP(USBB2_ULPITLL_DAT3) , ( IEN | M5)) /* dispc2_data15 */ \ - MV(CP(USBB2_ULPITLL_DAT4) , ( IEN | M5)) /* dispc2_data14 */ \ - MV(CP(USBB2_ULPITLL_DAT5) , ( IEN | M5)) /* dispc2_data13 */ \ - MV(CP(USBB2_ULPITLL_DAT6) , ( IEN | M5)) /* dispc2_data12 */ \ - MV(CP(USBB2_ULPITLL_DAT7) , ( IEN | M5)) /* dispc2_data11 */ \ - MV(CP(USBB2_HSIC_DATA) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \ - MV(CP(USBB2_HSIC_STROBE) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \ - MV(CP(UNIPRO_TX0) , ( PTD | IEN | M3)) /* gpio_171 */ \ - MV(CP(UNIPRO_TY0) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \ - MV(CP(UNIPRO_TX1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \ - MV(CP(UNIPRO_TY1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \ - MV(CP(UNIPRO_TX2) , ( PTU | IEN | M3)) /* gpio_0 */ \ - MV(CP(UNIPRO_TY2) , ( PTU | IEN | M3)) /* gpio_1 */ \ - MV(CP(UNIPRO_RX0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \ - MV(CP(UNIPRO_RY0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \ - MV(CP(UNIPRO_RX1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \ - MV(CP(UNIPRO_RY1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row3 */ \ - MV(CP(UNIPRO_RX2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row4 */ \ - MV(CP(UNIPRO_RY2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row5 */ \ - MV(CP(USBA0_OTG_CE) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* usba0_otg_ce */ \ - MV(CP(USBA0_OTG_DP) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \ - MV(CP(USBA0_OTG_DM) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \ - MV(CP(FREF_CLK1_OUT) , ( M0)) /* fref_clk1_out */ \ - MV(CP(FREF_CLK2_OUT) , ( PTD | IEN | M3)) /* gpio_182 */ \ - MV(CP(SYS_NIRQ1) , ( PTU | IEN | M0)) /* sys_nirq1 */ \ - MV(CP(SYS_NIRQ2) , ( PTU | IEN | M0)) /* sys_nirq2 */ \ - MV(CP(SYS_BOOT0) , ( PTU | IEN | M3)) /* gpio_184 */ \ - MV(CP(SYS_BOOT1) , ( M3)) /* gpio_185 */ \ - MV(CP(SYS_BOOT2) , ( PTD | IEN | M3)) /* gpio_186 */ \ - MV(CP(SYS_BOOT3) , ( M3)) /* gpio_187 */ \ - MV(CP(SYS_BOOT4) , ( M3)) /* gpio_188 */ \ - MV(CP(SYS_BOOT5) , ( PTD | IEN | M3)) /* gpio_189 */ \ - MV(CP(DPM_EMU0) , ( IEN | M0)) /* dpm_emu0 */ \ - MV(CP(DPM_EMU1) , ( IEN | M0)) /* dpm_emu1 */ \ - MV(CP(DPM_EMU2) , ( IEN | M0)) /* dpm_emu2 */ \ - MV(CP(DPM_EMU3) , ( IEN | M5)) /* dispc2_data10 */ \ - MV(CP(DPM_EMU4) , ( IEN | M5)) /* dispc2_data9 */ \ - MV(CP(DPM_EMU5) , ( IEN | M5)) /* dispc2_data16 */ \ - MV(CP(DPM_EMU6) , ( IEN | M5)) /* dispc2_data17 */ \ - MV(CP(DPM_EMU7) , ( IEN | M5)) /* dispc2_hsync */ \ - MV(CP(DPM_EMU8) , ( IEN | M5)) /* dispc2_pclk */ \ - MV(CP(DPM_EMU9) , ( IEN | M5)) /* dispc2_vsync */ \ - MV(CP(DPM_EMU10) , ( IEN | M5)) /* dispc2_de */ \ - MV(CP(DPM_EMU11) , ( IEN | M5)) /* dispc2_data8 */ \ - MV(CP(DPM_EMU12) , ( IEN | M5)) /* dispc2_data7 */ \ - MV(CP(DPM_EMU13) , ( IEN | M5)) /* dispc2_data6 */ \ - MV(CP(DPM_EMU14) , ( IEN | M5)) /* dispc2_data5 */ \ - MV(CP(DPM_EMU15) , ( IEN | M5)) /* dispc2_data4 */ \ - MV(CP(DPM_EMU16) , ( M3)) /* gpio_27 */ \ - MV(CP(DPM_EMU17) , ( IEN | M5)) /* dispc2_data2 */ \ - MV(CP(DPM_EMU18) , ( IEN | M5)) /* dispc2_data1 */ \ - MV(CP(DPM_EMU19) , ( IEN | M5)) /* dispc2_data0 */ \ - MV1(WK(PAD0_SIM_IO) , ( IEN | M0)) /* sim_io */ \ - MV1(WK(PAD1_SIM_CLK) , ( M0)) /* sim_clk */ \ - MV1(WK(PAD0_SIM_RESET) , ( M0)) /* sim_reset */ \ - MV1(WK(PAD1_SIM_CD) , ( PTU | IEN | M0)) /* sim_cd */ \ - MV1(WK(PAD0_SIM_PWRCTRL) , ( M0)) /* sim_pwrctrl */ \ - MV1(WK(PAD1_SR_SCL) , ( PTU | IEN | M0)) /* sr_scl */ \ - MV1(WK(PAD0_SR_SDA) , ( PTU | IEN | M0)) /* sr_sda */ \ - MV1(WK(PAD1_FREF_XTAL_IN) , ( M0)) /* # */ \ - MV1(WK(PAD0_FREF_SLICER_IN) , ( M0)) /* fref_slicer_in */ \ - MV1(WK(PAD1_FREF_CLK_IOREQ) , ( M0)) /* fref_clk_ioreq */ \ - MV1(WK(PAD0_FREF_CLK0_OUT) , ( M2)) /* sys_drm_msecure */ \ - MV1(WK(PAD1_FREF_CLK3_REQ) , ( PTU | IEN | M0)) /* # */ \ - MV1(WK(PAD0_FREF_CLK3_OUT) , ( M0)) /* fref_clk3_out */ \ - MV1(WK(PAD1_FREF_CLK4_REQ) , ( PTU | IEN | M0)) /* # */ \ - MV1(WK(PAD0_FREF_CLK4_OUT) , ( M0)) /* # */ \ - MV1(WK(PAD1_SYS_32K) , ( IEN | M0)) /* sys_32k */ \ - MV1(WK(PAD0_SYS_NRESPWRON) , ( M0)) /* sys_nrespwron */ \ - MV1(WK(PAD1_SYS_NRESWARM) , ( M0)) /* sys_nreswarm */ \ - MV1(WK(PAD0_SYS_PWR_REQ) , ( PTU | M0)) /* sys_pwr_req */ \ - MV1(WK(PAD1_SYS_PWRON_RESET) , ( M3)) /* gpio_wk29 */ \ - MV1(WK(PAD0_SYS_BOOT6) , ( IEN | M3)) /* gpio_wk9 */ \ - MV1(WK(PAD1_SYS_BOOT7) , ( IEN | M3)) /* gpio_wk10 */ \ - MV1(WK(PAD1_FREF_CLK3_REQ), (M3)) /* gpio_wk30 */ \ - MV1(WK(PAD1_FREF_CLK4_REQ), (M3)) /* gpio_wk7 */ \ - MV1(WK(PAD0_FREF_CLK4_OUT), (M3)) /* gpio_wk8 */ - -#define MUX_DEFAULT_OMAP4_ALL() \ - MV(CP(GPMC_AD0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \ - MV(CP(GPMC_AD1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \ - MV(CP(GPMC_AD2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat2 */ \ - MV(CP(GPMC_AD3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat3 */ \ - MV(CP(GPMC_AD4), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat4 */ \ - MV(CP(GPMC_AD5), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat5 */ \ - MV(CP(GPMC_AD6), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat6 */ \ - MV(CP(GPMC_AD7), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat7 */ \ - MV(CP(GPMC_AD8), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_32 */ \ - MV(CP(GPMC_AD9), (M3_SAFE)) /* gpio_33 */ \ - MV(CP(GPMC_AD10), (M3_SAFE)) /* gpio_34 */ \ - MV(CP(GPMC_AD11), (M3_SAFE)) /* gpio_35 */ \ - MV(CP(GPMC_AD12), (M3_SAFE)) /* gpio_36 */ \ - MV(CP(GPMC_AD13), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_37 */ \ - MV(CP(GPMC_AD14), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_38 */ \ - MV(CP(GPMC_AD15), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \ - MV(CP(GPMC_A16), (M3_SAFE)) /* gpio_40 */ \ - MV(CP(GPMC_A17), (M3_SAFE)) /* gpio_41 */ \ - MV(CP(GPMC_A18), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row6 */ \ - MV(CP(GPMC_A19), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \ - MV(CP(GPMC_A20), (M3_SAFE)) /* gpio_44 */ \ - MV(CP(GPMC_A21), (M3_SAFE)) /* gpio_45 */ \ - MV(CP(GPMC_A22), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col6 */ \ - MV(CP(GPMC_A23), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \ - MV(CP(GPMC_A24), (M3_SAFE)) /* gpio_48 */ \ - MV(CP(GPMC_A25), (M3_SAFE)) /* gpio_49 */ \ - MV(CP(GPMC_NCS0), (M0)) /* gpmc_ncs0 */ \ - MV(CP(GPMC_NCS1), (M3_SAFE)) /* gpio_51 */ \ - MV(CP(GPMC_NCS2), (M3_SAFE)) /* gpio_52 */ \ - MV(CP(GPMC_NCS3), (M3_SAFE)) /* gpio_53 */ \ - MV(CP(GPMC_NWP), (M0_SAFE)) /* gpmc_nwp */ \ - MV(CP(GPMC_CLK), (M3_SAFE)) /* gpio_55 */ \ - MV(CP(GPMC_NADV_ALE), (M0)) /* gpmc_nadv_ale */ \ - MV(CP(GPMC_NOE), (PTU | OFF_EN | OFF_OUT_PTD | M1)) /* sdmmc2_clk */ \ - MV(CP(GPMC_NWE), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_cmd */ \ - MV(CP(GPMC_NBE0_CLE), (M0)) /* gpmc_nbe0_cle*/ \ - MV(CP(GPMC_NBE1), (M3_SAFE)) /* gpio_60 */ \ - MV(CP(GPMC_WAIT0), (M0)) /* gpmc_wait */ \ - MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \ - MV(CP(C2C_DATA11), (M3_SAFE)) /* gpio_100 */ \ - MV(CP(C2C_DATA12), (M1_SAFE)) /* dsi1_te0 */ \ - MV(CP(C2C_DATA13), (M3_SAFE)) /* gpio_102 */ \ - MV(CP(C2C_DATA14), (M1_SAFE)) /* dsi2_te0 */ \ - MV(CP(C2C_DATA15), (M3_SAFE)) /* gpio_104 */ \ - MV(CP(HDMI_HPD), (M0_SAFE)) /* hdmi_hpd */ \ - MV(CP(HDMI_CEC), (M0_SAFE)) /* hdmi_cec */ \ - MV(CP(HDMI_DDC_SCL), (M0_SAFE)) /* hdmi_ddc_scl */ \ - MV(CP(HDMI_DDC_SDA), (M0_SAFE)) /* hdmi_ddc_sda */ \ - MV(CP(CSI21_DX0), (M0_SAFE)) /* csi21_dx0 */ \ - MV(CP(CSI21_DY0), (M0_SAFE)) /* csi21_dy0 */ \ - MV(CP(CSI21_DX1), (M0_SAFE)) /* csi21_dx1 */ \ - MV(CP(CSI21_DY1), (M0_SAFE)) /* csi21_dy1 */ \ - MV(CP(CSI21_DX2), (M0_SAFE)) /* csi21_dx2 */ \ - MV(CP(CSI21_DY2), (M0_SAFE)) /* csi21_dy2 */ \ - MV(CP(CSI21_DX3), (M0_SAFE)) /* csi21_dx3 */ \ - MV(CP(CSI21_DY3), (M0_SAFE)) /* csi21_dy3 */ \ - MV(CP(CSI21_DX4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_75 */ \ - MV(CP(CSI21_DY4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_76 */ \ - MV(CP(CSI22_DX0), (M0_SAFE)) /* csi22_dx0 */ \ - MV(CP(CSI22_DY0), (M0_SAFE)) /* csi22_dy0 */ \ - MV(CP(CSI22_DX1), (M0_SAFE)) /* csi22_dx1 */ \ - MV(CP(CSI22_DY1), (M0_SAFE)) /* csi22_dy1 */ \ - MV(CP(CAM_SHUTTER), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \ - MV(CP(CAM_STROBE), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \ - MV(CP(CAM_GLOBALRESET), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \ - MV(CP(USBB1_ULPITLL_CLK), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \ - MV(CP(USBB1_ULPITLL_STP), (PTU | OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \ - MV(CP(USBB1_ULPITLL_DIR), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \ - MV(CP(USBB1_ULPITLL_NXT), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \ - MV(CP(USBB1_ULPITLL_DAT0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \ - MV(CP(USBB1_ULPITLL_DAT1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \ - MV(CP(USBB1_ULPITLL_DAT2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \ - MV(CP(USBB1_ULPITLL_DAT3), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \ - MV(CP(USBB1_ULPITLL_DAT4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \ - MV(CP(USBB1_ULPITLL_DAT5), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \ - MV(CP(USBB1_ULPITLL_DAT6), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \ - MV(CP(USBB1_ULPITLL_DAT7), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat7 */ \ - MV(CP(USBB1_HSIC_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_data */ \ - MV(CP(USBB1_HSIC_STROBE), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_strobe */ \ - MV(CP(USBC1_ICUSB_DP), (M0_SAFE)) /* usbc1_icusb_dp */ \ - MV(CP(USBC1_ICUSB_DM), (M0_SAFE)) /* usbc1_icusb_dm */ \ - MV(CP(SDMMC1_CLK), (PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc1_clk */ \ - MV(CP(SDMMC1_CMD), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_cmd */ \ - MV(CP(SDMMC1_DAT0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat0 */ \ - MV(CP(SDMMC1_DAT1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat1 */ \ - MV(CP(SDMMC1_DAT2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat2 */ \ - MV(CP(SDMMC1_DAT3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat3 */ \ - MV(CP(SDMMC1_DAT4), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat4 */ \ - MV(CP(SDMMC1_DAT5), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat5 */ \ - MV(CP(SDMMC1_DAT6), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat6 */ \ - MV(CP(SDMMC1_DAT7), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat7 */ \ - MV(CP(ABE_MCBSP2_CLKX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_clkx */ \ - MV(CP(ABE_MCBSP2_DR), (IEN | OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dr */ \ - MV(CP(ABE_MCBSP2_DX), (OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dx */ \ - MV(CP(ABE_MCBSP2_FSX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_fsx */ \ - MV(CP(ABE_MCBSP1_CLKX), (M1_SAFE)) /* abe_slimbus1_clock */ \ - MV(CP(ABE_MCBSP1_DR), (M1_SAFE)) /* abe_slimbus1_data */ \ - MV(CP(ABE_MCBSP1_DX), (OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp1_dx */ \ - MV(CP(ABE_MCBSP1_FSX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp1_fsx */ \ - MV(CP(ABE_PDM_UL_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_ul_data */ \ - MV(CP(ABE_PDM_DL_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_dl_data */ \ - MV(CP(ABE_PDM_FRAME), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_frame */ \ - MV(CP(ABE_PDM_LB_CLK), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_lb_clk */ \ - MV(CP(ABE_CLKS), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_clks */ \ - MV(CP(ABE_DMIC_CLK1), (M0_SAFE)) /* abe_dmic_clk1 */ \ - MV(CP(ABE_DMIC_DIN1), (M0_SAFE)) /* abe_dmic_din1 */ \ - MV(CP(ABE_DMIC_DIN2), (M0_SAFE)) /* abe_dmic_din2 */ \ - MV(CP(ABE_DMIC_DIN3), (M0_SAFE)) /* abe_dmic_din3 */ \ - MV(CP(UART2_CTS), (PTU | IEN | M0)) /* uart2_cts */ \ - MV(CP(UART2_RTS), (M0)) /* uart2_rts */ \ - MV(CP(UART2_RX), (PTU | IEN | M0)) /* uart2_rx */ \ - MV(CP(UART2_TX), (M0)) /* uart2_tx */ \ - MV(CP(HDQ_SIO), (M3_SAFE)) /* gpio_127 */ \ - MV(CP(I2C1_SCL), (PTU | IEN | M0)) /* i2c1_scl */ \ - MV(CP(I2C1_SDA), (PTU | IEN | M0)) /* i2c1_sda */ \ - MV(CP(I2C2_SCL), (PTU | IEN | M0)) /* i2c2_scl */ \ - MV(CP(I2C2_SDA), (PTU | IEN | M0)) /* i2c2_sda */ \ - MV(CP(I2C3_SCL), (PTU | IEN | M0)) /* i2c3_scl */ \ - MV(CP(I2C3_SDA), (PTU | IEN | M0)) /* i2c3_sda */ \ - MV(CP(I2C4_SCL), (PTU | IEN | M0)) /* i2c4_scl */ \ - MV(CP(I2C4_SDA), (PTU | IEN | M0)) /* i2c4_sda */ \ - MV(CP(MCSPI1_CLK), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_clk */ \ - MV(CP(MCSPI1_SOMI), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_somi */ \ - MV(CP(MCSPI1_SIMO), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_simo */ \ - MV(CP(MCSPI1_CS0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_cs0 */ \ - MV(CP(MCSPI1_CS1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* mcspi1_cs1 */ \ - MV(CP(MCSPI1_CS2), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_139 */ \ - MV(CP(MCSPI1_CS3), (M3_SAFE)) /* gpio_140 */ \ - MV(CP(UART3_CTS_RCTX), (PTU | IEN | M0)) /* uart3_tx */ \ - MV(CP(UART3_RTS_SD), (M0)) /* uart3_rts_sd */ \ - MV(CP(UART3_RX_IRRX), (IEN | M0)) /* uart3_rx */ \ - MV(CP(UART3_TX_IRTX), (M0)) /* uart3_tx */ \ - MV(CP(SDMMC5_CLK), (PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc5_clk */ \ - MV(CP(SDMMC5_CMD), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_cmd */ \ - MV(CP(SDMMC5_DAT0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat0 */ \ - MV(CP(SDMMC5_DAT1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat1 */ \ - MV(CP(SDMMC5_DAT2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat2 */ \ - MV(CP(SDMMC5_DAT3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat3 */ \ - MV(CP(MCSPI4_CLK), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_clk */ \ - MV(CP(MCSPI4_SIMO), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_simo */ \ - MV(CP(MCSPI4_SOMI), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_somi */ \ - MV(CP(MCSPI4_CS0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \ - MV(CP(UART4_RX), (IEN | M0)) /* uart4_rx */ \ - MV(CP(UART4_TX), (M0)) /* uart4_tx */ \ - MV(CP(USBB2_ULPITLL_CLK), (M3)) /* gpio_157 */ \ - MV(CP(USBB2_ULPITLL_STP), (M5)) /* dispc2_data23 */ \ - MV(CP(USBB2_ULPITLL_DIR), (M5)) /* dispc2_data22 */ \ - MV(CP(USBB2_ULPITLL_NXT), (M5)) /* dispc2_data21 */ \ - MV(CP(USBB2_ULPITLL_DAT0), (M5)) /* dispc2_data20 */ \ - MV(CP(USBB2_ULPITLL_DAT1), (M5)) /* dispc2_data19 */ \ - MV(CP(USBB2_ULPITLL_DAT2), (M5)) /* dispc2_data18 */ \ - MV(CP(USBB2_ULPITLL_DAT3), (M5)) /* dispc2_data15 */ \ - MV(CP(USBB2_ULPITLL_DAT4), (M5)) /* dispc2_data14 */ \ - MV(CP(USBB2_ULPITLL_DAT5), (M5)) /* dispc2_data13 */ \ - MV(CP(USBB2_ULPITLL_DAT6), (M5)) /* dispc2_data12 */ \ - MV(CP(USBB2_ULPITLL_DAT7), (M5)) /* dispc2_data11 */ \ - MV(CP(USBB2_HSIC_DATA), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \ - MV(CP(USBB2_HSIC_STROBE), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \ - MV(CP(UNIPRO_TX0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col0 */ \ - MV(CP(UNIPRO_TY0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \ - MV(CP(UNIPRO_TX1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \ - MV(CP(UNIPRO_TY1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \ - MV(CP(UNIPRO_TX2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_0 */ \ - MV(CP(UNIPRO_TY2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_1 */ \ - MV(CP(UNIPRO_RX0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \ - MV(CP(UNIPRO_RY0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \ - MV(CP(UNIPRO_RX1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \ - MV(CP(UNIPRO_RY1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row3 */ \ - MV(CP(UNIPRO_RX2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row4 */ \ - MV(CP(UNIPRO_RY2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row5 */ \ - MV(CP(USBA0_OTG_CE), (PTU | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* usba0_otg_ce */ \ - MV(CP(USBA0_OTG_DP), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \ - MV(CP(USBA0_OTG_DM), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \ - MV(CP(FREF_CLK1_OUT), (M0_SAFE)) /* fref_clk1_out */ \ - MV(CP(FREF_CLK2_OUT), (M0_SAFE)) /* fref_clk2_out */ \ - MV(CP(SYS_NIRQ1), (PTU | IEN | M0)) /* sys_nirq1 */ \ - MV(CP(SYS_NIRQ2), (PTU | IEN | M0)) /* sys_nirq2 */ \ - MV(CP(SYS_BOOT0), (M3_SAFE)) /* gpio_184 */ \ - MV(CP(SYS_BOOT1), (M3_SAFE)) /* gpio_185 */ \ - MV(CP(SYS_BOOT2), (M3_SAFE)) /* gpio_186 */ \ - MV(CP(SYS_BOOT3), (M3_SAFE)) /* gpio_187 */ \ - MV(CP(SYS_BOOT4), (M3_SAFE)) /* gpio_188 */ \ - MV(CP(SYS_BOOT5), (M3_SAFE)) /* gpio_189 */ \ - MV(CP(DPM_EMU0), (M0_SAFE)) /* dpm_emu0 */ \ - MV(CP(DPM_EMU1), (M0_SAFE)) /* dpm_emu1 */ \ - MV(CP(DPM_EMU2), (M0_SAFE)) /* dpm_emu2 */ \ - MV(CP(DPM_EMU3), (M5)) /* dispc2_data10 */ \ - MV(CP(DPM_EMU4), (M5)) /* dispc2_data9 */ \ - MV(CP(DPM_EMU5), (M5)) /* dispc2_data16 */ \ - MV(CP(DPM_EMU6), (M5)) /* dispc2_data17 */ \ - MV(CP(DPM_EMU7), (M5)) /* dispc2_hsync */ \ - MV(CP(DPM_EMU8), (M5)) /* dispc2_pclk */ \ - MV(CP(DPM_EMU9), (M5)) /* dispc2_vsync */ \ - MV(CP(DPM_EMU10), (M5)) /* dispc2_de */ \ - MV(CP(DPM_EMU11), (M5)) /* dispc2_data8 */ \ - MV(CP(DPM_EMU12), (M5)) /* dispc2_data7 */ \ - MV(CP(DPM_EMU13), (M5)) /* dispc2_data6 */ \ - MV(CP(DPM_EMU14), (M5)) /* dispc2_data5 */ \ - MV(CP(DPM_EMU15), (M5)) /* dispc2_data4 */ \ - MV(CP(DPM_EMU16), (M5)) /* dispc2_data3/dmtimer8_pwm_evt */ \ - MV(CP(DPM_EMU17), (M5)) /* dispc2_data2 */ \ - MV(CP(DPM_EMU18), (M5)) /* dispc2_data1 */ \ - MV(CP(DPM_EMU19), (M5)) /* dispc2_data0 */ \ - MV1(WK(PAD0_SIM_IO), (M0_SAFE)) /* sim_io */ \ - MV1(WK(PAD1_SIM_CLK), (M0_SAFE)) /* sim_clk */ \ - MV1(WK(PAD0_SIM_RESET), (M0_SAFE)) /* sim_reset */ \ - MV1(WK(PAD1_SIM_CD), (M0_SAFE)) /* sim_cd */ \ - MV1(WK(PAD0_SIM_PWRCTRL), (M0_SAFE)) /* sim_pwrctrl */ \ - MV1(WK(PAD1_SR_SCL), (PTU | IEN | M0)) /* sr_scl */ \ - MV1(WK(PAD0_SR_SDA), (PTU | IEN | M0)) /* sr_sda */ \ - MV1(WK(PAD1_FREF_XTAL_IN), (M0_SAFE)) /* # */ \ - MV1(WK(PAD0_FREF_SLICER_IN), (M0_SAFE)) /* fref_slicer_in */ \ - MV1(WK(PAD1_FREF_CLK_IOREQ), (M0_SAFE)) /* fref_clk_ioreq */ \ - MV1(WK(PAD0_FREF_CLK0_OUT), (M0)) /* sys_drm_msecure */ \ - MV1(WK(PAD1_FREF_CLK3_REQ), (M0)) /* # */ \ - MV1(WK(PAD0_FREF_CLK3_OUT), (M0_SAFE)) /* fref_clk3_out */ \ - MV1(WK(PAD1_FREF_CLK4_REQ), (M0_SAFE)) /* # */ \ - MV1(WK(PAD0_FREF_CLK4_OUT), (M0_SAFE)) /* # */ \ - MV1(WK(PAD1_SYS_32K), (IEN | M0_SAFE)) /* sys_32k */ \ - MV1(WK(PAD0_SYS_NRESPWRON), (IEN | M0_SAFE)) /* sys_nrespwron */ \ - MV1(WK(PAD1_SYS_NRESWARM), (IEN | M0_SAFE)) /* sys_nreswarm */ \ - MV1(WK(PAD0_SYS_PWR_REQ), (M0_SAFE)) /* sys_pwr_req */ \ - MV1(WK(PAD1_SYS_PWRON_RESET), (M3_SAFE)) /* gpio_wk29 */ \ - MV1(WK(PAD0_SYS_BOOT6), (M3_SAFE)) /* gpio_wk9 */ \ - MV1(WK(PAD1_SYS_BOOT7), (M3_SAFE)) /* gpio_wk10 */ \ - MV1(WK(PAD1_JTAG_TCK), (IEN | M0)) /* jtag_tck */ \ - MV1(WK(PAD0_JTAG_RTCK), (M0)) /* jtag_rtck */ \ - MV1(WK(PAD1_JTAG_TMS_TMSC), (IEN | M0)) /* jtag_tms_tmsc */ \ - MV1(WK(PAD0_JTAG_TDI), (IEN | M0)) /* jtag_tdi */ \ - MV1(WK(PAD1_JTAG_TDO), (M0)) /* jtag_tdo */ - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT_OMAP4(); - return; -} - -/****************************************************************************** - * Routine: update_mux() - * Description:Update balls which are different between boards. All should be - * updated to match functionality. However, I'm only updating ones - * which I'll be using for now. When power comes into play they - * all need updating. - *****************************************************************************/ -void update_mux(u32 btype, u32 mtype) -{ - /* REVISIT */ - return; - -} - -/* optionally do something like blinking LED */ -void board_hang (void) -{ while (0) {};} - -int nand_init(void) -{ - return 0; -} -void reset_phy(unsigned int base) -{ - *(volatile int*)(base + IODFT_TLGC) |= (1 << 10); -} diff --git a/x-loader/board/omap4430panda/syslib.c b/x-loader/board/omap4430panda/syslib.c deleted file mode 100644 index 2b16cc4..0000000 --- a/x-loader/board/omap4430panda/syslib.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/************************************************************ - * sdelay() - simple spin loop. Will be constant time as - * its generally used in bypass conditions only. This - * is necessary until timers are accessible. - * - * not inline to increase chances its in cache when called - *************************************************************/ -void sdelay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return (1); - if (i == bound) - return (0); - } while (1); -} - diff --git a/x-loader/board/overo/Makefile b/x-loader/board/overo/Makefile deleted file mode 100644 index 32f9bf1..0000000 --- a/x-loader/board/overo/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := overo.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/board/overo/config.mk b/x-loader/board/overo/config.mk deleted file mode 100644 index 7ee3014..0000000 --- a/x-loader/board/overo/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, -# -# Overo board uses TI OMAP35xx (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Overo has 1 bank of 128MB mPOP-SDRAM on CS0 -# Physical Address: -# 8000'0000 (bank0) - -# For use if you want X-Loader to relocate from SRAM to DDR -#TEXT_BASE = 0x80e80000 - -# For XIP in 64K of SRAM or debug (GP device has it all availabe) -# SRAM 40200000-4020FFFF base -# initial stack at 0x4020fffc used in s_init (below xloader). -# The run time stack is (above xloader, 2k below) -# If any globals exist there needs to be room for them also -TEXT_BASE = 0x40200800 diff --git a/x-loader/board/overo/overo.c b/x-loader/board/overo/overo.c deleted file mode 100644 index 8df53e5..0000000 --- a/x-loader/board/overo/overo.c +++ /dev/null @@ -1,1148 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * Jian Zhang - * Richard Woodruff - * - * Modified for overo - * Steve Sakoman - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* params for 37XX */ -#define CORE_DPLL_PARAM_M2 0x09 -#define CORE_DPLL_PARAM_M 0x360 -#define CORE_DPLL_PARAM_N 0xC - -/* Used to index into DPLL parameter tables */ -struct dpll_param { - unsigned int m; - unsigned int n; - unsigned int fsel; - unsigned int m2; -}; - -typedef struct dpll_param dpll_param; - -/* Following functions are exported from lowlevel_init.S */ -extern dpll_param *get_mpu_dpll_param(); -extern dpll_param *get_iva_dpll_param(); -extern dpll_param *get_core_dpll_param(); -extern dpll_param *get_per_dpll_param(); - -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v)) - -static char *rev_s[CPU_3XX_MAX_REV] = { - "1.0", - "2.0", - "2.1", - "3.0", - "3.1", - "UNKNOWN", - "UNKNOWN", - "3.1.2"}; - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - -void udelay (unsigned long usecs) { - delay(usecs); -} - -/***************************************** - * Routine: board_init - * Description: Early hardware init. - *****************************************/ -int board_init(void) -{ - return 0; -} - -/************************************************************* - * get_device_type(): tell if GP/HS/EMU/TST - *************************************************************/ -u32 get_device_type(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); - return mode >>= 8; -} - -/************************************************ - * get_sysboot_value(void) - return SYS_BOOT[4:0] - ************************************************/ -u32 get_sysboot_value(void) -{ - int mode; - mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK); - return mode; -} - -/************************************************************* - * Routine: get_mem_type(void) - returns the kind of memory connected - * to GPMC that we are trying to boot form. Uses SYS BOOT settings. - *************************************************************/ -u32 get_mem_type(void) -{ - u32 mem_type = get_sysboot_value(); - - switch (mem_type) { - case 0: - case 2: - case 4: - case 16: - case 22: - return GPMC_ONENAND; - - case 1: - case 12: - case 15: - case 21: - case 27: - return GPMC_NAND; - - case 3: - case 6: - return MMC_ONENAND; - - case 8: - case 11: - case 14: - case 20: - case 26: - return GPMC_MDOC; - - case 17: - case 18: - case 24: - return MMC_NAND; - - case 7: - case 10: - case 13: - case 19: - case 25: - default: - return GPMC_NOR; - } -} - -/****************************************** - * get_cpu_type(void) - extract cpu info - ******************************************/ -u32 get_cpu_type(void) -{ - return __raw_readl(CONTROL_OMAP_STATUS); -} - -/****************************************** - * get_cpu_id(void) - extract cpu id - * returns 0 for ES1.0, cpuid otherwise - ******************************************/ -u32 get_cpu_id(void) -{ - u32 cpuid = 0; - - /* - * On ES1.0 the IDCODE register is not exposed on L4 - * so using CPU ID to differentiate between ES1.0 and > ES1.0. - */ - __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid)); - if ((cpuid & 0xf) == 0x0) { - return 0; - } else { - /* Decode the IDs on > ES1.0 */ - cpuid = __raw_readl(CONTROL_IDCODE); - } - - return cpuid; -} - -/****************************************** - * get_cpu_family(void) - extract cpu info - ******************************************/ -u32 get_cpu_family(void) -{ - u16 hawkeye; - u32 cpu_family; - u32 cpuid = get_cpu_id(); - - if (cpuid == 0) - return CPU_OMAP34XX; - - hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff; - switch (hawkeye) { - case HAWKEYE_OMAP34XX: - cpu_family = CPU_OMAP34XX; - break; - case HAWKEYE_AM35XX: - cpu_family = CPU_AM35XX; - break; - case HAWKEYE_OMAP36XX: - cpu_family = CPU_OMAP36XX; - break; - default: - cpu_family = CPU_OMAP34XX; - } - - return cpu_family; -} - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - u32 cpuid = get_cpu_id(); - - if (cpuid == 0) - return CPU_3XX_ES10; - else - return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf; -} - -/****************************************** - * Print CPU information - ******************************************/ -int print_cpuinfo (void) -{ - char *cpu_family_s, *cpu_s, *sec_s; - - switch (get_cpu_family()) { - case CPU_OMAP34XX: - cpu_family_s = "OMAP"; - switch (get_cpu_type()) { - case OMAP3503: - cpu_s = "3503"; - break; - case OMAP3515: - cpu_s = "3515"; - break; - case OMAP3525: - cpu_s = "3525"; - break; - case OMAP3530: - cpu_s = "3530"; - break; - default: - cpu_s = "35XX"; - break; - } - break; - case CPU_AM35XX: - cpu_family_s = "AM"; - switch (get_cpu_type()) { - case AM3505: - cpu_s = "3505"; - break; - case AM3517: - cpu_s = "3517"; - break; - default: - cpu_s = "35XX"; - break; - } - break; - case CPU_OMAP36XX: - cpu_family_s = "OMAP"; - switch (get_cpu_type()) { - case OMAP3730: - cpu_s = "3630/3730"; - break; - default: - cpu_s = "36XX/37XX"; - break; - } - break; - default: - cpu_family_s = "OMAP"; - cpu_s = "35XX"; - } - - switch (get_device_type()) { - case TST_DEVICE: - sec_s = "TST"; - break; - case EMU_DEVICE: - sec_s = "EMU"; - break; - case HS_DEVICE: - sec_s = "HS"; - break; - case GP_DEVICE: - sec_s = "GP"; - break; - default: - sec_s = "?"; - } - - printf("%s%s-%s ES%s\n", - cpu_family_s, cpu_s, sec_s, rev_s[get_cpu_rev()]); - - return 0; -} - -/****************************************** - * cpu_is_3410(void) - returns true for 3410 - ******************************************/ -u32 cpu_is_3410(void) -{ - int status; - if (get_cpu_rev() < CPU_3430_ES2) { - return 0; - } else { - /* read scalability status and return 1 for 3410*/ - status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); - /* Check whether MPU frequency is set to 266 MHz which - * is nominal for 3410. If yes return true else false - */ - if (((status >> 8) & 0x3) == 0x2) - return 1; - else - return 0; - } -} - -/***************************************************************** - * Routine: get_board_revision - * Description: Returns the board revision - *****************************************************************/ -int get_board_revision(void) -{ - int revision; - unsigned char data; - - /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */ - /* these boards should return a revision number of 0 */ - /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */ - data = 0x01; - i2c_write(0x4B, 0x29, 1, &data, 1); - data = 0x0c; - i2c_write(0x4B, 0x2b, 1, &data, 1); - i2c_read(0x4B, 0x2a, 1, &data, 1); - - if (!omap_request_gpio(112) && - !omap_request_gpio(113) && - !omap_request_gpio(115)) { - - omap_set_gpio_direction(112, 1); - omap_set_gpio_direction(113, 1); - omap_set_gpio_direction(115, 1); - - revision = omap_get_gpio_datain(115) << 2 | - omap_get_gpio_datain(113) << 1 | - omap_get_gpio_datain(112); - - omap_free_gpio(112); - omap_free_gpio(113); - omap_free_gpio(115); - } else { - printf("Error: unable to acquire board revision GPIOs\n"); - revision = -1; - } - - return revision; -} - -/***************************************************************** - * sr32 - clear & set a value in a bit range for a 32 bit address - *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) -{ - u32 tmp, msk = 0; - msk = 1 << num_bits; - --msk; - tmp = __raw_readl(addr) & ~(msk << start_bit); - tmp |= value << start_bit; - __raw_writel(tmp, addr); -} - -/********************************************************************* - * wait_on_value() - common routine to allow waiting for changes in - * volatile regs. - *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) -{ - u32 i = 0, val; - do { - ++i; - val = __raw_readl(read_addr) & read_bit_mask; - if (val == match_value) - return 1; - if (i == bound) - return 0; - } while (1); -} - -#ifdef CFG_3430SDRAM_DDR -/********************************************************************* - * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. - *********************************************************************/ -void config_3430sdram_ddr(void) -{ - /* reset sdrc controller */ - __raw_writel(SOFTRESET, SDRC_SYSCONFIG); - wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); - __raw_writel(0, SDRC_SYSCONFIG); - - /* setup sdrc to ball mux */ - __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); - - switch (get_board_revision()) { - case 0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ - __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - break; - case 1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - break; - case 2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_1); - __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - break; - default: - __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */ - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); - __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0); - __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1); - __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0); - __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1); - } - - __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER); - - /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ - __raw_writel(CMD_NOP, SDRC_MANUAL_0); - __raw_writel(CMD_NOP, SDRC_MANUAL_1); - - delay(5000); - - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); - __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); - - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); - __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); - - /* set mr0 */ - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); - __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1); - - /* set up dll */ - __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); - delay(0x2000); /* give time to lock */ -} -#endif /* CFG_3430SDRAM_DDR */ - -/************************************************************* - * get_sys_clk_speed - determine reference oscillator speed - * based on known 32kHz clock and gptimer. - *************************************************************/ -u32 get_osc_clk_speed(void) -{ - u32 start, cstart, cend, cdiff, cdiv, val; - - val = __raw_readl(PRM_CLKSRC_CTRL); - - if (val & SYSCLKDIV_2) - cdiv = 2; - else - cdiv = 1; - - /* enable timer2 */ - val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; - __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ - - /* Enable I and F Clocks for GPT1 */ - val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; - __raw_writel(val, CM_ICLKEN_WKUP); - val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; - __raw_writel(val, CM_FCLKEN_WKUP); - - __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ - __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ - /* enable 32kHz source */ - /* enabled out of reset */ - /* determine sys_clk via gauging */ - - start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ - while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ - cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ - while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ - cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ - cdiff = cend - cstart; /* get elapsed ticks */ - cdiff *= cdiv; - - /* based on number of ticks assign speed */ - if (cdiff > 19000) - return S38_4M; - else if (cdiff > 15200) - return S26M; - else if (cdiff > 13000) - return S24M; - else if (cdiff > 9000) - return S19_2M; - else if (cdiff > 7600) - return S13M; - else - return S12M; -} - -/****************************************************************************** - * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on - * -- input oscillator clock frequency. - * - *****************************************************************************/ -void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) -{ - if (osc_clk == S38_4M) - *sys_clkin_sel = 4; - else if (osc_clk == S26M) - *sys_clkin_sel = 3; - else if (osc_clk == S19_2M) - *sys_clkin_sel = 2; - else if (osc_clk == S13M) - *sys_clkin_sel = 1; - else if (osc_clk == S12M) - *sys_clkin_sel = 0; -} - -/****************************************************************************** - * prcm_init() - inits clocks for PRCM as defined in clocks.h - * -- called from SRAM, or Flash (using temp SRAM stack). - *****************************************************************************/ -void prcm_init(void) -{ - u32 osc_clk = 0, sys_clkin_sel; - dpll_param *dpll_param_p; - u32 clk_index, sil_index; - - /* Gauge the input clock speed and find out the sys_clkin_sel - * value corresponding to the input clock. - */ - osc_clk = get_osc_clk_speed(); - get_sys_clkin_sel(osc_clk, &sys_clkin_sel); - - sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ - - /* If the input clock is greater than 19.2M always divide/2 */ - if (sys_clkin_sel > 2) { - sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */ - clk_index = sys_clkin_sel / 2; - } else { - sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */ - clk_index = sys_clkin_sel; - } - - sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ - - /* The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - sil_index = get_cpu_rev() - 1; - - /* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address of Core DPLL param table */ - dpll_param_p = (dpll_param *) get_core_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - /* CORE DPLL */ - /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); - - /* For 3430 ES1.0 Errata 1.50, default value directly doesnt - work. write another value and then default value. */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ - sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ - sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ - sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to PER DPLL param table */ - dpll_param_p = (dpll_param *) get_per_dpll_param(); - /* Moving it to the right sysclk base */ - dpll_param_p = dpll_param_p + clk_index; - /* PER DPLL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - - if (get_cpu_family() == CPU_OMAP36XX) { - sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */ - } else { - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ - } - - sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); - - /* Getting the base address to MPU DPLL param table */ - dpll_param_p = (dpll_param *) get_mpu_dpll_param(); - - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - - /* MPU DPLL (unlocked already) */ - sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); - - /* Getting the base address to IVA DPLL param table */ - dpll_param_p = (dpll_param *) get_iva_dpll_param(); - /* Moving it to the right sysclk and ES rev base */ - dpll_param_p = dpll_param_p + 3 * clk_index + sil_index; - /* IVA DPLL (set to 12*20=240MHz) */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); - sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ - sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ - sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); - - /* Set up GPTimers to sys_clk source only */ - sr32(CM_CLKSEL_PER, 0, 8, 0xff); - sr32(CM_CLKSEL_WKUP, 0, 1, 1); - - delay(5000); -} - -/***************************************** - * Routine: secure_unlock - * Description: Setup security registers for access - * (GP Device only) - *****************************************/ -void secure_unlock(void) -{ - /* Permission values for registers -Full fledged permissions to all */ - #define UNLOCK_1 0xFFFFFFFF - #define UNLOCK_2 0x00000000 - #define UNLOCK_3 0x0000FFFF - /* Protection Module Register Target APE (PM_RT)*/ - __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); - __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); - __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); - - __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); - __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); - - /* IVA Changes */ - __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); - __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); - - __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ -} - -/********************************************************** - * Routine: try_unlock_sram() - * Description: If chip is GP type, unlock the SRAM for - * general use. - ***********************************************************/ -void try_unlock_memory(void) -{ - int mode; - - /* if GP device unlock device SRAM for general use */ - /* secure code breaks for Secure/Emulation device - HS/E/T*/ - mode = get_device_type(); - if (mode == GP_DEVICE) - secure_unlock(); - return; -} - -/********************************************************** - * Routine: s_init - * Description: Does early system init of muxing and clocks. - * - Called at time when only stack is available. - **********************************************************/ - -void s_init(void) -{ - watchdog_init(); -#ifdef CONFIG_3430_AS_3410 - /* setup the scalability control register for - * 3430 to work in 3410 mode - */ - __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP); -#endif - try_unlock_memory(); - set_muxconf_regs(); - delay(100); - prcm_init(); - per_clocks_enable(); - config_3430sdram_ddr(); -} - -/******************************************************* - * Routine: misc_init_r - ********************************************************/ -int misc_init_r(void) -{ - print_cpuinfo(); - printf("Board revision: %d\n", get_board_revision()); - return 0; -} - -/****************************************************** - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - ******************************************************/ -void wait_for_command_complete(unsigned int wd_base) -{ - int pending = 1; - do { - pending = __raw_readl(wd_base + WWPS); - } while (pending); -} - -/**************************************** - * Routine: watchdog_init - * Description: Shut down watch dogs - *****************************************/ -void watchdog_init(void) -{ - /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is - * either taken care of by ROM (HS/EMU) or not accessible (GP). - * We need to take care of WD2-MPU or take a PRCM reset. WD3 - * should not be running and does not generate a PRCM reset. - */ - sr32(CM_FCLKEN_WKUP, 5, 1, 1); - sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - - __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); - wait_for_command_complete(WD2_BASE); - __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); -} - -/********************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - **********************************************/ -int dram_init(void) -{ - return 0; -} - -/***************************************************************** - * Routine: peripheral_enable - * Description: Enable the clks & power for perifs (GPT2, UART1,...) - ******************************************************************/ -void per_clocks_enable(void) -{ - /* Enable GP2 timer. */ - sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ - -#ifdef CFG_NS16550 - /* UART1 clocks */ - sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); - sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); - - /* UART 3 Clocks */ - sr32(CM_FCLKEN_PER, 11, 1, 0x1); - sr32(CM_ICLKEN_PER, 11, 1, 0x1); - -#endif - - /* Enable GPIO 4, 5, & 6 clocks */ - sr32(CM_FCLKEN_PER, 17, 3, 0x7); - sr32(CM_ICLKEN_PER, 17, 3, 0x7); - -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - /* Turn on all 3 I2C clocks */ - sr32(CM_FCLKEN1_CORE, 15, 3, 0x7); - sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */ -#endif - - /* Enable the ICLK for 32K Sync Timer as its used in udelay */ - sr32(CM_ICLKEN_WKUP, 2, 1, 0x1); - - sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON); - sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON); - sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON); - sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON); - sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON); - sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON); - sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON); - sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON); - sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON); - sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON); - sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON); - sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON); - - delay(1000); -} - -/* Set MUX for UART, GPMC, SDRC, GPIO */ - -#define MUX_VAL(OFFSET,VALUE)\ - __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_DEFAULT()\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ - MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ - MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ - MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ - MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\ - MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\ - MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\ - MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ - MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ - MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ - MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\ - /* - PEN_DOWN*/\ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M4)) /*GPIO_127*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M4)) /*GPIO_128*/\ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M4)) /*GPIO_129*/\ - MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ - MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ - MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ - MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ - MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ - MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ - MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ - MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ - MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ - MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ - MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ - MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ - MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/ - -/********************************************************** - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers - * specific to the hardware. Many pins need - * to be moved from protect to primary mode. - *********************************************************/ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); -} - -/********************************************************** - * Routine: nand+_init - * Description: Set up nand for nand and jffs2 commands - *********************************************************/ - -int nand_init(void) -{ - /* global settings */ - __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ - __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ - __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ - - /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0. - * We configure only GPMC CS0 with required values. Configiring other devices - * at other CS is done in u-boot. So we don't have to bother doing it here. - */ - __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); - delay(1000); - -#ifdef CFG_NAND_K9F1G08R0A - if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) { - __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((NAND_BASE_ADR>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (nand_chip()) { -#ifdef CFG_PRINTF - printf("Unsupported Chip!\n"); -#endif - return 1; - } - } -#endif - -#ifdef CFG_ONENAND - if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) { - __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); - __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); - - /* Enable the GPMC Mapping */ - __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | - ((ONENAND_BASE>>24) & 0x3F) | - (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); - delay(2000); - - if (onenand_chip()) { -#ifdef CFG_PRINTF - printf("OneNAND Unsupported !\n"); -#endif - return 1; - } - } -#endif - - return 0; -} - -/* optionally do something like blinking LED */ -void board_hang(void) -{ - while (0) - ; -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void raise(void) -{ -} - -/****************************************************************************** - * Dummy function to handle errors for EABI incompatibility - *****************************************************************************/ -void abort(void) -{ -} diff --git a/x-loader/board/overo/platform.S b/x-loader/board/overo/platform.S deleted file mode 100644 index 5869270..0000000 --- a/x-loader/board/overo/platform.S +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004-2006 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE /* sdram load addr from config.mk */ - -#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) -/************************************************************************** - * cpy_clk_code: relocates clock code into SRAM where its safer to execute - * R1 = SRAM destination address. - *************************************************************************/ -.global cpy_clk_code - cpy_clk_code: - /* Copy DPLL code into SRAM */ - adr r0, go_to_speed /* get addr of clock setting code */ - mov r2, #384 /* r2 size to copy (div by 32 bytes) */ - mov r1, r1 /* r1 <- dest address (passed in) */ - add r2, r2, r0 /* r2 <- source end address */ -next2: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next2 - mov pc, lr /* back to caller */ - -/* **************************************************************************** - * NOTE: 3430 X-loader currently does not use this code. -* It could be removed its is kept for compatabily with u-boot. - * - * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed - * -executed from SRAM. - * R0 = CM_CLKEN_PLL-bypass value - * R1 = CM_CLKSEL1_PLL-m, n, and divider values - * R2 = CM_CLKSEL_CORE-divider values - * R3 = CM_IDLEST_CKGEN - addr dpll lock wait - * - * Note: If core unlocks/relocks and SDRAM is running fast already it gets - * confused. A reset of the controller gets it back. Taking away its - * L3 when its not in self refresh seems bad for it. Normally, this code - * runs from flash before SDR is init so that should be ok. - ******************************************************************************/ -.global go_to_speed - go_to_speed: - stmfd sp!, {r4-r6} - - /* move into fast relock bypass */ - ldr r4, pll_ctl_add - str r0, [r4] -wait1: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - beq wait1 /* if lock, loop */ - - /* set new dpll dividers _after_ in bypass */ - ldr r5, pll_div_add1 - str r1, [r5] /* set m, n, m2 */ - ldr r5, pll_div_add2 - str r2, [r5] /* set l3/l4/.. dividers*/ - ldr r5, pll_div_add3 /* wkup */ - ldr r2, pll_div_val3 /* rsm val */ - str r2, [r5] - ldr r5, pll_div_add4 /* gfx */ - ldr r2, pll_div_val4 - str r2, [r5] - ldr r5, pll_div_add5 /* emu */ - ldr r2, pll_div_val5 - str r2, [r5] - - /* now prepare GPMC (flash) for new dpll speed */ - /* flash needs to be stable when we jump back to it */ - ldr r5, flash_cfg3_addr - ldr r2, flash_cfg3_val - str r2, [r5] - ldr r5, flash_cfg4_addr - ldr r2, flash_cfg4_val - str r2, [r5] - ldr r5, flash_cfg5_addr - ldr r2, flash_cfg5_val - str r2, [r5] - ldr r5, flash_cfg1_addr - ldr r2, [r5] - orr r2, r2, #0x3 /* up gpmc divider */ - str r2, [r5] - - /* lock DPLL3 and wait a bit */ - orr r0, r0, #0x7 /* set up for lock mode */ - str r0, [r4] /* lock */ - nop /* ARM slow at this point working at sys_clk */ - nop - nop - nop -wait2: - ldr r5, [r3] /* get status */ - and r5, r5, #0x1 /* isolate core status */ - cmp r5, #0x1 /* still locked? */ - bne wait2 /* if lock, loop */ - nop - nop - nop - nop - ldmfd sp!, {r4-r6} - mov pc, lr /* back to caller, locked */ - -_go_to_speed: .word go_to_speed - -/* these constants need to be close for PIC code */ -/* The Nor has to be in the Flash Base CS0 for this condition to happen */ -flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) -flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) -flash_cfg3_val: - .word STNOR_GPMC_CONFIG3 -flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) -flash_cfg4_val: - .word STNOR_GPMC_CONFIG4 -flash_cfg5_val: - .word STNOR_GPMC_CONFIG5 -flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) -pll_ctl_add: - .word CM_CLKEN_PLL -pll_div_add1: - .word CM_CLKSEL1_PLL -pll_div_add2: - .word CM_CLKSEL_CORE -pll_div_add3: - .word CM_CLKSEL_WKUP -pll_div_val3: - .word (WKUP_RSM << 1) -pll_div_add4: - .word CM_CLKSEL_GFX -pll_div_val4: - .word (GFX_DIV << 0) -pll_div_add5: - .word CM_CLKSEL1_EMU -pll_div_val5: - .word CLSEL1_EMU_VAL - -#endif - -.globl lowlevel_init -lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] /* stash old link register */ - mov ip, lr /* save link reg across call */ - bl s_init /* go setup pll,mux,memory */ - ldr ip, [sp] /* restore save ip */ - mov lr, ip /* restore link reg */ - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -REG_CONTROL_STATUS: - .word CONTROL_STATUS -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK - -/* DPLL(1-4) PARAM TABLES */ -/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal - * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). - * The values are defined for all possible sysclk and for ES1 and ES2. - */ - -mpu_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x0FE,0x07,0x05,0x01 -/* ES2 */ -.word 0x0FA,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x17D,0x0C,0x03,0x01 -/* ES2 */ -.word 0x1F4,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x179,0x12,0x04,0x01 -/* ES2 */ -.word 0x271,0x17,0x03,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x17D,0x19,0x03,0x01 -/* ES2 */ -.word 0x0FA,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x1FA,0x32,0x03,0x01 -/* ES2 */ -.word 0x271,0x2F,0x03,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_mpu_dpll_param -get_mpu_dpll_param: - adr r0, mpu_dpll_param - mov pc, lr - -iva_dpll_param: -/* 12MHz */ -/* ES1 */ -.word 0x07D,0x05,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x05,0x07,0x01 -/* 3410 */ -.word 0x085,0x05,0x07,0x01 - -/* 13MHz */ -/* ES1 */ -.word 0x0FA,0x0C,0x03,0x01 -/* ES2 */ -.word 0x168,0x0C,0x03,0x01 -/* 3410 */ -.word 0x10A,0x0C,0x03,0x01 - -/* 19.2MHz */ -/* ES1 */ -.word 0x082,0x09,0x07,0x01 -/* ES2 */ -.word 0x0E1,0x0B,0x06,0x01 -/* 3410 */ -.word 0x14C,0x17,0x03,0x01 - -/* 26MHz */ -/* ES1 */ -.word 0x07D,0x0C,0x07,0x01 -/* ES2 */ -.word 0x0B4,0x0C,0x07,0x01 -/* 3410 */ -.word 0x085,0x0C,0x07,0x01 - -/* 38.4MHz */ -/* ES1 */ -.word 0x13F,0x30,0x03,0x01 -/* ES2 */ -.word 0x0E1,0x17,0x06,0x01 -/* 3410 */ -.word 0x14C,0x2F,0x03,0x01 - - -.globl get_iva_dpll_param -get_iva_dpll_param: - adr r0, iva_dpll_param - mov pc, lr - -/* Core DPLL targets for L3 at 166 & L133 */ -core_dpll_param: -/* 12MHz */ -/* ES1 */ -.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 -/* ES2 */ -.word M_12,N_12,FSEL_12,M2_12 -/* 3410 */ -.word M_12,N_12,FSEL_12,M2_12 - -/* 13MHz */ -/* ES1 */ -.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 -/* ES2 */ -.word M_13,N_13,FSEL_13,M2_13 -/* 3410 */ -.word M_13,N_13,FSEL_13,M2_13 - -/* 19.2MHz */ -/* ES1 */ -.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 -/* ES2 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 -/* 3410 */ -.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 - -/* 26MHz */ -/* ES1 */ -.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 -/* ES2 */ -.word M_26,N_26,FSEL_26,M2_26 -/* 3410 */ -.word M_26,N_26,FSEL_26,M2_26 - -/* 38.4MHz */ -/* ES1 */ -.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 -/* ES2 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 -/* 3410 */ -.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 - -.globl get_core_dpll_param -get_core_dpll_param: - adr r0, core_dpll_param - mov pc, lr - -/* PER DPLL values are same for both ES1 and ES2 */ -per_dpll_param: -/* 12MHz */ -.word 0xD8,0x05,0x07,0x09 - -/* 13MHz */ -.word 0x1B0,0x0C,0x03,0x09 - -/* 19.2MHz */ -.word 0xE1,0x09,0x07,0x09 - -/* 26MHz */ -.word 0xD8,0x0C,0x07,0x09 - -/* 38.4MHz */ -.word 0xE1,0x13,0x07,0x09 - -.globl get_per_dpll_param -get_per_dpll_param: - adr r0, per_dpll_param - mov pc, lr - diff --git a/x-loader/board/overo/x-load.lds b/x-loader/board/overo/x-load.lds deleted file mode 100644 index 5f352d3..0000000 --- a/x-loader/board/overo/x-load.lds +++ /dev/null @@ -1,54 +0,0 @@ -/* - * November 2006 - Changed to support 3430sdp device - * Copyright (c) 2004-2006 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/omap3/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/x-loader/common/Makefile b/x-loader/common/Makefile deleted file mode 100644 index beb58eb..0000000 --- a/x-loader/common/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)libcommon.a - -AOBJS = - -COBJS = cmd_load.o cmd_monitor.o - -SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) - -CPPFLAGS += -I.. - -all: $(LIB) $(AOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/common/cmd_load.c b/x-loader/common/cmd_load.c deleted file mode 100644 index 122b797..0000000 --- a/x-loader/common/cmd_load.c +++ /dev/null @@ -1,555 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Serial up- and download support - */ -#include - -#define putc serial_putc -#define tstc serial_tstc - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} -static inline void udelay(unsigned long us) -{ - delay(us * 200); /* approximate */ -} - -#ifdef CFG_CMD_FAT -extern void * memcpy(void * dest,const void *src,size_t count); -#else -void * memcpy(void * dest,const void *src,size_t count) -{ - char *tmp = (char *) dest, *s = (char *) src; - - while (count--) - *tmp++ = *s++; - - return dest; -} -#endif - -/* -------------------------------------------------------------------- */ - -#define XON_CHAR 17 -#define XOFF_CHAR 19 -#define START_CHAR 0x01 -#define ETX_CHAR 0x03 -#define END_CHAR 0x0D -#define SPACE 0x20 -#define K_ESCAPE 0x23 -#define SEND_TYPE 'S' -#define DATA_TYPE 'D' -#define ACK_TYPE 'Y' -#define NACK_TYPE 'N' -#define BREAK_TYPE 'B' -#define tochar(x) ((char) (((x) + SPACE) & 0xff)) -#define untochar(x) ((int) (((x) - SPACE) & 0xff)) - -extern int os_data_count; -extern int os_data_header[8]; - -static void set_kerm_bin_mode(unsigned long *); -static int k_recv(void); -static ulong load_serial_bin (ulong offset); - -extern int lowlevel_monitor (void); - -char his_eol; /* character he needs at end of packet */ -int his_pad_count; /* number of pad chars he needs */ -char his_pad_char; /* pad chars he needs */ -char his_quote; /* quote chars he'll use */ - -int do_load_serial_bin (ulong offset, int baudrate) -{ - ulong addr; - int rcode = 0; - - printf ("## Ready for binary (kermit) download " - "to 0x%08lX at %d bps. Press 'M' to break into low level monitor.\n", - offset, - baudrate); - addr = load_serial_bin (offset); - if (addr == ~0) { - printf ("## Binary (kermit) download aborted\n"); - rcode = 1; - } else { - printf ("## Start Addr = 0x%08lX\n", addr); - } - - return rcode; -} - - -static ulong load_serial_bin (ulong offset) -{ - int size, i; - - set_kerm_bin_mode ((ulong *) offset); - size = k_recv (); - - /* - * Gather any trailing characters (for instance, the ^D which - * is sent by 'cu' after sending a file), and give the - * box some time (100 * 1 ms) - */ - for (i=0; i<100; ++i) { - if (tstc()) { - (void) getc(); - } - udelay(1000); - } - - printf("## Total Size = 0x%08x = %d Bytes\n", size, size); - - return offset; -} - -void send_pad (void) -{ - int count = his_pad_count; - - while (count-- > 0) - putc (his_pad_char); -} - -/* converts escaped kermit char to binary char */ -char ktrans (char in) -{ - if ((in & 0x60) == 0x40) { - return (char) (in & ~0x40); - } else if ((in & 0x7f) == 0x3f) { - return (char) (in | 0x40); - } else - return in; -} - -int chk1 (char *buffer) -{ - int total = 0; - - while (*buffer) { - total += *buffer++; - } - return (int) ((total + ((total >> 6) & 0x03)) & 0x3f); -} - -void s1_sendpacket (char *packet) -{ - send_pad (); - while (*packet) { - putc (*packet++); - } -} - -static char a_b[24]; -void send_ack (int n) -{ - a_b[0] = START_CHAR; - a_b[1] = tochar (3); - a_b[2] = tochar (n); - a_b[3] = ACK_TYPE; - a_b[4] = '\0'; - a_b[4] = tochar (chk1 (&a_b[1])); - a_b[5] = his_eol; - a_b[6] = '\0'; - s1_sendpacket (a_b); -} - -void send_nack (int n) -{ - a_b[0] = START_CHAR; - a_b[1] = tochar (3); - a_b[2] = tochar (n); - a_b[3] = NACK_TYPE; - a_b[4] = '\0'; - a_b[4] = tochar (chk1 (&a_b[1])); - a_b[5] = his_eol; - a_b[6] = '\0'; - s1_sendpacket (a_b); -} - - -/* os_data_* takes an OS Open image and puts it into memory, and - puts the boot header in an array named os_data_header - - if image is binary, no header is stored in os_data_header. -*/ -void (*os_data_init) (void); -void (*os_data_char) (char new_char); -static int os_data_state, os_data_state_saved; -int os_data_count; -static int os_data_count_saved; -static char *os_data_addr, *os_data_addr_saved; -static char *bin_start_address; -int os_data_header[8]; -static void bin_data_init (void) -{ - os_data_state = 0; - os_data_count = 0; - os_data_addr = bin_start_address; -} -static void os_data_save (void) -{ - os_data_state_saved = os_data_state; - os_data_count_saved = os_data_count; - os_data_addr_saved = os_data_addr; -} -static void os_data_restore (void) -{ - os_data_state = os_data_state_saved; - os_data_count = os_data_count_saved; - os_data_addr = os_data_addr_saved; -} -static void bin_data_char (char new_char) -{ - switch (os_data_state) { - case 0: /* data */ - *os_data_addr++ = new_char; - --os_data_count; - break; - } -} -static void set_kerm_bin_mode (unsigned long *addr) -{ - bin_start_address = (char *) addr; - os_data_init = bin_data_init; - os_data_char = bin_data_char; -} - - -/* k_data_* simply handles the kermit escape translations */ -static int k_data_escape, k_data_escape_saved; -void k_data_init (void) -{ - k_data_escape = 0; - os_data_init (); -} -void k_data_save (void) -{ - k_data_escape_saved = k_data_escape; - os_data_save (); -} -void k_data_restore (void) -{ - k_data_escape = k_data_escape_saved; - os_data_restore (); -} -void k_data_char (char new_char) -{ - if (k_data_escape) { - /* last char was escape - translate this character */ - os_data_char (ktrans (new_char)); - k_data_escape = 0; - } else { - if (new_char == his_quote) { - /* this char is escape - remember */ - k_data_escape = 1; - } else { - /* otherwise send this char as-is */ - os_data_char (new_char); - } - } -} - -#define SEND_DATA_SIZE 20 -char send_parms[SEND_DATA_SIZE]; -char *send_ptr; - -/* handle_send_packet interprits the protocol info and builds and - sends an appropriate ack for what we can do */ -void handle_send_packet (int n) -{ - int length = 3; - int bytes; - - /* initialize some protocol parameters */ - his_eol = END_CHAR; /* default end of line character */ - his_pad_count = 0; - his_pad_char = '\0'; - his_quote = K_ESCAPE; - - /* ignore last character if it filled the buffer */ - if (send_ptr == &send_parms[SEND_DATA_SIZE - 1]) - --send_ptr; - bytes = send_ptr - send_parms; /* how many bytes we'll process */ - do { - if (bytes-- <= 0) - break; - /* handle MAXL - max length */ - /* ignore what he says - most I'll take (here) is 94 */ - a_b[++length] = tochar (94); - if (bytes-- <= 0) - break; - /* handle TIME - time you should wait for my packets */ - /* ignore what he says - don't wait for my ack longer than 1 second */ - a_b[++length] = tochar (1); - if (bytes-- <= 0) - break; - /* handle NPAD - number of pad chars I need */ - /* remember what he says - I need none */ - his_pad_count = untochar (send_parms[2]); - a_b[++length] = tochar (0); - if (bytes-- <= 0) - break; - /* handle PADC - pad chars I need */ - /* remember what he says - I need none */ - his_pad_char = ktrans (send_parms[3]); - a_b[++length] = 0x40; /* He should ignore this */ - if (bytes-- <= 0) - break; - /* handle EOL - end of line he needs */ - /* remember what he says - I need CR */ - his_eol = untochar (send_parms[4]); - a_b[++length] = tochar (END_CHAR); - if (bytes-- <= 0) - break; - /* handle QCTL - quote control char he'll use */ - /* remember what he says - I'll use '#' */ - his_quote = send_parms[5]; - a_b[++length] = '#'; - if (bytes-- <= 0) - break; - /* handle QBIN - 8-th bit prefixing */ - /* ignore what he says - I refuse */ - a_b[++length] = 'N'; - if (bytes-- <= 0) - break; - /* handle CHKT - the clock check type */ - /* ignore what he says - I do type 1 (for now) */ - a_b[++length] = '1'; - if (bytes-- <= 0) - break; - /* handle REPT - the repeat prefix */ - /* ignore what he says - I refuse (for now) */ - a_b[++length] = 'N'; - if (bytes-- <= 0) - break; - /* handle CAPAS - the capabilities mask */ - /* ignore what he says - I only do long packets - I don't do windows */ - a_b[++length] = tochar (2); /* only long packets */ - a_b[++length] = tochar (0); /* no windows */ - a_b[++length] = tochar (94); /* large packet msb */ - a_b[++length] = tochar (94); /* large packet lsb */ - } while (0); - - a_b[0] = START_CHAR; - a_b[1] = tochar (length); - a_b[2] = tochar (n); - a_b[3] = ACK_TYPE; - a_b[++length] = '\0'; - a_b[length] = tochar (chk1 (&a_b[1])); - a_b[++length] = his_eol; - a_b[++length] = '\0'; - s1_sendpacket (a_b); -} - -/* k_recv receives a OS Open image file over kermit line */ -static int k_recv (void) -{ - char new_char; - char k_state, k_state_saved; - int sum; - int done; - int length; - int n, last_n; - int z = 0; - int len_lo, len_hi; - - /* initialize some protocol parameters */ - his_eol = END_CHAR; /* default end of line character */ - his_pad_count = 0; - his_pad_char = '\0'; - his_quote = K_ESCAPE; - - /* initialize the k_recv and k_data state machine */ - done = 0; - k_state = 0; - k_data_init (); - k_state_saved = k_state; - k_data_save (); - n = 0; /* just to get rid of a warning */ - last_n = -1; - - /* expect this "type" sequence (but don't check): - S: send initiate - F: file header - D: data (multiple) - Z: end of file - B: break transmission - */ - - /* enter main loop */ - while (!done) { - /* set the send packet pointer to begining of send packet parms */ - send_ptr = send_parms; - - /* With each packet, start summing the bytes starting with the length. - Save the current sequence number. - Note the type of the packet. - If a character less than SPACE (0x20) is received - error. - */ - -#if 0 - /* OLD CODE, Prior to checking sequence numbers */ - /* first have all state machines save current states */ - k_state_saved = k_state; - k_data_save (); -#endif - - /* get a packet */ - /* wait for the starting character or ^C */ - for (;;) { - switch (getc ()) { - case START_CHAR: /* start packet */ - goto START; - case ETX_CHAR: /* ^C waiting for packet */ - return (0); - case 'M': - lowlevel_monitor(); - break; - default: - ; - } - } -START: - /* get length of packet */ - sum = 0; - new_char = getc (); - if ((new_char & 0xE0) == 0) - goto packet_error; - sum += new_char & 0xff; - length = untochar (new_char); - /* get sequence number */ - new_char = getc (); - if ((new_char & 0xE0) == 0) - goto packet_error; - sum += new_char & 0xff; - n = untochar (new_char); - --length; - - /* NEW CODE - check sequence numbers for retried packets */ - /* Note - this new code assumes that the sequence number is correctly - * received. Handling an invalid sequence number adds another layer - * of complexity that may not be needed - yet! At this time, I'm hoping - * that I don't need to buffer the incoming data packets and can write - * the data into memory in real time. - */ - if (n == last_n) { - /* same sequence number, restore the previous state */ - k_state = k_state_saved; - k_data_restore (); - } else { - /* new sequence number, checkpoint the download */ - last_n = n; - k_state_saved = k_state; - k_data_save (); - } - /* END NEW CODE */ - - /* get packet type */ - new_char = getc (); - if ((new_char & 0xE0) == 0) - goto packet_error; - sum += new_char & 0xff; - k_state = new_char; - --length; - /* check for extended length */ - if (length == -2) { - /* (length byte was 0, decremented twice) */ - /* get the two length bytes */ - new_char = getc (); - if ((new_char & 0xE0) == 0) - goto packet_error; - sum += new_char & 0xff; - len_hi = untochar (new_char); - new_char = getc (); - if ((new_char & 0xE0) == 0) - goto packet_error; - sum += new_char & 0xff; - len_lo = untochar (new_char); - length = len_hi * 95 + len_lo; - /* check header checksum */ - new_char = getc (); - if ((new_char & 0xE0) == 0) - goto packet_error; - if (new_char != tochar ((sum + ((sum >> 6) & 0x03)) & 0x3f)) - goto packet_error; - sum += new_char & 0xff; -/* --length; */ /* new length includes only data and block check to come */ - } - /* bring in rest of packet */ - while (length > 1) { - new_char = getc (); - if ((new_char & 0xE0) == 0) - goto packet_error; - sum += new_char & 0xff; - --length; - if (k_state == DATA_TYPE) { - /* pass on the data if this is a data packet */ - k_data_char (new_char); - } else if (k_state == SEND_TYPE) { - /* save send pack in buffer as is */ - *send_ptr++ = new_char; - /* if too much data, back off the pointer */ - if (send_ptr >= &send_parms[SEND_DATA_SIZE]) - --send_ptr; - } - } - /* get and validate checksum character */ - new_char = getc (); - if ((new_char & 0xE0) == 0) - goto packet_error; - if (new_char != tochar ((sum + ((sum >> 6) & 0x03)) & 0x3f)) - goto packet_error; - /* get END_CHAR */ - new_char = getc (); - if (new_char != END_CHAR) { - packet_error: - /* restore state machines */ - k_state = k_state_saved; - k_data_restore (); - /* send a negative acknowledge packet in */ - send_nack (n); - } else if (k_state == SEND_TYPE) { - /* crack the protocol parms, build an appropriate ack packet */ - handle_send_packet (n); - } else { - /* send simple acknowledge packet in */ - send_ack (n); - /* quit if end of transmission */ - if (k_state == BREAK_TYPE) - done = 1; - } - ++z; - } - return ((ulong) os_data_addr - (ulong) bin_start_address); -} diff --git a/x-loader/common/cmd_monitor.c b/x-loader/common/cmd_monitor.c deleted file mode 100644 index 05ff5df..0000000 --- a/x-loader/common/cmd_monitor.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Simple command line monitor - * run in Kermit mode by starting with "M" - */ -#include -#include - -#define putc serial_putc -#define tstc serial_tstc - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} -static inline void udelay(unsigned long us) -{ - delay(us * 200); /* approximate */ -} - -typedef struct gpio { - unsigned char res1[0x34]; - unsigned int oe; /* 0x34 */ - unsigned int datain; /* 0x38 */ - unsigned char res2[0x54]; - unsigned int cleardataout; /* 0x90 */ - unsigned int setdataout; /* 0x94 */ -} gpio_t; - -// unclear if the functional clocks are enabled! - -static gpio_t *blocks[]={ // GPIO1 .. 6 - OMAP34XX_GPIO1_BASE, - OMAP34XX_GPIO2_BASE, - OMAP34XX_GPIO3_BASE, - OMAP34XX_GPIO4_BASE, - OMAP34XX_GPIO5_BASE, - OMAP34XX_GPIO6_BASE -}; - -static inline int gpio_get(int n) -{ - int bit=n % 32; - gpio_t *base=blocks[n/32]; - return (base->datain >> bit)&1; -} - -static inline int gpio_is_input(int n) -{ // geht nicht richtig - int bit=n % 32; - gpio_t *base=blocks[n/32]; - return (base->oe >> bit)&1; -} - -int strcmp(char *s1, char *s2) -{ - while(*s1 == *s2) { - if(*s1 == 0) - return 0; // same - s1++; - s2++; - } - return *s1 > *s2?1:-1; -} - -long xtol(char *s) -{ - long val=0; - while(1) - { - if(*s >= '0' && *s <= '9') - val=16*val+(*s++-'0'); - else if(*s >= 'A' && *s <= 'F') - val=16*val+(*s++-'A'+10); - else if(*s >= 'a' && *s <= 'f') - val=16*val+(*s++-'a'+10); - else - break; - } - return val; -} - -static char *addr=(char *) CFG_LOADADDR; -static char line[100]; -static char *argv[10]; - -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) - -#define MUX_VAL(OFFSET,VALUE)\ -__raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); - -#define CP(x) (CONTROL_PADCONF_##x) - -void testfn(void) -{ // code can be copied to SDRAM (assuming that it is position-independent!) - int i; - for(i=0; i<10; i++) { - if(i & 1) - MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | EN | M4)) /*GPT_PWM11/GPIO57*/ - else - MUX_VAL(CP(GPMC_nCS6), (IEN | PTU | EN | M4)) /*GPT_PWM11/GPIO57*/ - udelay(500*1000); - } -} - -int lowlevel_monitor (void) -{ // add testing code here - int i=0; - printf("Hello World!\n"); - while(1) { - char *c; - int argc=0; - int pos=0; - printf ("$ "); - while(1) { - line[pos]=getc(); - switch(line[pos]) { - case '\b': - case 0x7f: - if(pos > 0) { - putc('\b'); - pos--; - } - continue; - case 0: - case '\n': - continue; // ignore - case '\r': - break; // command - default: - if(pos < sizeof(line)/sizeof(line[0])) { - putc(line[pos]); - pos++; - } - continue; - } - line[pos]=0; - printf("\n"); - break; - } - c=line; - while(argc < sizeof(argv)/sizeof(argv[0])) { - while (*c == ' ' || *c == '\t') - c++; - if(*c == 0) - break; - argv[argc]=c; - while(*c != 0 && *c != '\t' && *c != ' ') - c++; - argc++; - if(*c == 0) - break; - *c=0; // substitute - c++; - } - if(argc == 0) - continue; // empty line -// printf("argc=%d argv[0]=%s\n", argc, argv[0]); - if(strcmp(argv[0], "c") == 0) { // c - copy test function to SDRAM and execute - extern void * memcpy(void * dest,const void *src,size_t count); - void (*fn)(void) = &testfn; - size_t cnt = 0x1000; - addr=(char *) CFG_LOADADDR; - printf("%08x (%d) --> %08x\n", fn, cnt, addr); - memcpy(addr, fn, cnt); - (*fn)(); - } - else if(strcmp(argv[0], "x") == 0) { // x [addr] - execute code - void (*fn)(void) = addr; - if(argc > 1) - fn = (void *) xtol(argv[1]); - (*fn)(); - } - else if(strcmp(argv[0], "l") == 0) { // l - loop - int d=1; - while(1) - printf ("Welcome to uart-monitor (%d)\n", d++), udelay(500*1000); - } - else if(strcmp(argv[0], "a") == 0) { // a [addr] - if(argc > 1) - addr=(char *) xtol(argv[1]); - printf("%08x\n", addr); - } - else if(strcmp(argv[0], "r") == 0) { // r [size] - int i; - int n=1; - if(argc > 1) - n=xtol(argv[1]); - printf("%08x:", addr); - for(i=0; i 1) - n=xtol(argv[1]); - printf("%08x:", addr); - for(i=0; i 1) - val=xtol(argv[1]); - if(argc > 2) - n=xtol(argv[2]); - for(i=0; i> 8) + (((unsigned int) addr) >> 16) + (((unsigned int) addr) >> 24); // build from address - if((((unsigned int)addr) & 0xfffff) == 0) // approx. 1 MByte per second - printf("%08x: %02x\n", addr, val); - *addr=val; // fill ram with prime pattern - } - printf("\nchecking\n"); - for(addr=(char *) CFG_LOADADDR; addr < 512*1024*1024+(char *) 0x80000000; addr++) { - unsigned char r=*addr; // read back - val=(unsigned int) addr + (((unsigned int) addr) >> 8) + (((unsigned int) addr) >> 16) + (((unsigned int) addr) >> 24); - if((((unsigned int)addr) & 0xfffff) == 0) - printf("%08x\n", addr); - if(r != val) // check RAM - printf("read error %8x: %2x %2x\n", addr, r, val); - } - printf("\ndone\n"); - addr=(char *) CFG_LOADADDR; - } -#if 0 - else if(strcmp(argv[0], "clk") == 0) { // clk - extern u32 osc_clk; - printf("clk=%d\n", osc_clk); - } -#endif - else if(strcmp(argv[0], "bl") == 0) { // blink backlight - int i; - for(i=0; i<10; i++) { - printf("blink %d\n", i+1); - // works only on GTA04A3 board since R209 is high compared to PTU - if(i & 1) - MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | EN | M4)) /*GPT_PWM11/GPIO57*/ - else - MUX_VAL(CP(GPMC_nCS6), (IEN | PTU | EN | M4)) /*GPT_PWM11/GPIO57*/ - udelay(500*1000); - } - } - else if(strcmp(argv[0], "g") == 0) { // g - read GPIO - unsigned int i; - int n=32*sizeof(blocks)/sizeof(blocks[0]); - printf("GPIO1 data: %08x\n", ((gpio_t *) OMAP34XX_GPIO1_BASE) -> datain); - printf("%03d:", 0); - for(i=0; i>= 16; - } - if(addr == 0x48002264) { - addr=0x480025DC; - printf("\n%08x", addr); - cols=0; - } - else { - addr+=4; - if(++cols == 8) - printf("\n%08x", addr), cols=0; - } - } - printf("\n"); - } - else if(strcmp(argv[0], "k") == 0) { // k - back to kermit mode - printf("Going back to Kermit mode\n"); - break; - } - else - { - printf("uart-monitor unknown command: %s\n", argv[0]); - printf("a: \n"); - printf("bl: \n"); - printf("c: \n"); - printf("f: fill RAM with pattern\n"); - printf("g: read GPIO\n"); - printf("k: back to Kermit mode\n"); - printf("l: \n"); - printf("m: read Pinmux\n"); - printf("r: \n"); - printf("ram: \n"); - printf("rl: \n"); - printf("rt: RAM test\n"); - printf("x: \n"); - } - } - return 0; -} - diff --git a/x-loader/config.mk b/x-loader/config.mk deleted file mode 100644 index f4c58e9..0000000 --- a/x-loader/config.mk +++ /dev/null @@ -1,208 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -######################################################################### - -ifneq ($(OBJTREE),$(SRCTREE)) -ifeq ($(CURDIR),$(SRCTREE)) -dir := -else -dir := $(subst $(SRCTREE)/,,$(CURDIR)) -endif - -obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/) -src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/) - -$(shell mkdir -p $(obj)) -else -obj := -src := -endif - -# clean the slate ... -PLATFORM_RELFLAGS = -PLATFORM_CPPFLAGS = -PLATFORM_LDFLAGS = - -# -# When cross-compiling on NetBSD, we have to define __PPC__ or else we -# will pick up a va_list declaration that is incompatible with the -# actual argument lists emitted by the compiler. -# -# [Tested on NetBSD/i386 1.5 + cross-powerpc-netbsd-1.3] - -ifeq ($(ARCH),ppc) -ifeq ($(CROSS_COMPILE),powerpc-netbsd-) -PLATFORM_CPPFLAGS+= -D__PPC__ -endif -ifeq ($(CROSS_COMPILE),powerpc-openbsd-) -PLATFORM_CPPFLAGS+= -D__PPC__ -endif -endif - -ifeq ($(ARCH),arm) -ifeq ($(CROSS_COMPILE),powerpc-netbsd-) -PLATFORM_CPPFLAGS+= -D__ARM__ -endif -ifeq ($(CROSS_COMPILE),powerpc-openbsd-) -PLATFORM_CPPFLAGS+= -D__ARM__ -endif -endif - -ifdef ARCH -sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules -endif -ifdef CPU -sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules -endif -ifdef VENDOR -BOARDDIR = $(VENDOR)/$(BOARD) -else -BOARDDIR = $(BOARD) -endif -ifdef BOARD -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk # include board specific rules -endif - -######################################################################### - -CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ - else if [ -x /bin/bash ]; then echo /bin/bash; \ - else echo sh; fi ; fi) - -ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) -HOSTCC = cc -else -HOSTCC = gcc -endif -HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -HOSTSTRIP = strip - -######################################################################### -# -# Option checker (courtesy linux kernel) to ensure -# only supported compiler options are used -# -cc-option = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \ - > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;) - -# -# Include the make variables (CC, etc...) -# -AS = $(CROSS_COMPILE)as -LD = $(CROSS_COMPILE)ld -CC = $(CROSS_COMPILE)gcc -CPP = $(CC) -E -AR = $(CROSS_COMPILE)ar -NM = $(CROSS_COMPILE)nm -STRIP = $(CROSS_COMPILE)strip -OBJCOPY = $(CROSS_COMPILE)objcopy -OBJDUMP = $(CROSS_COMPILE)objdump -RANLIB = $(CROSS_COMPILE)RANLIB - -RELFLAGS= $(PLATFORM_RELFLAGS) -DBGFLAGS= -g # -DDEBUG -OPTFLAGS= -Os #-fomit-frame-pointer -ifndef LDSCRIPT -#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/x-load.lds.debug -LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/x-load.lds -endif -OBJCFLAGS += --gap-fill=0xff - -gccincdir := $(shell $(CC) -print-file-name=include) - -CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ - -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) - -ifneq ($(OBJTREE),$(SRCTREE)) -CPPFLAGS += -I$(OBJTREE)/include -endif - -CPPFLAGS += -I$(TOPDIR)/include -CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ - -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) - -ifdef BUILD_TAG -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \ - -DBUILD_TAG='"$(BUILD_TAG)"' -else -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -endif - -AFLAGS_DEBUG := -Wa,-gstabs -AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) - -LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) - -# Location of a usable BFD library, where we define "usable" as -# "built for ${HOST}, supports ${TARGET}". Sensible values are -# - When cross-compiling: the root of the cross-environment -# - Linux/ppc (native): /usr -# - NetBSD/ppc (native): you lose ... (must extract these from the -# binutils build directory, plus the native and U-Boot include -# files don't like each other) -# -# So far, this is used only by tools/gdb/Makefile. - -ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) -BFD_ROOT_DIR = /usr/local/tools -else -ifeq ($(HOSTARCH),$(ARCH)) -# native -BFD_ROOT_DIR = /usr -else -#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386 -#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386 -BFD_ROOT_DIR = /opt/powerpc -endif -endif - -######################################################################### - -export CONFIG_SHELL HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \ - AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP \ - MAKE -export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS - -######################################################################### - -ifndef REMOTE_BUILD - -%.s: %.S - $(CPP) $(AFLAGS) -o $@ $< -%.o: %.S - $(CC) $(AFLAGS) -c -o $@ $< -%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $< - -else - -$(obj)%.s: %.S - $(CPP) $(AFLAGS) -o $@ $< -$(obj)%.o: %.S - $(CC) $(AFLAGS) -c -o $@ $< -$(obj)%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $< -endif - -######################################################################### diff --git a/x-loader/cpu/arm1136/Makefile b/x-loader/cpu/arm1136/Makefile deleted file mode 100644 index b556419..0000000 --- a/x-loader/cpu/arm1136/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).a - -START = start.o -COBJS = cpu.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/cpu/arm1136/config.mk b/x-loader/cpu/arm1136/config.mk deleted file mode 100644 index 3106824..0000000 --- a/x-loader/cpu/arm1136/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 - -PLATFORM_CPPFLAGS += -march=armv5 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -# diff --git a/x-loader/cpu/arm1136/cpu.c b/x-loader/cpu/arm1136/cpu.c deleted file mode 100644 index 1168fb9..0000000 --- a/x-loader/cpu/arm1136/cpu.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2004 Texas Insturments - * - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * udelay() is CPU specific code - */ - -#include - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_WB (1<<3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ - -int cpu_init (void) -{ - int i; - - /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); // invalidate both caches and flush btb - asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); // mem barrier to sync things - - return 0; -} - - - - - - - - diff --git a/x-loader/cpu/arm1136/start.S b/x-loader/cpu/arm1136/start.S deleted file mode 100644 index 16108d0..0000000 --- a/x-loader/cpu/arm1136/start.S +++ /dev/null @@ -1,218 +0,0 @@ -/* - * armboot - Startup Code for OMP2420/ARM1136 CPU-core - * - * Copyright (c) 2004 Texas Instruments - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * Copyright (c) 2004 Jian Zhang - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -.globl _start -_start: - b reset - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - -_hang: - .word do_hang - - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 /* now 16*4=64 */ - -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup Memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* Copy vectors to mask ROM indirect addr */ - adr r0, _start /* r0 <- current position of code */ - add r0, r0, #4 /* skip reset vector */ - mov r2, #64 /* r2 <- size to copy */ - add r2, r0, r2 /* r2 <- source end address */ - mov r1, #0x40000000 /* build vect addr */ - mov r3, #0x00200000 - add r1, r1, r3 - mov r3, #0xf800 - add r1, r1, r3 -next: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next /* loop until equal */ - - bl cpy_clk_code /* put dpll adjust code behind vectors */ - - /* the mask ROM code should have PLL and others stable */ - bl cpu_init_crit - -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - /* beq stack_setup */ - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub sp, r0, #128 /* leave 32 words for abort-stack */ - -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ - -//clbss_l:str r2, [r0] /* clear loop... */ -// add r0, r0, #4 -// cmp r0, r1 -// bne clbss_l - - ldr pc, _start_armboot - -_start_armboot: .word start_armboot - - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align -#ifndef CONFIG_ICACHE_OFF - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache -#endif - mcr p15, 0, r0, c1, c0, 0 - - /* - * Jump to board specific initialization... The Mask ROM will have already initialized - * basic memory. Go here to bump up clock rate and handle wake up conditions. - */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* pass on info about skipping some init portions */ - moveq r0,#0x1 /* flag to skip prcm and sdrc setup */ - movne r0,#0x0 - -//mov r0, #1 /* this skip memory init */ - - mov ip, lr /* persevere link reg across call */ - bl platformsetup /* go setup pll,mux,memory */ - - mov lr, ip /* restore link */ - mov pc, lr /* back to my caller */ - - -/* - * exception handler - */ - .align 5 -do_hang: - ldr sp, _TEXT_BASE /* use 32 words abort stack */ - bl hang /* hang and never return */ - diff --git a/x-loader/cpu/omap3/Makefile b/x-loader/cpu/omap3/Makefile deleted file mode 100644 index 678619c..0000000 --- a/x-loader/cpu/omap3/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).a - -START = start.o -COBJS = cpu.o mmc.o gpio.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/cpu/omap3/config.mk b/x-loader/cpu/omap3/config.mk deleted file mode 100644 index bd76483..0000000 --- a/x-loader/cpu/omap3/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 - -#PLATFORM_CPPFLAGS += -march=armv7-a -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32) -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/x-loader/cpu/omap3/cpu.c b/x-loader/cpu/omap3/cpu.c deleted file mode 100644 index 1cf422a..0000000 --- a/x-loader/cpu/omap3/cpu.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2004-2006 Texas Insturments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ -#include - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_WB (1<<3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ - -int cpu_init (void) -{ - return 0; -} - diff --git a/x-loader/cpu/omap3/gpio.c b/x-loader/cpu/omap3/gpio.c deleted file mode 100644 index aeb6066..0000000 --- a/x-loader/cpu/omap3/gpio.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * This work is derived from the linux 2.6.27 kernel source - * To fetch, use the kernel repository - * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - * Use the v2.6.27 tag. - * - * Below is the original's header including its copyright - * - * linux/arch/arm/plat-omap/gpio.c - * - * Support functions for OMAP GPIO - * - * Copyright (C) 2003-2005 Nokia Corporation - * Written by Juha Yrjölä - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include - -static struct gpio_bank gpio_bank_34xx[6] = { - { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX }, - { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX }, -}; - -static struct gpio_bank *gpio_bank = &gpio_bank_34xx[0]; - -static inline struct gpio_bank *get_gpio_bank(int gpio) -{ - return &gpio_bank[gpio >> 5]; -} - -static inline int get_gpio_index(int gpio) -{ - return gpio & 0x1f; -} - -static inline int gpio_valid(int gpio) -{ - if (gpio < 0) - return -1; - if (gpio < 192) - return 0; - return -1; -} - -static int check_gpio(int gpio) -{ - if (gpio_valid(gpio) < 0) { - printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); - return -1; - } - return 0; -} - -static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) -{ - void *reg = bank->base; - u32 l; - - switch (bank->method) { - case METHOD_GPIO_24XX: - reg += OMAP24XX_GPIO_OE; - break; - default: - return; - } - l = __raw_readl(reg); - if (is_input) - l |= 1 << gpio; - else - l &= ~(1 << gpio); - __raw_writel(l, reg); -} - -void omap_set_gpio_direction(int gpio, int is_input) -{ - struct gpio_bank *bank; - - if (check_gpio(gpio) < 0) - return; - bank = get_gpio_bank(gpio); - _set_gpio_direction(bank, get_gpio_index(gpio), is_input); -} - -static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) -{ - void *reg = bank->base; - u32 l = 0; - - switch (bank->method) { - case METHOD_GPIO_24XX: - if (enable) - reg += OMAP24XX_GPIO_SETDATAOUT; - else - reg += OMAP24XX_GPIO_CLEARDATAOUT; - l = 1 << gpio; - break; - default: - printf("omap3-gpio unknown bank method %s %d\n", - __FILE__, __LINE__); - return; - } - __raw_writel(l, reg); -} - -void omap_set_gpio_dataout(int gpio, int enable) -{ - struct gpio_bank *bank; - - if (check_gpio(gpio) < 0) - return; - bank = get_gpio_bank(gpio); - _set_gpio_dataout(bank, get_gpio_index(gpio), enable); -} - -int omap_get_gpio_datain(int gpio) -{ - struct gpio_bank *bank; - void *reg; - - if (check_gpio(gpio) < 0) - return -EINVAL; - bank = get_gpio_bank(gpio); - reg = bank->base; - switch (bank->method) { - case METHOD_GPIO_24XX: - reg += OMAP24XX_GPIO_DATAIN; - break; - default: - return -EINVAL; - } - return (__raw_readl(reg) - & (1 << get_gpio_index(gpio))) != 0; -} - -static void _reset_gpio(struct gpio_bank *bank, int gpio) -{ - _set_gpio_direction(bank, get_gpio_index(gpio), 1); -} - -int omap_request_gpio(int gpio) -{ - if (check_gpio(gpio) < 0) - return -EINVAL; - - return 0; -} - -void omap_free_gpio(int gpio) -{ - struct gpio_bank *bank; - - if (check_gpio(gpio) < 0) - return; - bank = get_gpio_bank(gpio); - - _reset_gpio(bank, gpio); -} diff --git a/x-loader/cpu/omap3/mmc.c b/x-loader/cpu/omap3/mmc.c deleted file mode 100644 index e0c63b0..0000000 --- a/x-loader/cpu/omap3/mmc.c +++ /dev/null @@ -1,565 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -const unsigned short mmc_transspeed_val[15][4] = { - {CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)}, - {CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)}, - {CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)}, - {CLKD(15, 1), CLKD(15, 10), CLKD(15, 100), CLKD(15, 1000)}, - {CLKD(20, 1), CLKD(20, 10), CLKD(20, 100), CLKD(20, 1000)}, - {CLKD(26, 1), CLKD(26, 10), CLKD(26, 100), CLKD(26, 1000)}, - {CLKD(30, 1), CLKD(30, 10), CLKD(30, 100), CLKD(30, 1000)}, - {CLKD(35, 1), CLKD(35, 10), CLKD(35, 100), CLKD(35, 1000)}, - {CLKD(40, 1), CLKD(40, 10), CLKD(40, 100), CLKD(40, 1000)}, - {CLKD(45, 1), CLKD(45, 10), CLKD(45, 100), CLKD(45, 1000)}, - {CLKD(52, 1), CLKD(52, 10), CLKD(52, 100), CLKD(52, 1000)}, - {CLKD(55, 1), CLKD(55, 10), CLKD(55, 100), CLKD(55, 1000)}, - {CLKD(60, 1), CLKD(60, 10), CLKD(60, 100), CLKD(60, 1000)}, - {CLKD(70, 1), CLKD(70, 10), CLKD(70, 100), CLKD(70, 1000)}, - {CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)} -}; - -mmc_card_data cur_card_data; -static block_dev_desc_t mmc_blk_dev; - -block_dev_desc_t *mmc_get_dev(int dev) -{ - return ((block_dev_desc_t *) &mmc_blk_dev); -} - -void twl4030_mmc_config(void) -{ - unsigned char data; - - data = 0x20; - i2c_write(0x4B, 0x82, 1, &data, 1); - data = 0x2; - i2c_write(0x4B, 0x85, 1, &data, 1); -} - -unsigned char mmc_board_init(void) -{ - unsigned int value = 0; - - twl4030_mmc_config(); - - value = CONTROL_PBIAS_LITE; - CONTROL_PBIAS_LITE = value | (1 << 2) | (1 << 1) | (1 << 9); - - value = CONTROL_DEV_CONF0; - CONTROL_DEV_CONF0 = value | (1 << 24); - - return 1; -} - -void mmc_init_stream(void) -{ - volatile unsigned int mmc_stat; - - OMAP_HSMMC_CON |= INIT_INITSTREAM; - - OMAP_HSMMC_CMD = MMC_CMD0; - do { - mmc_stat = OMAP_HSMMC_STAT; - } while (!(mmc_stat & CC_MASK)); - - OMAP_HSMMC_STAT = CC_MASK; - - OMAP_HSMMC_CMD = MMC_CMD0; - do { - mmc_stat = OMAP_HSMMC_STAT; - } while (!(mmc_stat & CC_MASK)); - - OMAP_HSMMC_STAT = OMAP_HSMMC_STAT; - OMAP_HSMMC_CON &= ~INIT_INITSTREAM; -} - -unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) -{ - unsigned int val; - - mmc_reg_out(OMAP_HSMMC_SYSCTL, (ICE_MASK | DTO_MASK | CEN_MASK), - (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); - - switch (iclk) { - case CLK_INITSEQ: - val = MMC_INIT_SEQ_CLK / 2; - break; - case CLK_400KHZ: - val = MMC_400kHz_CLK; - break; - case CLK_MISC: - val = clk_div; - break; - default: - return 0; - } - mmc_reg_out(OMAP_HSMMC_SYSCTL, - ICE_MASK | CLKD_MASK, (val << CLKD_OFFSET) | ICE_OSCILLATE); - - while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY) { - } - - OMAP_HSMMC_SYSCTL |= CEN_ENABLE; - return 1; -} - -unsigned char mmc_init_setup(void) -{ - unsigned int reg_val; - - mmc_board_init(); - - OMAP_HSMMC_SYSCONFIG |= MMC_SOFTRESET; - while ((OMAP_HSMMC_SYSSTATUS & RESETDONE) == 0) ; - - OMAP_HSMMC_SYSCTL |= SOFTRESETALL; - while ((OMAP_HSMMC_SYSCTL & SOFTRESETALL) != 0x0) ; - - OMAP_HSMMC_HCTL = DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0; - OMAP_HSMMC_CAPA |= VS30_3V0SUP | VS18_1V8SUP; - - reg_val = OMAP_HSMMC_CON & RESERVED_MASK; - - OMAP_HSMMC_CON = CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | - CDP_ACTIVEHIGH | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | - STR_BLOCK | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN; - - mmc_clock_config(CLK_INITSEQ, 0); - OMAP_HSMMC_HCTL |= SDBP_PWRON; - - OMAP_HSMMC_IE = 0x307f0033; - - mmc_init_stream(); - return 1; -} - -unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, - unsigned int *response) -{ - volatile unsigned int mmc_stat; - - while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS) { - } - - OMAP_HSMMC_BLK = BLEN_512BYTESLEN | NBLK_STPCNT; - OMAP_HSMMC_STAT = 0xFFFFFFFF; - OMAP_HSMMC_ARG = arg; - OMAP_HSMMC_CMD = cmd | CMD_TYPE_NORMAL | CICE_NOCHECK | - CCCE_NOCHECK | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | - DE_DISABLE; - - while (1) { - do { - mmc_stat = OMAP_HSMMC_STAT; - } while (mmc_stat == 0); - - if ((mmc_stat & ERRI_MASK) != 0) - return (unsigned char) mmc_stat; - - if (mmc_stat & CC_MASK) { - OMAP_HSMMC_STAT = CC_MASK; - response[0] = OMAP_HSMMC_RSP10; - if ((cmd & RSP_TYPE_MASK) == RSP_TYPE_LGHT136) { - response[1] = OMAP_HSMMC_RSP32; - response[2] = OMAP_HSMMC_RSP54; - response[3] = OMAP_HSMMC_RSP76; - } - break; - } - } - return 1; -} - -unsigned char mmc_read_data(unsigned int *output_buf) -{ - volatile unsigned int mmc_stat; - unsigned int read_count = 0; - - /* - * Start Polled Read - */ - while (1) { - do { - mmc_stat = OMAP_HSMMC_STAT; - } while (mmc_stat == 0); - - if ((mmc_stat & ERRI_MASK) != 0) - return (unsigned char) mmc_stat; - - if (mmc_stat & BRR_MASK) { - unsigned int k; - - OMAP_HSMMC_STAT |= BRR_MASK; - for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) { - *output_buf = OMAP_HSMMC_DATA; - output_buf++; - read_count += 4; - } - } - - if (mmc_stat & BWR_MASK) - OMAP_HSMMC_STAT |= BWR_MASK; - - if (mmc_stat & TC_MASK) { - OMAP_HSMMC_STAT |= TC_MASK; - break; - } - } - return 1; -} - -unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) -{ - unsigned char err; - unsigned int argument = 0; - unsigned int ocr_value, ocr_recvd, ret_cmd41, hcs_val; - unsigned int resp[4]; - unsigned short retry_cnt = 2000; - - /* Set to Initialization Clock */ - err = mmc_clock_config(CLK_400KHZ, 0); - if (err != 1) - return err; - - mmc_card_cur->RCA = MMC_RELATIVE_CARD_ADDRESS; - argument = 0x00000000; - - ocr_value = (0x1FF << 15); - err = mmc_send_cmd(MMC_CMD0, argument, resp); - if (err != 1) - return err; - - argument = SD_CMD8_CHECK_PATTERN | SD_CMD8_2_7_3_6_V_RANGE; - err = mmc_send_cmd(MMC_SDCMD8, argument, resp); - hcs_val = (err == 1) ? - MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR : - MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE; - - argument = 0x0000 << 16; - err = mmc_send_cmd(MMC_CMD55, argument, resp); - if (err == 1) { - mmc_card_cur->card_type = SD_CARD; - ocr_value |= hcs_val; - ret_cmd41 = MMC_ACMD41; - } else { - mmc_card_cur->card_type = MMC_CARD; - ocr_value |= MMC_OCR_REG_ACCESS_MODE_SECTOR; - ret_cmd41 = MMC_CMD1; - OMAP_HSMMC_CON &= ~OD; - OMAP_HSMMC_CON |= OPENDRAIN; - } - - argument = ocr_value; - err = mmc_send_cmd(ret_cmd41, argument, resp); - if (err != 1) - return err; - - ocr_recvd = ((mmc_resp_r3 *) resp)->ocr; - - while (!(ocr_recvd & (0x1 << 31)) && (retry_cnt > 0)) { - retry_cnt--; - if (mmc_card_cur->card_type == SD_CARD) { - argument = 0x0000 << 16; - err = mmc_send_cmd(MMC_CMD55, argument, resp); - } - - argument = ocr_value; - err = mmc_send_cmd(ret_cmd41, argument, resp); - if (err != 1) - return err; - ocr_recvd = ((mmc_resp_r3 *) resp)->ocr; - } - - if (!(ocr_recvd & (0x1 << 31))) - return 0; - - if (mmc_card_cur->card_type == MMC_CARD) { - if ((ocr_recvd & MMC_OCR_REG_ACCESS_MODE_MASK) == - MMC_OCR_REG_ACCESS_MODE_SECTOR) { - mmc_card_cur->mode = SECTOR_MODE; - } else { - mmc_card_cur->mode = BYTE_MODE; - } - - ocr_recvd &= ~MMC_OCR_REG_ACCESS_MODE_MASK; - } else { - if ((ocr_recvd & MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK) - == MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR) { - mmc_card_cur->mode = SECTOR_MODE; - } else { - mmc_card_cur->mode = BYTE_MODE; - } - ocr_recvd &= ~MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK; - } - - ocr_recvd &= ~(0x1 << 31); - if (!(ocr_recvd & ocr_value)) - return 0; - - err = mmc_send_cmd(MMC_CMD2, argument, resp); - if (err != 1) - return err; - - if (mmc_card_cur->card_type == MMC_CARD) { - argument = mmc_card_cur->RCA << 16; - err = mmc_send_cmd(MMC_CMD3, argument, resp); - if (err != 1) - return err; - } else { - argument = 0x00000000; - err = mmc_send_cmd(MMC_SDCMD3, argument, resp); - if (err != 1) - return err; - - mmc_card_cur->RCA = ((mmc_resp_r6 *) resp)->newpublishedrca; - } - - OMAP_HSMMC_CON &= ~OD; - OMAP_HSMMC_CON |= NOOPENDRAIN; - return 1; -} - -unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, - mmc_csd_reg_t *cur_csd) -{ - mmc_extended_csd_reg_t ext_csd; - unsigned int size, count, blk_len, blk_no, card_size, argument; - unsigned char err; - unsigned int resp[4]; - - if (mmc_dev_data->mode == SECTOR_MODE) { - if (mmc_dev_data->card_type == SD_CARD) { - card_size = - (((mmc_sd2_csd_reg_t *) cur_csd)-> - c_size_lsb & MMC_SD2_CSD_C_SIZE_LSB_MASK) | - ((((mmc_sd2_csd_reg_t *) cur_csd)-> - c_size_msb & MMC_SD2_CSD_C_SIZE_MSB_MASK) - << MMC_SD2_CSD_C_SIZE_MSB_OFFSET); - mmc_dev_data->size = card_size * 1024; - if (mmc_dev_data->size == 0) - return 0; - } else { - argument = 0x00000000; - err = mmc_send_cmd(MMC_CMD8, argument, resp); - if (err != 1) - return err; - err = mmc_read_data((unsigned int *) &ext_csd); - if (err != 1) - return err; - mmc_dev_data->size = ext_csd.sectorcount; - - if (mmc_dev_data->size == 0) - mmc_dev_data->size = 8388608; - } - } else { - if (cur_csd->c_size_mult >= 8) - return 0; - - if (cur_csd->read_bl_len >= 12) - return 0; - - /* Compute size */ - count = 1 << (cur_csd->c_size_mult + 2); - card_size = (cur_csd->c_size_lsb & MMC_CSD_C_SIZE_LSB_MASK) | - ((cur_csd->c_size_msb & MMC_CSD_C_SIZE_MSB_MASK) - << MMC_CSD_C_SIZE_MSB_OFFSET); - blk_no = (card_size + 1) * count; - blk_len = 1 << cur_csd->read_bl_len; - size = blk_no * blk_len; - mmc_dev_data->size = size / MMCSD_SECTOR_SIZE; - if (mmc_dev_data->size == 0) - return 0; - } - return 1; -} - -unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes, - mmc_card_data *mmc_c, - unsigned long *output_buf) -{ - unsigned char err; - unsigned int argument; - unsigned int resp[4]; - unsigned int num_sec_val = - (num_bytes + (MMCSD_SECTOR_SIZE - 1)) / MMCSD_SECTOR_SIZE; - unsigned int sec_inc_val; - - if (num_sec_val == 0) - return 1; - - if (mmc_c->mode == SECTOR_MODE) { - argument = start_sec; - sec_inc_val = 1; - } else { - argument = start_sec * MMCSD_SECTOR_SIZE; - sec_inc_val = MMCSD_SECTOR_SIZE; - } - - while (num_sec_val) { - err = mmc_send_cmd(MMC_CMD17, argument, resp); - if (err != 1) - return err; - - err = mmc_read_data((unsigned int *) output_buf); - if (err != 1) - return err; - - output_buf += (MMCSD_SECTOR_SIZE / 4); - argument += sec_inc_val; - num_sec_val--; - } - return 1; -} - -unsigned char configure_mmc(mmc_card_data *mmc_card_cur) -{ - unsigned char ret_val; - unsigned int argument; - unsigned int resp[4]; - unsigned int trans_clk, trans_fact, trans_unit, retries = 2; - mmc_csd_reg_t Card_CSD; - unsigned char trans_speed; - - ret_val = mmc_init_setup(); - - if (ret_val != 1) - return ret_val; - - do { - ret_val = mmc_detect_card(mmc_card_cur); - retries--; - } while ((retries > 0) && (ret_val != 1)); - - argument = mmc_card_cur->RCA << 16; - ret_val = mmc_send_cmd(MMC_CMD9, argument, resp); - if (ret_val != 1) - return ret_val; - - ((unsigned int *) &Card_CSD)[3] = resp[3]; - ((unsigned int *) &Card_CSD)[2] = resp[2]; - ((unsigned int *) &Card_CSD)[1] = resp[1]; - ((unsigned int *) &Card_CSD)[0] = resp[0]; - - if (mmc_card_cur->card_type == MMC_CARD) - mmc_card_cur->version = Card_CSD.spec_vers; - - trans_speed = Card_CSD.tran_speed; - - ret_val = mmc_send_cmd(MMC_CMD4, MMC_DSR_DEFAULT << 16, resp); - if (ret_val != 1) - return ret_val; - - trans_unit = trans_speed & MMC_CSD_TRAN_SPEED_UNIT_MASK; - trans_fact = trans_speed & MMC_CSD_TRAN_SPEED_FACTOR_MASK; - - if (trans_unit > MMC_CSD_TRAN_SPEED_UNIT_100MHZ) - return 0; - - if ((trans_fact < MMC_CSD_TRAN_SPEED_FACTOR_1_0) || - (trans_fact > MMC_CSD_TRAN_SPEED_FACTOR_8_0)) - return 0; - - trans_unit >>= 0; - trans_fact >>= 3; - - trans_clk = mmc_transspeed_val[trans_fact - 1][trans_unit] * 2; - ret_val = mmc_clock_config(CLK_MISC, trans_clk); - - if (ret_val != 1) - return ret_val; - - argument = mmc_card_cur->RCA << 16; - ret_val = mmc_send_cmd(MMC_CMD7_SELECT, argument, resp); - if (ret_val != 1) - return ret_val; - - /* Configure the block length to 512 bytes */ - argument = MMCSD_SECTOR_SIZE; - ret_val = mmc_send_cmd(MMC_CMD16, argument, resp); - if (ret_val != 1) - return ret_val; - - /* get the card size in sectors */ - ret_val = mmc_read_cardsize(mmc_card_cur, &Card_CSD); - if (ret_val != 1) - return ret_val; - - return 1; -} -unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt, - void *dst) -{ - omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data, - (unsigned long *) dst); - return 1; -} - -int mmc_init(int verbose) -{ - unsigned char ret; - - ret = configure_mmc(&cur_card_data); - - if (ret == 1) { - mmc_blk_dev.if_type = IF_TYPE_MMC; - mmc_blk_dev.part_type = PART_TYPE_DOS; - mmc_blk_dev.dev = 0; - mmc_blk_dev.lun = 0; - mmc_blk_dev.type = 0; - - /* FIXME fill in the correct size (is set to 32MByte) */ - mmc_blk_dev.blksz = MMCSD_SECTOR_SIZE; - mmc_blk_dev.lba = 0x10000; - mmc_blk_dev.removable = 0; - mmc_blk_dev.block_read = mmc_bread; - - fat_register_device(&mmc_blk_dev, 1); - return 1; - } - else - return 0; -} - -int mmc_read(ulong src, uchar *dst, int size) -{ - return 0; -} - -int mmc_write(uchar *src, ulong dst, int size) -{ - return 0; -} - -int mmc2info(ulong addr) -{ - return 0; -} diff --git a/x-loader/cpu/omap3/start.S b/x-loader/cpu/omap3/start.S deleted file mode 100644 index 4cbf437..0000000 --- a/x-loader/cpu/omap3/start.S +++ /dev/null @@ -1,224 +0,0 @@ -/* - * armboot - Startup Code for OMP2420/ARM1136 CPU-core - * - * Copyright (c) 2004-2006 Texas Instruments - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * Copyright (c) 2004 Jian Zhang - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -.globl _start -_start: - b reset - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - -_hang: - .word do_hang - - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 /* now 16*4=64 */ - -.global _end_vect -_end_vect: - - .balignl 16,0xdeadbeef -/* - ************************************************************************* - * - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * setup Memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack - * - ************************************************************************* - */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - -/* - * These are defined in the board-specific linker script. - */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end - -/* - * the actual reset code - */ - -reset: - /* - * set the cpu to SVC32 mode - */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - - /* Copy vectors to mask ROM indirect addr */ - adr r0, _start /* r0 <- current position of code */ - add r0, r0, #4 /* skip reset vector */ - mov r2, #64 /* r2 <- size to copy */ - add r2, r0, r2 /* r2 <- source end address */ - mov r1, #SRAM_OFFSET0 /* build vect addr */ - mov r3, #SRAM_OFFSET1 - add r1, r1, r3 - mov r3, #SRAM_OFFSET2 - add r1, r1, r3 -next: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - bne next /* loop until equal */ - - bl cpy_clk_code /* put dpll adjust code behind vectors */ - - /* the mask ROM code should have PLL and others stable */ - bl cpu_init_crit - -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* no need to relocate if XIP */ - beq stack_setup /* skip txt cpy if XIP(SRAM, SDRAM) */ - - ldr r2, _armboot_start - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ - -copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ - ble copy_loop - - /* Set up the stack */ -stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub sp, r0, #128 /* leave 32 words for abort-stack */ - and sp, sp, #~7 /* 8 byte alinged for (ldr/str)d */ - - /* Clear BSS (if any). Is below tx (watch load addr - need space) */ -clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear value */ -clbss_l: - str r2, [r0] /* clear BSS location */ - cmp r0, r1 /* are we at the end yet */ - add r0, r0, #4 /* increment clear index pointer */ - bne clbss_l /* keep clearing till at end */ - - ldr pc, _start_armboot /* jump to C code */ - -_start_armboot: .word start_armboot - - -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ -cpu_init_crit: - /* - * Invalidate L1 I/D - */ - mov r0, #0 /* set up for MCR */ - mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ - mcr p15, 0, r0, c7, c5, 1 /* invalidate icache */ - - /* Invalide L2 cache (gp device call point) - * - warning, this may have issues on EMU/HS devices - * this call can corrupt r0-r5 - */ - mov r12, #0x1 @ set up to invalide L2 -smi: .word 0xE1600070 @ Call SMI monitor - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002000 @ clear bits 13 (--V-) - bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) - orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align -#ifndef CONFIG_ICACHE_OFF - orr r0, r0, #0x00001800 @ set bit 11,12 (---I Z---) BTB,I-Cache -#endif - mcr p15, 0, r0, c1, c0, 0 - - /* - * Jump to board specific initialization... The Mask ROM will have already initialized - * basic memory. Go here to bump up clock rate and handle wake up conditions. - */ - adr r0, _start /* r0 <- current position of code */ - ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* pass on info about skipping some init portions */ - moveq r0,#0x1 /* flag to skip prcm and sdrc setup */ - movne r0,#0x0 - - mov ip, lr /* persevere link reg across call */ - bl lowlevel_init /* go setup pll,mux,memory */ - mov lr, ip /* restore link */ - mov pc, lr /* back to my caller */ - -/* - * exception handler - */ - .align 5 -do_hang: - ldr sp, _TEXT_BASE /* use 32 words abort stack */ - bl hang /* hang and never return */ - diff --git a/x-loader/cpu/omap4/Makefile b/x-loader/cpu/omap4/Makefile deleted file mode 100644 index 0b39db0..0000000 --- a/x-loader/cpu/omap4/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2009 -# Texas Instruments, -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(CPU).a - -START = start.o -COBJS = cpu.o mmc.o sys_info.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/cpu/omap4/config.mk b/x-loader/cpu/omap4/config.mk deleted file mode 100644 index 20972b5..0000000 --- a/x-loader/cpu/omap4/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ - -msoft-float - -PLATFORM_CPPFLAGS += -march=armv7-a -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/x-loader/cpu/omap4/cpu.c b/x-loader/cpu/omap4/cpu.c deleted file mode 100644 index 698bbdf..0000000 --- a/x-loader/cpu/omap4/cpu.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2004-2009 Texas Insturments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * CPU specific code - */ - -#include -#include - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_WB (1<<3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ - -int cpu_init (void) -{ - return 0; -} - -unsigned int cortex_a9_rev(void) -{ - - unsigned int i; - - /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (i)); - - return i; -} - -unsigned int omap_revision(void) -{ - unsigned int rev = cortex_a9_rev(); - - switch(rev) { - case 0x410FC091: - return OMAP4430_ES1_0; - case 0x411FC092: - if (__raw_readl(0x4a002204) == 0x3b95c02f) - return OMAP4430_ES2_1; - else - return OMAP4430_ES2_0; - default: - return OMAP4430_SILICON_ID_INVALID; - } -} diff --git a/x-loader/cpu/omap4/mmc.c b/x-loader/cpu/omap4/mmc.c deleted file mode 100644 index 6842402..0000000 --- a/x-loader/cpu/omap4/mmc.c +++ /dev/null @@ -1,547 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -const unsigned short mmc_transspeed_val[15][4] = { - {CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)}, - {CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)}, - {CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)}, - {CLKD(15, 1), CLKD(15, 10), CLKD(15, 100), CLKD(15, 1000)}, - {CLKD(20, 1), CLKD(20, 10), CLKD(20, 100), CLKD(20, 1000)}, - {CLKD(26, 1), CLKD(26, 10), CLKD(26, 100), CLKD(26, 1000)}, - {CLKD(30, 1), CLKD(30, 10), CLKD(30, 100), CLKD(30, 1000)}, - {CLKD(35, 1), CLKD(35, 10), CLKD(35, 100), CLKD(35, 1000)}, - {CLKD(40, 1), CLKD(40, 10), CLKD(40, 100), CLKD(40, 1000)}, - {CLKD(45, 1), CLKD(45, 10), CLKD(45, 100), CLKD(45, 1000)}, - {CLKD(52, 1), CLKD(52, 10), CLKD(52, 100), CLKD(52, 1000)}, - {CLKD(55, 1), CLKD(55, 10), CLKD(55, 100), CLKD(55, 1000)}, - {CLKD(60, 1), CLKD(60, 10), CLKD(60, 100), CLKD(60, 1000)}, - {CLKD(70, 1), CLKD(70, 10), CLKD(70, 100), CLKD(70, 1000)}, - {CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)} -}; - -mmc_card_data cur_card_data; -static block_dev_desc_t mmc_blk_dev; - -block_dev_desc_t *mmc_get_dev(int dev) -{ - return ((block_dev_desc_t *) &mmc_blk_dev); -} - -unsigned char mmc_board_init(void) -{ - unsigned int value = 0; - - return 1; -} - -void mmc_init_stream(void) -{ - volatile unsigned int mmc_stat; - - OMAP_HSMMC_CON |= INIT_INITSTREAM; - - OMAP_HSMMC_CMD = MMC_CMD0; - do { - mmc_stat = OMAP_HSMMC_STAT; - } while (!(mmc_stat & CC_MASK)); - - OMAP_HSMMC_STAT = CC_MASK; - - OMAP_HSMMC_CMD = MMC_CMD0; - do { - mmc_stat = OMAP_HSMMC_STAT; - } while (!(mmc_stat & CC_MASK)); - - OMAP_HSMMC_STAT = OMAP_HSMMC_STAT; - OMAP_HSMMC_CON &= ~INIT_INITSTREAM; -} - -unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) -{ - unsigned int val; - - mmc_reg_out(OMAP_HSMMC_SYSCTL, (ICE_MASK | DTO_MASK | CEN_MASK), - (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); - - switch (iclk) { - case CLK_INITSEQ: - val = MMC_INIT_SEQ_CLK / 2; - break; - case CLK_400KHZ: - val = MMC_400kHz_CLK; - break; - case CLK_MISC: - val = clk_div; - break; - default: - return 0; - } - mmc_reg_out(OMAP_HSMMC_SYSCTL, - ICE_MASK | CLKD_MASK, (val << CLKD_OFFSET) | ICE_OSCILLATE); - - while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY) { - } - - OMAP_HSMMC_SYSCTL |= CEN_ENABLE; - return 1; -} - -unsigned char mmc_init_setup(void) -{ - unsigned int reg_val; - - mmc_board_init(); - - OMAP_HSMMC_SYSCONFIG |= MMC_SOFTRESET; - while ((OMAP_HSMMC_SYSSTATUS & RESETDONE) == 0) ; - - OMAP_HSMMC_SYSCTL |= SOFTRESETALL; - while ((OMAP_HSMMC_SYSCTL & SOFTRESETALL) != 0x0) ; - - OMAP_HSMMC_HCTL = DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0; - OMAP_HSMMC_CAPA |= VS30_3V0SUP | VS18_1V8SUP; - - reg_val = OMAP_HSMMC_CON & RESERVED_MASK; - - OMAP_HSMMC_CON = CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | - CDP_ACTIVEHIGH | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | - STR_BLOCK | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN; - - mmc_clock_config(CLK_INITSEQ, 0); - OMAP_HSMMC_HCTL |= SDBP_PWRON; - - OMAP_HSMMC_IE = 0x307f0033; - - mmc_init_stream(); - return 1; -} - -unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, - unsigned int *response) -{ - volatile unsigned int mmc_stat; - - while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS) { - } - - OMAP_HSMMC_BLK = BLEN_512BYTESLEN | NBLK_STPCNT; - OMAP_HSMMC_STAT = 0xFFFFFFFF; - OMAP_HSMMC_ARG = arg; - OMAP_HSMMC_CMD = cmd | CMD_TYPE_NORMAL | CICE_NOCHECK | - CCCE_NOCHECK | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | - DE_DISABLE; - - while (1) { - do { - mmc_stat = OMAP_HSMMC_STAT; - } while (mmc_stat == 0); - - if ((mmc_stat & ERRI_MASK) != 0) - return (unsigned char) mmc_stat; - - if (mmc_stat & CC_MASK) { - OMAP_HSMMC_STAT = CC_MASK; - response[0] = OMAP_HSMMC_RSP10; - if ((cmd & RSP_TYPE_MASK) == RSP_TYPE_LGHT136) { - response[1] = OMAP_HSMMC_RSP32; - response[2] = OMAP_HSMMC_RSP54; - response[3] = OMAP_HSMMC_RSP76; - } - break; - } - } - return 1; -} - -unsigned char mmc_read_data(unsigned int *output_buf) -{ - volatile unsigned int mmc_stat; - unsigned int read_count = 0; - - /* - * Start Polled Read - */ - while (1) { - do { - mmc_stat = OMAP_HSMMC_STAT; - } while (mmc_stat == 0); - - if ((mmc_stat & ERRI_MASK) != 0) - return (unsigned char) mmc_stat; - - if (mmc_stat & BRR_MASK) { - unsigned int k; - - OMAP_HSMMC_STAT |= BRR_MASK; - for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) { - *output_buf = OMAP_HSMMC_DATA; - output_buf++; - read_count += 4; - } - } - - if (mmc_stat & BWR_MASK) - OMAP_HSMMC_STAT |= BWR_MASK; - - if (mmc_stat & TC_MASK) { - OMAP_HSMMC_STAT |= TC_MASK; - break; - } - } - return 1; -} - -unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) -{ - unsigned char err; - unsigned int argument = 0; - unsigned int ocr_value, ocr_recvd, ret_cmd41, hcs_val; - unsigned int resp[4]; - unsigned short retry_cnt = 2000; - - /* Set to Initialization Clock */ - err = mmc_clock_config(CLK_400KHZ, 0); - if (err != 1) - return err; - - mmc_card_cur->RCA = MMC_RELATIVE_CARD_ADDRESS; - argument = 0x00000000; - - ocr_value = (0x1FF << 15); - err = mmc_send_cmd(MMC_CMD0, argument, resp); - if (err != 1) - return err; - - argument = SD_CMD8_CHECK_PATTERN | SD_CMD8_2_7_3_6_V_RANGE; - err = mmc_send_cmd(MMC_SDCMD8, argument, resp); - hcs_val = (err == 1) ? - MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR : - MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE; - - argument = 0x0000 << 16; - err = mmc_send_cmd(MMC_CMD55, argument, resp); - if (err == 1) { - mmc_card_cur->card_type = SD_CARD; - ocr_value |= hcs_val; - ret_cmd41 = MMC_ACMD41; - } else { - mmc_card_cur->card_type = MMC_CARD; - ocr_value |= MMC_OCR_REG_ACCESS_MODE_SECTOR; - ret_cmd41 = MMC_CMD1; - OMAP_HSMMC_CON &= ~OD; - OMAP_HSMMC_CON |= OPENDRAIN; - } - - argument = ocr_value; - err = mmc_send_cmd(ret_cmd41, argument, resp); - if (err != 1) - return err; - - ocr_recvd = ((mmc_resp_r3 *) resp)->ocr; - - while (!(ocr_recvd & (0x1 << 31)) && (retry_cnt > 0)) { - retry_cnt--; - if (mmc_card_cur->card_type == SD_CARD) { - argument = 0x0000 << 16; - err = mmc_send_cmd(MMC_CMD55, argument, resp); - } - - argument = ocr_value; - err = mmc_send_cmd(ret_cmd41, argument, resp); - if (err != 1) - return err; - ocr_recvd = ((mmc_resp_r3 *) resp)->ocr; - } - - if (!(ocr_recvd & (0x1 << 31))) - return 0; - - if (mmc_card_cur->card_type == MMC_CARD) { - if ((ocr_recvd & MMC_OCR_REG_ACCESS_MODE_MASK) == - MMC_OCR_REG_ACCESS_MODE_SECTOR) { - mmc_card_cur->mode = SECTOR_MODE; - } else { - mmc_card_cur->mode = BYTE_MODE; - } - - ocr_recvd &= ~MMC_OCR_REG_ACCESS_MODE_MASK; - } else { - if ((ocr_recvd & MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK) - == MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR) { - mmc_card_cur->mode = SECTOR_MODE; - } else { - mmc_card_cur->mode = BYTE_MODE; - } - ocr_recvd &= ~MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK; - } - - ocr_recvd &= ~(0x1 << 31); - if (!(ocr_recvd & ocr_value)) - return 0; - - err = mmc_send_cmd(MMC_CMD2, argument, resp); - if (err != 1) - return err; - - if (mmc_card_cur->card_type == MMC_CARD) { - argument = mmc_card_cur->RCA << 16; - err = mmc_send_cmd(MMC_CMD3, argument, resp); - if (err != 1) - return err; - } else { - argument = 0x00000000; - err = mmc_send_cmd(MMC_SDCMD3, argument, resp); - if (err != 1) - return err; - - mmc_card_cur->RCA = ((mmc_resp_r6 *) resp)->newpublishedrca; - } - - OMAP_HSMMC_CON &= ~OD; - OMAP_HSMMC_CON |= NOOPENDRAIN; - return 1; -} - -unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, - mmc_csd_reg_t *cur_csd) -{ - mmc_extended_csd_reg_t ext_csd; - unsigned int size, count, blk_len, blk_no, card_size, argument; - unsigned char err; - unsigned int resp[4]; - - if (mmc_dev_data->mode == SECTOR_MODE) { - if (mmc_dev_data->card_type == SD_CARD) { - card_size = - (((mmc_sd2_csd_reg_t *) cur_csd)-> - c_size_lsb & MMC_SD2_CSD_C_SIZE_LSB_MASK) | - ((((mmc_sd2_csd_reg_t *) cur_csd)-> - c_size_msb & MMC_SD2_CSD_C_SIZE_MSB_MASK) - << MMC_SD2_CSD_C_SIZE_MSB_OFFSET); - mmc_dev_data->size = card_size * 1024; - if (mmc_dev_data->size == 0) - return 0; - } else { - argument = 0x00000000; - err = mmc_send_cmd(MMC_CMD8, argument, resp); - if (err != 1) - return err; - err = mmc_read_data((unsigned int *) &ext_csd); - if (err != 1) - return err; - mmc_dev_data->size = ext_csd.sectorcount; - - if (mmc_dev_data->size == 0) - mmc_dev_data->size = 8388608; - } - } else { - if (cur_csd->c_size_mult >= 8) - return 0; - - if (cur_csd->read_bl_len >= 12) - return 0; - - /* Compute size */ - count = 1 << (cur_csd->c_size_mult + 2); - card_size = (cur_csd->c_size_lsb & MMC_CSD_C_SIZE_LSB_MASK) | - ((cur_csd->c_size_msb & MMC_CSD_C_SIZE_MSB_MASK) - << MMC_CSD_C_SIZE_MSB_OFFSET); - blk_no = (card_size + 1) * count; - blk_len = 1 << cur_csd->read_bl_len; - size = blk_no * blk_len; - mmc_dev_data->size = size / MMCSD_SECTOR_SIZE; - if (mmc_dev_data->size == 0) - return 0; - } - return 1; -} - -unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes, - mmc_card_data *mmc_c, - unsigned long *output_buf) -{ - unsigned char err; - unsigned int argument; - unsigned int resp[4]; - unsigned int num_sec_val = - (num_bytes + (MMCSD_SECTOR_SIZE - 1)) / MMCSD_SECTOR_SIZE; - unsigned int sec_inc_val; - - if (num_sec_val == 0) - return 1; - - if (mmc_c->mode == SECTOR_MODE) { - argument = start_sec; - sec_inc_val = 1; - } else { - argument = start_sec * MMCSD_SECTOR_SIZE; - sec_inc_val = MMCSD_SECTOR_SIZE; - } - - while (num_sec_val) { - err = mmc_send_cmd(MMC_CMD17, argument, resp); - if (err != 1) - return err; - - err = mmc_read_data((unsigned int *) output_buf); - if (err != 1) - return err; - - output_buf += (MMCSD_SECTOR_SIZE / 4); - argument += sec_inc_val; - num_sec_val--; - } - return 1; -} - -unsigned char configure_mmc(mmc_card_data *mmc_card_cur) -{ - unsigned char ret_val; - unsigned int argument; - unsigned int resp[4]; - unsigned int trans_clk, trans_fact, trans_unit, retries = 2; - mmc_csd_reg_t Card_CSD; - unsigned char trans_speed; - - ret_val = mmc_init_setup(); - - if (ret_val != 1) - return ret_val; - - do { - ret_val = mmc_detect_card(mmc_card_cur); - retries--; - } while ((retries > 0) && (ret_val != 1)); - - argument = mmc_card_cur->RCA << 16; - ret_val = mmc_send_cmd(MMC_CMD9, argument, resp); - if (ret_val != 1) - return ret_val; - - ((unsigned int *) &Card_CSD)[3] = resp[3]; - ((unsigned int *) &Card_CSD)[2] = resp[2]; - ((unsigned int *) &Card_CSD)[1] = resp[1]; - ((unsigned int *) &Card_CSD)[0] = resp[0]; - - if (mmc_card_cur->card_type == MMC_CARD) - mmc_card_cur->version = Card_CSD.spec_vers; - - trans_speed = Card_CSD.tran_speed; - - ret_val = mmc_send_cmd(MMC_CMD4, MMC_DSR_DEFAULT << 16, resp); - if (ret_val != 1) - return ret_val; - - trans_unit = trans_speed & MMC_CSD_TRAN_SPEED_UNIT_MASK; - trans_fact = trans_speed & MMC_CSD_TRAN_SPEED_FACTOR_MASK; - - if (trans_unit > MMC_CSD_TRAN_SPEED_UNIT_100MHZ) - return 0; - - if ((trans_fact < MMC_CSD_TRAN_SPEED_FACTOR_1_0) || - (trans_fact > MMC_CSD_TRAN_SPEED_FACTOR_8_0)) - return 0; - - trans_unit >>= 0; - trans_fact >>= 3; - - trans_clk = mmc_transspeed_val[trans_fact - 1][trans_unit] * 2; - ret_val = mmc_clock_config(CLK_MISC, trans_clk); - - if (ret_val != 1) - return ret_val; - - argument = mmc_card_cur->RCA << 16; - ret_val = mmc_send_cmd(MMC_CMD7_SELECT, argument, resp); - if (ret_val != 1) - return ret_val; - - /* Configure the block length to 512 bytes */ - argument = MMCSD_SECTOR_SIZE; - ret_val = mmc_send_cmd(MMC_CMD16, argument, resp); - if (ret_val != 1) - return ret_val; - - /* get the card size in sectors */ - ret_val = mmc_read_cardsize(mmc_card_cur, &Card_CSD); - if (ret_val != 1) - return ret_val; - - return 1; -} -unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt, - void *dst) -{ - omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data, - (unsigned long *) dst); - return 1; -} - -int mmc_init(int verbose) -{ - unsigned char ret; - - ret = configure_mmc(&cur_card_data); - - if (ret == 1) { - mmc_blk_dev.if_type = IF_TYPE_MMC; - mmc_blk_dev.part_type = PART_TYPE_DOS; - mmc_blk_dev.dev = 0; - mmc_blk_dev.lun = 0; - mmc_blk_dev.type = 0; - - /* FIXME fill in the correct size (is set to 32MByte) */ - mmc_blk_dev.blksz = MMCSD_SECTOR_SIZE; - mmc_blk_dev.lba = 0x10000; - mmc_blk_dev.removable = 0; - mmc_blk_dev.block_read = mmc_bread; - - fat_register_device(&mmc_blk_dev, 1); - return 1; - } - else - return 0; -} - -int mmc_read(ulong src, uchar *dst, int size) -{ - return 0; -} - -int mmc_write(uchar *src, ulong dst, int size) -{ - return 0; -} - -int mmc2info(ulong addr) -{ - return 0; -} diff --git a/x-loader/cpu/omap4/sys_info.c b/x-loader/cpu/omap4/sys_info.c deleted file mode 100644 index 29d39e6..0000000 --- a/x-loader/cpu/omap4/sys_info.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - - -/****************************************** - * get_cpu_rev(void) - extract version info - ******************************************/ -u32 get_cpu_rev(void) -{ - return CPU_4430_ES1; - -} - - diff --git a/x-loader/disk/Makefile b/x-loader/disk/Makefile deleted file mode 100644 index 512b1cb..0000000 --- a/x-loader/disk/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -#CFLAGS += -DET_DEBUG -DDEBUG - -LIB = $(obj)libdisk.a - -COBJS = part.o - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/disk/part.c b/x-loader/disk/part.c deleted file mode 100644 index a367f13..0000000 --- a/x-loader/disk/part.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#undef PART_DEBUG - -#ifdef PART_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ - (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ - (CONFIG_COMMANDS & CFG_CMD_USB) || \ - defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) ) - -/* ------------------------------------------------------------------------- */ -/* - * reports device info to the user - */ -void dev_print (block_dev_desc_t *dev_desc) -{ -#ifdef CONFIG_LBA48 - uint64_t lba512; /* number of blocks if 512bytes block size */ -#else - lbaint_t lba512; -#endif - - if (dev_desc->type==DEV_TYPE_UNKNOWN) { - return; - } - if (dev_desc->if_type==IF_TYPE_SCSI) { - printf ("(%d:%d) ", dev_desc->target,dev_desc->lun); - } - if (dev_desc->if_type==IF_TYPE_IDE) { - printf ("Model: %s Firm: %s Ser#: %s\n", - dev_desc->vendor, - dev_desc->revision, - dev_desc->product); - } else { - printf ("Vendor: %s Prod.: %s Rev: %s\n", - dev_desc->vendor, - dev_desc->product, - dev_desc->revision); - } - printf (" Type: "); - switch (dev_desc->type & 0x1F) { - case DEV_TYPE_HARDDISK: printf ("Hard Disk"); - break; - case DEV_TYPE_CDROM: printf ("CD ROM"); - break; - case DEV_TYPE_OPDISK: printf ("Optical Device"); - break; - case DEV_TYPE_TAPE: printf ("Tape"); - break; - default: printf ("# %02X #", dev_desc->type & 0x1F); - break; - } - if ((dev_desc->lba * dev_desc->blksz)>0L) { - ulong mb, mb_quot, mb_rem, gb, gb_quot, gb_rem; - lbaint_t lba; - - lba = dev_desc->lba; - - lba512 = (lba * (dev_desc->blksz/512)); - mb = (10 * lba512) / 2048; /* 2048 = (1024 * 1024) / 512 MB */ - /* round to 1 digit */ - mb_quot = mb / 10; - mb_rem = mb - (10 * mb_quot); - - gb = mb / 1024; - gb_quot = gb / 10; - gb_rem = gb - (10 * gb_quot); -#ifdef CONFIG_LBA48 - if (dev_desc->lba48) - printf (" Supports 48-bit addressing\n"); -#endif -#if defined(CFG_64BIT_LBA) && defined(CFG_64BIT_VSPRINTF) - printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%qd x %ld)\n", - mb_quot, mb_rem, - gb_quot, gb_rem, - lba, - dev_desc->blksz); -#else - printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\n", - mb_quot, mb_rem, - gb_quot, gb_rem, - (ulong)lba, - dev_desc->blksz); -#endif - } else { - printf (" Capacity: not available\n"); - } -} -#endif /* CFG_CMD_IDE || CFG_CMD_SCSI || CFG_CMD_USB || CONFIG_MMC */ - -#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ - (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ - (CONFIG_COMMANDS & CFG_CMD_USB) || \ - (CONFIG_COMMANDS & CFG_CMD_MMC) || \ - defined(CONFIG_SYSTEMACE) ) - -#if defined(CONFIG_MAC_PARTITION) || \ - defined(CONFIG_DOS_PARTITION) || \ - defined(CONFIG_ISO_PARTITION) || \ - defined(CONFIG_AMIGA_PARTITION) - -void init_part (block_dev_desc_t * dev_desc) -{ -#ifdef CONFIG_ISO_PARTITION - if (test_part_iso(dev_desc) == 0) { - dev_desc->part_type = PART_TYPE_ISO; - return; - } -#endif - -#ifdef CONFIG_MAC_PARTITION - if (test_part_mac(dev_desc) == 0) { - dev_desc->part_type = PART_TYPE_MAC; - return; - } -#endif - -#ifdef CONFIG_DOS_PARTITION - if (test_part_dos(dev_desc) == 0) { - dev_desc->part_type = PART_TYPE_DOS; - return; - } -#endif - -#ifdef CONFIG_AMIGA_PARTITION - if (test_part_amiga(dev_desc) == 0) { - dev_desc->part_type = PART_TYPE_AMIGA; - return; - } -#endif -} - - -int get_partition_info (block_dev_desc_t *dev_desc, int part, disk_partition_t *info) -{ - switch (dev_desc->part_type) { -#ifdef CONFIG_MAC_PARTITION - case PART_TYPE_MAC: - if (get_partition_info_mac(dev_desc,part,info) == 0) { - PRINTF ("## Valid MAC partition found ##\n"); - return (0); - } - break; -#endif - -#ifdef CONFIG_DOS_PARTITION - case PART_TYPE_DOS: - if (get_partition_info_dos(dev_desc,part,info) == 0) { - PRINTF ("## Valid DOS partition found ##\n"); - return (0); - } - break; -#endif - -#ifdef CONFIG_ISO_PARTITION - case PART_TYPE_ISO: - if (get_partition_info_iso(dev_desc,part,info) == 0) { - PRINTF ("## Valid ISO boot partition found ##\n"); - return (0); - } - break; -#endif - -#ifdef CONFIG_AMIGA_PARTITION - case PART_TYPE_AMIGA: - if (get_partition_info_amiga(dev_desc, part, info) == 0) - { - PRINTF ("## Valid Amiga partition found ##\n"); - return (0); - } - break; -#endif - default: - break; - } - return (-1); -} - -static void print_part_header (const char *type, block_dev_desc_t * dev_desc) -{ - switch (dev_desc->if_type) { - case IF_TYPE_IDE: printf ("IDE"); - break; - case IF_TYPE_SCSI: printf ("SCSI"); - break; - case IF_TYPE_ATAPI: printf ("ATAPI"); - break; - case IF_TYPE_USB: printf ("USB"); - break; - case IF_TYPE_DOC: printf ("DOC"); - break; - default: printf ("UNKNOWN"); - break; - } - printf (" device %d -- Partition Type: %s\n\n", - dev_desc->dev, type); -} - -void print_part (block_dev_desc_t * dev_desc) -{ - - switch (dev_desc->part_type) { -#ifdef CONFIG_MAC_PARTITION - case PART_TYPE_MAC: - PRINTF ("## Testing for valid MAC partition ##\n"); - print_part_header ("MAC", dev_desc); - print_part_mac (dev_desc); - return; -#endif -#ifdef CONFIG_DOS_PARTITION - case PART_TYPE_DOS: - PRINTF ("## Testing for valid DOS partition ##\n"); - print_part_header ("DOS", dev_desc); - print_part_dos (dev_desc); - return; -#endif - -#ifdef CONFIG_ISO_PARTITION - case PART_TYPE_ISO: - PRINTF ("## Testing for valid ISO Boot partition ##\n"); - print_part_header ("ISO", dev_desc); - print_part_iso (dev_desc); - return; -#endif - -#ifdef CONFIG_AMIGA_PARTITION - case PART_TYPE_AMIGA: - PRINTF ("## Testing for a valid Amiga partition ##\n"); - print_part_header ("AMIGA", dev_desc); - print_part_amiga (dev_desc); - return; -#endif - } -} - - -#else /* neither MAC nor DOS nor ISO partition configured */ -# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION nor CONFIG_ISO_PARTITION configured! -#endif - -#endif /* (CONFIG_COMMANDS & CFG_CMD_IDE) || CONFIG_COMMANDS & CFG_CMD_SCSI) */ diff --git a/x-loader/drivers/Makefile b/x-loader/drivers/Makefile deleted file mode 100644 index da3feda..0000000 --- a/x-loader/drivers/Makefile +++ /dev/null @@ -1,84 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -# CFLAGS += -DET_DEBUG -DDEBUG - -LIB = $(obj)libdrivers.a -COBJS = serial.o ns16550.o omap24xx_i2c.o - -ifeq ($(BOARD), omap3430sdp) -COBJS += k9f1g08r0a.o -endif - -ifeq ($(BOARD), omap3430labrador) -COBJS += k9f1g08r0a.o -endif - -ifeq ($(BOARD), omap3530beagle) -COBJS += k9f1g08r0a.o -endif - -ifeq ($(BOARD), omap3530gta04) -COBJS += k9f1g08r0a.o -endif - -ifeq ($(BOARD), omap3evm) -COBJS += k9f1g08r0a.o onenand.o -endif - -ifeq ($(BOARD), overo) -COBJS += k9f1g08r0a.o -endif - -ifeq ($(BOARD), omap2420h4) -COBJS += k9k1216.o -endif - -ifeq ($(BOARD), omap2430sdp) -COBJS += k9k1216.o -endif - -## Disabled for now: -## cs8900.o ct69000.o dataflash.o dc2114x.o ds1722.o \ -## lan91c96.o mw_eeprom.o natsemi.o \ -## smc91111.o smiLynxEM.o spi_eeprom.o sym53c8xx.o \ -## - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -all: $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/drivers/k9f1g08r0a.c b/x-loader/drivers/k9f1g08r0a.c deleted file mode 100644 index 988533c..0000000 --- a/x-loader/drivers/k9f1g08r0a.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - * (C) Copyright 2004 Texas Instruments - * Jian Zhang - * - * Samsung K9F1G08R0AQ0C NAND chip driver for an OMAP2420 board - * - * This file is based on the following u-boot file: - * common/cmd_nand.c - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#include -#include - -#ifdef CFG_NAND_K9F1G08R0A - -#define K9F1G08R0A_MFR 0xec /* Samsung */ -#define K9F1G08R0A_ID 0xa1 /* part # */ - -/* Since Micron and Samsung parts are similar in geometry and bus width - * we can use the same driver. Need to revisit to make this file independent - * of part/manufacturer - */ -#define MT29F1G_MFR 0x2c /* Micron */ -#define MT29F1G_MFR2 0x20 /* numonyx */ -#define MT29F1G_MFR3 0xad /* Hynix */ -#define MT29F1G_ID 0xa1 /* x8, 1GiB */ -#define MT29F2G_ID 0xba /* x16, 2GiB */ -#define MT29F4G_ID 0xbc /* x16, 4GiB */ - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE (ADDR_COLUMN | ADDR_PAGE) - -#define ADDR_OOB (0x4 | ADDR_COLUMN_PAGE) - -#define PAGE_SIZE 2048 -#define OOB_SIZE 64 -#define MAX_NUM_PAGES 64 - -#define ECC_CHECK_ENABLE -#define ECC_SIZE 24 -#define ECC_STEPS 3 - -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %0, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -static int nand_read_page(u_char *buf, ulong page_addr); -static int nand_read_oob(u_char * buf, ulong page_addr); - -/* JFFS2 large page layout for 3-byte ECC per 256 bytes ECC layout */ -/* This is the only SW ECC supported by u-boot. So to load u-boot - * this should be supported */ -static u_char ecc_pos[] = - {40, 41, 42, 43, 44, 45, 46, 47, - 48, 49, 50, 51, 52, 53, 54, 55, - 56, 57, 58, 59, 60, 61, 62, 63}; -static u_char eccvalid_pos = 4; - -static unsigned long chipsize = (256 << 20); - -#ifdef NAND_16BIT -static int bus_width = 16; -#else -static int bus_width = 8; -#endif - -/* NanD_Command: Send a flash command to the flash chip */ -static int NanD_Command(unsigned char command) -{ - NAND_CTL_SETCLE(NAND_ADDR); - - WRITE_NAND_COMMAND(command, NAND_ADDR); - NAND_CTL_CLRCLE(NAND_ADDR); - - if(command == NAND_CMD_RESET){ - unsigned char ret_val; - NanD_Command(NAND_CMD_STATUS); - do{ - ret_val = READ_NAND(NAND_ADDR);/* wait till ready */ - } while((ret_val & 0x40) != 0x40); - } - - NAND_WAIT_READY(); - return 0; -} - - -/* NanD_Address: Set the current address for the flash chip */ -static int NanD_Address(unsigned int numbytes, unsigned long ofs) -{ - uchar u; - - NAND_CTL_SETALE(NAND_ADDR); - - if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE - || numbytes == ADDR_OOB) - { - ushort col = ofs; - - u = col & 0xff; - WRITE_NAND_ADDRESS(u, NAND_ADDR); - - u = (col >> 8) & 0x07; - if (numbytes == ADDR_OOB) - u = u | ((bus_width == 16) ? (1 << 2) : (1 << 3)); - WRITE_NAND_ADDRESS(u, NAND_ADDR); - } - - if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE - || numbytes == ADDR_OOB) - { - u = (ofs >> 11) & 0xff; - WRITE_NAND_ADDRESS(u, NAND_ADDR); - u = (ofs >> 19) & 0xff; - WRITE_NAND_ADDRESS(u, NAND_ADDR); - - /* One more address cycle for devices > 128MiB */ - if (chipsize > (128 << 20)) { - u = (ofs >> 27) & 0xff; - WRITE_NAND_ADDRESS(u, NAND_ADDR); - } - } - - NAND_CTL_CLRALE(NAND_ADDR); - - NAND_WAIT_READY(); - return 0; -} - -int nand_readid(int *mfr, int *id) -{ - NAND_ENABLE_CE(); - - if (NanD_Command(NAND_CMD_RESET)) { - NAND_DISABLE_CE(); - return 1; - } - - if (NanD_Command(NAND_CMD_READID)) { - NAND_DISABLE_CE(); - return 1; - } - - NanD_Address(ADDR_COLUMN, 0); - - *mfr = READ_NAND(NAND_ADDR); - *id = READ_NAND(NAND_ADDR); - - NAND_DISABLE_CE(); - return 0; -} - -/* read chip mfr and id - * return 0 if they match board config - * return 1 if not - */ -int nand_chip() -{ - int mfr, id; - - NAND_ENABLE_CE(); - - if (NanD_Command(NAND_CMD_RESET)) { - printf("Err: RESET\n"); - NAND_DISABLE_CE(); - return 1; - } - - if (NanD_Command(NAND_CMD_READID)) { - printf("Err: READID\n"); - NAND_DISABLE_CE(); - return 1; - } - - NanD_Address(ADDR_COLUMN, 0); - - mfr = READ_NAND(NAND_ADDR); - id = READ_NAND(NAND_ADDR); - - NAND_DISABLE_CE(); - - if (((mfr == MT29F1G_MFR || mfr == MT29F1G_MFR2 || mfr == MT29F1G_MFR3) && - (id == MT29F1G_ID || id == MT29F2G_ID || id == MT29F4G_ID)) || - (mfr == K9F1G08R0A_MFR && (id == K9F1G08R0A_ID))) { - return 0; - } else { - if ((mfr == 0) && (id == 0)) { - printf("No NAND detected\n"); - return 0; - } else { - printf("Unknown chip: mfr was 0x%02x, id was 0x%02x\n", mfr, id); - return 1; - } - } -} - -/* read a block data to buf - * return 1 if the block is bad or ECC error can't be corrected for any page - * return 0 on sucess - */ -int nand_read_block(unsigned char *buf, ulong block_addr) -{ - int i, offset = 0; - -#ifdef ECC_CHECK_ENABLE - u16 oob_buf[OOB_SIZE >> 1]; - - /* check bad block */ - /* 0th word in spare area needs be 0xff */ - if (nand_read_oob(oob_buf, block_addr) || (oob_buf[0] & 0xff) != 0xff){ - printf("Skipped bad block at 0x%x\n", block_addr); - return 1; /* skip bad block */ - } -#endif - /* read the block page by page*/ - for (i=0; i> 1 : PAGE_SIZE; - p = buf; - for (cntr = 0; cntr < len; cntr++){ - *p++ = READ_NAND(NAND_ADDR); - delay(10); - } - -#ifdef ECC_CHECK_ENABLE - p = oob_buf; - len = (bus_width == 16) ? OOB_SIZE >> 1 : OOB_SIZE; - for (cntr = 0; cntr < len; cntr++){ - *p++ = READ_NAND(NAND_ADDR); - delay(10); - } - count = 0; - NAND_DISABLE_CE(); /* set pin high */ - - /* Pick the ECC bytes out of the oob data */ - for (cntr = 0; cntr < ECC_SIZE; cntr++) - ecc_code[cntr] = oob_buf[ecc_pos[cntr]]; - - for(count = 0; count < ECC_SIZE; count += ECC_STEPS) { - nand_calculate_ecc (buf, &ecc_calc[0]); - if (nand_correct_data (buf, &ecc_code[count], &ecc_calc[0]) == -1) { - printf ("ECC Failed, page 0x%08x\n", page_addr); - for (val=0; val <256; val++) - printf("%x ", buf[val]); - printf("\n"); - for (;;); - return 1; - } - buf += 256; - page_addr += 256; - } -#endif - return 0; -} - -/* read from the 16 bytes of oob data that correspond to a 512 / 2048 byte page. - */ -static int nand_read_oob(u_char *buf, ulong page_addr) -{ - u16 val; - int cntr; - int len; - -#ifdef NAND_16BIT - u16 *p; -#else - u_char *p; -#endif - p = buf; - len = (bus_width == 16) ? OOB_SIZE >> 1 : OOB_SIZE; - - NAND_ENABLE_CE(); /* set pin low */ - NanD_Command(NAND_CMD_READ0); - NanD_Address(ADDR_OOB, page_addr); - NanD_Command(NAND_CMD_READSTART); - NAND_WAIT_READY(); - - /* A delay seems to be helping here. needs more investigation */ - delay(10000); - for (cntr = 0; cntr < len; cntr++) - *p++ = READ_NAND(NAND_ADDR); - - NAND_WAIT_READY(); - NAND_DISABLE_CE(); /* set pin high */ - - return 0; -} - -#endif diff --git a/x-loader/drivers/k9k1216.c b/x-loader/drivers/k9k1216.c deleted file mode 100644 index 888fb6b..0000000 --- a/x-loader/drivers/k9k1216.c +++ /dev/null @@ -1,258 +0,0 @@ -/* - * (C) Copyright 2004 Texas Instruments - * Jian Zhang - * - * Samsung K9K1216Q0C NAND chip driver for an OMAP2420 board - * - * This file is based on the following u-boot file: - * common/cmd_nand.c - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifdef CFG_NAND_K9K1216 - -#define K9K1216_MFR 0xec -#define K9K1216_ID 0x46 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define PAGE_SIZE 512 -/******************************************************* - * Routine: delay - * Description: spinning delay to use before udelay works - ******************************************************/ -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -static int nand_read_page(u_char *buf, ulong page_addr); -static int nand_read_oob(u_char * buf, ulong page_addr); - -/* JFFS2 512-byte-page ECC layout */ -static u_char ecc_pos[] = {0,1,2,3,6,7}; -static u_char eccvalid_pos = 4; - -/* NanD_Command: Send a flash command to the flash chip */ -static int NanD_Command(unsigned char command) -{ - NAND_CTL_SETCLE(NAND_ADDR); - WRITE_NAND_COMMAND(command, NAND_ADDR); - NAND_CTL_CLRCLE(NAND_ADDR); - - if(command == NAND_CMD_RESET){ - unsigned char ret_val; - NanD_Command(NAND_CMD_STATUS); - do{ - ret_val = READ_NAND(NAND_ADDR);/* wait till ready */ - } while((ret_val & 0x40) != 0x40); - } - - NAND_WAIT_READY(); - return 0; -} - -/* NanD_Address: Set the current address for the flash chip */ -static int NanD_Address(int numbytes, unsigned long ofs) -{ - int i; - - NAND_CTL_SETALE(NAND_ADDR); - - if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) - WRITE_NAND_ADDRESS(ofs, NAND_ADDR); - - ofs = ofs >> 9; - - if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) - for (i = 0; i < 3; i++, ofs = ofs >> 8) - WRITE_NAND_ADDRESS(ofs, NAND_ADDR); - - NAND_CTL_CLRALE(NAND_ADDR); - - NAND_WAIT_READY(); - return 0; -} - -/* read chip mfr and id - * return 0 if they match board config - * return 1 if not - */ -int nand_chip() -{ - int mfr, id; - - NAND_ENABLE_CE(); - - if (NanD_Command(NAND_CMD_RESET)) { - printf("Err: RESET\n"); - NAND_DISABLE_CE(); - return 1; - } - - if (NanD_Command(NAND_CMD_READID)) { - printf("Err: READID\n"); - NAND_DISABLE_CE(); - return 1; - } - - NanD_Address(ADDR_COLUMN, 0); - - mfr = READ_NAND(NAND_ADDR); - id = READ_NAND(NAND_ADDR); - - NAND_DISABLE_CE(); - - return (mfr != K9K1216_MFR || id != K9K1216_ID); -} - -/* read a block data to buf - * return 1 if the block is bad or ECC error can't be corrected for any page - * return 0 on sucess - */ -int nand_read_block(unsigned char *buf, ulong block_addr) -{ - int i, offset = 0; - uchar oob_buf[16]; - - /* check bad block */ - /* 0th and 5th words need be 0xffff */ - if (nand_read_oob(oob_buf, block_addr) || -// oob_buf[0] != 0xff || oob_buf[1] != 0xff || -// oob_buf[10] != 0xff || oob_buf[11] != 0xff ){ - oob_buf[5] != 0xff){ - printf("Skipped bad block at 0x%x\n", block_addr); - return 1; /* skip bad block */ - } - - /* read the block page by page*/ - for (i=0; i<32; i++){ - if (nand_read_page(buf+offset, block_addr + offset)) - return 1; - offset += PAGE_SIZE; - } - - return 0; -} -static count = 0; -/* read a page with ECC */ -static int nand_read_page(u_char *buf, ulong page_addr) -{ - u_char ecc_code[6]; - u_char ecc_calc[3]; - u_char oob_buf[16]; - u_char *p; - u16 val; - int cntr; - - NAND_ENABLE_CE(); - NanD_Command(NAND_CMD_READ0); - NanD_Address(ADDR_COLUMN_PAGE, page_addr); - NAND_WAIT_READY(); - - delay(500); /* we go through NFC need a bigger delay. 200 is not enough */ - - p = buf; - for (cntr = 0; cntr < 256; cntr++){ - val = READ_NAND(NAND_ADDR); - *p++ = val & 0xff; - *p++ = val >> 8; - } - - p = oob_buf; - for (cntr = 0; cntr < 8; cntr++){ - val = READ_NAND(NAND_ADDR); - *p++ = val & 0xff; - *p++ = val >> 8; - } - count = 1; - NAND_DISABLE_CE(); /* set pin high */ - - /* Pick the ECC bytes out of the oob data */ - for (cntr = 0; cntr < 6; cntr++) - ecc_code[cntr] = oob_buf[ecc_pos[cntr]]; - - if ((oob_buf[eccvalid_pos] & 0x0f) != 0x0f) { - nand_calculate_ecc (buf, &ecc_calc[0]); - if (nand_correct_data (buf, &ecc_code[0], &ecc_calc[0]) == -1) { - printf ("ECC Failed, page 0x%08x\n", page_addr); - for (val=0; val <256; val++) - printf("%x ", buf[val]); - printf("\n"); - for (;;); - return 1; - } - } - - if ((oob_buf[eccvalid_pos] & 0xf0) != 0xf0) { - nand_calculate_ecc (buf + 256, &ecc_calc[0]); - if (nand_correct_data (buf + 256, &ecc_code[3], &ecc_calc[0]) == -1) { - printf ("ECC Failed, page 0x%08x\n", page_addr+0x100); - for (val=0; val <256; val++) - printf("%x ", buf[val+256]); - printf("\n"); - for (;;); - return 1; - } - } - - return 0; -} - -/* read from the 16 bytes of oob data that correspond to a 512 byte page. - */ -static int nand_read_oob(u_char *buf, ulong page_addr) -{ - u16 val; - int cntr; - - NAND_ENABLE_CE(); /* set pin low */ - NanD_Command(NAND_CMD_READOOB); - NanD_Address(ADDR_COLUMN_PAGE, page_addr); - NAND_WAIT_READY(); - -/* do { - *(volatile u32 *)(0x6800A07c) = NAND_CMD_STATUS; - val = *(volatile u32 *)(0x6800A084); - printf("val = %x\n", val); - } while ((val & 0x40) != 0x40); -*/ - /* the above code from OSTBoot doesn't work, we use delay */ - delay(500); /* we go through NFC need a bigger delay. 200 is not enough */ - - for (cntr = 0; cntr < 8; cntr++){ - val = READ_NAND(NAND_ADDR); - *buf++ = val & 0xff; - *buf++ = val >> 8; - } - - NAND_WAIT_READY(); - NAND_DISABLE_CE(); /* set pin high */ - - return 0; -} - -#endif diff --git a/x-loader/drivers/ns16550.c b/x-loader/drivers/ns16550.c deleted file mode 100644 index b5a5c12..0000000 --- a/x-loader/drivers/ns16550.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * COM1 NS16550 support - * originally from linux source (arch/ppc/boot/ns16550.c) - * modified to use CFG_ISA_MEM and new defines - */ - -#include - -#ifdef CFG_PRINTF -#ifdef CFG_NS16550 - -#include - -#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ -#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */ -#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */ - -void NS16550_init (NS16550_t com_port, int baud_divisor) -{ - com_port->ier = 0x00; -#ifdef CONFIG_OMAP - com_port->mdr1 = 0x7; /* mode select reset TL16C750*/ -#endif - com_port->lcr = LCR_BKSE | LCRVAL; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCRVAL; - com_port->mcr = MCRVAL; - com_port->fcr = FCRVAL; -#if defined(CONFIG_OMAP) - com_port->mdr1 = 0; /* select uart mode */ -#endif -} - -void NS16550_reinit (NS16550_t com_port, int baud_divisor) -{ - com_port->ier = 0x00; - com_port->lcr = LCR_BKSE; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = LCRVAL; - com_port->mcr = MCRVAL; - com_port->fcr = FCRVAL; -} - -void NS16550_putc (NS16550_t com_port, char c) -{ - while ((com_port->lsr & LSR_THRE) == 0); - com_port->thr = c; -} - -char NS16550_getc (NS16550_t com_port) -{ - while ((com_port->lsr & LSR_DR) == 0); - return (com_port->rbr); -} - -int NS16550_tstc (NS16550_t com_port) -{ - return ((com_port->lsr & LSR_DR) != 0); -} - -#endif -#endif diff --git a/x-loader/drivers/omap24xx_i2c.c b/x-loader/drivers/omap24xx_i2c.c deleted file mode 100644 index 7782e9d..0000000 --- a/x-loader/drivers/omap24xx_i2c.c +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Basic I2C functions - * - * Copyright (c) 2004 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Author: Jian Zhang jzhang@ti.com, Texas Instruments - * - * Copyright (c) 2003 Wolfgang Denk, wd@denx.de - * Rewritten to fit into the current U-Boot framework - * - * Adapted for OMAP2420 I2C, r-woodruff2@ti.com - * - */ - -#include - -#if defined(CONFIG_DRIVER_OMAP24XX_I2C) || defined(CONFIG_DRIVER_OMAP34XX_I2C) - -#include -#include - -#define inb(a) __raw_readb(a) -#define outb(a,v) __raw_writeb(a,v) -#define inw(a) __raw_readw(a) -#define outw(a,v) __raw_writew(a,v) - -static void wait_for_bb (void); -static u16 wait_for_pin (void); -static void flush_fifo(void); - -void i2c_init (int speed, int slaveadd) -{ - u16 scl; - - outw(0x2, I2C_SYSC); /* for ES2 after soft reset */ - udelay(1000); - outw(0x0, I2C_SYSC); /* will probably self clear but */ - - if (inw (I2C_CON) & I2C_CON_EN) { - outw (0, I2C_CON); - udelay (50000); - } - - /* 12Mhz I2C module clock */ - outw (0, I2C_PSC); - speed = speed/1000; /* 100 or 400 */ - scl = ((12000/(speed*2)) - 7); /* use 7 when PSC = 0 */ - outw (scl, I2C_SCLL); - outw (scl, I2C_SCLH); - /* own address */ - outw (slaveadd, I2C_OA); - outw (I2C_CON_EN, I2C_CON); - - /* have to enable intrrupts or OMAP i2c module doesn't work */ - outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); - udelay (1000); - flush_fifo(); - outw (0xFFFF, I2C_STAT); - outw (0, I2C_CNT); -} - -static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) -{ - int i2c_error = 0; - u16 status; - - /* wait until bus not busy */ - wait_for_bb (); - - /* one byte only */ - outw (1, I2C_CNT); - /* set slave address */ - outw (devaddr, I2C_SA); - /* no stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); - - status = wait_for_pin (); - - if (status & I2C_STAT_XRDY) { - /* Important: have to use byte access */ - *(volatile u8 *) (I2C_DATA) = regoffset; - udelay (20000); - if (inw (I2C_STAT) & I2C_STAT_NACK) { - i2c_error = 1; - } - } else { - i2c_error = 1; - } - - if (!i2c_error) { - /* free bus, otherwise we can't use a combined transction */ - outw (0, I2C_CON); - while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { - udelay (10000); - /* Have to clear pending interrupt to clear I2C_STAT */ - outw (0xFFFF, I2C_STAT); - } - - wait_for_bb (); - /* set slave address */ - outw (devaddr, I2C_SA); - /* read one byte from slave */ - outw (1, I2C_CNT); - /* need stop bit here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, - I2C_CON); - - status = wait_for_pin (); - if (status & I2C_STAT_RRDY) { -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - *value = inb(I2C_DATA); -#else - *value = inw(I2C_DATA); -#endif - udelay (20000); - } else { - i2c_error = 1; - } - - if (!i2c_error) { - outw (I2C_CON_EN, I2C_CON); - while (inw (I2C_STAT) - || (inw (I2C_CON) & I2C_CON_MST)) { - udelay (10000); - outw (0xFFFF, I2C_STAT); - } - } - } - flush_fifo(); - outw (0xFFFF, I2C_STAT); - outw (0, I2C_CNT); - return i2c_error; -} - -static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) -{ - int i2c_error = 0; - u16 status, stat; - - /* wait until bus not busy */ - wait_for_bb (); - - /* two bytes */ - outw (2, I2C_CNT); - /* set slave address */ - outw (devaddr, I2C_SA); - /* stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, I2C_CON); - - /* wait until state change */ - status = wait_for_pin (); - - if (status & I2C_STAT_XRDY) { -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - /* send out 1 byte */ - outb(regoffset, I2C_DATA); - outw(I2C_STAT_XRDY, I2C_STAT); - status = wait_for_pin(); - if ((status & I2C_STAT_XRDY)) { - /* send out next 1 byte */ - outb(value, I2C_DATA); - outw(I2C_STAT_XRDY, I2C_STAT); - } else { - i2c_error = 1; - } -#else - /* send out two bytes */ - outw ((value << 8) + regoffset, I2C_DATA); -#endif - - /* must have enough delay to allow BB bit to go low */ - udelay (50000); - if (inw (I2C_STAT) & I2C_STAT_NACK) { - i2c_error = 1; - } - } else { - i2c_error = 1; - } - - if (!i2c_error) { - int eout = 200; - - outw (I2C_CON_EN, I2C_CON); - while ((stat = inw (I2C_STAT)) || (inw (I2C_CON) & I2C_CON_MST)) { - udelay (1000); - /* have to read to clear intrrupt */ - outw (0xFFFF, I2C_STAT); - if(--eout == 0) /* better leave with error than hang */ - break; - } - } - flush_fifo(); - outw (0xFFFF, I2C_STAT); - outw (0, I2C_CNT); - return i2c_error; -} - -static void flush_fifo(void) -{ u16 stat; - - /* note: if you try and read data when its not there or ready - * you get a bus error - */ - while(1){ - stat = inw(I2C_STAT); - if(stat == I2C_STAT_RRDY){ -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - inb(I2C_DATA); -#else - inw(I2C_DATA); -#endif - outw(I2C_STAT_RRDY,I2C_STAT); - udelay(1000); - }else - break; - } -} - -int i2c_probe (uchar chip) -{ - int res = 1; /* default = fail */ - - if (chip == inw (I2C_OA)) { - return res; - } - - /* wait until bus not busy */ - wait_for_bb (); - - /* try to read one byte */ - outw (1, I2C_CNT); - /* set slave address */ - outw (chip, I2C_SA); - /* stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); - /* enough delay for the NACK bit set */ - udelay (50000); - - if (!(inw (I2C_STAT) & I2C_STAT_NACK)) { - res = 0; /* success case */ - flush_fifo(); - outw(0xFFFF, I2C_STAT); - } else { - outw(0xFFFF, I2C_STAT); /* failue, clear sources*/ - outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ - udelay(20000); - wait_for_bb (); - } - flush_fifo(); - outw (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ - outw(0xFFFF, I2C_STAT); - return res; -} - -int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - int i; - - if (alen > 1) { - printf ("I2C read: addr len %d not supported\n", alen); - return 1; - } - - if (addr + len > 256) { - printf ("I2C read: address out of range\n"); - return 1; - } - - for (i = 0; i < len; i++) { - if (i2c_read_byte (chip, addr + i, &buffer[i])) { - printf ("I2C read: I/O error\n"); - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - return 1; - } - } - - return 0; -} - -int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - int i; - - if (alen > 1) { - printf ("I2C read: addr len %d not supported\n", alen); - return 1; - } - - if (addr + len > 256) { - printf ("I2C read: address out of range\n"); - return 1; - } - - for (i = 0; i < len; i++) { - if (i2c_write_byte (chip, addr + i, buffer[i])) { - printf ("I2C read: I/O error\n"); - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - return 1; - } - } - - return 0; -} - -static void wait_for_bb (void) -{ - int timeout = 10; - u16 stat; - - outw(0xFFFF, I2C_STAT); /* clear current interruts...*/ - while ((stat = inw (I2C_STAT) & I2C_STAT_BB) && timeout--) { - outw (stat, I2C_STAT); - udelay (50000); - } - - if (timeout <= 0) { - printf ("timed out in wait_for_bb: I2C_STAT=%x\n", - inw (I2C_STAT)); - } - outw(0xFFFF, I2C_STAT); /* clear delayed stuff*/ -} - -static u16 wait_for_pin (void) -{ - u16 status; - int timeout = 10; - - do { - udelay (1000); - status = inw (I2C_STAT); - } while ( !(status & - (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | - I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | - I2C_STAT_AL)) && timeout--); - - if (timeout <= 0) { - printf ("timed out in wait_for_pin: I2C_STAT=%x\n", - inw (I2C_STAT)); - outw(0xFFFF, I2C_STAT); -} - return status; -} - -#endif /* CONFIG_DRIVER_OMAP24XX_I2C */ diff --git a/x-loader/drivers/onenand.c b/x-loader/drivers/onenand.c deleted file mode 100644 index 9902a0d..0000000 --- a/x-loader/drivers/onenand.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * (C) Copyright 2005 Samsung Electronis - * Kyungmin Park - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#include - -#include "onenand_regs.h" - -#define onenand_readw(a) (*(volatile unsigned short *)(a)) -#define onenand_writew(v, a) ((*(volatile unsigned short *)(a)) = (u16) (v)) - -#define SAMSUNG_MFR_ID 0xEC -#define KFM1G16Q2A_DEV_ID 0x30 -#define KFN2G16Q2A_DEV_ID 0x40 - - -#define THIS_ONENAND(a) (ONENAND_ADDR + (a)) - -#define READ_INTERRUPT() \ - onenand_readw(THIS_ONENAND(ONENAND_REG_INTERRUPT)) - -#define READ_CTRL_STATUS() \ - onenand_readw(THIS_ONENAND(ONENAND_REG_CTRL_STATUS)) - -#define READ_ECC_STATUS() \ - onenand_readw(THIS_ONENAND(ONENAND_REG_ECC_STATUS)) - -#define SET_EMIFS_CS_CONFIG(v) \ - (*(volatile unsigned long *)(OMAP_EMIFS_CS_CONFIG) = (v)) - -#define onenand_block_address(block) (block) -#define onenand_sector_address(page) (page << 2) -#define onenand_buffer_address() ((1 << 3) << 8) -#define onenand_bufferram_address(block) (0) - -#if defined(CFG_SYNC_BURST_READ) && defined(CONFIG_OMAP1610) -static inline void set_sync_burst_read(void) -{ - unsigned int value; - value = 0 - | (0x1 << 15) /* Read Mode: Synchronous */ - | (0x4 << 12) /* Burst Read Latency: 4 cycles */ - | (0x4 << 9) /* Burst Length: 8 word */ - | (0x1 << 7) /* RDY signal plarity */ - | (0x1 << 6) /* INT signal plarity */ - | (0x1 << 5) /* I/O buffer enable */ - ; - onenand_writew(value, THIS_ONENAND(ONENAND_REG_SYS_CFG1)); - - value = 0 - | (4 << 16) /* Synchronous Burst Read */ - | (1 << 12) /* PGWST/WELEN */ - | (1 << 8) /* WRWST */ - | (4 << 4) /* RDWST */ - | (1 << 0) /* FCLKDIV => 48MHz */ - ; - SET_EMIFS_CS_CONFIG(value); -} - -static inline void set_async_read(void) -{ - unsigned int value; - value = 0 - | (0x0 << 15) /* Read Mode: Asynchronous */ - | (0x4 << 12) /* Burst Read Latency: 4 cycles */ - | (0x0 << 9) /* Burst Length: continuous */ - | (0x1 << 7) /* RDY signal plarity */ - | (0x1 << 6) /* INT signal plarity */ - | (0x0 << 5) /* I/O buffer disable */ - ; - onenand_writew(value, THIS_ONENAND(ONENAND_REG_SYS_CFG1)); - - value = 0 - | (0 << 16) /* Asynchronous Read */ - | (1 << 12) /* PGWST/WELEN */ - | (1 << 8) /* WRWST */ - | (3 << 4) /* RDWST */ - | (1 << 0) /* FCLKDIV => 48MHz */ - ; - SET_EMIFS_CS_CONFIG(value); -} -#else -#define set_sync_burst_read(...) do { } while (0) -#define set_async_read(...) do { } while (0) -#endif - -int -onenand_chip() -{ - unsigned short mf_id, dev_id; - mf_id = (*(volatile unsigned short *)(THIS_ONENAND(ONENAND_REG_MANUFACTURER_ID))); - dev_id = (*(volatile unsigned short *)(THIS_ONENAND(ONENAND_REG_DEVICE_ID))); - - if(mf_id == SAMSUNG_MFR_ID) { - if (dev_id == KFM1G16Q2A_DEV_ID) { - printf("Detected Samsung MuxOneNAND1G Flash \r\n"); - return 0; - } else if (dev_id == KFN2G16Q2A_DEV_ID) { - printf("Detected Samsung MuxOneNAND2G Flash \r\n"); - return 0; - } else { - printf(" ONENAND Flash unsupported\r\n"); - return 1; - } - } else { - printf("ONENAND Flash Unsupported\r\n"); - return 1; - } -} - -/* read a page with ECC */ -static inline int onenand_read_page(ulong block, ulong page, u_char *buf) -{ - unsigned long *base; - -#ifndef __HAVE_ARCH_MEMCPY32 - unsigned int offset, value; - unsigned long *p; - unsigned int ctrl, ecc; - unsigned short bbmarker; -#endif - - onenand_writew(onenand_block_address(block), - THIS_ONENAND(ONENAND_REG_START_ADDRESS1)); - - onenand_writew(onenand_sector_address(page), - THIS_ONENAND(ONENAND_REG_START_ADDRESS8)); - - onenand_writew(onenand_buffer_address(), - THIS_ONENAND(ONENAND_REG_START_BUFFER)); - - onenand_writew(onenand_bufferram_address(block), - THIS_ONENAND(ONENAND_REG_START_ADDRESS2)); - - onenand_writew(ONENAND_INT_CLEAR, THIS_ONENAND(ONENAND_REG_INTERRUPT)); - - onenand_writew(ONENAND_CMD_READ, THIS_ONENAND(ONENAND_REG_COMMAND)); - -#ifndef __HAVE_ARCH_MEMCPY32 - p = (unsigned long *) buf; -#endif - base = (unsigned long *) (ONENAND_ADDR + ONENAND_DATARAM); - - while (!(READ_INTERRUPT() & ONENAND_INT_MASTER)) - continue; - - ctrl = READ_CTRL_STATUS(); - - if (ctrl & ONENAND_CTRL_ERROR) { - hang(); - } - - if (READ_INTERRUPT() & ONENAND_INT_READ) { - - ecc = READ_ECC_STATUS(); - if (ecc & ONENAND_ECC_2BIT_ALL) { - hang(); - } - - /* Check if the block is bad. Bad block markers */ - /* are stored in spare area of 1st or 2nd page */ - if ((page == 0) || (page == 1)) - { - unsigned long *spareArea = (unsigned long *) (ONENAND_ADDR + ONENAND_SPARERAM); - bbmarker = *spareArea; - /* for bad block markers */ - if (bbmarker != 0xFFFF){ - return 1; - } - } - } - -#ifdef __HAVE_ARCH_MEMCPY32 - /* 32 bytes boundary memory copy */ - memcpy32(buf, base, ONENAND_PAGE_SIZE); -#else - for (offset = 0; offset < (ONENAND_PAGE_SIZE >> 2); offset++) { - value = *(base + offset); - *p++ = value; - } -#endif - - return 0; -} - -#define ONENAND_START_PAGE 0 -#define ONENAND_PAGES_PER_BLOCK 64 - -/** - * onenand_read_block - Read a block data to buf - * @return 0 on sucess - */ - -int onenand_read_block(unsigned char *buf, ulong block) -{ - int page, offset = 0; - - set_sync_burst_read(); - - /* NOTE: you must read page from page 1 of block 0 */ - /* read the block page by page*/ - for (page = ONENAND_START_PAGE; - page < ONENAND_PAGES_PER_BLOCK; page++) { - - if (onenand_read_page(block, page, buf + offset)){ - set_async_read(); - return 1; - } - - offset += ONENAND_PAGE_SIZE; - } - - set_async_read(); - - return 0; -} - diff --git a/x-loader/drivers/onenand_regs.h b/x-loader/drivers/onenand_regs.h deleted file mode 100644 index d8acc8c..0000000 --- a/x-loader/drivers/onenand_regs.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * linux/include/linux/mtd/onenand_regs.h - * - * OneNAND Register header file - * - * Copyright (C) 2005 Samsung Electronics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ONENAND_REG_H -#define __ONENAND_REG_H - -/* Memory Address Map Translation (Word order) */ -#define ONENAND_MEMORY_MAP(x) ((x) << 1) - -/* - * External BufferRAM area - */ -#define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000) -#define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200) -#define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010) - -/* - * OneNAND Registers - */ -#define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000) -#define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001) -#define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002) -#define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003) -#define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004) -#define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005) -#define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006) - -#define ONENAND_REG_START_ADDRESS1 ONENAND_MEMORY_MAP(0xF100) -#define ONENAND_REG_START_ADDRESS2 ONENAND_MEMORY_MAP(0xF101) -#define ONENAND_REG_START_ADDRESS3 ONENAND_MEMORY_MAP(0xF102) -#define ONENAND_REG_START_ADDRESS4 ONENAND_MEMORY_MAP(0xF103) -#define ONENAND_REG_START_ADDRESS5 ONENAND_MEMORY_MAP(0xF104) -#define ONENAND_REG_START_ADDRESS6 ONENAND_MEMORY_MAP(0xF105) -#define ONENAND_REG_START_ADDRESS7 ONENAND_MEMORY_MAP(0xF106) -#define ONENAND_REG_START_ADDRESS8 ONENAND_MEMORY_MAP(0xF107) - -#define ONENAND_REG_START_BUFFER ONENAND_MEMORY_MAP(0xF200) -#define ONENAND_REG_COMMAND ONENAND_MEMORY_MAP(0xF220) -#define ONENAND_REG_SYS_CFG1 ONENAND_MEMORY_MAP(0xF221) -#define ONENAND_REG_SYS_CFG2 ONENAND_MEMORY_MAP(0xF222) -#define ONENAND_REG_CTRL_STATUS ONENAND_MEMORY_MAP(0xF240) -#define ONENAND_REG_INTERRUPT ONENAND_MEMORY_MAP(0xF241) -#define ONENAND_REG_START_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24C) -#define ONENAND_REG_END_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24D) -#define ONENAND_REG_WP_STATUS ONENAND_MEMORY_MAP(0xF24E) - -#define ONENAND_REG_ECC_STATUS ONENAND_MEMORY_MAP(0xFF00) -#define ONENAND_REG_ECC_M0 ONENAND_MEMORY_MAP(0xFF01) -#define ONENAND_REG_ECC_S0 ONENAND_MEMORY_MAP(0xFF02) -#define ONENAND_REG_ECC_M1 ONENAND_MEMORY_MAP(0xFF03) -#define ONENAND_REG_ECC_S1 ONENAND_MEMORY_MAP(0xFF04) -#define ONENAND_REG_ECC_M2 ONENAND_MEMORY_MAP(0xFF05) -#define ONENAND_REG_ECC_S2 ONENAND_MEMORY_MAP(0xFF06) -#define ONENAND_REG_ECC_M3 ONENAND_MEMORY_MAP(0xFF07) -#define ONENAND_REG_ECC_S3 ONENAND_MEMORY_MAP(0xFF08) - -/* - * Device ID Register F001h (R) - */ -#define ONENAND_DEVICE_DENSITY_SHIFT (4) -#define ONENAND_DEVICE_IS_DDP (1 << 3) -#define ONENAND_DEVICE_IS_DEMUX (1 << 2) -#define ONENAND_DEVICE_VCC_MASK (0x3) - -#define ONENAND_DEVICE_DENSITY_512Mb (0x002) - -/* - * Version ID Register F002h (R) - */ -#define ONENAND_VERSION_PROCESS_SHIFT (8) - -/* - * Start Address 1 F100h (R/W) - */ -#define ONENAND_DDP_SHIFT (15) - -/* - * Start Address 8 F107h (R/W) - */ -#define ONENAND_FPA_MASK (0x3f) -#define ONENAND_FPA_SHIFT (2) -#define ONENAND_FSA_MASK (0x03) - -/* - * Start Buffer Register F200h (R/W) - */ -#define ONENAND_BSA_MASK (0x03) -#define ONENAND_BSA_SHIFT (8) -#define ONENAND_BSA_BOOTRAM (0 << 2) -#define ONENAND_BSA_DATARAM0 (2 << 2) -#define ONENAND_BSA_DATARAM1 (3 << 2) -#define ONENAND_BSC_MASK (0x03) - -/* - * Command Register F220h (R/W) - */ -#define ONENAND_CMD_READ (0x00) -#define ONENAND_CMD_READOOB (0x13) -#define ONENAND_CMD_PROG (0x80) -#define ONENAND_CMD_PROGOOB (0x1A) -#define ONENAND_CMD_UNLOCK (0x23) -#define ONENAND_CMD_LOCK (0x2A) -#define ONENAND_CMD_LOCK_TIGHT (0x2C) -#define ONENAND_CMD_ERASE (0x94) -#define ONENAND_CMD_RESET (0xF0) -#define ONENAND_CMD_READID (0x90) - -/* NOTE: Those are not *REAL* commands */ -#define ONENAND_CMD_BUFFERRAM (0x1978) - -/* - * System Configuration 1 Register F221h (R, R/W) - */ -#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15) -#define ONENAND_SYS_CFG1_BRL (12) -#define ONENAND_SYS_CFG1_BL (9) -#define ONENAND_SYS_CFG1_NO_ECC (1 << 8) -#define ONENAND_SYS_CFG1_RDY (1 << 7) -#define ONENAND_SYS_CFG1_INT (1 << 6) -#define ONENAND_SYS_CFG1_IOBE (1 << 5) -#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4) - -/* - * Controller Status Register F240h (R) - */ -#define ONENAND_CTRL_ONGO (1 << 15) -#define ONENAND_CTRL_LOCK (1 << 14) -#define ONENAND_CTRL_LOAD (1 << 13) -#define ONENAND_CTRL_PROGRAM (1 << 12) -#define ONENAND_CTRL_ERASE (1 << 11) -#define ONENAND_CTRL_ERROR (1 << 10) -#define ONENAND_CTRL_RSTB (1 << 7) - -/* - * Interrupt Status Register F241h (R) - */ -#define ONENAND_INT_MASTER (1 << 15) -#define ONENAND_INT_READ (1 << 7) -#define ONENAND_INT_WRITE (1 << 6) -#define ONENAND_INT_ERASE (1 << 5) -#define ONENAND_INT_RESET (1 << 4) -#define ONENAND_INT_CLEAR (0 << 0) - -/* - * NAND Flash Write Protection Status Register F24Eh (R) - */ -#define ONENAND_WP_US (1 << 2) -#define ONENAND_WP_LS (1 << 1) -#define ONENAND_WP_LTS (1 << 0) - -/* - * ECC Status Reigser FF00h (R) - */ -#define ONENAND_ECC_1BIT (1 << 0) -#define ONENAND_ECC_2BIT (1 << 1) -#define ONENAND_ECC_2BIT_ALL (0xAAAA) - -#endif /* __ONENAND_REG_H */ diff --git a/x-loader/drivers/serial.c b/x-loader/drivers/serial.c deleted file mode 100644 index 026acf9..0000000 --- a/x-loader/drivers/serial.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#ifdef CFG_PRINTF -#ifdef CFG_NS16550_SERIAL - -#include -#ifdef CFG_NS87308 -#include -#endif - -#if CONFIG_CONS_INDEX == 1 -static NS16550_t console = (NS16550_t) CFG_NS16550_COM1; -#elif CONFIG_CONS_INDEX == 2 -static NS16550_t console = (NS16550_t) CFG_NS16550_COM2; -#elif CONFIG_CONS_INDEX == 3 -static NS16550_t console = (NS16550_t) CFG_NS16550_COM3; -#elif CONFIG_CONS_INDEX == 4 -static NS16550_t console = (NS16550_t) CFG_NS16550_COM4; -#else -#error no valid console defined -#endif - -static int calc_divisor (void) -{ - return (CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE); -} - -int serial_init (void) -{ - int clock_divisor = calc_divisor(); - -#ifdef CFG_NS87308 - initialise_ns87308(); -#endif - - NS16550_init(console, clock_divisor); - - return (0); -} - -void -serial_putc(const char c) -{ - if (c == '\n') - NS16550_putc(console, '\r'); - - NS16550_putc(console, c); -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - - -int -serial_getc(void) -{ - return NS16550_getc(console); -} - -int -serial_tstc(void) -{ - return NS16550_tstc(console); -} - -void -serial_setbrg (void) -{ - int clock_divisor; - - clock_divisor = calc_divisor(); - NS16550_reinit(console, clock_divisor); -} - -#endif -#endif diff --git a/x-loader/fs/Makefile b/x-loader/fs/Makefile deleted file mode 100644 index a2f61e7..0000000 --- a/x-loader/fs/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000, 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# - -SUBDIRS := fat - -$(obj).depend all: - @for dir in $(SUBDIRS) ; do \ - $(MAKE) -C $$dir $@ ; done diff --git a/x-loader/fs/fat/Makefile b/x-loader/fs/fat/Makefile deleted file mode 100644 index 2fa428c..0000000 --- a/x-loader/fs/fat/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)libfat.a - -AOBJS = -COBJS = fat.o file.o - -SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) - -all: $(LIB) $(AOBJS) - -$(LIB): $(obj).depend $(OBJS) - $(AR) crv $@ $(OBJS) - - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/fs/fat/fat.c b/x-loader/fs/fat/fat.c deleted file mode 100644 index e32cb62..0000000 --- a/x-loader/fs/fat/fat.c +++ /dev/null @@ -1,960 +0,0 @@ -/* - * fat.c - * - * R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg - * - * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6 - * 2003-03-10 - kharris@nexus-tech.net - ported to uboot - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#ifdef CFG_CMD_FAT - -/* - * Convert a string to lowercase. - */ -static void -downcase(char *str) -{ - while (*str != '\0') { - TOLOWER(*str); - str++; - } -} - -static block_dev_desc_t *cur_dev = NULL; -static unsigned long part_offset = 0; -static int cur_part = 1; - -#define DOS_PART_TBL_OFFSET 0x1be -#define DOS_PART_MAGIC_OFFSET 0x1fe -#define DOS_FS_TYPE_OFFSET 0x52 - -int strncmp(const char * cs,const char * ct,size_t count) -{ - register signed char __res = 0; - - while (count) { - if ((__res = *cs - *ct++) != 0 || !*cs++) - break; - count--; - } - - return __res; -} - -char * strcpy(char * dest,const char *src) -{ - char *tmp = dest; - - while ((*dest++ = *src++) != '\0') - /* nothing */; - return tmp; -} - -int strcmp(const char * cs,const char * ct) -{ - register signed char __res; - - while (1) { - if ((__res = *cs - *ct++) != 0 || !*cs++) - break; - } - - return __res; -} -void * memcpy(void * dest,const void *src,size_t count) -{ - char *tmp = (char *) dest, *s = (char *) src; - - while (count--) - *tmp++ = *s++; - - return dest; -} - - -int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr) -{ - startblock += part_offset; - if (cur_dev == NULL) - return -1; - if (cur_dev->block_read) { - return cur_dev->block_read (cur_dev->dev, startblock, getsize, (unsigned long *)bufptr); - } - return -1; -} - - -int -fat_register_device(block_dev_desc_t *dev_desc, int part_no) -{ - unsigned char buffer[SECTOR_SIZE]; - - if (!dev_desc->block_read) - return -1; - cur_dev=dev_desc; - /* check if we have a MBR (on floppies we have only a PBR) */ - if (dev_desc->block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) { - printf ("** Can't read from device %d **\n", dev_desc->dev); - return -1; - } - if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || - buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) { - /* no signature found */ - return -1; - } - if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { - /* ok, we assume we are on a PBR only */ - cur_part = 1; - part_offset=0; - } - else { -#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ - (CONFIG_COMMANDS & CFG_CMD_USB) || (CONFIG_COMMANDS & CFG_CMD_MMC) || defined(CONFIG_SYSTEMACE) - disk_partition_t info; - if(!get_partition_info(dev_desc, part_no, &info)) { - part_offset = info.start; - cur_part = part_no; - } - else { - printf ("** Partition %d not valid on device %d **\n",part_no,dev_desc->dev); - return -1; - } -#else - part_offset = buffer[DOS_PART_TBL_OFFSET+8] | - buffer[DOS_PART_TBL_OFFSET+9] <<8 | - buffer[DOS_PART_TBL_OFFSET+10]<<16 | - buffer[DOS_PART_TBL_OFFSET+11]<<24; - - cur_part = 1; -#endif - } - return 0; -} - - -/* - * Get the first occurence of a directory delimiter ('/' or '\') in a string. - * Return index into string if found, -1 otherwise. - */ -static int -dirdelim(char *str) -{ - char *start = str; - - while (*str != '\0') { - if (ISDIRDELIM(*str)) return str - start; - str++; - } - return -1; -} - - -/* - * Match volume_info fs_type strings. - * Return 0 on match, -1 otherwise. - */ -static int -compare_sign(char *str1, char *str2) -{ - char *end = str1+SIGNLEN; - - while (str1 != end) { - if (*str1 != *str2) { - return -1; - } - str1++; - str2++; - } - - return 0; -} - - -/* - * Extract zero terminated short name from a directory entry. - */ -static void get_name (dir_entry *dirent, char *s_name) -{ - char *ptr; - - memcpy (s_name, dirent->name, 8); - s_name[8] = '\0'; - ptr = s_name; - while (*ptr && *ptr != ' ') - ptr++; - if (dirent->ext[0] && dirent->ext[0] != ' ') { - *ptr = '.'; - ptr++; - memcpy (ptr, dirent->ext, 3); - ptr[3] = '\0'; - while (*ptr && *ptr != ' ') - ptr++; - } - *ptr = '\0'; - if (*s_name == DELETED_FLAG) - *s_name = '\0'; - else if (*s_name == aRING) - *s_name = 'å'; - downcase (s_name); -} - -/* - * Get the entry at index 'entry' in a FAT (12/16/32) table. - * On failure 0x00 is returned. - */ -static __u32 -get_fatent(fsdata *mydata, __u32 entry) -{ - __u32 bufnum; - __u32 offset; - __u32 ret = 0x00; - - switch (mydata->fatsize) { - case 32: - bufnum = entry / FAT32BUFSIZE; - offset = entry - bufnum * FAT32BUFSIZE; - break; - case 16: - bufnum = entry / FAT16BUFSIZE; - offset = entry - bufnum * FAT16BUFSIZE; - break; - case 12: - bufnum = entry / FAT12BUFSIZE; - offset = entry - bufnum * FAT12BUFSIZE; - break; - - default: - /* Unsupported FAT size */ - return ret; - } - /* Read a new block of FAT entries into the cache. */ - if (bufnum != mydata->fatbufnum) { - int getsize = FATBUFSIZE/FS_BLOCK_SIZE; - __u8 *bufptr = mydata->fatbuf; - __u32 fatlength = mydata->fatlength; - __u32 startblock = bufnum * FATBUFBLOCKS; - unsigned long i; - - fatlength *= SECTOR_SIZE; /* We want it in bytes now */ - startblock += mydata->fat_sect; /* Offset from start of disk */ - - if (getsize > fatlength) getsize = fatlength; - if (disk_read(startblock, getsize, bufptr) < 0) { - FAT_DPRINT("Error reading FAT blocks\n"); - return ret; - } - mydata->fatbufnum = bufnum; - } - - /* Get the actual entry from the table */ - switch (mydata->fatsize) { - case 32: - ret = FAT2CPU32(((__u32*)mydata->fatbuf)[offset]); - break; - case 16: - ret = FAT2CPU16(((__u16*)mydata->fatbuf)[offset]); - break; - case 12: { - __u32 off16 = (offset*3)/4; - __u16 val1, val2; - - switch (offset & 0x3) { - case 0: - ret = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); - ret &= 0xfff; - break; - case 1: - val1 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); - val1 &= 0xf000; - val2 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16+1]); - val2 &= 0x00ff; - ret = (val2 << 4) | (val1 >> 12); - break; - case 2: - val1 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); - val1 &= 0xff00; - val2 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16+1]); - val2 &= 0x000f; - ret = (val2 << 8) | (val1 >> 8); - break; - case 3: - ret = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]);; - ret = (ret & 0xfff0) >> 4; - break; - default: - break; - } - } - break; - } - FAT_DPRINT("ret: %d, offset: %d\n", ret, offset); - - return ret; -} - -static int memcmp(__u8 *p1, __u8 *p2, unsigned long len) -{ - while(len-- > 0) { - __u8 diff=(*p1++ - *p2++); - if(diff) - return diff; - } - return 0; // equal -} - -/* - * Read at most 'size' bytes from the specified cluster into 'buffer'. - * Return 0 on success, -1 otherwise. - */ -static int -get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) -{ - int idx = 0; - __u32 startsect; - __u8 tmpbuf[FS_BLOCK_SIZE]; - - if (clustnum > 0) { - startsect = mydata->data_begin + clustnum*mydata->clust_size; - } else { - startsect = mydata->rootdir_sect; - } - - // sacrifice speed for reliability (RAM-Test) - - idx = size/FS_BLOCK_SIZE; - while(idx-- > 0) { // read full blocks - if (disk_read(startsect, 1 , tmpbuf) < 0) { - FAT_DPRINT("Error reading data\n"); - return -1; - } - memcpy(buffer, tmpbuf, FS_BLOCK_SIZE); - if(memcmp(buffer, tmpbuf, FS_BLOCK_SIZE) != 0) { - FAT_ERROR("Memory error at 0x%8x\n", buffer); - return -1; - } - startsect++; - buffer += FS_BLOCK_SIZE; - } - - if(size % FS_BLOCK_SIZE) { // read last fragment - idx= size/FS_BLOCK_SIZE; - if (disk_read(startsect, 1, tmpbuf) < 0) { - FAT_DPRINT("Error reading data\n"); - return -1; - } - - memcpy(buffer, tmpbuf, size % FS_BLOCK_SIZE); - if(memcmp(buffer, tmpbuf, size % FS_BLOCK_SIZE) != 0) { - FAT_ERROR("Memory error at 0x%8x\n", buffer); - return -1; - } - return 0; - } - - return 0; -} - - -/* - * Read at most 'maxsize' bytes from the file associated with 'dentptr' - * into 'buffer'. - * Return the number of bytes read or -1 on fatal errors. - */ -static long -get_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, - unsigned long maxsize) -{ - unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0; - unsigned int bytesperclust = mydata->clust_size * SECTOR_SIZE; - __u32 curclust = START(dentptr); - __u32 endclust, newclust; - unsigned long actsize; - - FAT_DPRINT("Filesize: %ld bytes\n", filesize); - - if (maxsize > 0 && filesize > maxsize) filesize = maxsize; - - FAT_DPRINT("Reading: %ld bytes\n", filesize); - - actsize=bytesperclust; - endclust=curclust; - do { - /* search for consecutive clusters */ - while(actsize < filesize) { - newclust = get_fatent(mydata, endclust); - if((newclust -1)!=endclust) - goto getit; - if (newclust <= 0x0001 || newclust >= 0xfffff0) { - FAT_DPRINT("curclust: 0x%x\n", newclust); - FAT_DPRINT("Invalid FAT entry\n"); - return gotsize; - } - endclust=newclust; - actsize+= bytesperclust; - } - /* actsize >= file size */ - actsize -= bytesperclust; - /* get remaining clusters */ - if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) { - FAT_ERROR("Error reading cluster\n"); - return -1; - } - /* get remaining bytes */ - gotsize += (int)actsize; - filesize -= actsize; - buffer += actsize; - actsize= filesize; - if (get_cluster(mydata, endclust, buffer, (int)actsize) != 0) { - FAT_ERROR("Error reading cluster\n"); - return -1; - } - gotsize+=actsize; - return gotsize; -getit: - if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) { - FAT_ERROR("Error reading cluster\n"); - return -1; - } - gotsize += (int)actsize; - filesize -= actsize; - buffer += actsize; - curclust = get_fatent(mydata, endclust); - if (curclust <= 0x0001 || curclust >= 0xfffff0) { - FAT_DPRINT("curclust: 0x%x\n", curclust); - FAT_ERROR("Invalid FAT entry\n"); - return gotsize; - } - actsize=bytesperclust; - endclust=curclust; - } while (1); -} - - -#ifdef CONFIG_SUPPORT_VFAT -/* - * Extract the file name information from 'slotptr' into 'l_name', - * starting at l_name[*idx]. - * Return 1 if terminator (zero byte) is found, 0 otherwise. - */ -static int -slot2str(dir_slot *slotptr, char *l_name, int *idx) -{ - int j; - - for (j = 0; j <= 8; j += 2) { - l_name[*idx] = slotptr->name0_4[j]; - if (l_name[*idx] == 0x00) return 1; - (*idx)++; - } - for (j = 0; j <= 10; j += 2) { - l_name[*idx] = slotptr->name5_10[j]; - if (l_name[*idx] == 0x00) return 1; - (*idx)++; - } - for (j = 0; j <= 2; j += 2) { - l_name[*idx] = slotptr->name11_12[j]; - if (l_name[*idx] == 0x00) return 1; - (*idx)++; - } - - return 0; -} - -/* Calculate short name checksum */ -static __u8 -mkcksum(const char *str) -{ - int i; - __u8 ret = 0; - - for (i = 0; i < 11; i++) { - ret = (((ret&1)<<7)|((ret&0xfe)>>1)) + str[i]; - } - - return ret; -} -#endif - - -/* - * Get the directory entry associated with 'filename' from the directory - * starting at 'startsect' - */ - - -static dir_entry *get_dentfromdir (fsdata * mydata, int startsect, - char *filename, dir_entry * retdent, - int dols) -{ - -} - -#if 0 -__u8 get_dentfromdir_block[MAX_CLUSTSIZE]; -static dir_entry *get_dentfromdir (fsdata * mydata, int startsect, - char *filename, dir_entry * retdent, - int dols) -{ - __u16 prevcksum = 0xffff; - __u32 curclust = START (retdent); - int files = 0, dirs = 0; - - while (1) { - dir_entry *dentptr; - int i; - - if (get_cluster (mydata, curclust, get_dentfromdir_block, - mydata->clust_size * SECTOR_SIZE) != 0) { - FAT_DPRINT ("Error: reading directory block\n"); - return NULL; - } - dentptr = (dir_entry *) get_dentfromdir_block; - for (i = 0; i < DIRENTSPERCLUST; i++) { - char s_name[14], l_name[256]; - - l_name[0] = '\0'; - if (dentptr->name[0] == DELETED_FLAG) { - dentptr++; - continue; - } - if ((dentptr->attr & ATTR_VOLUME)) { - /* Volume label or VFAT entry */ - dentptr++; - continue; - } - if (dentptr->name[0] == 0) { - if (dols) { - printf ("\n%d file(s), %d dir(s)\n\n", files, dirs); - } - FAT_DPRINT ("Dentname == NULL - %d\n", i); - return NULL; - } -#ifdef CONFIG_SUPPORT_VFAT - if (dols && mkcksum (dentptr->name) == prevcksum) { - dentptr++; - continue; - } -#endif - get_name (dentptr, s_name); - if (dols) { - int isdir = (dentptr->attr & ATTR_DIR); - char dirc; - int doit = 0; - - if (isdir) { - dirs++; - dirc = '/'; - doit = 1; - } else { - dirc = ' '; - if (s_name[0] != 0) { - files++; - doit = 1; - } - } - if (doit) { - if (dirc == ' ') { - printf (" %8ld %s%c\n", - (long) FAT2CPU32 (dentptr->size), s_name, - dirc); - } else { - printf (" %s%c\n", s_name, dirc); - } - } - dentptr++; - continue; - } - if (strcmp (filename, s_name) && strcmp (filename, l_name)) { - FAT_DPRINT ("Mismatch: |%s|%s|\n", s_name, l_name); - dentptr++; - continue; - } - memcpy (retdent, dentptr, sizeof (dir_entry)); - - FAT_DPRINT ("DentName: %s", s_name); - FAT_DPRINT (", start: 0x%x", START (dentptr)); - FAT_DPRINT (", size: 0x%x %s\n", - FAT2CPU32 (dentptr->size), - (dentptr->attr & ATTR_DIR) ? "(DIR)" : ""); - - return retdent; - } - curclust = get_fatent (mydata, curclust); - if (curclust <= 0x0001 || curclust >= 0xfffff0) { - FAT_DPRINT ("curclust: 0x%x\n", curclust); - FAT_ERROR ("Invalid FAT entry\n"); - return NULL; - } - } - - return NULL; -} -#endif - - -/* - * Read boot sector and volume info from a FAT filesystem - */ -static int -read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) -{ - __u8 block[FS_BLOCK_SIZE]; - volume_info *vistart; - - printf("Reading boot sector\n"); - - if (disk_read(0, 1, block) < 0) { - FAT_DPRINT("Error: reading block\n"); - return -1; - } - - memcpy(bs, block, sizeof(boot_sector)); - bs->reserved = FAT2CPU16(bs->reserved); - bs->fat_length = FAT2CPU16(bs->fat_length); - bs->secs_track = FAT2CPU16(bs->secs_track); - bs->heads = FAT2CPU16(bs->heads); -#if 0 /* UNUSED */ - bs->hidden = FAT2CPU32(bs->hidden); -#endif - bs->total_sect = FAT2CPU32(bs->total_sect); - - /* FAT32 entries */ - if (bs->fat_length == 0) { - /* Assume FAT32 */ - bs->fat32_length = FAT2CPU32(bs->fat32_length); - bs->flags = FAT2CPU16(bs->flags); - bs->root_cluster = FAT2CPU32(bs->root_cluster); - bs->info_sector = FAT2CPU16(bs->info_sector); - bs->backup_boot = FAT2CPU16(bs->backup_boot); - vistart = (volume_info*) (block + sizeof(boot_sector)); - *fatsize = 32; - } else { - vistart = (volume_info*) &(bs->fat32_length); - *fatsize = 0; - } - memcpy(volinfo, vistart, sizeof(volume_info)); - - /* Terminate fs_type string. Writing past the end of vistart - is ok - it's just the buffer. */ - vistart->fs_type[8] = '\0'; - - if (*fatsize == 32) { - if (compare_sign(FAT32_SIGN, vistart->fs_type) == 0) { - return 0; - } - } else { - if (compare_sign(FAT12_SIGN, vistart->fs_type) == 0) { - *fatsize = 12; - return 0; - } - if (compare_sign(FAT16_SIGN, vistart->fs_type) == 0) { - *fatsize = 16; - return 0; - } - } - - FAT_DPRINT("Error: broken fs_type sign\n"); - return -1; -} - -#if 0 -__u8 do_fat_read_block[MAX_CLUSTSIZE]; /* Block buffer */ -#endif - -__u8 *fnamecopy = 0x80500000; -__u8 *do_fat_read_block = 0x80500880; - -boot_sector bs; -volume_info volinfo; -fsdata datablock; - -long -do_fat_read(const char *filename, void *buffer, unsigned long maxsize, - int dols) -{ -#if CONFIG_NIOS /* NIOS CPU cannot access big automatic arrays */ - static -#endif - fsdata *mydata = &datablock; - dir_entry *dentptr; - __u16 prevcksum = 0xffff; - char *subname = ""; - int rootdir_size, cursect, curclus; - int idx, isdir = 0; - int files = 0, dirs = 0; - long ret = 0; - int firsttime; - - if (read_bootsectandvi (&bs, &volinfo, &mydata->fatsize)) { - printf ("Error: reading boot sector\n"); - return -1; - } - if (mydata->fatsize == 32) { - mydata->fatlength = bs.fat32_length; - } else { - mydata->fatlength = bs.fat_length; - } - mydata->fat_sect = bs.reserved; - cursect = mydata->rootdir_sect - = mydata->fat_sect + mydata->fatlength * bs.fats; - curclus = bs.root_cluster; // For FAT32 only - mydata->clust_size = bs.cluster_size; - if (mydata->fatsize == 32) { - rootdir_size = mydata->clust_size; - mydata->data_begin = mydata->rootdir_sect /* + rootdir_size */ - - (mydata->clust_size * 2); - } else { - rootdir_size = ((bs.dir_entries[1] * (int) 256 + bs.dir_entries[0]) - * sizeof (dir_entry)) / SECTOR_SIZE; - mydata->data_begin = mydata->rootdir_sect + rootdir_size - - (mydata->clust_size * 2); - } - mydata->fatbufnum = -1; - - FAT_DPRINT ("FAT%d, fatlength: %d\n", mydata->fatsize, - mydata->fatlength); - FAT_DPRINT ("Rootdir begins at sector: %d, offset: %x, size: %d\n" - "Data begins at: %d\n", - mydata->rootdir_sect, mydata->rootdir_sect * SECTOR_SIZE, - rootdir_size, mydata->data_begin); - FAT_DPRINT ("Cluster size: %d\n", mydata->clust_size); - - /* "cwd" is always the root... */ - while (ISDIRDELIM (*filename)) - filename++; - /* Make a copy of the filename and convert it to lowercase */ - strcpy (fnamecopy, filename); - downcase (fnamecopy); - if (*fnamecopy == '\0') { - if (!dols){ - printf("\n not there\n"); - return -1; - } - dols = LS_ROOT; - } else if ((idx = dirdelim (fnamecopy)) >= 0) { - isdir = 1; - fnamecopy[idx] = '\0'; - subname = fnamecopy + idx + 1; - /* Handle multiple delimiters */ - while (ISDIRDELIM (*subname)) - subname++; - } else if (dols) { - isdir = 1; - } - - while (1) { - int i; - - if (disk_read (cursect, mydata->clust_size, do_fat_read_block) < 0) { - printf ("Error: reading rootdir block\n"); - return -1; - } - dentptr = (dir_entry *) do_fat_read_block; - for (i = 0; i < DIRENTSPERBLOCK; i++) { - char s_name[14], l_name[256]; - - l_name[0] = '\0'; - if ((dentptr->attr & ATTR_VOLUME)) { - /* Volume label or VFAT entry */ - dentptr++; - continue; - } else if (dentptr->name[0] == 0) { - FAT_DPRINT ("RootDentname == NULL - %d\n", i); - if (dols == LS_ROOT) { - printf ("\n%d file(s), %d dir(s)\n\n", files, dirs); - return 0; - } - return -1; - } -#ifdef CONFIG_SUPPORT_VFAT - else if (dols == LS_ROOT - && mkcksum (dentptr->name) == prevcksum) { - dentptr++; - continue; - } -#endif - get_name (dentptr, s_name); - if (dols == LS_ROOT) { - int isdir = (dentptr->attr & ATTR_DIR); - char dirc; - int doit = 0; - - if (isdir) { - dirc = '/'; - if (s_name[0] != 0) { - dirs++; - doit = 1; - } - } else { - dirc = ' '; - if (s_name[0] != 0) { - files++; - doit = 1; - } - } - if (doit) { - if (dirc == ' ') { - printf (" %8ld %s%c\n", - (long) FAT2CPU32 (dentptr->size), s_name, - dirc); - } else { - printf (" %s%c\n", s_name, dirc); - } - } - dentptr++; - continue; - } - if (strcmp (fnamecopy, s_name) && strcmp (fnamecopy, l_name)) { - FAT_DPRINT ("RootMismatch: |%s|%s|\n", s_name, l_name); - dentptr++; - continue; - } - if (isdir && !(dentptr->attr & ATTR_DIR)) - return -1; - - FAT_DPRINT ("RootName: %s", s_name); - FAT_DPRINT (", start: 0x%x", START (dentptr)); - FAT_DPRINT (", size: 0x%x %s\n", - FAT2CPU32 (dentptr->size), isdir ? "(DIR)" : ""); - - goto rootdir_done; /* We got a match */ - } - - if (mydata->fatsize != 32) - cursect++; - else { - // FAT32 does not guarantee contiguous root directory - curclus = get_fatent (mydata, curclus); - cursect = (curclus * mydata->clust_size) + mydata->data_begin; - - FAT_DPRINT ("root clus %d sector %d\n", curclus, cursect); - } - } - rootdir_done: - - firsttime = 1; - while (isdir) { - int startsect = mydata->data_begin - + START (dentptr) * mydata->clust_size; - dir_entry dent; - char *nextname = NULL; - - dent = *dentptr; - dentptr = &dent; - idx = dirdelim (subname); - if (idx >= 0) { - subname[idx] = '\0'; - nextname = subname + idx + 1; - /* Handle multiple delimiters */ - while (ISDIRDELIM (*nextname)) - nextname++; - if (dols && *nextname == '\0') - firsttime = 0; - } else { - if (dols && firsttime) { - firsttime = 0; - } else { - isdir = 0; - } - } - - if (get_dentfromdir (mydata, startsect, subname, dentptr, - isdir ? 0 : dols) == NULL) { - if (dols && !isdir) - return 0; - return -1; - } - - if (idx >= 0) { - if (!(dentptr->attr & ATTR_DIR)) - return -1; - subname = nextname; - } - } - ret = get_contents (mydata, dentptr, buffer, maxsize); - FAT_DPRINT ("Size: %d, got: %ld\n", FAT2CPU32 (dentptr->size), ret); - - return ret; -} - - -int -file_fat_detectfs(void) -{ - boot_sector bs; - volume_info volinfo; - int fatsize; - char vol_label[12]; - - if(cur_dev==NULL) { - printf("No current device\n"); - return 1; - } -#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ - (CONFIG_COMMANDS & CFG_CMD_USB) || (CONFIG_MMC) - printf("Interface: "); - switch(cur_dev->if_type) { - case IF_TYPE_IDE : printf("IDE"); break; - case IF_TYPE_SCSI : printf("SCSI"); break; - case IF_TYPE_ATAPI : printf("ATAPI"); break; - case IF_TYPE_USB : printf("USB"); break; - case IF_TYPE_DOC : printf("DOC"); break; - case IF_TYPE_MMC : printf("MMC"); break; - default : printf("Unknown"); - } - printf("\n Device %d: ",cur_dev->dev); - dev_print(cur_dev); -#endif - if(read_bootsectandvi(&bs, &volinfo, &fatsize)) { - printf("\nNo valid FAT fs found\n"); - return 1; - } - memcpy (vol_label, volinfo.volume_label, 11); - vol_label[11] = '\0'; - volinfo.fs_type[5]='\0'; - printf("Partition %d: Filesystem: %s \"%s\"\n",cur_part,volinfo.fs_type,vol_label); - return 0; -} - - -int -file_fat_ls(const char *dir) -{ - return do_fat_read(dir, NULL, 0, LS_YES); -} - - -long -file_fat_read(const char *filename, void *buffer, unsigned long maxsize) -{ - long ret; - ret = do_fat_read(filename, buffer, maxsize, LS_NO); - return ret; -} - -#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FAT) */ diff --git a/x-loader/fs/fat/file.c b/x-loader/fs/fat/file.c deleted file mode 100644 index 5994271..0000000 --- a/x-loader/fs/fat/file.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * file.c - * - * Mini "VFS" by Marcus Sundberg - * - * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6 - * 2003-03-10 - kharris@nexus-tech.net - ported to uboot - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_FAT) - -/* Supported filesystems */ -static const struct filesystem filesystems[] = { - { file_fat_detectfs, file_fat_ls, file_fat_read, "FAT" }, -}; -#define NUM_FILESYS (sizeof(filesystems)/sizeof(struct filesystem)) - -/* The filesystem which was last detected */ -static int current_filesystem = FSTYPE_NONE; - -/* The current working directory */ -#define CWD_LEN 511 -char file_cwd[CWD_LEN+1] = "/"; - -const char * -file_getfsname(int idx) -{ - if (idx < 0 || idx >= NUM_FILESYS) return NULL; - - return filesystems[idx].name; -} - - -static void -pathcpy(char *dest, const char *src) -{ - char *origdest = dest; - - do { - if (dest-file_cwd >= CWD_LEN) { - *dest = '\0'; - return; - } - *(dest) = *(src); - if (*src == '\0') { - if (dest-- != origdest && ISDIRDELIM(*dest)) { - *dest = '\0'; - } - return; - } - ++dest; - if (ISDIRDELIM(*src)) { - while (ISDIRDELIM(*src)) src++; - } else { - src++; - } - } while (1); -} - - -int -file_cd(const char *path) -{ - if (ISDIRDELIM(*path)) { - while (ISDIRDELIM(*path)) path++; - strncpy(file_cwd+1, path, CWD_LEN-1); - } else { - const char *origpath = path; - char *tmpstr = file_cwd; - int back = 0; - - while (*tmpstr != '\0') tmpstr++; - do { - tmpstr--; - } while (ISDIRDELIM(*tmpstr)); - - while (*path == '.') { - path++; - while (*path == '.') { - path++; - back++; - } - if (*path != '\0' && !ISDIRDELIM(*path)) { - path = origpath; - back = 0; - break; - } - while (ISDIRDELIM(*path)) path++; - origpath = path; - } - - while (back--) { - /* Strip off path component */ - while (!ISDIRDELIM(*tmpstr)) { - tmpstr--; - } - if (tmpstr == file_cwd) { - /* Incremented again right after the loop. */ - tmpstr--; - break; - } - /* Skip delimiters */ - while (ISDIRDELIM(*tmpstr)) tmpstr--; - } - tmpstr++; - if (*path == '\0') { - if (tmpstr == file_cwd) { - *tmpstr = '/'; - tmpstr++; - } - *tmpstr = '\0'; - return 0; - } - *tmpstr = '/'; - pathcpy(tmpstr+1, path); - } - - return 0; -} - - -int -file_detectfs(void) -{ - int i; - - current_filesystem = FSTYPE_NONE; - - for (i = 0; i < NUM_FILESYS; i++) { - if (filesystems[i].detect() == 0) { - strcpy(file_cwd, "/"); - current_filesystem = i; - break; - } - } - - return current_filesystem; -} - - -int -file_ls(const char *dir) -{ - char fullpath[1024]; - const char *arg; - - if (current_filesystem == FSTYPE_NONE) { - printf("Can't list files without a filesystem!\n"); - return -1; - } - - if (ISDIRDELIM(*dir)) { - arg = dir; - } else { - sprintf(fullpath, "%s/%s", file_cwd, dir); - arg = fullpath; - } - return filesystems[current_filesystem].ls(arg); -} - - -long -file_read(const char *filename, void *buffer, unsigned long maxsize) -{ - char fullpath[1024]; - const char *arg; - - if (current_filesystem == FSTYPE_NONE) { - printf("Can't load file without a filesystem!\n"); - return -1; - } - - if (ISDIRDELIM(*filename)) { - arg = filename; - } else { - sprintf(fullpath, "%s/%s", file_cwd, filename); - arg = fullpath; - } - - return filesystems[current_filesystem].read(arg, buffer, maxsize); -} - -#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FAT) */ diff --git a/x-loader/include/asm/arch-arm1136/bits.h b/x-loader/include/asm/arch-arm1136/bits.h deleted file mode 100644 index dc3273e..0000000 --- a/x-loader/include/asm/arch-arm1136/bits.h +++ /dev/null @@ -1,49 +0,0 @@ -/* bits.h - * Copyright (c) 2004 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ -#ifndef __bits_h -#define __bits_h 1 - -#define BIT0 (1<<0) -#define BIT1 (1<<1) -#define BIT2 (1<<2) -#define BIT3 (1<<3) -#define BIT4 (1<<4) -#define BIT5 (1<<5) -#define BIT6 (1<<6) -#define BIT7 (1<<7) -#define BIT8 (1<<8) -#define BIT9 (1<<9) -#define BIT10 (1<<10) -#define BIT11 (1<<11) -#define BIT12 (1<<12) -#define BIT13 (1<<13) -#define BIT14 (1<<14) -#define BIT15 (1<<15) -#define BIT16 (1<<16) -#define BIT17 (1<<17) -#define BIT18 (1<<18) -#define BIT19 (1<<19) -#define BIT20 (1<<20) -#define BIT21 (1<<21) -#define BIT22 (1<<22) -#define BIT23 (1<<23) -#define BIT24 (1<<24) -#define BIT25 (1<<25) -#define BIT26 (1<<26) -#define BIT27 (1<<27) -#define BIT28 (1<<28) -#define BIT29 (1<<29) -#define BIT30 (1<<30) -#define BIT31 (1<<31) - -#endif - diff --git a/x-loader/include/asm/arch-arm1136/clocks.h b/x-loader/include/asm/arch-arm1136/clocks.h deleted file mode 100644 index 8e00d2e..0000000 --- a/x-loader/include/asm/arch-arm1136/clocks.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP24XX_CLOCKS_H_ -#define _OMAP24XX_CLOCKS_H_ - -#define COMMIT_DIVIDERS 0x1 -#define MODE_BYPASS_FAST 0x2 -#define APLL_LOCK 0xc -#define DPLL_LOCK 0x3 /* DPLL lock */ -#define LDELAY 12000000 - -#if defined(CONFIG_OMAP242X) -#include -#elif defined(CONFIG_OMAP243X) -#include -#endif - -#define S12M 12000000 -#define S13M 13000000 -#define S19_2M 19200000 -#define S24M 24000000 -#define S26M 26000000 -#define S38_4M 38400000 - -#endif - - - - - - - - diff --git a/x-loader/include/asm/arch-arm1136/clocks242x.h b/x-loader/include/asm/arch-arm1136/clocks242x.h deleted file mode 100644 index 0ae1c4e..0000000 --- a/x-loader/include/asm/arch-arm1136/clocks242x.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP242X_CLOCKS_H_ -#define _OMAP242X_CLOCKS_H_ - -/****************************************************************************; -; PRCM Scheme I -; -; Enable clocks and DPLL for: -; DPLL=330, DPLLout=660 M=1,N=55 CM_CLKSEL1_PLL[21:8] 12/2*55 -; Core=660 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=330 (mpu domain) 2 CM_CLKSEL_MPU[4:0] -; DSPF=220 (dsp domain) 3 CM_CLKSEL_DSP[4:0] -; DSPI=110 6 CM_CLKSEL_DSP[6:5] -; DSP_S activated CM_CLKSEL_DSP[7] -; IVAF=165 (dsp domain) 4 CM_CLKSEL_DSP[12:8] -; IVAF=82.5 auto -; IVAI auto -; IVA_MPU auto -; IVA_S bypass CM_CLKSEL_DSP[13] -; GFXF=82.5 (gfx domain) 8 CM_CLKSEL_FGX[2:0] -; SSI_SSRF=220 3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=110 auto -; L3=165Mhz (sdram) 4 CM_CLKSEL1_CORE[4:0] -; L4=82.5Mhz 8 -; C_L4_USB=41.25 16 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define I_DPLL_OUT_X2 0x2 /* x2 core out */ -#define I_MPU_DIV 0x2 /* mpu = core/2 */ -#define I_DSP_DIV 0x3c3 /* dsp & iva divider */ -#define I_GFX_DIV 0x2 -#define I_BUS_DIV 0x04601044 -#ifdef INPUT_CLK_13MHZ -#define I_DPLL_330 0x0114AC00 /* 13MHz */ -#else -#define I_DPLL_330 0x01837100 /* 12MHz */ -#endif - -/****************************************************************************; -; PRCM Scheme II -; -; Enable clocks and DPLL for: -; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 -; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] -; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] -; DSPI=100 6 CM_CLKSEL_DSP[6:5] -; DSP_S bypass CM_CLKSEL_DSP[7] -; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8] -; IVAF=100 auto -; IVAI auto -; IVA_MPU auto -; IVA_S bypass CM_CLKSEL_DSP[13] -; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0] -; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=100 auto -; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0] -; L4=100Mhz 6 -; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define II_DPLL_OUT_X2 0x2 /* x2 core out */ -#define II_MPU_DIV 0x2 /* mpu = core/2 */ -#define II_DSP_DIV 0x343 /* dsp & iva divider */ -#define II_GFX_DIV 0x2 -#define II_BUS_DIV 0x04601026 -#ifdef INPUT_CLK_13MHZ -#define II_DPLL_300 0x0112CC00 /* 13MHz */ -#else -#define II_DPLL_300 0x01832100 /* 12MHz */ -#endif - -/****************************************************************************; -; PRCM Scheme III -; -; Enable clocks and DPLL for: -; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 -; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] -; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] -; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] -; DSP_S ACTIVATED CM_CLKSEL_DSP[7] -; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8] -; IVAF=88.67 auto -; IVAI auto -; IVA_MPU auto -; IVA_S ACTIVATED CM_CLKSEL_DSP[13] -; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]: -; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20] -; SSI_SSTF=88.67 auto -; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0] -; L4=66.5Mhz /8 -; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5] -***************************************************************************/ -#define III_DPLL_OUT_X2 0x2 /* x2 core out */ -#define III_MPU_DIV 0x2 /* mpu = core/2 */ -#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ -#define III_GFX_DIV 0x2 -#define III_BUS_DIV 0x08301044 -#ifdef INPUT_CLK_13MHZ -#define III_DPLL_266 0x0110AC00 /* 13MHz */ -#else -#define III_DPLL_266 0x01885500 /* 12MHz */ -#endif - -/* set defaults for boot up */ -#ifdef PRCM_CONFIG_I -# define DPLL_OUT I_DPLL_OUT_X2 -# define MPU_DIV I_MPU_DIV -# define DSP_DIV I_DSP_DIV -# define GFX_DIV I_GFX_DIV -# define BUS_DIV I_BUS_DIV -# define DPLL_VAL I_DPLL_266 -#elif PRCM_CONFIG_II -# define DPLL_OUT II_DPLL_OUT_X2 -# define MPU_DIV II_MPU_DIV -# define DSP_DIV II_DSP_DIV -# define GFX_DIV II_GFX_DIV -# define BUS_DIV II_BUS_DIV -# define DPLL_VAL II_DPLL_300 -#elif PRCM_CONFIG_III -# define DPLL_OUT III_DPLL_OUT_X2 -# define MPU_DIV III_MPU_DIV -# define DSP_DIV III_DSP_DIV -# define GFX_DIV III_GFX_DIV -# define BUS_DIV III_BUS_DIV -# define DPLL_VAL III_DPLL_266 -#endif - -#endif diff --git a/x-loader/include/asm/arch-arm1136/clocks243x.h b/x-loader/include/asm/arch-arm1136/clocks243x.h deleted file mode 100644 index 18d2e46..0000000 --- a/x-loader/include/asm/arch-arm1136/clocks243x.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * (C) Copyright 2005 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP243X_CLOCKS_H_ -#define _OMAP243X_CLOCKS_H_ - -/* cm_clksel core fields not ratio governed */ -#define RX_CLKSEL_DSS1 (0x10 << 8) -#define RX_CLKSEL_DSS2 (0x0 << 13) -#define RX_CLKSEL_SSI (0x5 << 20) - -/* 2430 Ratio's */ -/* 2430-Ratio Config 1 */ -#define R1_CLKSEL_L3 (4 << 0) -#define R1_CLKSEL_L4 (2 << 5) -#define R1_CLKSEL_USB (4 << 25) -#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \ - | RX_CLKSEL_DSS1 | R1_CLKSEL_L4 | R1_CLKSEL_L3 -#define R1_CLKSEL_MPU (2 << 0) -#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU -#define R1_CLKSEL_DSP (2 << 0) -#define R1_CLKSEL_DSP_IF (2 << 5) -#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF -#define R1_CLKSEL_GFX (2 << 0) -#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX -#define R1_CLKSEL_MDM (4 << 0) -#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM - -/* 2430-Ratio Config 2 */ -#define R2_CLKSEL_L3 (6 << 0) -#define R2_CLKSEL_L4 (2 << 5) -#define R2_CLKSEL_USB (2 << 25) -#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \ - | RX_CLKSEL_DSS1 | R2_CLKSEL_L4 | R2_CLKSEL_L3 -#define R2_CLKSEL_MPU (2 << 0) -#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU -#define R2_CLKSEL_DSP (2 << 0) -#define R2_CLKSEL_DSP_IF (3 << 5) -#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF -#define R2_CLKSEL_GFX (2 << 0) -#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX -#define R2_CLKSEL_MDM (6 << 0) -#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM - -/* 2430-Ratio Boot */ -#define RB_CLKSEL_L3 (1 << 0) -#define RB_CLKSEL_L4 (1 << 5) -#define RB_CLKSEL_USB (1 << 25) -#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \ - | RX_CLKSEL_DSS1 | RB_CLKSEL_L4 | RB_CLKSEL_L3 -#define RB_CLKSEL_MPU (1 << 0) -#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU -#define RB_CLKSEL_DSP (1 << 0) -#define RB_CLKSEL_DSP_IF (1 << 5) -#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF -#define RB_CLKSEL_GFX (1 << 0) -#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX -#define RB_CLKSEL_MDM (1 << 0) -#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM - -/* 2430 Target modes: Along with each configuration the CPU has several modes - * which goes along with them. Modes mainly are the addition of descrite DPLL - * combinations to go along with a ratio. - */ -/* hardware goverend */ -#define MX_48M_SRC (0 << 3) -#define MX_54M_SRC (0 << 5) -#define MX_APLLS_CLIKIN_12 (3 << 23) -#define MX_APLLS_CLIKIN_13 (2 << 23) -#define MX_APLLS_CLIKIN_19_2 (0 << 23) - -/* 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed */ - -/* boot (boot) */ -#define MB_DPLL_MULT (1 << 12) -#define MB_DPLL_DIV (0 << 8) -#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ - | MB_DPLL_MULT | MX_APLLS_CLIKIN_12 - -#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ - | MB_DPLL_MULT | MX_APLLS_CLIKIN_13 - -#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ - | MB_DPLL_MULT | MX_APLLS_CLIKIN_19 - -/* #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz */ - -#define M2_DPLL_MULT_12 (55 << 12) -#define M2_DPLL_DIV_12 (1 << 8) -#define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_12 \ - | M2_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 -/* Use 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, relock time issue */ -#define M2_DPLL_MULT_13 (330 << 12) -#define M2_DPLL_DIV_13 (12 << 8) -#define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_13 \ - | M2_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 -#define M2_DPLL_MULT_19 (275 << 12) -#define M2_DPLL_DIV_19 (15 << 8) -#define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_19 \ - | M2_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 - -/* #3 (ratio2) DPLL = 330*2 = 660MHz, L3=110MHz */ -#define M3_DPLL_MULT_12 (55 << 12) -#define M3_DPLL_DIV_12 (1 << 8) -#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_12 \ - | M3_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 -#define M3_DPLL_MULT_13 (330 << 12) -#define M3_DPLL_DIV_13 (12 << 8) -#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_13 \ - | M3_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 -#define M3_DPLL_MULT_19 (275 << 12) -#define M3_DPLL_DIV_19 (15 << 8) -#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_19 \ - | M3_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 - -/* #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz*/ -#define M4_DPLL_MULT_12 (133 << 12) -#define M4_DPLL_DIV_12 (3 << 8) -#define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_12 \ - | M4_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 -#define M4_DPLL_MULT_13 (399 << 12) -#define M4_DPLL_DIV_13 (12 << 8) -#define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_13 \ - | M4_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 -#define M4_DPLL_MULT_19 (145 << 12) -#define M4_DPLL_DIV_19 (6 << 8) -#define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_19 \ - | M4_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 - -/* #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz, L3=133MHz */ -#define M5A_DPLL_MULT_12 (133 << 12) -#define M5A_DPLL_DIV_12 (5 << 8) -#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_12 \ - | M5A_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 -#define M5A_DPLL_MULT_13 (266 << 12) -#define M5A_DPLL_DIV_13 (12 << 8) -#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_13 \ - | M5A_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 -#define M5A_DPLL_MULT_19 (180 << 12) -#define M5A_DPLL_DIV_19 (12 << 8) -#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_19 \ - | M5A_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 - -/* #5b (ratio1) target DPLL = 200*2 = 400MHz, L3=100MHz */ -#define M5B_DPLL_MULT_12 (50 << 12) -#define M5B_DPLL_DIV_12 (2 << 8) -#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_12 \ - | M5B_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 -#define M5B_DPLL_MULT_13 (200 << 12) -#define M5B_DPLL_DIV_13 (12 << 8) - -#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_13 \ - | M5B_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 -#define M5B_DPLL_MULT_19 (125 << 12) -#define M5B_DPLL_DIV_19 (31 << 8) -#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_19 \ - | M5B_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 - -/* 2430 - chassis (sedna) */ - /* 165 (ratio1) same as above #2 */ - /* 150 (ratio1)*/ - /* 133 (ratio2) same as above #4 */ - /* 110 (ratio2) same as above #3*/ - /* 104 (ratio2)*/ - /* boot (boot) */ - -/* high and low operation value */ -#define MX_CLKSEL2_PLL_2x_VAL (2 << 0) -#define MX_CLKSEL2_PLL_1x_VAL (1 << 0) - -/* set defaults for boot up */ -#if defined(PRCM_CONFIG_2) /* ARM-330MHz IVA2-330MHz L3-165MHz */ -# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL -# define MPU_DIV R1_CLKSEL_MPU -# define DSP_DIV R1_CM_CLKSEL_DSP_VAL -# define GFX_DIV R1_CM_CLKSEL_GFX_VAL -# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL -# define DPLL_VAL M2_CM_CLKSEL1_PLL_13_VAL -# define MDM_DIV R2_CM_CLKSEL_MDM_VAL -#elif defined(PRCM_CONFIG_3) /* ARM-330MHz IVA2-330MHz L3-110MHz */ -# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL -# define MPU_DIV R2_CLKSEL_MPU -# define DSP_DIV R2_CM_CLKSEL_DSP_VAL -# define GFX_DIV R2_CM_CLKSEL_GFX_VAL -# define BUS_DIV R2_CM_CLKSEL1_CORE_VAL -# define DPLL_VAL M3_CM_CLKSEL1_PLL_13_VAL -# define MDM_DIV R2_CM_CLKSEL_MDM_VAL -#elif defined(PRCM_CONFIG_5A) /* ARM-266MHz IVA2-266MHz L3-133MHz */ -# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL -# define MPU_DIV R1_CLKSEL_MPU -# define DSP_DIV R1_CM_CLKSEL_DSP_VAL -# define GFX_DIV R1_CM_CLKSEL_GFX_VAL -# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL -# define DPLL_VAL M5A_CM_CLKSEL1_PLL_13_VAL -# define MDM_DIV R2_CM_CLKSEL_MDM_VAL -#elif defined(PRCM_CONFIG_5B) /* ARM-200MHz IVA2-200MHz L3-100MHz */ -# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL -# define MPU_DIV R1_CLKSEL_MPU -# define DSP_DIV R1_CM_CLKSEL_DSP_VAL -# define GFX_DIV R1_CM_CLKSEL_GFX_VAL -# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL -# define DPLL_VAL M5B_CM_CLKSEL1_PLL_13_VAL -# define MDM_DIV R1_CM_CLKSEL_MDM_VAL -#endif - -#endif diff --git a/x-loader/include/asm/arch-arm1136/mem.h b/x-loader/include/asm/arch-arm1136/mem.h deleted file mode 100644 index 2a3da73..0000000 --- a/x-loader/include/asm/arch-arm1136/mem.h +++ /dev/null @@ -1,383 +0,0 @@ - -/* - * (C) Copyright 2004-2005 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP24XX_MEM_H_ -#define _OMAP24XX_MEM_H_ - -#define SDRC_CS0_OSET 0x0 -#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ - -#ifndef __ASSEMBLY__ -/* struct's for holding data tables for current boards, they are getting used - early in init when NO global access are there */ -struct sdrc_data_s { - u32 sdrc_sharing; - u32 sdrc_mdcfg_0_ddr; - u32 sdrc_mdcfg_0_sdr; - u32 sdrc_actim_ctrla_0; - u32 sdrc_actim_ctrlb_0; - u32 sdrc_rfr_ctrl; - u32 sdrc_mr_0_ddr; - u32 sdrc_mr_0_sdr; - u32 sdrc_dllab_ctrl; -} /*__attribute__ ((packed))*/; -typedef struct sdrc_data_s sdrc_data_t; - -typedef enum { - STACKED = 0, - IP_DDR = 1, - COMBO_DDR = 2, - IP_SDR = 3, -} mem_t; - -#endif - -/* set the 243x-SDRC incoming address convention */ -#if defined(SDRC_B_R_C) -#define B_ALL (0 << 6) /* bank-row-column */ -#elif defined(SDRC_B1_R_B0_C) -#define B_ALL (1 << 6) /* bank1-row-bank0-column */ -#elif defined(SDRC_R_B_C) -#define B_ALL (2 << 6) /* row-bank-column */ -#endif - -/* Slower full frequency range default timings for x32 operation*/ -#define H4_2420_SDRC_SHARING 0x00000100 -#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */ -#define H4_2420_SDRC_MR_0_SDR 0x00000031 -#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */ -#define SDP_2430_SDRC_MDCFG_0_DDR (0x02584019|B_ALL) /* Infin ddr module */ -#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */ -#define H4_2420_SDRC_MR_0_DDR 0x00000032 - -#define H4_2422_SDRC_SHARING 0x00004b00 -#define H4_2422_SDRC_MDCFG_MONO_DDR 0x01A02011 /* stacked mono die ddr on 2422 */ -#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked dual die ddr on 2422 */ -#define H4_2422_SDRC_MR_0_DDR 0x00000032 - -#define H4_2423_SDRC_SHARING 0x00004900 /* 2420POP board cke1 not connected */ -#define H4_2423_SDRC_MDCFG_0_DDR 0x01A02011 /* stacked dual die ddr on 2423 */ -#define H4_2423_SDRC_MDCFG_1_DDR 0x00801011 /* stacked dual die ddr on 2423 */ - -/* ES1 work around timings */ -#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */ -#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020 -#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */ - -/* optimized timings good for current shipping parts */ -#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485 -#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e -#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */ -#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ -#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 -#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50 = 0x3de */ -#define SDP_24XX_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50 = 0x4e2 */ -#define H4_242X_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 90deg, allow DPLLout*1 to work (combo)*/ -#define H4_242X_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 90deg, for ES2 */ -#define SDP_24XX_SDRC_DLLAB_CTRL_165MHz 0x0000170C /* 72deg, code will recalc dll load */ - -/* Infineon part of 2430SDP (133MHz optimized) ~ 7.5ns - * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 - * TDPL = 15/7.5 = 2 - * TRRD = 15/2.5 = 2 - * TRCD = 22.5/7.5 = 3 - * TRP = 22.5/7.5 = 3 - * TRAS = 45/7.5 = 6 - * TRC = 65/7.5 = 8.6->9 - * TRFC = 75/7.5 = 10 - * ACTIMB - * TCKE = 2 - * XSR = 120/7.5 = 16 - */ -#define TDAL_133 5 -#define TDPL_133 2 -#define TRRD_133 2 -#define TRCD_133 3 -#define TRP_133 3 -#define TRAS_133 6 -#define TRC_133 9 -#define TRFC_133 10 -#define V_ACTIMA_133 ((TRFC_133 << 27) | (TRC_133 << 22) | (TRAS_133 << 18) |(TRP_133 << 15) | \ - (TRCD_133 << 12) |(TRRD_133 << 9) |(TDPL_133 << 6) | (TDAL_133)) - -#define TCKE_133 2 -#define XSR_133 16 -#define V_ACTIMB_133 ((TCKE_133 << 12) | (XSR_133 << 0)) - -/* Infineon part of 2430SDP (165MHz optimized) 6.06ns - * ACTIMA - * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 18/6 = 3 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 72/6 = 12 - * ACTIMB - * TCKE = 2 - * XSR = 120/6 = 20 - */ -#define TDAL_165 6 -#define TDPL_165 3 -#define TRRD_165 2 -#define TRCD_165 3 -#define TRP_165 3 -#define TRAS_165 7 -#define TRC_165 10 -#define TRFC_165 12 -#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) |(TRP_165 << 15) | \ - (TRCD_165 << 12) |(TRRD_165 << 9) |(TDPL_165 << 6) | (TDAL_165)) - -#define TCKE_165 2 -#define XSR_165 20 -#define V_ACTIMB_165 ((TCKE_165 << 12) | (XSR_165 << 0)) - -#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133 -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2420_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_100MHz -# define SDP_2430_SDRC_DLLAB_CTRL 0x0000730E -# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz -# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz -# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz -# define H4_2422_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_100MHz -#elif defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3) -# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz -# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133 -# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz -# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz -# define H4_2420_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_133MHz -# define SDP_2430_SDRC_DLLAB_CTRL 0x0000730E -# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz -# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz -# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz -# define H4_2422_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_133MHz -#elif defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) -# define H4_2420_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 -# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 -# define H4_2420_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 -# define H4_2420_SDRC_RFR_CTRL SDP_24XX_SDRC_RFR_CTRL_165MHz -# define H4_2420_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz -# define SDP_2430_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz -# define H4_2422_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 -# define H4_2422_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 -# define H4_2422_SDRC_RFR_CTRL SDP_24XX_SDRC_RFR_CTRL_165MHz -# define H4_2422_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz -#endif - -/* - * GPMC settings - - * Definitions is as per the following format - * # define _GPMC_CONFIG - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of the same. - * if values are independent of the board, this definition will be present in this file - * if values are dependent on the board, then this should go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * STNOR - Intel Strata Flash - * SMNAND - Samsung NAND - * MPDB - H4 MPDB board - * SBNOR - Sibley NOR - * ONNAND - Samsung One NAND - * - * include/configs/file.h contains the following defn - for all CS we are interested - * #define OMAP24XX_GPMC_CSx PART - * #define OMAP24XX_GPMC_CSx_SIZE Size - * #define OMAP24XX_GPMC_CSx_MAP Map - * Where: - * x - CS number - * PART - Part Name as defined above - * SIZE - how big is the mapping to be - * GPMC_SIZE_128M - 0x8 - * GPMC_SIZE_64M - 0xC - * GPMC_SIZE_32M - 0xE - * GPMC_SIZE_16M - 0xF - * MAP - Map this CS to which address(GPMC address space)- Absolute address - * >>24 before being used. - */ - -#define GPMC_SIZE_256M 0x0 -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) /* L3 at 100MHz */ -# define SMNAND_GPMC_CONFIG1 0x0 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x00000A80 -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x000f0f01 -# define STNOR_GPMC_CONFIG3 0x00050502 -# define STNOR_GPMC_CONFIG4 0x0C060C06 -# define STNOR_GPMC_CONFIG5 0x01131F1F -# define STNOR_GPMC_CONFIG6 0x0 /* 0? Not defined so far... this value is reset val as per gpmc doc */ -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001F1F00 -# define MPDB_GPMC_CONFIG3 0x00080802 -# define MPDB_GPMC_CONFIG4 0x1C091C09 -# define MPDB_GPMC_CONFIG5 0x031A1F1F -# define MPDB_GPMC_CONFIG6 0x000003C2 -#endif - -#if defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3) /* L3 at 133MHz */ -# define SMNAND_GPMC_CONFIG1 0x00001800 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x00000A80 -# define SMNAND_GPMC_CONFIG7 0x00000C44 - -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x00151501 -# define STNOR_GPMC_CONFIG3 0x00060602 -# define STNOR_GPMC_CONFIG4 0x10081008 -# define STNOR_GPMC_CONFIG5 0x01131F1F -# define STNOR_GPMC_CONFIG6 0x000004c4 - -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001f1f01 -# define MPDB_GPMC_CONFIG3 0x00080803 -# define MPDB_GPMC_CONFIG4 0x1C091C09 -# define MPDB_GPMC_CONFIG5 0x041f1F1F -# define MPDB_GPMC_CONFIG6 0x000004C4 - -# define SIBNOR_GPMC_CONFIG1 0x3 -# define SIBNOR_GPMC_CONFIG2 0x00151501 -# define SIBNOR_GPMC_CONFIG3 0x00060602 -# define SIBNOR_GPMC_CONFIG4 0x10081008 -# define SIBNOR_GPMC_CONFIG5 0x01131F1F -# define SIBNOR_GPMC_CONFIG6 0x00000000 - -# define ONENAND_GPMC_CONFIG1 0x00001200 -# define ONENAND_GPMC_CONFIG2 0x000c0c01 -# define ONENAND_GPMC_CONFIG3 0x00030301 -# define ONENAND_GPMC_CONFIG4 0x0c040c04 -# define ONENAND_GPMC_CONFIG5 0x010C1010 -# define ONENAND_GPMC_CONFIG6 0x00000000 - -# define PCMCIA_GPMC_CONFIG1 0x01E91200 -# define PCMCIA_GPMC_CONFIG2 0x001E1E01 -# define PCMCIA_GPMC_CONFIG3 0x00020203 -# define PCMCIA_GPMC_CONFIG4 0x1D041D04 -# define PCMCIA_GPMC_CONFIG5 0x031D1F1F -# define PCMCIA_GPMC_CONFIG6 0x000004C4 -#endif /* endif CFG_PRCM_III */ - -#if defined (PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) /* L3 at 165MHz */ -# define SMNAND_GPMC_CONFIG1 0x00001800 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x00000A80 -# define SMNAND_GPMC_CONFIG7 0x00000C44 - -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x00151501 -# define STNOR_GPMC_CONFIG3 0x00060602 -# define STNOR_GPMC_CONFIG4 0x11091109 -# define STNOR_GPMC_CONFIG5 0x01141F1F -# define STNOR_GPMC_CONFIG6 0x000004c4 - -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001f1f01 -# define MPDB_GPMC_CONFIG3 0x00080803 -# define MPDB_GPMC_CONFIG4 0x1c0b1c0a -# define MPDB_GPMC_CONFIG5 0x041f1F1F -# define MPDB_GPMC_CONFIG6 0x000004C4 - -# define SIBNOR_GPMC_CONFIG1 0x3 -# define SIBNOR_GPMC_CONFIG2 0x00151501 -# define SIBNOR_GPMC_CONFIG3 0x00060602 -# define SIBNOR_GPMC_CONFIG4 0x11091109 -# define SIBNOR_GPMC_CONFIG5 0x01141F1F -# define SIBNOR_GPMC_CONFIG6 0x00000000 - -# define ONENAND_GPMC_CONFIG1 0x00001200 -# define ONENAND_GPMC_CONFIG2 0x000F0F01 -# define ONENAND_GPMC_CONFIG3 0x00030301 -# define ONENAND_GPMC_CONFIG4 0x0F040F04 -# define ONENAND_GPMC_CONFIG5 0x010F1010 -# define ONENAND_GPMC_CONFIG6 0x00000000 - -# define PCMCIA_GPMC_CONFIG1 0x01E91200 -# define PCMCIA_GPMC_CONFIG2 0x001E1E01 -# define PCMCIA_GPMC_CONFIG3 0x00020203 -# define PCMCIA_GPMC_CONFIG4 0x1D041D04 -# define PCMCIA_GPMC_CONFIG5 0x031D1F1F -# define PCMCIA_GPMC_CONFIG6 0x000004C4 - -#endif - -#if 0 -/* Board Specific Settings for each of the configurations for chips - * whose values change as per platform. - None currently - */ -#if CONFIG_OMAP24XXH4 -#include -#endif - -#if CONFIG_2430SDP -#include -#endif - -#endif /* if 0 */ - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#define PROC_NOR 1 -#define PROC_NAND 2 -#define PISMO_SIBLEY0 3 -#define PISMO_SIBLEY1 4 -#define PISMO_ONENAND 5 -#define DBG_MPDB 6 -#define PISMO_PCMCIA 7 - -/* make it readable for the gpmc_init */ -#define PROC_NOR_BASE FLASH_BASE -#define PROC_NAND_BASE NAND_BASE -#define PISMO_SIB0_BASE SIBLEY_MAP1 -#define PISMO_SIB1_BASE SIBLEY_MAP2 -#define PISMO_ONEN_BASE ONENAND_MAP -#define DBG_MPDB_BASE DEBUG_BASE -#define PISMO_PCMCIA_BASE PCMCIA_BASE - -#endif /* endif _OMAP24XX_MEM_H_ */ diff --git a/x-loader/include/asm/arch-arm1136/omap2420.h b/x-loader/include/asm/arch-arm1136/omap2420.h deleted file mode 100644 index 2164b68..0000000 --- a/x-loader/include/asm/arch-arm1136/omap2420.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (C) 2005 Texas Instruments, - * - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP2420_SYS_H_ -#define _OMAP2420_SYS_H_ - -#include - - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - - -/* - * 2420 specific Section - */ - -/* CONTROL */ -#define OMAP2420_CTRL_BASE (0x48000000) -#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) - -/* TAP information */ -#define OMAP2420_TAP_BASE (0x48014000) -#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) - -/* GPMC */ -#define OMAP2420_GPMC_BASE (0x6800A000) -#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) -#define GPMC_SYSSTATUS (OMAP2420_GPMC_BASE+0x14) -#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) -#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) -#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) -#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) -#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) -#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) -#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) -#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) -#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) -#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) -#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) -#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) -#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) -#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) -#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) - -/* SMS */ -#define OMAP2420_SMS_BASE 0x68008000 -#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) - -/* SDRC */ -#define OMAP2420_SDRC_BASE 0x68009000 -#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) -#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) -#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) -#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) -#define SDRC_DLLA_STATUS (OMAP2420_SDRC_BASE+0x64) -#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) -#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) -#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) -#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) -#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) -#define SDRC_MCFG_1 (OMAP2420_SDRC_BASE+0xB0) -#define SDRC_MR_1 (OMAP2420_SDRC_BASE+0xB4) -#define SDRC_EMR2_1 (OMAP2420_SDRC_BASE+0xBC) -#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) -#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) -#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) -#define SDRC_RFR_CTRL1 (OMAP2420_SDRC_BASE+0xD4) -#define SDRC_MANUAL_1 (OMAP2420_SDRC_BASE+0xD8) - -#define OMAP2420_SDRC_CS0 0x80000000 -#define OMAP2420_SDRC_CS1 0xA0000000 - -#define LOADDLL BIT2 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET BIT1 -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - - -/* UART */ -#define OMAP2420_UART1 0x4806A000 -#define OMAP2420_UART2 0x4806C000 -#define OMAP2420_UART3 0x4806E000 - -/* General Purpose Timers */ -#define OMAP2420_GPT1 0x48028000 -#define OMAP2420_GPT2 0x4802A000 -#define OMAP2420_GPT3 0x48078000 -#define OMAP2420_GPT4 0x4807A000 -#define OMAP2420_GPT5 0x4807C000 -#define OMAP2420_GPT6 0x4807E000 -#define OMAP2420_GPT7 0x48080000 -#define OMAP2420_GPT8 0x48082000 -#define OMAP2420_GPT9 0x48084000 -#define OMAP2420_GPT10 0x48086000 -#define OMAP2420_GPT11 0x48088000 -#define OMAP2420_GPT12 0x4808A000 - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE 0x48020000 -#define WD2_BASE 0x48022000 -#define WD3_BASE 0x48024000 -#define WD4_BASE 0x48026000 -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define OMAP2420_CM_BASE 0x48008000 -#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) -#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) -#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) -#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) -#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) -#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) -#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) -#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) -#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) -#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) -#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) -#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) -#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) -#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) -#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) -#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) - -/* - * H4 specific Section - */ - -/* - * The 2420's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - */ -#if defined(CONFIG_OMAP2420H4) -/* GPMC */ -#ifdef CONFIG_VIRTIO_A /* Pre version B */ -# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x04000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ -#else -# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x08000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ -#endif - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) - -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define PERIFERAL_PORT_BASE 0x480FE003 - -/* FPGA on Debug board.*/ -#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) -#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) -#endif /* endif CONFIG_2420H4 */ - -#endif - diff --git a/x-loader/include/asm/arch-arm1136/omap2430.h b/x-loader/include/asm/arch-arm1136/omap2430.h deleted file mode 100644 index cf2b0f9..0000000 --- a/x-loader/include/asm/arch-arm1136/omap2430.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP2430_SYS_H_ -#define _OMAP2430_SYS_H_ - -#include - - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - -/* device type */ -#define DEVICE_MASK (BIT8|BIT9|BIT10) -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/* - * 2430 specific Section - */ -#define OMAP243X_CORE_L4_IO_BASE 0x48000000 -#define OMAP243X_WAKEUP_L4_IO_BASE 0x49000000 -#define OMAP24XX_L4_IO_BASE OMAP243X_CORE_L4_IO_BASE - - -/* CONTROL */ -#define OMAP24XX_CTRL_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x2000) -#define CONTROL_STATUS (OMAP24XX_CTRL_BASE + 0x2F8) - -/* TAP information */ -#define OMAP24XX_TAP_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0xA000) -#define TAP_IDCODE_REG (OMAP24XX_TAP_BASE+0x204) - -/* - GPMC : In 2430 NOR and NAND can coexist. - During NAND booting , NAND is at CS0 and NOR at CS1 - and Debug FPGA is GPMC_CS5 -*/ -#define OMAP24XX_GPMC_BASE (0x6E000000) - -#define GPMC_SYSCONFIG (OMAP24XX_GPMC_BASE+0x10) -#define GPMC_SYSSTATUS (OMAP24XX_GPMC_BASE+0x14) -#define GPMC_IRQENABLE (OMAP24XX_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP24XX_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP24XX_GPMC_BASE+0x50) -#define GPMC_CONFIG1_0 (OMAP24XX_GPMC_BASE+0x60) -#define GPMC_CONFIG2_0 (OMAP24XX_GPMC_BASE+0x64) -#define GPMC_CONFIG3_0 (OMAP24XX_GPMC_BASE+0x68) -#define GPMC_CONFIG4_0 (OMAP24XX_GPMC_BASE+0x6C) -#define GPMC_CONFIG5_0 (OMAP24XX_GPMC_BASE+0x70) -#define GPMC_CONFIG6_0 (OMAP24XX_GPMC_BASE+0x74) -#define GPMC_CONFIG7_0 (OMAP24XX_GPMC_BASE+0x78) -#define GPMC_CONFIG1_1 (OMAP24XX_GPMC_BASE+0x90) -#define GPMC_CONFIG2_1 (OMAP24XX_GPMC_BASE+0x94) -#define GPMC_CONFIG3_1 (OMAP24XX_GPMC_BASE+0x98) -#define GPMC_CONFIG4_1 (OMAP24XX_GPMC_BASE+0x9C) -#define GPMC_CONFIG5_1 (OMAP24XX_GPMC_BASE+0xA0) -#define GPMC_CONFIG6_1 (OMAP24XX_GPMC_BASE+0xA4) -#define GPMC_CONFIG7_1 (OMAP24XX_GPMC_BASE+0xA8) -#define GPMC_CONFIG1_5 (OMAP24XX_GPMC_BASE+0x150) -#define GPMC_CONFIG2_5 (OMAP24XX_GPMC_BASE+0x154) -#define GPMC_CONFIG3_5 (OMAP24XX_GPMC_BASE+0x158) -#define GPMC_CONFIG4_5 (OMAP24XX_GPMC_BASE+0x15C) -#define GPMC_CONFIG5_5 (OMAP24XX_GPMC_BASE+0x160) -#define GPMC_CONFIG6_5 (OMAP24XX_GPMC_BASE+0x164) -#define GPMC_CONFIG7_5 (OMAP24XX_GPMC_BASE+0x168) - - -/* SMS */ -#define OMAP24XX_SMS_BASE 0x6C000000 -#define SMS_SYSCONFIG (OMAP24XX_SMS_BASE+0x10) - -/* SDRC */ -#define OMAP24XX_SDRC_BASE 0x6D000000 -#define OMAP24XX_SDRC_CS0 0x80000000 -#define OMAP24XX_SDRC_CS1 0xA0000000 -#define SDRC_SYSCONFIG (OMAP24XX_SDRC_BASE+0x10) -#define SDRC_STATUS (OMAP24XX_SDRC_BASE+0x14) -#define SDRC_SHARING (OMAP24XX_SDRC_BASE+0x44) -#define SDRC_DLLA_CTRL (OMAP24XX_SDRC_BASE+0x60) -#define SDRC_DLLA_STATUS (OMAP24XX_SDRC_BASE+0x64) -#define SDRC_DLLB_CTRL (OMAP24XX_SDRC_BASE+0x68) -#define SDRC_POWER (OMAP24XX_SDRC_BASE+0x70) -#define SDRC_MCFG_0 (OMAP24XX_SDRC_BASE+0x80) -#define SDRC_MR_0 (OMAP24XX_SDRC_BASE+0x84) -#define SDRC_ACTIM_CTRLA_0 (OMAP24XX_SDRC_BASE+0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP24XX_SDRC_BASE+0xA0) -#define SDRC_MCFG_1 (OMAP24XX_SDRC_BASE+0xB0) -#define SDRC_ACTIM_CTRLA_1 (OMAP24XX_SDRC_BASE+0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP24XX_SDRC_BASE+0xC8) -#define SDRC_RFR_CTRL (OMAP24XX_SDRC_BASE+0xA4) -#define SDRC_MANUAL_0 (OMAP24XX_SDRC_BASE+0xA8) -#define SDRC_RFR_CTRL1 (OMAP24XX_SDRC_BASE+0xD4) - -#define LOADDLL BIT2 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET BIT1 -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - - -/* UART */ -#define OMAP2430_UART1 0x4806A000 -#define OMAP2430_UART2 0x4806C000 -#define OMAP2430_UART3 0x4806E000 - -/* General Purpose Timers */ -#define OMAP24XX_GPT1 (OMAP243X_WAKEUP_L4_IO_BASE+0x18000) -#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000) -#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000) -#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000) -#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000) -#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000) -#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000) -#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000) -#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000) -#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000) -#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000) -#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000 - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x14000) -#define WD2_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x16000) -#define WD3_BASE (OMAP24XX_L4_IO_BASE+0x24000) /* not present */ -#define WD4_BASE (OMAP24XX_L4_IO_BASE+0x26000) - -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x20000) -#define S32K_CR (SYNC_32KTIMER_BASE+0x10) - -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define OMAP24XX_CM_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x06000) - -#define PRCM_CLKSRC_CTRL (OMAP24XX_CM_BASE+0x060) -#define PRCM_CLKOUT_CTRL (OMAP24XX_CM_BASE+0x070) -#define PRCM_CLKEMUL_CTRL (OMAP24XX_CM_BASE+0x078) -#define PRCM_CLKCFG_CTRL (OMAP24XX_CM_BASE+0x080) -#define PRCM_CLKCFG_STATUS (OMAP24XX_CM_BASE+0x084) -#define CM_CLKSEL_MPU (OMAP24XX_CM_BASE+0x140) -#define CM_FCLKEN1_CORE (OMAP24XX_CM_BASE+0x200) -#define CM_FCLKEN2_CORE (OMAP24XX_CM_BASE+0x204) -#define CM_ICLKEN1_CORE (OMAP24XX_CM_BASE+0x210) -#define CM_ICLKEN2_CORE (OMAP24XX_CM_BASE+0x214) -#define CM_CLKSEL1_CORE (OMAP24XX_CM_BASE+0x240) -#define CM_CLKSEL_WKUP (OMAP24XX_CM_BASE+0x440) -#define CM_CLKSEL2_CORE (OMAP24XX_CM_BASE+0x244) -#define CM_FCLKEN_GFX (OMAP24XX_CM_BASE+0x300) -#define CM_ICLKEN_GFX (OMAP24XX_CM_BASE+0x310) -#define CM_CLKSEL_GFX (OMAP24XX_CM_BASE+0x340) -#define RM_RSTCTRL_GFX (OMAP24XX_CM_BASE+0x350) -#define CM_FCLKEN_WKUP (OMAP24XX_CM_BASE+0x400) -#define CM_ICLKEN_WKUP (OMAP24XX_CM_BASE+0x410) -#define PM_RSTCTRL_WKUP (OMAP24XX_CM_BASE+0x450) -#define CM_CLKEN_PLL (OMAP24XX_CM_BASE+0x500) -#define CM_IDLEST_CKGEN (OMAP24XX_CM_BASE+0x520) -#define CM_CLKSEL1_PLL (OMAP24XX_CM_BASE+0x540) -#define CM_CLKSEL2_PLL (OMAP24XX_CM_BASE+0x544) -#define CM_CLKSEL_DSP (OMAP24XX_CM_BASE+0x840) -#define CM_CLKSEL_MDM (OMAP24XX_CM_BASE+0xC40) - -/* SMX-APE */ -#define SMX_APE_BASE 0x68000000 -#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) -#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) -#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) -#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) - -/* IVA2 */ -#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) - -/* - * The 2430's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - */ -#if defined(CONFIG_OMAP243X) - -/* GPMC */ -/* This is being used by the macros in mem.h. PHYS_FLASH_1 is defined to H4_CS0_BASE */ -# define H4_CS1_BASE 0x09000000 /* flash (64 Meg aligned) */ -#define CFG_FLASH_BASE H4_CS1_BASE -#define DEBUG_BASE 0x08000000 - -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) - -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define PERIFERAL_PORT_BASE 0x480FE003 - -#endif /* endif CONFIG_2430SDP */ - -#endif - diff --git a/x-loader/include/asm/arch-arm1136/sizes.h b/x-loader/include/asm/arch-arm1136/sizes.h deleted file mode 100644 index 3dddd8e..0000000 --- a/x-loader/include/asm/arch-arm1136/sizes.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_31M 0x01F00000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ - diff --git a/x-loader/include/asm/arch-arm1136/sys_info.h b/x-loader/include/asm/arch-arm1136/sys_info.h deleted file mode 100644 index 94a09cd..0000000 --- a/x-loader/include/asm/arch-arm1136/sys_info.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright 2005 (C) Texas Instruments, - * (C) Copyright 2004 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP24XX_SYS_INFO_H_ -#define _OMAP24XX_SYS_INFO_H_ - -#if 0 -typedef struct h4_system_data { - /* base board info */ - u32 base_b_rev; /* rev from base board i2c */ - /* cpu board info */ - u32 cpu_b_rev; /* rev from cpu board i2c */ - u32 cpu_b_mux; /* mux type on daughter board */ - u32 cpu_b_ddr_type; /* mem type */ - u32 cpu_b_ddr_speed; /* ddr speed rating */ - u32 cpu_b_switches; /* boot ctrl switch settings */ - /* cpu info */ - u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ - u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ -} h4_sys_data; - -#endif - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module*/ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_2420 0x2420 -#define CPU_2422 0x2422 /* 2420 + 64M stacked */ -#define CPU_2423 0x2423 /* 2420 + 96M stacked */ -#define CPU_2430 0x2430 - -/* 242x real hardware: - * ES1 = rev 0 - * ES2 = rev 1 - * ES2.05 = rev 2 - * ES2.1 = rev 3 - * ES2.1.1 = rev 4 - */ - -/* 242x code defines: - * ES1 = 0+1 = 1 - * ES2 = 1+1 = 2 - * ES2.05 = 2+1 = 3 - * ES2.1 = 3+1 = 4 - * Es2.1.1 = 4+1 = 5 - */ -#define CPU_2422_ES1 1 -#define CPU_2422_ES2 2 -#define CPU_2422_ES2_05 3 -#define CPU_2422_ES2_1 4 -#define CPU_2422_ES2_1_1 5 - -#define CPU_2420_ES1 1 -#define CPU_2420_ES2 2 -#define CPU_2420_ES2_05 3 -#define CPU_2420_ES2_1 4 -#define CPU_2420_ES2_1_1 5 - -#define CPU_242X_ES1 1 -#define CPU_242X_ES2 2 -#define CPU_242X_ES2_05 3 -#define CPU_242X_ES2_1 4 -#define CPU_242X_ES2_1_1 5 - -#define CPU_2420_2422_ES1 1 -#define CPU_2420_2422_ES2_1 4 - -/* 243x real hardware: - * ES1 = rev 0 - * ES2 = rev 1 - * - * 243x code defines: - * ES1 = 0+1 = 1 - * ES2 = 1+1 = 2 - */ -#define CPU_2430_ES1 1 -#define CPU_2430_ES2 2 - -#ifdef VPOM2430 -# define CPU_2430_VIRTIO 3 -#else -# define CPU_2430_VIRTIO 1 -#endif -#define CPU_2430_ZEBU 0xD - -#define CPU_2420_CHIPID 0x0B5D9000 -#define CPU_2430_CHIPID 0x0B68A000 -#define CPU_24XX_ID_MASK 0x0FFFF000 -#define CPU_242X_REV_MASK 0xF0000000 -#define CPU_242X_PID_MASK 0x000F0000 - -#define BOARD_H4_MENELAUS 1 -#define BOARD_H4_SDP 2 -#define BOARD_H4_MENELAUS_HRP 3 -#define BOARD_SDP_2430 4 - -#define GPMC_MUXED 1 -#define GPMC_NONMUXED 0 - -#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ -#define TYPE_NOR 0x000 -#define TYPE_ONENAND 0x800 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ - -#endif diff --git a/x-loader/include/asm/arch-arm926ejs/sizes.h b/x-loader/include/asm/arch-arm926ejs/sizes.h deleted file mode 100644 index ef0b99b..0000000 --- a/x-loader/include/asm/arch-arm926ejs/sizes.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307 - * USA - */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ diff --git a/x-loader/include/asm/arch-omap3/bits.h b/x-loader/include/asm/arch-omap3/bits.h deleted file mode 100644 index 8522335..0000000 --- a/x-loader/include/asm/arch-omap3/bits.h +++ /dev/null @@ -1,48 +0,0 @@ -/* bits.h - * Copyright (c) 2004 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ -#ifndef __bits_h -#define __bits_h 1 - -#define BIT0 (1<<0) -#define BIT1 (1<<1) -#define BIT2 (1<<2) -#define BIT3 (1<<3) -#define BIT4 (1<<4) -#define BIT5 (1<<5) -#define BIT6 (1<<6) -#define BIT7 (1<<7) -#define BIT8 (1<<8) -#define BIT9 (1<<9) -#define BIT10 (1<<10) -#define BIT11 (1<<11) -#define BIT12 (1<<12) -#define BIT13 (1<<13) -#define BIT14 (1<<14) -#define BIT15 (1<<15) -#define BIT16 (1<<16) -#define BIT17 (1<<17) -#define BIT18 (1<<18) -#define BIT19 (1<<19) -#define BIT20 (1<<20) -#define BIT21 (1<<21) -#define BIT22 (1<<22) -#define BIT23 (1<<23) -#define BIT24 (1<<24) -#define BIT25 (1<<25) -#define BIT26 (1<<26) -#define BIT27 (1<<27) -#define BIT28 (1<<28) -#define BIT29 (1<<29) -#define BIT30 (1<<30) -#define BIT31 (1<<31) - -#endif diff --git a/x-loader/include/asm/arch-omap3/clocks.h b/x-loader/include/asm/arch-omap3/clocks.h deleted file mode 100644 index 4f93a96..0000000 --- a/x-loader/include/asm/arch-omap3/clocks.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP34XX_CLOCKS_H_ -#define _OMAP34XX_CLOCKS_H_ - -#define LDELAY 12000000 - -#define S12M 12000000 -#define S13M 13000000 -#define S19_2M 19200000 -#define S24M 24000000 -#define S26M 26000000 -#define S38_4M 38400000 - -#define FCK_IVA2_ON 0x00000001 -#define FCK_CORE1_ON 0x03fffe29 -#define ICK_CORE1_ON 0x3ffffffb -#define ICK_CORE2_ON 0x0000001f -#define FCK_WKUP_ON 0x000000e9 -#define ICK_WKUP_ON 0x0000003f -#define FCK_DSS_ON 0x00000005 -#define ICK_DSS_ON 0x00000001 -#define FCK_CAM_ON 0x00000001 -#define ICK_CAM_ON 0x00000001 -#define FCK_PER_ON 0x0003ffff -#define ICK_PER_ON 0x0003ffff - -#include - -#endif diff --git a/x-loader/include/asm/arch-omap3/clocks343x.h b/x-loader/include/asm/arch-omap3/clocks343x.h deleted file mode 100644 index 7aedaa1..0000000 --- a/x-loader/include/asm/arch-omap3/clocks343x.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP343X_CLOCKS_H_ -#define _OMAP343X_CLOCKS_H_ - -#define PLL_STOP 1 /* PER & IVA */ -#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ -#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ -#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ - -/* The following configurations are OPP and SysClk value independant - * and hence are defined here. All the other DPLL related values are - * tabulated in lowlevel_init.S. - */ - -/* CORE DPLL */ -# define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ -# define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ -# define CORE_FUSB_DIV 2 /* 41.5MHz: */ -# define CORE_L4_DIV 2 /* 83MHz : L4 */ -# define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ -# define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ -# define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ - -/* PER DPLL */ -# define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ -# define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ -# define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */ -# define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ - -# define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) - -#ifdef PRCM_CLK_CFG2_332MHZ -# define M_12 0xA6 -# define N_12 0x05 -# define FSEL_12 0x07 -# define M2_12 0x01 /* M3 of 2 */ - -# define M_12_ES1 0x19F -# define N_12_ES1 0x0E -# define FSL_12_ES1 0x03 -# define M2_12_ES1 0x1 /* M3 of 2 */ - -# define M_13 0x14C -# define N_13 0x0C -# define FSEL_13 0x03 -# define M2_13 0x01 /* M3 of 2 */ - -# define M_13_ES1 0x1B2 -# define N_13_ES1 0x10 -# define FSL_13_ES1 0x03 -# define M2_13_ES1 0x01 /* M3 of 2 */ - -# define M_19p2 0x19F -# define N_19p2 0x17 -# define FSEL_19p2 0x03 -# define M2_19p2 0x01 /* M3 of 2 */ - -# define M_19p2_ES1 0x19F -# define N_19p2_ES1 0x17 -# define FSL_19p2_ES1 0x03 -# define M2_19p2_ES1 0x01 /* M3 of 2 */ - -# define M_26 0xA6 -# define N_26 0x0C -# define FSEL_26 0x07 -# define M2_26 0x01 /* M3 of 2 */ - -# define M_26_ES1 0x1B2 -# define N_26_ES1 0x21 -# define FSL_26_ES1 0x03 -# define M2_26_ES1 0x01 /* M3 of 2 */ - -# define M_38p4 0x19F -# define N_38p4 0x2F -# define FSEL_38p4 0x03 -# define M2_38p4 0x01 /* M3 of 2 */ - -# define M_38p4_ES1 0x19F -# define N_38p4_ES1 0x2F -# define FSL_38p4_ES1 0x03 -# define M2_38p4_ES1 0x01 /* M3 of 2 */ - -#elif defined(PRCM_CLK_CFG2_266MHZ) -# define M_12 0x85 -# define N_12 0x05 -# define FSEL_12 0x07 -# define M2_12 0x02 /* M3 of 2 */ - -# define M_12_ES1 0x85 /* 0x10A */ -# define N_12_ES1 0x05 /* 0x05 */ -# define FSL_12_ES1 0x07 /* 0x7 */ -# define M2_12_ES1 0x2 /* 0x2 with an M3 of 4*/ - -# define M_13 0x10A -# define N_13 0x0C -# define FSEL_13 0x3 -# define M2_13 0x1 /* M3 of 2 */ - -# define M_13_ES1 0x10A /* 0x214 */ -# define N_13_ES1 0x0C /* 0xC */ -# define FSL_13_ES1 0x3 /* 0x3 */ -# define M2_13_ES1 0x1 /* 0x2 with an M3 of 4*/ - -# define M_19p2 0x115 -# define N_19p2 0x13 -# define FSEL_19p2 0x03 -# define M2_19p2 0x01 /* M3 of 2 */ - -# define M_19p2_ES1 0x115 /* 0x299 */ -# define N_19p2_ES1 0x13 /* 0x17 */ -# define FSL_19p2_ES1 0x03 /* 0x03 */ -# define M2_19p2_ES1 0x01 /* 0x2 with M3 of 4 */ - -# define M_26 0x85 -# define N_26 0x0C -# define FSEL_26 0x07 -# define M2_26 0x01 /* M3 of 2 */ - -# define M_26_ES1 0x85 /* 0x10A */ -# define N_26_ES1 0x0C /* 0xC */ -# define FSL_26_ES1 0x07 /* 0x7 */ -# define M2_26_ES1 0x01 /* 0x2 with an M3 of 4 */ - -# define M_38p4 0x11C -# define N_38p4 0x28 -# define FSEL_38p4 0x03 -# define M2_38p4 0x01 /* M3 of 2 */ - -# define M_38p4_ES1 0x11C /* 0x299 */ -# define N_38p4_ES1 0x28 /* 0x2f */ -# define FSL_38p4_ES1 0x03 /* 0x3 */ -# define M2_38p4_ES1 0x01 /* 0x2 with an M3 of 4*/ - - # endif - -#endif /* endif _OMAP343X_CLOCKS_H_ */ diff --git a/x-loader/include/asm/arch-omap3/cpu.h b/x-loader/include/asm/arch-omap3/cpu.h deleted file mode 100644 index 0828e73..0000000 --- a/x-loader/include/asm/arch-omap3/cpu.h +++ /dev/null @@ -1,257 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _OMAP34XX_CPU_H -#define _OMAP34XX_CPU_H -#include - -/* Register offsets of common modules */ -/* Control */ -#define CONTROL_STATUS (OMAP34XX_CTRL_BASE + 0x2F0) -#define OMAP34XX_MCR (OMAP34XX_CTRL_BASE + 0x8C) -#define CONTROL_SCALABLE_OMAP_STATUS (OMAP34XX_CTRL_BASE + 0x44C) -#define CONTROL_SCALABLE_OMAP_OCP (OMAP34XX_CTRL_BASE + 0x534) - - -/* Tap Information */ -#define TAP_IDCODE_REG (OMAP34XX_TAP_BASE+0x204) -#define PRODUCTION_ID (OMAP34XX_TAP_BASE+0x208) - -/* device type */ -#define DEVICE_MASK (BIT8|BIT9|BIT10) -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/* We are not concerned with BIT5 as it only determines - * the prirotiy between memory or perpheral booting - */ -#define SYSBOOT_MASK (BIT0|BIT1|BIT2|BIT3|BIT4) - -/* GPMC CS3/cs4/cs6 not avaliable */ -#define GPMC_BASE (OMAP34XX_GPMC_BASE) -#define GPMC_SYSCONFIG (OMAP34XX_GPMC_BASE+0x10) -#define GPMC_IRQSTATUS (OMAP34XX_GPMC_BASE+0x18) -#define GPMC_IRQENABLE (OMAP34XX_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP34XX_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) -#define GPMC_STATUS (OMAP34XX_GPMC_BASE+0x54) - -#define GPMC_CONFIG_CS0 (OMAP34XX_GPMC_BASE+0x60) -#define GPMC_CONFIG_WIDTH (0x30) - -#define GPMC_CONFIG1 (0x00) -#define GPMC_CONFIG2 (0x04) -#define GPMC_CONFIG3 (0x08) -#define GPMC_CONFIG4 (0x0C) -#define GPMC_CONFIG5 (0x10) -#define GPMC_CONFIG6 (0x14) -#define GPMC_CONFIG7 (0x18) -#define GPMC_NAND_CMD (0x1C) -#define GPMC_NAND_ADR (0x20) -#define GPMC_NAND_DAT (0x24) - -#define GPMC_ECC_CONFIG (0x1F4) -#define GPMC_ECC_CONTROL (0x1F8) -#define GPMC_ECC_SIZE_CONFIG (0x1FC) -#define GPMC_ECC1_RESULT (0x200) -#define GPMC_ECC2_RESULT (0x204) -#define GPMC_ECC3_RESULT (0x208) -#define GPMC_ECC4_RESULT (0x20C) -#define GPMC_ECC5_RESULT (0x210) -#define GPMC_ECC6_RESULT (0x214) -#define GPMC_ECC7_RESULT (0x218) -#define GPMC_ECC8_RESULT (0x21C) -#define GPMC_ECC9_RESULT (0x220) - - -/* GPMC Mapping */ -# define FLASH_BASE 0x10000000 /* NOR flash (aligned to 256 Meg) */ -# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (aligned to 64 Meg) */ -# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (aligned to 256 Meg) */ -# define DEBUG_BASE 0x08000000 /* debug board */ -# define NAND_BASE 0x30000000 /* NAND addr (actual size small port)*/ -# define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ -# define ONENAND_MAP 0x20000000 /* OneNand addr (actual size small port */ - -/* SMS */ -#define SMS_SYSCONFIG (OMAP34XX_SMS_BASE+0x10) -#define SMS_RG_ATT0 (OMAP34XX_SMS_BASE+0x48) -#define SMS_CLASS_ARB0 (OMAP34XX_SMS_BASE+0xD0) -#define BURSTCOMPLETE_GROUP7 BIT31 - -/* SDRC */ -#define SDRC_SYSCONFIG (OMAP34XX_SDRC_BASE+0x10) -#define SDRC_STATUS (OMAP34XX_SDRC_BASE+0x14) -#define SDRC_CS_CFG (OMAP34XX_SDRC_BASE+0x40) -#define SDRC_SHARING (OMAP34XX_SDRC_BASE+0x44) -#define SDRC_DLLA_CTRL (OMAP34XX_SDRC_BASE+0x60) -#define SDRC_DLLA_STATUS (OMAP34XX_SDRC_BASE+0x64) -#define SDRC_DLLB_CTRL (OMAP34XX_SDRC_BASE+0x68) -#define SDRC_DLLB_STATUS (OMAP34XX_SDRC_BASE+0x6C) -#define DLLPHASE BIT1 -#define LOADDLL BIT2 -#define DLL_DELAY_MASK 0xFF00 -#define DLL_NO_FILTER_MASK (BIT8|BIT9) - -#define SDRC_POWER (OMAP34XX_SDRC_BASE+0x70) -#define WAKEUPPROC BIT26 - -#define SDRC_MCFG_0 (OMAP34XX_SDRC_BASE+0x80) -#define SDRC_MCFG_1 (OMAP34XX_SDRC_BASE+0xB0) -#define SDRC_MR_0 (OMAP34XX_SDRC_BASE+0x84) -#define SDRC_MR_1 (OMAP34XX_SDRC_BASE+0xB4) -#define SDRC_ACTIM_CTRLA_0 (OMAP34XX_SDRC_BASE+0x9C) -#define SDRC_ACTIM_CTRLB_0 (OMAP34XX_SDRC_BASE+0xA0) -#define SDRC_ACTIM_CTRLA_1 (OMAP34XX_SDRC_BASE+0xC4) -#define SDRC_ACTIM_CTRLB_1 (OMAP34XX_SDRC_BASE+0xC8) -#define SDRC_RFR_CTRL_0 (OMAP34XX_SDRC_BASE+0xA4) -#define SDRC_RFR_CTRL_1 (OMAP34XX_SDRC_BASE+0xD4) -#define SDRC_MANUAL_0 (OMAP34XX_SDRC_BASE+0xA8) -#define SDRC_MANUAL_1 (OMAP34XX_SDRC_BASE+0xD8) -#define OMAP34XX_SDRC_CS0 0x80000000 -#define OMAP34XX_SDRC_CS1 0xA0000000 -#define CMD_NOP 0x0 -#define CMD_PRECHARGE 0x1 -#define CMD_AUTOREFRESH 0x2 -#define CMD_ENTR_PWRDOWN 0x3 -#define CMD_EXIT_PWRDOWN 0x4 -#define CMD_ENTR_SRFRSH 0x5 -#define CMD_CKE_HIGH 0x6 -#define CMD_CKE_LOW 0x7 -#define SOFTRESET BIT1 -#define SMART_IDLE (0x2 << 3) -#define REF_ON_IDLE (0x1 << 6) - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ -#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ - -/* Watchdog */ -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* PRCM */ -#define CM_FCLKEN_IVA2 0x48004000 -#define CM_CLKEN_PLL_IVA2 0x48004004 -#define CM_IDLEST_PLL_IVA2 0x48004024 -#define CM_CLKSEL1_PLL_IVA2 0x48004040 -#define CM_CLKSEL2_PLL_IVA2 0x48004044 -#define CM_CLKEN_PLL_MPU 0x48004904 -#define CM_IDLEST_PLL_MPU 0x48004924 -#define CM_CLKSEL1_PLL_MPU 0x48004940 -#define CM_CLKSEL2_PLL_MPU 0x48004944 -#define CM_FCLKEN1_CORE 0x48004a00 -#define CM_ICLKEN1_CORE 0x48004a10 -#define CM_ICLKEN2_CORE 0x48004a14 -#define CM_CLKSEL_CORE 0x48004a40 -#define CM_FCLKEN_GFX 0x48004b00 -#define CM_ICLKEN_GFX 0x48004b10 -#define CM_CLKSEL_GFX 0x48004b40 -#define CM_FCLKEN_WKUP 0x48004c00 -#define CM_ICLKEN_WKUP 0x48004c10 -#define CM_CLKSEL_WKUP 0x48004c40 -#define CM_IDLEST_WKUP 0x48004c20 -#define CM_CLKEN_PLL 0x48004d00 -#define CM_IDLEST_CKGEN 0x48004d20 -#define CM_CLKSEL1_PLL 0x48004d40 -#define CM_CLKSEL2_PLL 0x48004d44 -#define CM_CLKSEL3_PLL 0x48004d48 -#define CM_FCLKEN_DSS 0x48004e00 -#define CM_ICLKEN_DSS 0x48004e10 -#define CM_CLKSEL_DSS 0x48004e40 -#define CM_FCLKEN_CAM 0x48004f00 -#define CM_ICLKEN_CAM 0x48004f10 -#define CM_CLKSEL_CAM 0x48004F40 -#define CM_FCLKEN_PER 0x48005000 -#define CM_ICLKEN_PER 0x48005010 -#define CM_CLKSEL_PER 0x48005040 -#define CM_CLKSEL1_EMU 0x48005140 - -#define PRM_CLKSEL 0x48306d40 -#define PRM_RSTCTRL 0x48307250 -#define PRM_CLKSRC_CTRL 0x48307270 - -#define SYSCLKDIV_2 (0x1 << 7) - -/* SMX-APE */ -#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) -#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) -#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) -#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) -#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) - -#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) -#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) -#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) -#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) - -#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) -#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) -#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) - -#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) -#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) -#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) -#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) - -#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) -#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) -#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) - -#define IVA2_REQ_INFO_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x68) -#define IVA2_READ_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x70) -#define IVA2_WRITE_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x78) - -#define IVA2_REQ_INFO_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x88) -#define IVA2_READ_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x90) -#define IVA2_WRITE_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x98) - -#define IVA2_REQ_INFO_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xA8) -#define IVA2_READ_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB0) -#define IVA2_WRITE_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB8) - -/* I2C base */ -#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) -#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) -#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) - -#endif diff --git a/x-loader/include/asm/arch-omap3/gpio.h b/x-loader/include/asm/arch-omap3/gpio.h deleted file mode 100644 index 30f633c..0000000 --- a/x-loader/include/asm/arch-omap3/gpio.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * This work is derived from the linux 2.6.27 kernel source - * To fetch, use the kernel repository - * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - * Use the v2.6.27 tag. - * - * Below is the original's header including its copyright - * - * linux/arch/arm/plat-omap/gpio.c - * - * Support functions for OMAP GPIO - * - * Copyright (C) 2003-2005 Nokia Corporation - * Written by Juha Yrjölä - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef _GPIO_H -#define _GPIO_H - -#define OMAP24XX_GPIO_REVISION 0x0000 -#define OMAP24XX_GPIO_SYSCONFIG 0x0010 -#define OMAP24XX_GPIO_SYSSTATUS 0x0014 -#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 -#define OMAP24XX_GPIO_IRQSTATUS2 0x0028 -#define OMAP24XX_GPIO_IRQENABLE2 0x002c -#define OMAP24XX_GPIO_IRQENABLE1 0x001c -#define OMAP24XX_GPIO_WAKE_EN 0x0020 -#define OMAP24XX_GPIO_CTRL 0x0030 -#define OMAP24XX_GPIO_OE 0x0034 -#define OMAP24XX_GPIO_DATAIN 0x0038 -#define OMAP24XX_GPIO_DATAOUT 0x003c -#define OMAP24XX_GPIO_LEVELDETECT0 0x0040 -#define OMAP24XX_GPIO_LEVELDETECT1 0x0044 -#define OMAP24XX_GPIO_RISINGDETECT 0x0048 -#define OMAP24XX_GPIO_FALLINGDETECT 0x004c -#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 -#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 -#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 -#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 -#define OMAP24XX_GPIO_CLEARWKUENA 0x0080 -#define OMAP24XX_GPIO_SETWKUENA 0x0084 -#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 -#define OMAP24XX_GPIO_SETDATAOUT 0x0094 - -struct gpio_bank { - void *base; - int method; -}; - -#define METHOD_GPIO_24XX 4 - -/* This is the interface */ - -/* Request a gpio before using it */ -int omap_request_gpio(int gpio); -/* Reset and free a gpio after using it */ -void omap_free_gpio(int gpio); -/* Sets the gpio as input or output */ -void omap_set_gpio_direction(int gpio, int is_input); -/* Set or clear a gpio output */ -void omap_set_gpio_dataout(int gpio, int enable); -/* Get the value of a gpio input */ -int omap_get_gpio_datain(int gpio); - -#endif /* _GPIO_H_ */ diff --git a/x-loader/include/asm/arch-omap3/i2c.h b/x-loader/include/asm/arch-omap3/i2c.h deleted file mode 100644 index 28ae5ca..0000000 --- a/x-loader/include/asm/arch-omap3/i2c.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * (C) Copyright 2004-2008 - * Texas Instruments, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _I2C_H_ -#define _I2C_H_ - -#define I2C_DEFAULT_BASE I2C_BASE1 - -#define I2C_REV (I2C_DEFAULT_BASE + 0x00) -#define I2C_IE (I2C_DEFAULT_BASE + 0x04) -#define I2C_STAT (I2C_DEFAULT_BASE + 0x08) -#define I2C_IV (I2C_DEFAULT_BASE + 0x0c) -#define I2C_BUF (I2C_DEFAULT_BASE + 0x14) -#define I2C_CNT (I2C_DEFAULT_BASE + 0x18) -#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c) -#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20) -#define I2C_CON (I2C_DEFAULT_BASE + 0x24) -#define I2C_OA (I2C_DEFAULT_BASE + 0x28) -#define I2C_SA (I2C_DEFAULT_BASE + 0x2c) -#define I2C_PSC (I2C_DEFAULT_BASE + 0x30) -#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34) -#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38) -#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c) - -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ -#define I2C_IE_GC_IE (1 << 5) -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_GC (1 << 5) -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ - -/* I2C Buffer Configuration Register (I2C_BUF): */ - -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ - /* (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C System Test Register (I2C_SYSTEST): */ - -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ - -#define I2C_SCLL_SCLL (0) -#define I2C_SCLL_SCLL_M (0xFF) -#define I2C_SCLL_HSSCLL (8) -#define I2C_SCLH_HSSCLL_M (0xFF) -#define I2C_SCLH_SCLH (0) -#define I2C_SCLH_SCLH_M (0xFF) -#define I2C_SCLH_HSSCLH (8) -#define I2C_SCLH_HSSCLH_M (0xFF) - -#define OMAP_I2C_STANDARD 100 -#define OMAP_I2C_FAST_MODE 400 -#define OMAP_I2C_HIGH_SPEED 3400 - -#define SYSTEM_CLOCK_12 12000 -#define SYSTEM_CLOCK_13 13000 -#define SYSTEM_CLOCK_192 19200 -#define SYSTEM_CLOCK_96 96000 - -#define I2C_IP_CLK SYSTEM_CLOCK_96 -#define I2C_PSC_MAX (0x0f) -#define I2C_PSC_MIN (0x00) - -#endif /* _I2C_H_ */ diff --git a/x-loader/include/asm/arch-omap3/mem.h b/x-loader/include/asm/arch-omap3/mem.h deleted file mode 100644 index 284c665..0000000 --- a/x-loader/include/asm/arch-omap3/mem.h +++ /dev/null @@ -1,589 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP34XX_MEM_H_ -#define _OMAP34XX_MEM_H_ - -#define SDRC_CS0_OSET 0x0 -#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ - -#ifndef __ASSEMBLY__ - -typedef enum { - STACKED = 0, - IP_DDR = 1, - COMBO_DDR = 2, - IP_SDR = 3, -} mem_t; - - -/* Memory that can be connected to GPMC */ -#define GPMC_NOR 0 -#define GPMC_NAND 1 -#define GPMC_MDOC 2 -#define GPMC_ONENAND 3 -#define MMC_NAND 4 -#define MMC_ONENAND 5 -#define GPMC_NONE 6 -#define GPMC_ONENAND_TRY 7 - -#endif - -/* set the 343x-SDRC incoming address convention */ -#if defined(SDRC_B_R_C) -#define B_ALL (0 << 6) /* bank-row-column */ -#elif defined(SDRC_B1_R_B0_C) -#define B_ALL (1 << 6) /* bank1-row-bank0-column */ -#elif defined(SDRC_R_B_C) -#define B_ALL (2 << 6) /* row-bank-column */ -#endif - -/* Future memory combinations based on past */ -#define SDP_SDRC_MDCFG_MONO_DDR 0x0 -#define SDP_COMBO_MDCFG_0_DDR 0x0 -#define SDP_SDRC_MDCFG_0_SDR 0x0 - -/* Slower full frequency range default timings for x32 operation*/ -#define SDP_SDRC_SHARING 0x00000100 -#define SDP_SDRC_MR_0_SDR 0x00000031 - -#ifdef CONFIG_3430ZEBU -#define SDP_SDRC_MDCFG_0_DDR (0x02582019|B_ALL) /* Infin ddr module */ -#else -#define SDP_SDRC_MDCFG_0_DDR (0x02584019|B_ALL) -#define SDP_SDRC_MDCFG_0_DDR_MICRON_XM (0x03588019|B_ALL) -#define SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM (0x04590019|B_ALL) -#define SDP_SDRC_MDCFG_0_DDR_HYNIX (0x03588019|B_ALL) -#endif - -#define SDP_SDRC_MR_0_DDR 0x00000032 - -/* Diabling power down mode using CKE pin */ -#define SDP_SDRC_POWER_POP 0x00000081 - -/* optimized timings good for current shipping parts */ -#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 -#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ -#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ -#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ - -#define DLL_OFFSET 0 -#define DLL_WRITEDDRCLKX2DIS 1 -#define DLL_ENADLL 1 -#define DLL_LOCKDLL 0 -#define DLL_DLLPHASE_72 0 -#define DLL_DLLPHASE_90 1 - -// rkw - need to find of 90/72 degree recommendation for speed like before. -#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ - (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) - -/* Infineon part of 3430SDP (133MHz optimized) ~ 7.5ns - * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 - * TDPL = 15/7.5 = 2 - * TRRD = 15/2.5 = 2 - * TRCD = 22.5/7.5 = 3 - * TRP = 22.5/7.5 = 3 - * TRAS = 45/7.5 = 6 - * TRC = 65/7.5 = 8.6->9 - * TRFC = 75/7.5 = 10 - * ACTIMB - * TCKE = 2 - * XSR = 120/7.5 = 16 - */ -#define INFINEON_TDAL_133 5 -#define INFINEON_TDPL_133 2 -#define INFINEON_TRRD_133 2 -#define INFINEON_TRCD_133 3 -#define INFINEON_TRP_133 3 -#define INFINEON_TRAS_133 6 -#define INFINEON_TRC_133 9 -#define INFINEON_TRFC_133 10 -#define INFINEON_V_ACTIMA_133 ((INFINEON_TRFC_133 << 27) | (INFINEON_TRC_133 << 22) | (INFINEON_TRAS_133 << 18) \ - |(INFINEON_TRP_133 << 15) | (INFINEON_TRCD_133 << 12) |(INFINEON_TRRD_133 << 9) |(INFINEON_TDPL_133 << 6) \ - | (INFINEON_TDAL_133)) - -#define INFINEON_TWTR_133 1 -#define INFINEON_TCKE_133 2 -#define INFINEON_TXP_133 2 -#define INFINEON_XSR_133 16 -#define INFINEON_V_ACTIMB_133 ((INFINEON_TCKE_133 << 12) | (INFINEON_XSR_133 << 0)) | \ - (INFINEON_TXP_133 << 8) | (INFINEON_TWTR_133 << 16) - -#define INFINEON_V_ACTIMA_100 INFINEON_V_ACTIMA_133 -#define INFINEON_V_ACTIMB_100 INFINEON_V_ACTIMB_133 - - -/* Infineon part of 3430SDP (165MHz optimized) 6.06ns - * ACTIMA - * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 18/6 = 3 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 72/6 = 12 - * ACTIMB - * TCKE = 2 - * XSR = 120/6 = 20 - */ -#define INFINEON_TDAL_165 6 -#define INFINEON_TDPL_165 3 -#define INFINEON_TRRD_165 2 -#define INFINEON_TRCD_165 3 -#define INFINEON_TRP_165 3 -#define INFINEON_TRAS_165 7 -#define INFINEON_TRC_165 10 -#define INFINEON_TRFC_165 12 -#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) \ - | (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) |(INFINEON_TRRD_165 << 9) | \ - (INFINEON_TDPL_165 << 6) | (INFINEON_TDAL_165)) - -#define INFINEON_TWTR_165 1 -#define INFINEON_TCKE_165 2 -#define INFINEON_TXP_165 2 -#define INFINEON_XSR_165 20 -#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | (INFINEON_XSR_165 << 0)) | \ - (INFINEON_TXP_165 << 8) | (INFINEON_TWTR_165 << 16) - -/* Micron part of 3430 EVM (133MHz optimized) ~ 7.5ns - * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 - * TDPL = 15/7.5 = 2 - * TRRD = 15/7.5 = 2 - * TRCD = 22.5/7.5 = 3 - * TRP = 22.5/7.5 = 3 - * TRAS = 45/7.5 = 6 - * TRC = 75/7.5 = 10 - * TRFC = 125/7.5 = 16.6->17 - * ACTIMB - * TWTR = 1 - * TCKE = 1 - * TXSR = 138/7.5 = 18.3->19 - * TXP = 25/7.5 = 3.3->4 - */ -#define MICRON_TDAL_133 5 -#define MICRON_TDPL_133 2 -#define MICRON_TRRD_133 2 -#define MICRON_TRCD_133 3 -#define MICRON_TRP_133 3 -#define MICRON_TRAS_133 6 -#define MICRON_TRC_133 10 -#define MICRON_TRFC_133 17 -#define MICRON_V_ACTIMA_133 ((MICRON_TRFC_133 << 27) | (MICRON_TRC_133 << 22) | (MICRON_TRAS_133 << 18) \ - |(MICRON_TRP_133 << 15) | (MICRON_TRCD_133 << 12) |(MICRON_TRRD_133 << 9) |(MICRON_TDPL_133 << 6) \ - | (MICRON_TDAL_133)) - -#define MICRON_TWTR_133 1 -#define MICRON_TCKE_133 1 -#define MICRON_TXSR_133 19 -#define MICRON_TXP_133 4 -#define MICRON_V_ACTIMB_133 ((MICRON_TWTR_133 << 16) | (MICRON_TCKE_133 << 12) | (MICRON_TXP_133 << 8) \ - | (MICRON_TXSR_133 << 0)) - -#define MICRON_V_ACTIMA_100 MICRON_V_ACTIMA_133 -#define MICRON_V_ACTIMB_100 MICRON_V_ACTIMB_133 - -/* Micron part of 3430 EVM (165MHz optimized) 6.06ns - * ACTIMA - * TDAL = Twr/Tck + Trp/tck = 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 18/6 = 3 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 125/6 = 21 - * ACTIMB - * TWTR = 1 - * TCKE = 1 - * TXSR = 138/6 = 23 - * TXP = 25/6 = 4.1 ~5 - */ -#define MICRON_TDAL_165 6 -#define MICRON_TDPL_165 3 -#define MICRON_TRRD_165 2 -#define MICRON_TRCD_165 3 -#define MICRON_TRP_165 3 -#define MICRON_TRAS_165 7 -#define MICRON_TRC_165 10 -#define MICRON_TRFC_165 21 -#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) \ - | (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) |(MICRON_TRRD_165 << 9) | \ - (MICRON_TDPL_165 << 6) | (MICRON_TDAL_165)) - -#define MICRON_TWTR_165 1 -#define MICRON_TCKE_165 1 -#define MICRON_TXP_165 5 -#define MICRON_XSR_165 23 -#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | (MICRON_XSR_165 << 0)) | \ - (MICRON_TXP_165 << 8) | (MICRON_TWTR_165 << 16) - -/* Micron part (200MHz optimized) 5 ns - */ -#define MICRON_TDAL_200 6 -#define MICRON_TDPL_200 3 -#define MICRON_TRRD_200 2 -#define MICRON_TRCD_200 3 -#define MICRON_TRP_200 3 -#define MICRON_TRAS_200 8 -#define MICRON_TRC_200 11 -#define MICRON_TRFC_200 15 -#define MICRON_V_ACTIMA_200 ((MICRON_TRFC_200 << 27) | (MICRON_TRC_200 << 22) | (MICRON_TRAS_200 << 18) \ - | (MICRON_TRP_200 << 15) | (MICRON_TRCD_200 << 12) |(MICRON_TRRD_200 << 9) | \ - (MICRON_TDPL_200 << 6) | (MICRON_TDAL_200)) - -#define MICRON_TWTR_200 2 -#define MICRON_TCKE_200 4 -#define MICRON_TXP_200 2 -#define MICRON_XSR_200 23 -#define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | (MICRON_XSR_200 << 0)) | \ - (MICRON_TXP_200 << 8) | (MICRON_TWTR_200 << 16) - -/* NUMONYX part of IGEP0020 (165MHz optimized) 6.06ns - * ACTIMA - * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 22.5/6 = 3.75 -> 4 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 140/6 = 23.3 -> 24 - * ACTIMB - * TWTR = 2 - * TCKE = 2 - * TXSR = 200/6 = 33.3 -> 34 - * TXP = 1.0 + 1.1 = 2.1 -> 3 ¿? - */ -#define NUMONYX_TDAL_165 6 -#define NUMONYX_TDPL_165 3 -#define NUMONYX_TRRD_165 2 -#define NUMONYX_TRCD_165 4 -#define NUMONYX_TRP_165 3 -#define NUMONYX_TRAS_165 7 -#define NUMONYX_TRC_165 10 -#define NUMONYX_TRFC_165 24 -#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) \ - | (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) |(NUMONYX_TRRD_165 << 9) | \ - (NUMONYX_TDPL_165 << 6) | (NUMONYX_TDAL_165)) - -#define NUMONYX_TWTR_165 2 -#define NUMONYX_TCKE_165 2 -#define NUMONYX_TXP_165 3 -#define NUMONYX_XSR_165 34 -#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | (NUMONYX_XSR_165 << 0)) | \ - (NUMONYX_TXP_165 << 8) | (NUMONYX_TWTR_165 << 16) - -/* - * Hynix part of Overo (165MHz optimized) 6.06ns - * ACTIMA - * ACTIMA - * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 - * TDPL (Twr) = 15/6 = 2.5 -> 3 - * TRRD = 12/6 = 2 - * TRCD = 18/6 = 3 - * TRP = 18/6 = 3 - * TRAS = 42/6 = 7 - * TRC = 60/6 = 10 - * TRFC = 97.5/6 = 17 - * ACTIMB - * TWTR = 1 - * TCKE = 1 - * TXP = 1+1 - * XSR = 140/6 = 24 - */ -#define HYNIX_TDAL_165 6 -#define HYNIX_TDPL_165 3 -#define HYNIX_TRRD_165 2 -#define HYNIX_TRCD_165 3 -#define HYNIX_TRP_165 3 -#define HYNIX_TRAS_165 7 -#define HYNIX_TRC_165 10 -#define HYNIX_TRFC_165 21 -#define HYNIX_V_ACTIMA_165 ((HYNIX_TRFC_165 << 27) | \ - (HYNIX_TRC_165 << 22) | (HYNIX_TRAS_165 << 18) | \ - (HYNIX_TRP_165 << 15) | (HYNIX_TRCD_165 << 12) | \ - (HYNIX_TRRD_165 << 9) | (HYNIX_TDPL_165 << 6) | \ - (HYNIX_TDAL_165)) - -#define HYNIX_TWTR_165 1 -#define HYNIX_TCKE_165 1 -#define HYNIX_TXP_165 2 -#define HYNIX_XSR_165 24 -#define HYNIX_V_ACTIMB_165 ((HYNIX_TCKE_165 << 12) | \ - (HYNIX_XSR_165 << 0) | (HYNIX_TXP_165 << 8) | \ - (HYNIX_TWTR_165 << 16)) - -/* New and compatability speed defines */ -#if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) -# define L3_100MHZ /* Use with <= 100MHz SDRAM */ -#elif defined (PRCM_CLK_CFG2_266MHZ) || defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) -# define L3_133MHZ /* Use with <= 133MHz SDRAM*/ -#elif defined(PRCM_CLK_CFG2_332MHZ) || defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) -# define L3_165MHZ /* Use with <= 165MHz SDRAM (L3=166 on 3430) */ -#endif - -#if defined(L3_100MHZ) -# define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_100 -# define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_100 -#elif defined(L3_133MHZ) -# define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_133 -# define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_133 -#elif defined(L3_165MHZ) -# define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_165 -# define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_165 -# define NUMONYX_SDRC_ACTIM_CTRLA_0 NUMONYX_V_ACTIMA_165 -# define NUMONYX_SDRC_ACTIM_CTRLB_0 NUMONYX_V_ACTIMB_165 -#endif - - -#if defined(L3_100MHZ) -# define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_100 -# define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_100 -#elif defined(L3_133MHZ) -# define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_133 -# define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_133 -#elif defined(L3_165MHZ) -# define INFINEON_SDRC_ACTIM_CTRLA_0 INFINEON_V_ACTIMA_165 -# define INFINEON_SDRC_ACTIM_CTRLB_0 INFINEON_V_ACTIMB_165 -#endif - -#if defined(L3_100MHZ) -# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_100MHz -#elif defined(L3_133MHZ) -# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_133MHz -#elif defined(L3_165MHZ) -# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz -#endif - -/* - * GPMC settings - - * Definitions is as per the following format - * # define _GPMC_CONFIG - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of - * the same. if values are independent of the board, this definition will be - * present in this file if values are dependent on the board, then this should - * go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * STNOR - Intel Strata Flash - * SMNAND - Samsung NAND - * M_NAND - Micron Large page x16 NAND - * MPDB - H4 MPDB board - * SBNOR - Sibley NOR - * ONNAND - Samsung One NAND - * - * include/configs/file.h contains the defn - for all CS we are interested - * #define OMAP34XX_GPMC_CSx PART - * #define OMAP34XX_GPMC_CSx_SIZE Size - * #define OMAP34XX_GPMC_CSx_MAP Map - * Where: - * x - CS number - * PART - Part Name as defined above - * SIZE - how big is the mapping to be - * GPMC_SIZE_128M - 0x8 - * GPMC_SIZE_64M - 0xC - * GPMC_SIZE_32M - 0xE - * GPMC_SIZE_16M - 0xF - * MAP - Map this CS to which address(GPMC address space)- Absolute address - * >>24 before being used. - */ -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#if defined(L3_100MHZ) -# define SMNAND_GPMC_CONFIG1 0x0 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x00000A80 - -# define M_NAND_GPMC_CONFIG1 0x00001800 -# define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2 -# define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3 -# define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4 -# define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5 -# define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6 -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x000f0f01 -# define STNOR_GPMC_CONFIG3 0x00050502 -# define STNOR_GPMC_CONFIG4 0x0C060C06 -# define STNOR_GPMC_CONFIG5 0x01131F1F -# define STNOR_GPMC_CONFIG6 0x0 /* 0? */ -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001F1F00 -# define MPDB_GPMC_CONFIG3 0x00080802 -# define MPDB_GPMC_CONFIG4 0x1C091C09 -# define MPDB_GPMC_CONFIG5 0x031A1F1F -# define MPDB_GPMC_CONFIG6 0x000003C2 -#endif - -#if defined(L3_133MHZ) -# define SMNAND_GPMC_CONFIG1 0x00000800 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x00000A80 -# define SMNAND_GPMC_CONFIG7 0x00000C44 - -# define M_NAND_GPMC_CONFIG1 0x00001800 -# define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2 -# define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3 -# define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4 -# define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5 -# define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6 -# define M_NAND_GPMC_CONFIG7 SMNAND_GPMC_CONFIG7 - -# define STNOR_GPMC_CONFIG1 0x1203 -# define STNOR_GPMC_CONFIG2 0x00151501 -# define STNOR_GPMC_CONFIG3 0x00060602 -# define STNOR_GPMC_CONFIG4 0x10081008 -# define STNOR_GPMC_CONFIG5 0x01131F1F -# define STNOR_GPMC_CONFIG6 0x000004c4 - -# define SIBNOR_GPMC_CONFIG1 0x1200 -# define SIBNOR_GPMC_CONFIG2 0x001f1f00 -# define SIBNOR_GPMC_CONFIG3 0x00080802 -# define SIBNOR_GPMC_CONFIG4 0x1C091C09 -# define SIBNOR_GPMC_CONFIG5 0x01131F1F -# define SIBNOR_GPMC_CONFIG6 0x000003C2 - -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001f1f01 -# define MPDB_GPMC_CONFIG3 0x00080803 -# define MPDB_GPMC_CONFIG4 0x1C091C09 -# define MPDB_GPMC_CONFIG5 0x041f1F1F -# define MPDB_GPMC_CONFIG6 0x000004C4 - -# define P2_GPMC_CONFIG1 0x0 -# define P2_GPMC_CONFIG2 0x0 -# define P2_GPMC_CONFIG3 0x0 -# define P2_GPMC_CONFIG4 0x0 -# define P2_GPMC_CONFIG5 0x0 -# define P2_GPMC_CONFIG6 0x0 - -# define ONENAND_GPMC_CONFIG1 0x00001200 -# define ONENAND_GPMC_CONFIG2 0x000c0c01 -# define ONENAND_GPMC_CONFIG3 0x00030301 -# define ONENAND_GPMC_CONFIG4 0x0c040c04 -# define ONENAND_GPMC_CONFIG5 0x010C1010 -# define ONENAND_GPMC_CONFIG6 0x00000000 - -#endif /* endif L3_133MHZ */ - -#if defined (L3_165MHZ) -# define SMNAND_GPMC_CONFIG1 0x00000800 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x1F0F0A80 -# define SMNAND_GPMC_CONFIG7 0x00000C44 - -# define M_NAND_GPMC_CONFIG1 0x00001800 -# define M_NAND_GPMC_CONFIG2 SMNAND_GPMC_CONFIG2 -# define M_NAND_GPMC_CONFIG3 SMNAND_GPMC_CONFIG3 -# define M_NAND_GPMC_CONFIG4 SMNAND_GPMC_CONFIG4 -# define M_NAND_GPMC_CONFIG5 SMNAND_GPMC_CONFIG5 -# define M_NAND_GPMC_CONFIG6 SMNAND_GPMC_CONFIG6 -# define M_NAND_GPMC_CONFIG7 SMNAND_GPMC_CONFIG7 - -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x00151501 -# define STNOR_GPMC_CONFIG3 0x00060602 -# define STNOR_GPMC_CONFIG4 0x11091109 -# define STNOR_GPMC_CONFIG5 0x01141F1F -# define STNOR_GPMC_CONFIG6 0x000004c4 - -# define SIBNOR_GPMC_CONFIG1 0x1200 -# define SIBNOR_GPMC_CONFIG2 0x001f1f00 -# define SIBNOR_GPMC_CONFIG3 0x00080802 -# define SIBNOR_GPMC_CONFIG4 0x1C091C09 -# define SIBNOR_GPMC_CONFIG5 0x01131F1F -# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 - -# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 -# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 -# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 -# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 -# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F -# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 - -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001f1f01 -# define MPDB_GPMC_CONFIG3 0x00080803 -# define MPDB_GPMC_CONFIG4 0x1c0b1c0a -# define MPDB_GPMC_CONFIG5 0x041f1F1F -# define MPDB_GPMC_CONFIG6 0x1F0F04C4 - -# define P2_GPMC_CONFIG1 0x0 -# define P2_GPMC_CONFIG2 0x0 -# define P2_GPMC_CONFIG3 0x0 -# define P2_GPMC_CONFIG4 0x0 -# define P2_GPMC_CONFIG5 0x0 -# define P2_GPMC_CONFIG6 0x0 - -# define ONENAND_GPMC_CONFIG1 0x00001200 -# define ONENAND_GPMC_CONFIG2 0x000F0F01 -# define ONENAND_GPMC_CONFIG3 0x00030301 -# define ONENAND_GPMC_CONFIG4 0x0F040F04 -# define ONENAND_GPMC_CONFIG5 0x010F1010 -# define ONENAND_GPMC_CONFIG6 0x1F060000 - -#endif - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#define PISMO1_NOR 1 -#define PISMO1_NAND 2 -#define PISMO2_CS0 3 -#define PISMO2_CS1 4 -#define PISMO1_ONENAND 5 -#define POP_ONENAND 5 -#define DBG_MPDB 6 -#define PISMO2_NAND_CS0 7 -#define PISMO2_NAND_CS1 8 - -/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE NAND_BASE -#define PISMO2_CS0_BASE PISMO2_MAP1 -#define PISMO1_ONEN_BASE ONENAND_MAP -#define POP_ONEN_BASE ONENAND_MAP -#define DBG_MPDB_BASE DEBUG_BASE - -#endif /* endif _OMAP34XX_MEM_H_ */ diff --git a/x-loader/include/asm/arch-omap3/mmc.h b/x-loader/include/asm/arch-omap3/mmc.h deleted file mode 100644 index 8631aae..0000000 --- a/x-loader/include/asm/arch-omap3/mmc.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_H -#define MMC_H - -#include "mmc_host_def.h" - -/* Responses */ -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK) -#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) - -/* All supported commands */ -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD7_DESELECT (INDEX(7) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE) -#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) -#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) - -#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16) -#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16) -#define MMC_DSR_DEFAULT (0x0404) -#define SD_CMD8_CHECK_PATTERN (0xAA) -#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8) - -/* Clock Configurations and Macros */ - -#define MMC_CLOCK_REFERENCE (96) -#define MMC_RELATIVE_CARD_ADDRESS (0x1234) -#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80) -#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400) -#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1) -#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u)) - -#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29) -#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29) -#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29) - -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30) -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30) -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30) - -#define MMC_SD2_CSD_C_SIZE_LSB_MASK (0xFFFF) -#define MMC_SD2_CSD_C_SIZE_MSB_MASK (0x003F) -#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET (16) -#define MMC_CSD_C_SIZE_LSB_MASK (0x0003) -#define MMC_CSD_C_SIZE_MSB_MASK (0x03FF) -#define MMC_CSD_C_SIZE_MSB_OFFSET (2) - -#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0) -#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3) -#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0) -#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3) -#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3) - -typedef struct { - unsigned not_used:1; - unsigned crc:7; - unsigned ecc:2; - unsigned file_format:2; - unsigned tmp_write_protect:1; - unsigned perm_write_protect:1; - unsigned copy:1; - unsigned file_format_grp:1; - unsigned content_prot_app:1; - unsigned reserved_1:4; - unsigned write_bl_partial:1; - unsigned write_bl_len:4; - unsigned r2w_factor:3; - unsigned default_ecc:2; - unsigned wp_grp_enable:1; - unsigned wp_grp_size:5; - unsigned erase_grp_mult:5; - unsigned erase_grp_size:5; - unsigned c_size_mult:3; - unsigned vdd_w_curr_max:3; - unsigned vdd_w_curr_min:3; - unsigned vdd_r_curr_max:3; - unsigned vdd_r_curr_min:3; - unsigned c_size_lsb:2; - unsigned c_size_msb:10; - unsigned reserved_2:2; - unsigned dsr_imp:1; - unsigned read_blk_misalign:1; - unsigned write_blk_misalign:1; - unsigned read_bl_partial:1; - unsigned read_bl_len:4; - unsigned ccc:12; - unsigned tran_speed:8; - unsigned nsac:8; - unsigned taac:8; - unsigned reserved_3:2; - unsigned spec_vers:4; - unsigned csd_structure:2; -} mmc_csd_reg_t; - -/* csd for sd2.0 */ -typedef struct { - unsigned not_used:1; - unsigned crc:7; - unsigned reserved_1:2; - unsigned file_format:2; - unsigned tmp_write_protect:1; - unsigned perm_write_protect:1; - unsigned copy:1; - unsigned file_format_grp:1; - unsigned reserved_2:5; - unsigned write_bl_partial:1; - unsigned write_bl_len:4; - unsigned r2w_factor:3; - unsigned reserved_3:2; - unsigned wp_grp_enable:1; - unsigned wp_grp_size:7; - unsigned sector_size:7; - unsigned erase_blk_len:1; - unsigned reserved_4:1; - unsigned c_size_lsb:16; - unsigned c_size_msb:6; - unsigned reserved_5:6; - unsigned dsr_imp:1; - unsigned read_blk_misalign:1; - unsigned write_blk_misalign:1; - unsigned read_bl_partial:1; - unsigned read_bl_len:4; - unsigned ccc:12; - unsigned tran_speed:8; - unsigned nsac:8; - unsigned taac:8; - unsigned reserved_6:6; - unsigned csd_structure:2; -} mmc_sd2_csd_reg_t; - -/* extended csd - 512 bytes long */ -typedef struct { - unsigned char reserved_1[181]; - unsigned char erasedmemorycontent; - unsigned char reserved_2; - unsigned char buswidthmode; - unsigned char reserved_3; - unsigned char highspeedinterfacetiming; - unsigned char reserved_4; - unsigned char powerclass; - unsigned char reserved_5; - unsigned char commandsetrevision; - unsigned char reserved_6; - unsigned char commandset; - unsigned char extendedcsdrevision; - unsigned char reserved_7; - unsigned char csdstructureversion; - unsigned char reserved_8; - unsigned char cardtype; - unsigned char reserved_9[3]; - unsigned char powerclass_52mhz_1_95v; - unsigned char powerclass_26mhz_1_95v; - unsigned char powerclass_52mhz_3_6v; - unsigned char powerclass_26mhz_3_6v; - unsigned char reserved_10; - unsigned char minreadperf_4b_26mhz; - unsigned char minwriteperf_4b_26mhz; - unsigned char minreadperf_8b_26mhz_4b_52mhz; - unsigned char minwriteperf_8b_26mhz_4b_52mhz; - unsigned char minreadperf_8b_52mhz; - unsigned char minwriteperf_8b_52mhz; - unsigned char reserved_11; - unsigned int sectorcount; - unsigned char reserved_12[288]; - unsigned char supportedcommandsets; - unsigned char reserved_13[7]; -} mmc_extended_csd_reg_t; - -/* mmc sd responce */ -typedef struct { - unsigned int ocr; -} mmc_resp_r3; - -typedef struct { - unsigned short cardstatus; - unsigned short newpublishedrca; -} mmc_resp_r6; - -extern mmc_card_data mmc_dev; - -unsigned char mmc_lowlevel_init(void); -unsigned char mmc_send_command(unsigned int cmd, unsigned int arg, - unsigned int *response); -unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd); -unsigned char mmc_set_opendrain(unsigned char state); -unsigned char mmc_read_data(unsigned int *output_buf); - -#endif /* MMC_H */ diff --git a/x-loader/include/asm/arch-omap3/mmc_host_def.h b/x-loader/include/asm/arch-omap3/mmc_host_def.h deleted file mode 100644 index 408d1e2..0000000 --- a/x-loader/include/asm/arch-omap3/mmc_host_def.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -/* - * OMAP HSMMC register definitions - */ -#define OMAP_HSMMC_SYSCONFIG (*(volatile unsigned int *) 0x4809C010) -#define OMAP_HSMMC_SYSSTATUS (*(volatile unsigned int *) 0x4809C014) -#define OMAP_HSMMC_CON (*(volatile unsigned int *) 0x4809C02C) -#define OMAP_HSMMC_BLK (*(volatile unsigned int *) 0x4809C104) -#define OMAP_HSMMC_ARG (*(volatile unsigned int *) 0x4809C108) -#define OMAP_HSMMC_CMD (*(volatile unsigned int *) 0x4809C10C) -#define OMAP_HSMMC_RSP10 (*(volatile unsigned int *) 0x4809C110) -#define OMAP_HSMMC_RSP32 (*(volatile unsigned int *) 0x4809C114) -#define OMAP_HSMMC_RSP54 (*(volatile unsigned int *) 0x4809C118) -#define OMAP_HSMMC_RSP76 (*(volatile unsigned int *) 0x4809C11C) -#define OMAP_HSMMC_DATA (*(volatile unsigned int *) 0x4809C120) -#define OMAP_HSMMC_PSTATE (*(volatile unsigned int *) 0x4809C124) -#define OMAP_HSMMC_HCTL (*(volatile unsigned int *) 0x4809C128) -#define OMAP_HSMMC_SYSCTL (*(volatile unsigned int *) 0x4809C12C) -#define OMAP_HSMMC_STAT (*(volatile unsigned int *) 0x4809C130) -#define OMAP_HSMMC_IE (*(volatile unsigned int *) 0x4809C134) -#define OMAP_HSMMC_CAPA (*(volatile unsigned int *) 0x4809C140) - -/* T2 Register definitions */ -#define CONTROL_DEV_CONF0 (*(volatile unsigned int *) 0x48002274) -#define CONTROL_PBIAS_LITE (*(volatile unsigned int *) 0x48002520) - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define DATI_CMDDIS (0x1 << 1) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE (512) -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -typedef struct { - unsigned int card_type; - unsigned int version; - unsigned int mode; - unsigned int size; - unsigned int RCA; -} mmc_card_data; - -#define mmc_reg_out(addr, mask, val)\ - (addr) = (((addr)) & (~(mask))) | ((val) & (mask)); - -#endif /* MMC_HOST_DEF_H */ diff --git a/x-loader/include/asm/arch-omap3/mux.h b/x-loader/include/asm/arch-omap3/mux.h deleted file mode 100644 index ca140a9..0000000 --- a/x-loader/include/asm/arch-omap3/mux.h +++ /dev/null @@ -1,437 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * Syed Mohammed Khasim - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP3430_MUX_H_ -#define _OMAP3430_MUX_H_ - -/* - * OFF_PD - Off mode pull type down - * OFF_PU - Off mode pull type up - * OFF_OUT_PTD - Off Mode Mux low for OUT - * OFF_OUT_PTU - Off Mode Mux high for OUT - * OFF_IN - Off Mode Mux set to IN - * OFF_OUT - Off Mode Mux set to OUT - * OFF_EN - Off Mode Mux Enable - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - */ - -#define OFF_PD (1 << 12) -#define OFF_PU (3 << 12) -#define OFF_OUT_PTD (0 << 11) -#define OFF_OUT_PTU (1 << 11) -#define OFF_IN (1 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) - -#define IEN (1 << 8) - -#define IDIS (0 << 8) -#define PTU (1 << 4) -#define PTD (0 << 4) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -#ifdef CONFIG_OFF_PADCONF -#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) -#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) -#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) -#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) -#else -#define OFF_IN_PD 0 -#define OFF_IN_PU 0 -#define OFF_OUT_PD 0 -#define OFF_OUT_PU 0 -#endif /* #ifdef CONFIG_OFF_PADCONF */ - -/* - * To get the actual address the offset has to added - * with OMAP34XX_CTRL_BASE to get the actual address - */ - -/*SDRC*/ -#define CONTROL_PADCONF_SDRC_D0 0x0030 -#define CONTROL_PADCONF_SDRC_D1 0x0032 -#define CONTROL_PADCONF_SDRC_D2 0x0034 -#define CONTROL_PADCONF_SDRC_D3 0x0036 -#define CONTROL_PADCONF_SDRC_D4 0x0038 -#define CONTROL_PADCONF_SDRC_D5 0x003A -#define CONTROL_PADCONF_SDRC_D6 0x003C -#define CONTROL_PADCONF_SDRC_D7 0x003E -#define CONTROL_PADCONF_SDRC_D8 0x0040 -#define CONTROL_PADCONF_SDRC_D9 0x0042 -#define CONTROL_PADCONF_SDRC_D10 0x0044 -#define CONTROL_PADCONF_SDRC_D11 0x0046 -#define CONTROL_PADCONF_SDRC_D12 0x0048 -#define CONTROL_PADCONF_SDRC_D13 0x004A -#define CONTROL_PADCONF_SDRC_D14 0x004C -#define CONTROL_PADCONF_SDRC_D15 0x004E -#define CONTROL_PADCONF_SDRC_D16 0x0050 -#define CONTROL_PADCONF_SDRC_D17 0x0052 -#define CONTROL_PADCONF_SDRC_D18 0x0054 -#define CONTROL_PADCONF_SDRC_D19 0x0056 -#define CONTROL_PADCONF_SDRC_D20 0x0058 -#define CONTROL_PADCONF_SDRC_D21 0x005A -#define CONTROL_PADCONF_SDRC_D22 0x005C -#define CONTROL_PADCONF_SDRC_D23 0x005E -#define CONTROL_PADCONF_SDRC_D24 0x0060 -#define CONTROL_PADCONF_SDRC_D25 0x0062 -#define CONTROL_PADCONF_SDRC_D26 0x0064 -#define CONTROL_PADCONF_SDRC_D27 0x0066 -#define CONTROL_PADCONF_SDRC_D28 0x0068 -#define CONTROL_PADCONF_SDRC_D29 0x006A -#define CONTROL_PADCONF_SDRC_D30 0x006C -#define CONTROL_PADCONF_SDRC_D31 0x006E -#define CONTROL_PADCONF_SDRC_CLK 0x0070 -#define CONTROL_PADCONF_SDRC_DQS0 0x0072 -#define CONTROL_PADCONF_SDRC_DQS1 0x0074 -#define CONTROL_PADCONF_SDRC_DQS2 0x0076 -#define CONTROL_PADCONF_SDRC_DQS3 0x0078 -/*GPMC*/ -#define CONTROL_PADCONF_GPMC_A1 0x007A -#define CONTROL_PADCONF_GPMC_A2 0x007C -#define CONTROL_PADCONF_GPMC_A3 0x007E -#define CONTROL_PADCONF_GPMC_A4 0x0080 -#define CONTROL_PADCONF_GPMC_A5 0x0082 -#define CONTROL_PADCONF_GPMC_A6 0x0084 -#define CONTROL_PADCONF_GPMC_A7 0x0086 -#define CONTROL_PADCONF_GPMC_A8 0x0088 -#define CONTROL_PADCONF_GPMC_A9 0x008A -#define CONTROL_PADCONF_GPMC_A10 0x008C -#define CONTROL_PADCONF_GPMC_D0 0x008E -#define CONTROL_PADCONF_GPMC_D1 0x0090 -#define CONTROL_PADCONF_GPMC_D2 0x0092 -#define CONTROL_PADCONF_GPMC_D3 0x0094 -#define CONTROL_PADCONF_GPMC_D4 0x0096 -#define CONTROL_PADCONF_GPMC_D5 0x0098 -#define CONTROL_PADCONF_GPMC_D6 0x009A -#define CONTROL_PADCONF_GPMC_D7 0x009C -#define CONTROL_PADCONF_GPMC_D8 0x009E -#define CONTROL_PADCONF_GPMC_D9 0x00A0 -#define CONTROL_PADCONF_GPMC_D10 0x00A2 -#define CONTROL_PADCONF_GPMC_D11 0x00A4 -#define CONTROL_PADCONF_GPMC_D12 0x00A6 -#define CONTROL_PADCONF_GPMC_D13 0x00A8 -#define CONTROL_PADCONF_GPMC_D14 0x00AA -#define CONTROL_PADCONF_GPMC_D15 0x00AC -#define CONTROL_PADCONF_GPMC_nCS0 0x00AE -#define CONTROL_PADCONF_GPMC_nCS1 0x00B0 -#define CONTROL_PADCONF_GPMC_nCS2 0x00B2 -#define CONTROL_PADCONF_GPMC_nCS3 0x00B4 -#define CONTROL_PADCONF_GPMC_nCS4 0x00B6 -#define CONTROL_PADCONF_GPMC_nCS5 0x00B8 -#define CONTROL_PADCONF_GPMC_nCS6 0x00BA -#define CONTROL_PADCONF_GPMC_nCS7 0x00BC -#define CONTROL_PADCONF_GPMC_CLK 0x00BE -#define CONTROL_PADCONF_GPMC_nADV_ALE 0x00C0 -#define CONTROL_PADCONF_GPMC_nOE 0x00C2 -#define CONTROL_PADCONF_GPMC_nWE 0x00C4 -#define CONTROL_PADCONF_GPMC_nBE0_CLE 0x00C6 -#define CONTROL_PADCONF_GPMC_nBE1 0x00C8 -#define CONTROL_PADCONF_GPMC_nWP 0x00CA -#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC -#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE -#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 -#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 -/*DSS*/ -#define CONTROL_PADCONF_DSS_PCLK 0x00D4 -#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 -#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 -#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA -#define CONTROL_PADCONF_DSS_DATA0 0x00DC -#define CONTROL_PADCONF_DSS_DATA1 0x00DE -#define CONTROL_PADCONF_DSS_DATA2 0x00E0 -#define CONTROL_PADCONF_DSS_DATA3 0x00E2 -#define CONTROL_PADCONF_DSS_DATA4 0x00E4 -#define CONTROL_PADCONF_DSS_DATA5 0x00E6 -#define CONTROL_PADCONF_DSS_DATA6 0x00E8 -#define CONTROL_PADCONF_DSS_DATA7 0x00EA -#define CONTROL_PADCONF_DSS_DATA8 0x00EC -#define CONTROL_PADCONF_DSS_DATA9 0x00EE -#define CONTROL_PADCONF_DSS_DATA10 0x00F0 -#define CONTROL_PADCONF_DSS_DATA11 0x00F2 -#define CONTROL_PADCONF_DSS_DATA12 0x00F4 -#define CONTROL_PADCONF_DSS_DATA13 0x00F6 -#define CONTROL_PADCONF_DSS_DATA14 0x00F8 -#define CONTROL_PADCONF_DSS_DATA15 0x00FA -#define CONTROL_PADCONF_DSS_DATA16 0x00FC -#define CONTROL_PADCONF_DSS_DATA17 0x00FE -#define CONTROL_PADCONF_DSS_DATA18 0x0100 -#define CONTROL_PADCONF_DSS_DATA19 0x0102 -#define CONTROL_PADCONF_DSS_DATA20 0x0104 -#define CONTROL_PADCONF_DSS_DATA21 0x0106 -#define CONTROL_PADCONF_DSS_DATA22 0x0108 -#define CONTROL_PADCONF_DSS_DATA23 0x010A -/*CAMERA*/ -#define CONTROL_PADCONF_CAM_HS 0x010C -#define CONTROL_PADCONF_CAM_VS 0x010E -#define CONTROL_PADCONF_CAM_XCLKA 0x0110 -#define CONTROL_PADCONF_CAM_PCLK 0x0112 -#define CONTROL_PADCONF_CAM_FLD 0x0114 -#define CONTROL_PADCONF_CAM_D0 0x0116 -#define CONTROL_PADCONF_CAM_D1 0x0118 -#define CONTROL_PADCONF_CAM_D2 0x011A -#define CONTROL_PADCONF_CAM_D3 0x011C -#define CONTROL_PADCONF_CAM_D4 0x011E -#define CONTROL_PADCONF_CAM_D5 0x0120 -#define CONTROL_PADCONF_CAM_D6 0x0122 -#define CONTROL_PADCONF_CAM_D7 0x0124 -#define CONTROL_PADCONF_CAM_D8 0x0126 -#define CONTROL_PADCONF_CAM_D9 0x0128 -#define CONTROL_PADCONF_CAM_D10 0x012A -#define CONTROL_PADCONF_CAM_D11 0x012C -#define CONTROL_PADCONF_CAM_XCLKB 0x012E -#define CONTROL_PADCONF_CAM_WEN 0x0130 -#define CONTROL_PADCONF_CAM_STROBE 0x0132 -#define CONTROL_PADCONF_CSI2_DX0 0x0134 -#define CONTROL_PADCONF_CSI2_DY0 0x0136 -#define CONTROL_PADCONF_CSI2_DX1 0x0138 -#define CONTROL_PADCONF_CSI2_DY1 0x013A -/*Audio Interface */ -#define CONTROL_PADCONF_McBSP2_FSX 0x013C -#define CONTROL_PADCONF_McBSP2_CLKX 0x013E -#define CONTROL_PADCONF_McBSP2_DR 0x0140 -#define CONTROL_PADCONF_McBSP2_DX 0x0142 -#define CONTROL_PADCONF_ -#define CONTROL_PADCONF_MMC1_CLK 0x0144 -#define CONTROL_PADCONF_MMC1_CMD 0x0146 -#define CONTROL_PADCONF_MMC1_DAT0 0x0148 -#define CONTROL_PADCONF_MMC1_DAT1 0x014A -#define CONTROL_PADCONF_MMC1_DAT2 0x014C -#define CONTROL_PADCONF_MMC1_DAT3 0x014E -#define CONTROL_PADCONF_MMC1_DAT4 0x0150 -#define CONTROL_PADCONF_MMC1_DAT5 0x0152 -#define CONTROL_PADCONF_MMC1_DAT6 0x0154 -#define CONTROL_PADCONF_MMC1_DAT7 0x0156 -/*Wireless LAN */ -#define CONTROL_PADCONF_MMC2_CLK 0x0158 -#define CONTROL_PADCONF_MMC2_CMD 0x015A -#define CONTROL_PADCONF_MMC2_DAT0 0x015C -#define CONTROL_PADCONF_MMC2_DAT1 0x015E -#define CONTROL_PADCONF_MMC2_DAT2 0x0160 -#define CONTROL_PADCONF_MMC2_DAT3 0x0162 -#define CONTROL_PADCONF_MMC2_DAT4 0x0164 -#define CONTROL_PADCONF_MMC2_DAT5 0x0166 -#define CONTROL_PADCONF_MMC2_DAT6 0x0168 -#define CONTROL_PADCONF_MMC2_DAT7 0x016A -/*Bluetooth*/ -#define CONTROL_PADCONF_McBSP3_DX 0x016C -#define CONTROL_PADCONF_McBSP3_DR 0x016E -#define CONTROL_PADCONF_McBSP3_CLKX 0x0170 -#define CONTROL_PADCONF_McBSP3_FSX 0x0172 -#define CONTROL_PADCONF_UART2_CTS 0x0174 -#define CONTROL_PADCONF_UART2_RTS 0x0176 -#define CONTROL_PADCONF_UART2_TX 0x0178 -#define CONTROL_PADCONF_UART2_RX 0x017A -/*Modem Interface */ -#define CONTROL_PADCONF_UART1_TX 0x017C -#define CONTROL_PADCONF_UART1_RTS 0x017E -#define CONTROL_PADCONF_UART1_CTS 0x0180 -#define CONTROL_PADCONF_UART1_RX 0x0182 -#define CONTROL_PADCONF_McBSP4_CLKX 0x0184 -#define CONTROL_PADCONF_McBSP4_DR 0x0186 -#define CONTROL_PADCONF_McBSP4_DX 0x0188 -#define CONTROL_PADCONF_McBSP4_FSX 0x018A -#define CONTROL_PADCONF_McBSP1_CLKR 0x018C -#define CONTROL_PADCONF_McBSP1_FSR 0x018E -#define CONTROL_PADCONF_McBSP1_DX 0x0190 -#define CONTROL_PADCONF_McBSP1_DR 0x0192 -#define CONTROL_PADCONF_McBSP_CLKS 0x0194 -#define CONTROL_PADCONF_McBSP1_FSX 0x0196 -#define CONTROL_PADCONF_McBSP1_CLKX 0x0198 -/*Serial Interface*/ -#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A -#define CONTROL_PADCONF_UART3_RTS_SD 0x019C -#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E -#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 -#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 -#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 -#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 -#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 -#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA -#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC -#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE -#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 -#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 -#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 -#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 -#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 -#define CONTROL_PADCONF_I2C1_SCL 0x01BA -#define CONTROL_PADCONF_I2C1_SDA 0x01BC -#define CONTROL_PADCONF_I2C2_SCL 0x01BE -#define CONTROL_PADCONF_I2C2_SDA 0x01C0 -#define CONTROL_PADCONF_I2C3_SCL 0x01C2 -#define CONTROL_PADCONF_I2C3_SDA 0x01C4 -#define CONTROL_PADCONF_I2C4_SCL 0x0A00 -#define CONTROL_PADCONF_I2C4_SDA 0x0A02 -#define CONTROL_PADCONF_HDQ_SIO 0x01C6 -#define CONTROL_PADCONF_McSPI1_CLK 0x01C8 -#define CONTROL_PADCONF_McSPI1_SIMO 0x01CA -#define CONTROL_PADCONF_McSPI1_SOMI 0x01CC -#define CONTROL_PADCONF_McSPI1_CS0 0x01CE -#define CONTROL_PADCONF_McSPI1_CS1 0x01D0 -#define CONTROL_PADCONF_McSPI1_CS2 0x01D2 -#define CONTROL_PADCONF_McSPI1_CS3 0x01D4 -#define CONTROL_PADCONF_McSPI2_CLK 0x01D6 -#define CONTROL_PADCONF_McSPI2_SIMO 0x01D8 -#define CONTROL_PADCONF_McSPI2_SOMI 0x01DA -#define CONTROL_PADCONF_McSPI2_CS0 0x01DC -#define CONTROL_PADCONF_McSPI2_CS1 0x01DE -/*Control and debug */ -#define CONTROL_PADCONF_SYS_32K 0x0A04 -#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 -#define CONTROL_PADCONF_SYS_nIRQ 0x01E0 -#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A -#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C -#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E -#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 -#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 -#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 -#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 -#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 -#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A -#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 -#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C -#define CONTROL_PADCONF_JTAG_TCK 0x0A1E -#define CONTROL_PADCONF_JTAG_TMS 0x0A20 -#define CONTROL_PADCONF_JTAG_TDI 0x0A22 -#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 -#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 -#define CONTROL_PADCONF_ETK_CLK 0x0A28 -#define CONTROL_PADCONF_ETK_CTL 0x0A2A -#define CONTROL_PADCONF_ETK_D0 0x0A2C -#define CONTROL_PADCONF_ETK_D1 0x0A2E -#define CONTROL_PADCONF_ETK_D2 0x0A30 -#define CONTROL_PADCONF_ETK_D3 0x0A32 -#define CONTROL_PADCONF_ETK_D4 0x0A34 -#define CONTROL_PADCONF_ETK_D5 0x0A36 -#define CONTROL_PADCONF_ETK_D6 0x0A38 -#define CONTROL_PADCONF_ETK_D7 0x0A3A -#define CONTROL_PADCONF_ETK_D8 0x0A3C -#define CONTROL_PADCONF_ETK_D9 0x0A3E -#define CONTROL_PADCONF_ETK_D10 0x0A40 -#define CONTROL_PADCONF_ETK_D11 0x0A42 -#define CONTROL_PADCONF_ETK_D12 0x0A44 -#define CONTROL_PADCONF_ETK_D13 0x0A46 -#define CONTROL_PADCONF_ETK_D14 0x0A48 -#define CONTROL_PADCONF_ETK_D15 0x0A4A - -#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 -#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA -#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC -#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE -#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 -#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 -#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 -#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 -#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 -#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA -#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC -#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE -#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 -#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 -#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 -#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 -#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 -#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA - -/*Die to Die */ -#define CONTROL_PADCONF_d2d_mcad0 0x01E4 -#define CONTROL_PADCONF_d2d_mcad1 0x01E6 -#define CONTROL_PADCONF_d2d_mcad2 0x01E8 -#define CONTROL_PADCONF_d2d_mcad3 0x01EA -#define CONTROL_PADCONF_d2d_mcad4 0x01EC -#define CONTROL_PADCONF_d2d_mcad5 0x01EE -#define CONTROL_PADCONF_d2d_mcad6 0x01F0 -#define CONTROL_PADCONF_d2d_mcad7 0x01F2 -#define CONTROL_PADCONF_d2d_mcad8 0x01F4 -#define CONTROL_PADCONF_d2d_mcad9 0x01F6 -#define CONTROL_PADCONF_d2d_mcad10 0x01F8 -#define CONTROL_PADCONF_d2d_mcad11 0x01FA -#define CONTROL_PADCONF_d2d_mcad12 0x01FC -#define CONTROL_PADCONF_d2d_mcad13 0x01FE -#define CONTROL_PADCONF_d2d_mcad14 0x0200 -#define CONTROL_PADCONF_d2d_mcad15 0x0202 -#define CONTROL_PADCONF_d2d_mcad16 0x0204 -#define CONTROL_PADCONF_d2d_mcad17 0x0206 -#define CONTROL_PADCONF_d2d_mcad18 0x0208 -#define CONTROL_PADCONF_d2d_mcad19 0x020A -#define CONTROL_PADCONF_d2d_mcad20 0x020C -#define CONTROL_PADCONF_d2d_mcad21 0x020E -#define CONTROL_PADCONF_d2d_mcad22 0x0210 -#define CONTROL_PADCONF_d2d_mcad23 0x0212 -#define CONTROL_PADCONF_d2d_mcad24 0x0214 -#define CONTROL_PADCONF_d2d_mcad25 0x0216 -#define CONTROL_PADCONF_d2d_mcad26 0x0218 -#define CONTROL_PADCONF_d2d_mcad27 0x021A -#define CONTROL_PADCONF_d2d_mcad28 0x021C -#define CONTROL_PADCONF_d2d_mcad29 0x021E -#define CONTROL_PADCONF_d2d_mcad30 0x0220 -#define CONTROL_PADCONF_d2d_mcad31 0x0222 -#define CONTROL_PADCONF_d2d_mcad32 0x0224 -#define CONTROL_PADCONF_d2d_mcad33 0x0226 -#define CONTROL_PADCONF_d2d_mcad34 0x0228 -#define CONTROL_PADCONF_d2d_mcad35 0x022A -#define CONTROL_PADCONF_d2d_mcad36 0x022C -#define CONTROL_PADCONF_d2d_clk26mi 0x022E -#define CONTROL_PADCONF_d2d_nrespwron 0x0230 -#define CONTROL_PADCONF_d2d_nreswarm 0x0232 -#define CONTROL_PADCONF_d2d_arm9nirq 0x0234 -#define CONTROL_PADCONF_d2d_uma2p6fiq 0x0236 -#define CONTROL_PADCONF_d2d_spint 0x0238 -#define CONTROL_PADCONF_d2d_frint 0x023A -#define CONTROL_PADCONF_d2d_dmareq0 0x023C -#define CONTROL_PADCONF_d2d_dmareq1 0x023E -#define CONTROL_PADCONF_d2d_dmareq2 0x0240 -#define CONTROL_PADCONF_d2d_dmareq3 0x0242 -#define CONTROL_PADCONF_d2d_n3gtrst 0x0244 -#define CONTROL_PADCONF_d2d_n3gtdi 0x0246 -#define CONTROL_PADCONF_d2d_n3gtdo 0x0248 -#define CONTROL_PADCONF_d2d_n3gtms 0x024A -#define CONTROL_PADCONF_d2d_n3gtck 0x024C -#define CONTROL_PADCONF_d2d_n3grtck 0x024E -#define CONTROL_PADCONF_d2d_mstdby 0x0250 -#define CONTROL_PADCONF_d2d_swakeup 0x0A4C -#define CONTROL_PADCONF_d2d_idlereq 0x0252 -#define CONTROL_PADCONF_d2d_idleack 0x0254 -#define CONTROL_PADCONF_d2d_mwrite 0x0256 -#define CONTROL_PADCONF_d2d_swrite 0x0258 -#define CONTROL_PADCONF_d2d_mread 0x025A -#define CONTROL_PADCONF_d2d_sread 0x025C -#define CONTROL_PADCONF_d2d_mbusflag 0x025E -#define CONTROL_PADCONF_d2d_sbusflag 0x0260 -#define CONTROL_PADCONF_sdrc_cke0 0x0262 -#define CONTROL_PADCONF_sdrc_cke1 0x0264 - -#endif diff --git a/x-loader/include/asm/arch-omap3/omap3430.h b/x-loader/include/asm/arch-omap3/omap3430.h deleted file mode 100644 index 117d752..0000000 --- a/x-loader/include/asm/arch-omap3/omap3430.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * Richard Woodruff - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP3430_SYS_H_ -#define _OMAP3430_SYS_H_ - -#include - -/* - * 3430 specific Section - */ - -/* Stuff on L3 Interconnect */ -#define SMX_APE_BASE 0x68000000 - -/* L3 Firewall */ -#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048) -#define A_READPERM0 (SMX_APE_BASE + 0x05050) -#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058) - -/* GPMC */ -#define OMAP34XX_GPMC_BASE (0x6E000000) - -/* SMS */ -#define OMAP34XX_SMS_BASE 0x6C000000 - -/* SDRC */ -#define OMAP34XX_SDRC_BASE 0x6D000000 - -/* - * L4 Peripherals - L4 Wakeup and L4 Core now - */ -#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 - -#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000 - -#define OMAP34XX_L4_PER 0x49000000 - -#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE - -/* CONTROL */ -#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE+0x2000) - -/* TAP information dont know for 3430*/ -#define OMAP34XX_TAP_BASE (0x49000000) /*giving some junk for virtio */ - -/* UART */ -#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE+0x6a000) -#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE+0x6c000) -#define OMAP34XX_UART3 (OMAP34XX_L4_PER+0x20000) - -/* General Purpose Timers */ -#define OMAP34XX_GPT1 0x48318000 -#define OMAP34XX_GPT2 0x49032000 -#define OMAP34XX_GPT3 0x49034000 -#define OMAP34XX_GPT4 0x49036000 -#define OMAP34XX_GPT5 0x49038000 -#define OMAP34XX_GPT6 0x4903A000 -#define OMAP34XX_GPT7 0x4903C000 -#define OMAP34XX_GPT8 0x4903E000 -#define OMAP34XX_GPT9 0x49040000 -#define OMAP34XX_GPT10 0x48086000 -#define OMAP34XX_GPT11 0x48088000 -#define OMAP34XX_GPT12 0x48304000 - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE (0x4830C000) -#define WD2_BASE (0x48314000) -#define WD3_BASE (0x49030000) - -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE (0x48320000) -#define S32K_CR (SYNC_32KTIMER_BASE+0x10) - -/* omap3 GPIO registers */ -#define OMAP34XX_GPIO1_BASE 0x48310000 -#define OMAP34XX_GPIO2_BASE 0x49050000 -#define OMAP34XX_GPIO3_BASE 0x49052000 -#define OMAP34XX_GPIO4_BASE 0x49054000 -#define OMAP34XX_GPIO5_BASE 0x49056000 -#define OMAP34XX_GPIO6_BASE 0x49058000 - -/* - * SDP3430 specific Section - */ - -/* - * The 343x's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - * Same as in SDP3430 - */ -#ifdef CONFIG_OMAP34XX -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00200000 -#define SRAM_OFFSET2 0x0000F800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) - -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC -#endif - -#if defined(CONFIG_3430SDP) || defined(CONFIG_OMAP3EVM) -/* FPGA on Debug board.*/ -#define ETH_CONTROL_REG (DEBUG_BASE+0x30b) -#define LAN_RESET_REGISTER (DEBUG_BASE+0x1c) - -#define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60) -#define LED_REGISTER (DEBUG_BASE+0x40) -#define FPGA_REV_REGISTER (DEBUG_BASE+0x10) -#define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800) -#define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900) -#define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00) -#define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00) -#define ENHANCED_UI_EE_NAME "750-2075" -#endif - -/* - * 343x real hardware: - * ES1 = rev 0 - * - * ES2 onwards, the value maps to contents of IDCODE register [31:28]. - * - * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing. - */ -#define CPU_3XX_ES10 0 -#define CPU_3XX_ES20 1 -#define CPU_3XX_ES21 2 -#define CPU_3XX_ES30 3 -#define CPU_3XX_ES31 4 -#define CPU_3XX_ES312 7 -#define CPU_3XX_MAX_REV 8 - -#define CPU_3XX_ID_SHIFT 28 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -/* - * Control idcode register contains hawkeye and revision info - */ -#define CONTROL_IDCODE 0x4830A204 -#define CONTROL_OMAP_STATUS 0x4800244C - -/* - * Hawkeye values - */ -#define HAWKEYE_OMAP34XX 0xb7ae -#define HAWKEYE_AM35XX 0xb868 -#define HAWKEYE_OMAP36XX 0xb891 - -#define HAWKEYE_SHIFT 12 - -/* - * Define CPU families - */ -#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */ -#define CPU_AM35XX 0x3500 /* AM35xx devices */ -#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */ - -/* - * Control status register values corresponding to cpu variants - */ -#define OMAP3503 0x5c00 -#define OMAP3515 0x1c00 -#define OMAP3525 0x4c00 -#define OMAP3530 0x0c00 - -#define AM3505 0x5c00 -#define AM3517 0x1c00 - -#define OMAP3730 0x0c00 - -#endif /* _OMAP3430_SYS_H_ */ diff --git a/x-loader/include/asm/arch-omap3/rev.h b/x-loader/include/asm/arch-omap3/rev.h deleted file mode 100755 index c0e95d4..0000000 --- a/x-loader/include/asm/arch-omap3/rev.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * - * Richard Woodruff - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP34XX_REV_H_ -#define _OMAP34XX_REV_H_ - -#define CDB_DDR_COMBO /* combo part on cpu daughter card */ -#define CDB_DDR_IPDB /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_3430 0x3430 - -#define CPU_3430_ES1 1 -#define CPU_3430_ES2 1 - -#endif diff --git a/x-loader/include/asm/arch-omap3/sizes.h b/x-loader/include/asm/arch-omap3/sizes.h deleted file mode 100644 index aaba18f..0000000 --- a/x-loader/include/asm/arch-omap3/sizes.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_31M 0x01F00000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ diff --git a/x-loader/include/asm/arch-omap3/sys_info.h b/x-loader/include/asm/arch-omap3/sys_info.h deleted file mode 100644 index 18e2b49..0000000 --- a/x-loader/include/asm/arch-omap3/sys_info.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP34XX_SYS_INFO_H_ -#define _OMAP34XX_SYS_INFO_H_ - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module*/ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_3430 0x3430 - -/* 343x real hardware: - * ES1 = rev 0 - */ - -/* 343x code defines: - * ES1 = 0+1 = 1 - * ES1 = 1+1 = 1 - */ -#define CPU_3430_ES1 1 -#define CPU_3430_ES2 2 - -/* Currently Virtio models this one */ -#define CPU_3430_CHIPID 0x0B68A000 - -#define GPMC_MUXED 1 -#define GPMC_NONMUXED 0 - -#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ -#define TYPE_NOR 0x000 -#define TYPE_ONENAND 0x800 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ -#define I2C_TRITON2 0x4B /* addres of power group */ - -#define BOOT_FAST_XIP 0x1f - -/* SDP definitions according to FPGA Rev. Is this OK?? */ -#define SDP_3430_V1 0x1 -#define SDP_3430_V2 0x2 - -#define BOARD_3430_LABRADOR 0x80 -#define BOARD_3430_LABRADOR_V1 0x1 - -#endif diff --git a/x-loader/include/asm/arch-omap3/sys_proto.h b/x-loader/include/asm/arch-omap3/sys_proto.h deleted file mode 100644 index 7ac53a2..0000000 --- a/x-loader/include/asm/arch-omap3/sys_proto.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2004-2006 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP34XX_SYS_PROTO_H_ -#define _OMAP34XX_SYS_PROTO_H_ - -void prcm_init(void); -void per_clocks_enable(void); - -void memif_init(void); -void sdrc_init(void); -void do_sdrc_init(u32,u32); -void gpmc_init(void); - -void ether_init(void); -void watchdog_init(void); -void set_muxconf_regs(void); - -u32 get_cpu_type(void); -u32 get_cpu_rev(void); -u32 cpu_is_3410(void); -u32 get_mem_type(void); -u32 get_sysboot_value(void); -u32 get_gpmc0_base(void); -u32 is_gpmc_muxed(void); -u32 get_gpmc0_type(void); -u32 get_gpmc0_width(void); -u32 get_board_type(void); -void display_board_info(u32); -void update_mux(u32,u32); -u32 get_sdr_cs_size(u32 offset); -u32 running_in_sdram(void); -u32 running_in_sram(void); -u32 running_in_flash(void); -u32 running_from_internal_boot(void); -u32 get_device_type(void); - -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value); -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); -void sdelay(unsigned long loops); - -#endif diff --git a/x-loader/include/asm/arch-omap4/bits.h b/x-loader/include/asm/arch-omap4/bits.h deleted file mode 100644 index 541dd97..0000000 --- a/x-loader/include/asm/arch-omap4/bits.h +++ /dev/null @@ -1,48 +0,0 @@ -/* bits.h - * Copyright (c) 2004-2009 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ -#ifndef __bits_h -#define __bits_h 1 - -#define BIT0 (1<<0) -#define BIT1 (1<<1) -#define BIT2 (1<<2) -#define BIT3 (1<<3) -#define BIT4 (1<<4) -#define BIT5 (1<<5) -#define BIT6 (1<<6) -#define BIT7 (1<<7) -#define BIT8 (1<<8) -#define BIT9 (1<<9) -#define BIT10 (1<<10) -#define BIT11 (1<<11) -#define BIT12 (1<<12) -#define BIT13 (1<<13) -#define BIT14 (1<<14) -#define BIT15 (1<<15) -#define BIT16 (1<<16) -#define BIT17 (1<<17) -#define BIT18 (1<<18) -#define BIT19 (1<<19) -#define BIT20 (1<<20) -#define BIT21 (1<<21) -#define BIT22 (1<<22) -#define BIT23 (1<<23) -#define BIT24 (1<<24) -#define BIT25 (1<<25) -#define BIT26 (1<<26) -#define BIT27 (1<<27) -#define BIT28 (1<<28) -#define BIT29 (1<<29) -#define BIT30 (1<<30) -#define BIT31 (1<<31) - -#endif diff --git a/x-loader/include/asm/arch-omap4/clocks.h b/x-loader/include/asm/arch-omap4/clocks.h deleted file mode 100644 index a65cbda..0000000 --- a/x-loader/include/asm/arch-omap4/clocks.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP44XX_CLOCKS_H_ -#define _OMAP44XX_CLOCKS_H_ - -#define LDELAY 12000000 - -#define S12M 12000000 -#define S13M 13000000 -#define S16_8M 16800000 -#define S19_2M 19200000 -#define S24M 24000000 -#define S26M 26000000 -#define S27M 27000000 -#define S38_4M 38400000 - -#include - -#endif diff --git a/x-loader/include/asm/arch-omap4/clocks443x.h b/x-loader/include/asm/arch-omap4/clocks443x.h deleted file mode 100644 index 63280f7..0000000 --- a/x-loader/include/asm/arch-omap4/clocks443x.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP443X_CLOCKS_H_ -#define _OMAP443X_CLOCKS_H_ - -#define PLL_STOP 1 /* PER & IVA */ -#define PLL_MN_POWER_BYPASS 4 -#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ -#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ -#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ - -/* The following configurations are OPP and SysClk value independant - * and hence are defined here. All the other DPLL related values are - * tabulated in lowlevel_init.S. - */ - -/* CORE DPLL */ -# define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ -# define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ -# define CORE_FUSB_DIV 2 /* 41.5MHz: */ -# define CORE_L4_DIV 2 /* 83MHz : L4 */ -# define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ -# define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ -# define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ - -/* PER DPLL */ -# define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ -# define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ -# define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */ -# define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ - -# define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) - -#ifdef PRCM_CLK_CFG2_332MHZ -# define M_12 0xA6 -# define N_12 0x05 -# define FSEL_12 0x07 -# define M2_12 0x01 /* M3 of 2 */ - -# define M_12_ES1 0x0E -# define FSL_12_ES1 0x03 -# define M2_12_ES1 0x1 /* M3 of 2 */ - -# define M_13 0x14C -# define N_13 0x0C -# define FSEL_13 0x03 -# define M2_13 0x01 /* M3 of 2 */ - -# define M_13_ES1 0x1B2 -# define N_13_ES1 0x10 -# define FSL_13_ES1 0x03 -# define M2_13_ES1 0x01 /* M3 of 2 */ - -# define M_19p2 0x19F -# define N_19p2 0x17 -# define FSEL_19p2 0x03 -# define M2_19p2 0x01 /* M3 of 2 */ - -# define M_19p2_ES1 0x19F -# define N_19p2_ES1 0x17 -# define FSL_19p2_ES1 0x03 -# define M2_19p2_ES1 0x01 /* M3 of 2 */ - -# define M_26 0xA6 -# define N_26 0x0C -# define FSEL_26 0x07 -# define M2_26 0x01 /* M3 of 2 */ - -# define M_26_ES1 0x1B2 -# define N_26_ES1 0x21 -# define FSL_26_ES1 0x03 -# define M2_26_ES1 0x01 /* M3 of 2 */ - -# define M_38p4 0x19F -# define N_38p4 0x2F -# define FSEL_38p4 0x03 -# define M2_38p4 0x01 /* M3 of 2 */ - -# define M_38p4_ES1 0x19F -# define N_38p4_ES1 0x2F -# define FSL_38p4_ES1 0x03 -# define M2_38p4_ES1 0x01 /* M3 of 2 */ - -#elif defined(PRCM_CLK_CFG2_266MHZ) -# define M_12 0x85 -# define N_12 0x05 -# define FSEL_12 0x07 -# define M2_12 0x02 /* M3 of 2 */ - -# define M_12_ES1 0x85 /* 0x10A */ -# define N_12_ES1 0x05 /* 0x05 */ -# define FSL_12_ES1 0x07 /* 0x7 */ -# define M2_12_ES1 0x2 /* 0x2 with an M3 of 4*/ - -# define M_13 0x10A -# define N_13 0x0C -# define FSEL_13 0x3 -# define M2_13 0x1 /* M3 of 2 */ - -# define M_13_ES1 0x10A /* 0x214 */ -# define N_13_ES1 0x0C /* 0xC */ -# define FSL_13_ES1 0x3 /* 0x3 */ -# define M2_13_ES1 0x1 /* 0x2 with an M3 of 4*/ - -# define M_19p2 0x115 -# define N_19p2 0x13 -# define FSEL_19p2 0x03 -# define M2_19p2 0x01 /* M3 of 2 */ - -# define M_19p2_ES1 0x115 /* 0x299 */ -# define N_19p2_ES1 0x13 /* 0x17 */ -# define FSL_19p2_ES1 0x03 /* 0x03 */ -# define M2_19p2_ES1 0x01 /* 0x2 with M3 of 4 */ - -# define M_26 0x85 -# define N_26 0x0C -# define FSEL_26 0x07 -# define M2_26 0x01 /* M3 of 2 */ - -# define M_26_ES1 0x85 /* 0x10A */ -# define N_26_ES1 0x0C /* 0xC */ -# define FSL_26_ES1 0x07 /* 0x7 */ -# define M2_26_ES1 0x01 /* 0x2 with an M3 of 4 */ - -# define M_38p4 0x11C -# define N_38p4 0x28 -# define FSEL_38p4 0x03 -# define M2_38p4 0x01 /* M3 of 2 */ - -# define M_38p4_ES1 0x11C /* 0x299 */ -# define N_38p4_ES1 0x28 /* 0x2f */ -# define FSL_38p4_ES1 0x03 /* 0x3 */ -# define M2_38p4_ES1 0x01 /* 0x2 with an M3 of 4*/ - -#endif - -#endif /* endif _OMAP443X_CLOCKS_H_ */ diff --git a/x-loader/include/asm/arch-omap4/cpu.h b/x-loader/include/asm/arch-omap4/cpu.h deleted file mode 100644 index 94aeb9f..0000000 --- a/x-loader/include/asm/arch-omap4/cpu.h +++ /dev/null @@ -1,464 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _OMAP44XX_CPU_H -#define _OMAP44XX_CPU_H -#include - -/* Register offsets of common modules */ -/* Control */ -#define CONTROL_STATUS (OMAP44XX_CTRL_BASE + 0x2F0) -#define OMAP44XX_MCR (OMAP44XX_CTRL_BASE + 0x8C) -#define CONTROL_SCALABLE_OMAP_STATUS (OMAP44XX_CTRL_BASE + 0x44C) -#define CONTROL_SCALABLE_OMAP_OCP (OMAP44XX_CTRL_BASE + 0x534) - - -/* Tap Information */ -#define TAP_IDCODE_REG (OMAP44XX_TAP_BASE+0x204) -#define PRODUCTION_ID (OMAP44XX_TAP_BASE+0x208) - -/* device type */ -#define DEVICE_MASK (BIT8|BIT9|BIT10) -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 - -/* GPMC CS3/cs4/cs6 not avaliable */ -#define GPMC_BASE (OMAP44XX_GPMC_BASE) -#define GPMC_SYSCONFIG (OMAP44XX_GPMC_BASE+0x10) -#define GPMC_IRQSTATUS (OMAP44XX_GPMC_BASE+0x18) -#define GPMC_IRQENABLE (OMAP44XX_GPMC_BASE+0x1C) -#define GPMC_TIMEOUT_CONTROL (OMAP44XX_GPMC_BASE+0x40) -#define GPMC_CONFIG (OMAP44XX_GPMC_BASE+0x50) -#define GPMC_STATUS (OMAP44XX_GPMC_BASE+0x54) - -#define GPMC_CONFIG_CS0 (OMAP44XX_GPMC_BASE+0x60) -#define GPMC_CONFIG_WIDTH (0x30) - -#define GPMC_CONFIG1 (0x00) -#define GPMC_CONFIG2 (0x04) -#define GPMC_CONFIG3 (0x08) -#define GPMC_CONFIG4 (0x0C) -#define GPMC_CONFIG5 (0x10) -#define GPMC_CONFIG6 (0x14) -#define GPMC_CONFIG7 (0x18) -#define GPMC_NAND_CMD (0x1C) -#define GPMC_NAND_ADR (0x20) -#define GPMC_NAND_DAT (0x24) - -#define GPMC_ECC_CONFIG (0x1F4) -#define GPMC_ECC_CONTROL (0x1F8) -#define GPMC_ECC_SIZE_CONFIG (0x1FC) -#define GPMC_ECC1_RESULT (0x200) -#define GPMC_ECC2_RESULT (0x204) -#define GPMC_ECC3_RESULT (0x208) -#define GPMC_ECC4_RESULT (0x20C) -#define GPMC_ECC5_RESULT (0x210) -#define GPMC_ECC6_RESULT (0x214) -#define GPMC_ECC7_RESULT (0x218) -#define GPMC_ECC8_RESULT (0x21C) -#define GPMC_ECC9_RESULT (0x220) - -#define GPMC_PREFETCH_CONFIG1 (0x1e0) -#define GPMC_PREFETCH_CONFIG2 (0x1e4) -#define GPMC_PREFETCH_CONTROL (0x1ec) -#define GPMC_PREFETCH_STATUS (0x1f0) - -/* GPMC Mapping */ -# define FLASH_BASE 0x10000000 /* NOR flash (aligned to 256 Meg) */ -# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (aligned to 64 Meg) */ -# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (aligned to 256 Meg) */ -# define DEBUG_BASE 0x08000000 /* debug board */ -# define NAND_BASE 0x30000000 /* NAND addr (actual size small port)*/ -# define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ -# define ONENAND_MAP 0x20000000 /* OneNand addr (actual size small port */ - -/* DMM */ -#define DMM_SYSCONFIG (OMAP44XX_DMM_BASE+0x10) -#define DMM_LISA_MAP (OMAP44XX_DMM_BASE+0x100) - -/* SMS */ -#define SMS_SYSCONFIG (OMAP44XX_SMS_BASE+0x10) -#define SMS_RG_ATT0 (OMAP44XX_SMS_BASE+0x48) -#define SMS_CLASS_ARB0 (OMAP44XX_SMS_BASE+0xD0) -#define BURSTCOMPLETE_GROUP7 BIT31 - -#define SDRC_CS_CFG (OMAP44XX_SDRC_BASE+0x40) -#define OMAP44XX_SDRC_CS0 0x80000000 -#define SDRC_POWER (OMAP44XX_SDRC_BASE+0x70) -#define SDRC_MCFG_0 (OMAP44XX_SDRC_BASE+0x80) -#define SDRC_MR_0 (OMAP44XX_SDRC_BASE+0x84) - -/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ -#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ - -/* Watchdog */ -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* FIXME */ -#define PRM_RSTCTRL 0x48307250 - /* PRCM */ -#define CM_SYS_CLKSEL 0x4a306110 - -/* PRM.CKGEN module registers */ -#define CM_ABE_PLL_REF_CLKSEL 0x4a30610c - - -/* PRM.WKUP_CM module registers */ -#define CM_WKUP_CLKSTCTRL 0x4a307800 -#define CM_WKUP_L4WKUP_CLKCTRL 0x4a307820 -#define CM_WKUP_WDT1_CLKCTRL 0x4a307828 -#define CM_WKUP_WDT2_CLKCTRL 0x4a307830 -#define CM_WKUP_GPIO1_CLKCTRL 0x4a307838 -#define CM_WKUP_TIMER1_CLKCTRL 0x4a307840 -#define CM_WKUP_TIMER12_CLKCTRL 0x4a307848 -#define CM_WKUP_SYNCTIMER_CLKCTRL 0x4a307850 -#define CM_WKUP_USIM_CLKCTRL 0x4a307858 -#define CM_WKUP_SARRAM_CLKCTRL 0x4a307860 -#define CM_WKUP_KEYBOARD_CLKCTRL 0x4a307878 -#define CM_WKUP_RTC_CLKCTRL 0x4a307880 -#define CM_WKUP_BANDGAP_CLKCTRL 0x4a307888 - -/* CM1.CKGEN module registers */ -#define CM_CLKSEL_CORE 0x4a004100 -#define CM_CLKSEL_ABE 0x4a004108 -#define CM_DLL_CTRL 0x4a004110 -#define CM_CLKMODE_DPLL_CORE 0x4a004120 -#define CM_IDLEST_DPLL_CORE 0x4a004124 -#define CM_AUTOIDLE_DPLL_CORE 0x4a004128 -#define CM_CLKSEL_DPLL_CORE 0x4a00412c -#define CM_DIV_M2_DPLL_CORE 0x4a004130 -#define CM_DIV_M3_DPLL_CORE 0x4a004134 -#define CM_DIV_M4_DPLL_CORE 0x4a004138 -#define CM_DIV_M5_DPLL_CORE 0x4a00413c -#define CM_DIV_M6_DPLL_CORE 0x4a004140 -#define CM_DIV_M7_DPLL_CORE 0x4a004144 -#define CM_SSC_DELTAMSTEP_DPLL_CORE 0x4a004148 -#define CM_SSC_MODFREQDIV_DPLL_CORE 0x4a00414c -#define CM_EMU_OVERRIDE_DPLL_CORE 0x4a004150 -#define CM_CLKMODE_DPLL_MPU 0x4a004160 -#define CM_IDLEST_DPLL_MPU 0x4a004164 -#define CM_AUTOIDLE_DPLL_MPU 0x4a004168 -#define CM_CLKSEL_DPLL_MPU 0x4a00416c -#define CM_DIV_M2_DPLL_MPU 0x4a004170 -#define CM_SSC_DELTAMSTEP_DPLL_MPU 0x4a004188 -#define CM_SSC_MODFREQDIV_DPLL_MPU 0x4a00418c -#define CM_BYPCLK_DPLL_MPU 0x4a00419c -#define CM_CLKMODE_DPLL_IVA 0x4a0041a0 -#define CM_IDLEST_DPLL_IVA 0x4a0041a4 -#define CM_AUTOIDLE_DPLL_IVA 0x4a0041a8 -#define CM_CLKSEL_DPLL_IVA 0x4a0041ac -#define CM_DIV_M4_DPLL_IVA 0x4a0041b8 -#define CM_DIV_M5_DPLL_IVA 0x4a0041bc -#define CM_SSC_DELTAMSTEP_DPLL_IVA 0x4a0041c8 -#define CM_SSC_MODFREQDIV_DPLL_IVA 0x4a0041cc -#define CM_BYPCLK_DPLL_IVA 0x4a0041dc -#define CM_CLKMODE_DPLL_ABE 0x4a0041e0 -#define CM_IDLEST_DPLL_ABE 0x4a0041e4 -#define CM_AUTOIDLE_DPLL_ABE 0x4a0041e8 -#define CM_CLKSEL_DPLL_ABE 0x4a0041ec -#define CM_DIV_M2_DPLL_ABE 0x4a0041f0 -#define CM_DIV_M3_DPLL_ABE 0x4a0041f4 -#define CM_SSC_DELTAMSTEP_DPLL_ABE 0x4a004208 -#define CM_SSC_MODFREQDIV_DPLL_ABE 0x4a00420c -#define CM_CLKMODE_DPLL_DDRPHY 0x4a004220 -#define CM_IDLEST_DPLL_DDRPHY 0x4a004224 -#define CM_AUTOIDLE_DPLL_DDRPHY 0x4a004228 -#define CM_CLKSEL_DPLL_DDRPHY 0x4a00422c -#define CM_DIV_M2_DPLL_DDRPHY 0x4a004230 -#define CM_DIV_M4_DPLL_DDRPHY 0x4a004238 -#define CM_DIV_M5_DPLL_DDRPHY 0x4a00423c -#define CM_DIV_M6_DPLL_DDRPHY 0x4a004240 -#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY 0x4a004248 - -/* CM1.ABE register offsets */ -#define CM1_ABE_CLKSTCTRL 0x4a004500 -#define CM1_ABE_L4ABE_CLKCTRL 0x4a004520 -#define CM1_ABE_AESS_CLKCTRL 0x4a004528 -#define CM1_ABE_PDM_CLKCTRL 0x4a004530 -#define CM1_ABE_DMIC_CLKCTRL 0x4a004538 -#define CM1_ABE_MCASP_CLKCTRL 0x4a004540 -#define CM1_ABE_MCBSP1_CLKCTRL 0x4a004548 -#define CM1_ABE_MCBSP2_CLKCTRL 0x4a004550 -#define CM1_ABE_MCBSP3_CLKCTRL 0x4a004558 -#define CM1_ABE_SLIMBUS_CLKCTRL 0x4a004560 -#define CM1_ABE_TIMER5_CLKCTRL 0x4a004568 -#define CM1_ABE_TIMER6_CLKCTRL 0x4a004570 -#define CM1_ABE_TIMER7_CLKCTRL 0x4a004578 -#define CM1_ABE_TIMER8_CLKCTRL 0x4a004580 -#define CM1_ABE_WDT3_CLKCTRL 0x4a004588 - -/* CM1.DSP register offsets */ -#define DSP_CLKSTCTRL 0x4a004400 -#define DSP_DSP_CLKCTRL 0x4a004420 - -/* CM2.CKGEN module registers */ -#define CM_CLKSEL_DUCATI_ISS_ROOT 0x4a008100 -#define CM_CLKSEL_USB_60MHz 0x4a008104 -#define CM_SCALE_FCLK 0x4a008108 -#define CM_CORE_DVFS_PERF1 0x4a008110 -#define CM_CORE_DVFS_PERF2 0x4a008114 -#define CM_CORE_DVFS_PERF3 0x4a008118 -#define CM_CORE_DVFS_PERF4 0x4a00811c -#define CM_CORE_DVFS_CURRENT 0x4a008124 -#define CM_IVA_DVFS_PERF_TESLA 0x4a008128 -#define CM_IVA_DVFS_PERF_IVAHD 0x4a00812c -#define CM_IVA_DVFS_PERF_ABE 0x4a008130 -#define CM_IVA_DVFS_CURRENT 0x4a008138 -#define CM_CLKMODE_DPLL_PER 0x4a008140 -#define CM_IDLEST_DPLL_PER 0x4a008144 -#define CM_AUTOIDLE_DPLL_PER 0x4a008148 -#define CM_CLKSEL_DPLL_PER 0x4a00814c -#define CM_DIV_M2_DPLL_PER 0x4a008150 -#define CM_DIV_M3_DPLL_PER 0x4a008154 -#define CM_DIV_M4_DPLL_PER 0x4a008158 -#define CM_DIV_M5_DPLL_PER 0x4a00815c -#define CM_DIV_M6_DPLL_PER 0x4a008160 -#define CM_DIV_M7_DPLL_PER 0x4a008164 -#define CM_SSC_DELTAMSTEP_DPLL_PER 0x4a008168 -#define CM_SSC_MODFREQDIV_DPLL_PER 0x4a00816c -#define CM_EMU_OVERRIDE_DPLL_PER 0x4a008170 -#define CM_CLKMODE_DPLL_USB 0x4a008180 -#define CM_IDLEST_DPLL_USB 0x4a008184 -#define CM_AUTOIDLE_DPLL_USB 0x4a008188 -#define CM_CLKSEL_DPLL_USB 0x4a00818c -#define CM_DIV_M2_DPLL_USB 0x4a008190 -#define CM_SSC_DELTAMSTEP_DPLL_USB 0x4a0081a8 -#define CM_SSC_MODFREQDIV_DPLL_USB 0x4a0081ac -#define CM_CLKDCOLDO_DPLL_USB 0x4a0081b4 -#define CM_CLKMODE_DPLL_UNIPRO 0x4a0081c0 -#define CM_IDLEST_DPLL_UNIPRO 0x4a0081c4 -#define CM_AUTOIDLE_DPLL_UNIPRO 0x4a0081c8 -#define CM_CLKSEL_DPLL_UNIPRO 0x4a0081cc -#define CM_DIV_M2_DPLL_UNIPRO 0x4a0081d0 -#define CM_SSC_DELTAMSTEP_DPLL_UNIPRO 0x4a0081e8 -#define CM_SSC_MODFREQDIV_DPLL_UNIPRO 0x4a0081ec - -/* CM2.CORE module registers */ -#define CM_L3_1_CLKSTCTRL 0x4a008700 -#define CM_L3_1_DYNAMICDEP 0x4a008708 -#define CM_L3_1_L3_1_CLKCTRL 0x4a008720 -#define CM_L3_2_CLKSTCTRL 0x4a008800 -#define CM_L3_2_DYNAMICDEP 0x4a008808 -#define CM_L3_2_L3_2_CLKCTRL 0x4a008820 -#define CM_L3_2_GPMC_CLKCTRL 0x4a008828 -#define CM_L3_2_OCMC_RAM_CLKCTRL 0x4a008830 -#define CM_DUCATI_CLKSTCTRL 0x4a008900 -#define CM_DUCATI_STATICDEP 0x4a008904 -#define CM_DUCATI_DYNAMICDEP 0x4a008908 -#define CM_DUCATI_DUCATI_CLKCTRL 0x4a008920 -#define CM_SDMA_CLKSTCTRL 0x4a008a00 -#define CM_SDMA_STATICDEP 0x4a008a04 -#define CM_SDMA_DYNAMICDEP 0x4a008a08 -#define CM_SDMA_SDMA_CLKCTRL 0x4a008a20 -#define CM_MEMIF_CLKSTCTRL 0x4a008b00 -#define CM_MEMIF_DMM_CLKCTRL 0x4a008b20 -#define CM_MEMIF_EMIF_FW_CLKCTRL 0x4a008b28 -#define CM_MEMIF_EMIF_1_CLKCTRL 0x4a008b30 -#define CM_MEMIF_EMIF_2_CLKCTRL 0x4a008b38 -#define CM_MEMIF_DLL_CLKCTRL 0x4a008b40 -#define CM_MEMIF_EMIF_H1_CLKCTRL 0x4a008b50 -#define CM_MEMIF_EMIF_H2_CLKCTRL 0x4a008b58 -#define CM_MEMIF_DLL_H_CLKCTRL 0x4a008b60 -#define CM_D2D_CLKSTCTRL 0x4a008c00 -#define CM_D2D_STATICDEP 0x4a008c04 -#define CM_D2D_DYNAMICDEP 0x4a008c08 -#define CM_D2D_SAD2D_CLKCTRL 0x4a008c20 -#define CM_D2D_MODEM_ICR_CLKCTRL 0x4a008c28 -#define CM_D2D_SAD2D_FW_CLKCTRL 0x4a008c30 -#define CM_L4CFG_CLKSTCTRL 0x4a008d00 -#define CM_L4CFG_DYNAMICDEP 0x4a008d08 -#define CM_L4CFG_L4_CFG_CLKCTRL 0x4a008d20 -#define CM_L4CFG_HW_SEM_CLKCTRL 0x4a008d28 -#define CM_L4CFG_MAILBOX_CLKCTRL 0x4a008d30 -#define CM_L4CFG_SAR_ROM_CLKCTRL 0x4a008d38 -#define CM_L3INSTR_CLKSTCTRL 0x4a008e00 -#define CM_L3INSTR_L3_3_CLKCTRL 0x4a008e20 -#define CM_L3INSTR_L3_INSTR_CLKCTRL 0x4a008e28 -#define CM_L3INSTR_OCP_WP1_CLKCTRL 0x4a008e40 - -/* CM2.L4PER register offsets */ -#define CM_L4PER_CLKSTCTRL 0x4a009400 -#define CM_L4PER_DYNAMICDEP 0x4a009408 -#define CM_L4PER_ADC_CLKCTRL 0x4a009420 -#define CM_L4PER_DMTIMER10_CLKCTRL 0x4a009428 -#define CM_L4PER_DMTIMER11_CLKCTRL 0x4a009430 -#define CM_L4PER_DMTIMER2_CLKCTRL 0x4a009438 -#define CM_L4PER_DMTIMER3_CLKCTRL 0x4a009440 -#define CM_L4PER_DMTIMER4_CLKCTRL 0x4a009448 -#define CM_L4PER_DMTIMER9_CLKCTRL 0x4a009450 -#define CM_L4PER_ELM_CLKCTRL 0x4a009458 -#define CM_L4PER_GPIO2_CLKCTRL 0x4a009460 -#define CM_L4PER_GPIO3_CLKCTRL 0x4a009468 -#define CM_L4PER_GPIO4_CLKCTRL 0x4a009470 -#define CM_L4PER_GPIO5_CLKCTRL 0x4a009478 -#define CM_L4PER_GPIO6_CLKCTRL 0x4a009480 -#define CM_L4PER_HDQ1W_CLKCTRL 0x4a009488 -#define CM_L4PER_HECC1_CLKCTRL 0x4a009490 -#define CM_L4PER_HECC2_CLKCTRL 0x4a009498 -#define CM_L4PER_I2C1_CLKCTRL 0x4a0094a0 -#define CM_L4PER_I2C2_CLKCTRL 0x4a0094a8 -#define CM_L4PER_I2C3_CLKCTRL 0x4a0094b0 -#define CM_L4PER_I2C4_CLKCTRL 0x4a0094b8 -#define CM_L4PER_L4PER_CLKCTRL 0x4a0094c0 -#define CM_L4PER_MCASP2_CLKCTRL 0x4a0094d0 -#define CM_L4PER_MCASP3_CLKCTRL 0x4a0094d8 -#define CM_L4PER_MCBSP4_CLKCTRL 0x4a0094e0 -#define CM_L4PER_MGATE_CLKCTRL 0x4a0094e8 -#define CM_L4PER_MCSPI1_CLKCTRL 0x4a0094f0 -#define CM_L4PER_MCSPI2_CLKCTRL 0x4a0094f8 -#define CM_L4PER_MCSPI3_CLKCTRL 0x4a009500 -#define CM_L4PER_MCSPI4_CLKCTRL 0x4a009508 -#define CM_L4PER_MMCSD3_CLKCTRL 0x4a009520 -#define CM_L4PER_MMCSD4_CLKCTRL 0x4a009528 -#define CM_L4PER_MSPROHG_CLKCTRL 0x4a009530 -#define CM_L4PER_SLIMBUS2_CLKCTRL 0x4a009538 -#define CM_L4PER_UART1_CLKCTRL 0x4a009540 -#define CM_L4PER_UART2_CLKCTRL 0x4a009548 -#define CM_L4PER_UART3_CLKCTRL 0x4a009550 -#define CM_L4PER_UART4_CLKCTRL 0x4a009558 -#define CM_L4PER_MMCSD5_CLKCTRL 0x4a009560 -#define CM_L4PER_I2C5_CLKCTRL 0x4a009568 -#define CM_L4SEC_CLKSTCTRL 0x4a009580 -#define CM_L4SEC_STATICDEP 0x4a009584 -#define CM_L4SEC_DYNAMICDEP 0x4a009588 -#define CM_L4SEC_AES1_CLKCTRL 0x4a0095a0 -#define CM_L4SEC_AES2_CLKCTRL 0x4a0095a8 -#define CM_L4SEC_DES3DES_CLKCTRL 0x4a0095b0 -#define CM_L4SEC_PKAEIP29_CLKCTRL 0x4a0095b8 -#define CM_L4SEC_RNG_CLKCTRL 0x4a0095c0 -#define CM_L4SEC_SHA2MD51_CLKCTRL 0x4a0095c8 -#define CM_L4SEC_CRYPTODMA_CLKCTRL 0x4a0095d8 - -/* CM2.IVAHD */ -#define IVAHD_CLKSTCTRL 0x4a008f00 -#define IVAHD_IVAHD_CLKCTRL 0x4a008f20 -#define IVAHD_SL2_CLKCTRL 0x4a008f28 - -/* CM2.L3INIT */ -#define CM_L3INIT_HSMMC1_CLKCTRL 0x4a009328 -#define CM_L3INIT_HSMMC2_CLKCTRL 0x4a009330 -#define CM_L3INIT_HSI_CLKCTRL 0x4a009338 -#define CM_L3INIT_UNIPRO1_CLKCTRL 0x4a009340 -#define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4a009358 -#define CM_L3INIT_HSUSBOTG_CLKCTRL 0x4a009360 -#define CM_L3INIT_HSUSBTLL_CLKCTRL 0x4a009368 -#define CM_L3INIT_P1500_CLKCTRL 0x4a009378 -#define CM_L3INIT_FSUSB_CLKCTRL 0x4a0093d0 -#define CM_L3INIT_USBPHY_CLKCTRL 0x4a0093e0 - -/* CM2.CAM */ -#define CM_CAM_CLKSTCTRL 0x4a009000 -#define CM_CAM_ISS_CLKCTRL 0x4a009020 -#define CM_CAM_FDIF_CLKCTRL 0x4a009028 - -/* CM2.DSS */ -#define CM_DSS_CLKSTCTRL 0x4a009100 -#define CM_DSS_DSS_CLKCTRL 0x4a009120 -#define CM_DSS_DEISS_CLKCTRL 0x4a009128 - -/* CM2.SGX */ -#define CM_SGX_CLKSTCTRL 0x4a009200 -#define CM_SGX_SGX_CLKCTRL 0x4a009220 - -/* SMX-APE */ -#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) -#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) -#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) -#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) -#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) - -#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) -#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) -#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) -#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) - -#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) -#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) -#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) - -#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) -#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) -#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) -#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) - -#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) -#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) -#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) - -#define IVA2_REQ_INFO_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x68) -#define IVA2_READ_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x70) -#define IVA2_WRITE_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x78) - -#define IVA2_REQ_INFO_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x88) -#define IVA2_READ_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x90) -#define IVA2_WRITE_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x98) - -#define IVA2_REQ_INFO_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xA8) -#define IVA2_READ_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB0) -#define IVA2_WRITE_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB8) - -/* I2C base */ -#define I2C_BASE1 (OMAP44XX_L4_PER + 0x70000) -#define I2C_BASE2 (OMAP44XX_L4_PER + 0x72000) -#define I2C_BASE3 (OMAP44XX_L4_PER + 0x60000) - -#ifdef CONFIG_LCD - extern void lcd_disable(void); - extern void lcd_panel_disable(void); -#endif - -/* Silicon revisions */ -#define OMAP4430_SILICON_ID_INVALID 0 -#define OMAP4430_ES1_0 1 -#define OMAP4430_ES2_0 2 -#define OMAP4430_ES2_1 3 - -#ifndef __ASSEMBLY__ -/*Functions for silicon revision */ -unsigned int omap_revision(void); -unsigned int cortex_a9_rev(void); - -void big_delay(unsigned int count); -#endif - -#endif diff --git a/x-loader/include/asm/arch-omap4/mem.h b/x-loader/include/asm/arch-omap4/mem.h deleted file mode 100644 index e277eca..0000000 --- a/x-loader/include/asm/arch-omap4/mem.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP44XX_MEM_H_ -#define _OMAP44XX_MEM_H_ - -#ifndef __ASSEMBLY__ - -typedef enum { - STACKED = 0, - IP_DDR = 1, - COMBO_DDR = 2, - IP_SDR = 3, -} mem_t; - -/* Memory that can be connected to GPMC */ -#define GPMC_NOR 0 -#define GPMC_NAND 1 -#define GPMC_MDOC 2 -#define GPMC_ONENAND 3 -#define MMC_NAND 4 -#define MMC_ONENAND 5 -#define GPMC_NONE 6 -#define GPMC_ONENAND_TRY 7 - -#endif - - -/* New and compatability speed defines */ -#if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II)\ - || defined(PRCM_CONFIG_5B) -# define L3_100MHZ /* Use with <= 100MHz SDRAM */ -#elif defined(PRCM_CLK_CFG2_266MHZ) || defined(PRCM_CONFIG_III)\ - || defined(PRCM_CONFIG_5A) -# define L3_133MHZ /* Use with <= 133MHz SDRAM*/ -#elif defined(PRCM_CLK_CFG2_332MHZ) || defined(PRCM_CONFIG_I) \ - || defined(PRCM_CONFIG_2) -# define L3_165MHZ /* Use with <= 165MHz SDRAM (L3=166 on 4430) */ -#endif - -/* - * GPMC settings - - * Definitions is as per the following format - * # define _GPMC_CONFIG - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of - * the same. if values are independent of the board, this definition will be - * present in this file if values are dependent on the board, then this should - * go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * STNOR - Intel Strata Flash - * SMNAND - Samsung NAND - * M_NAND - Micron Large page x16 NAND - * MPDB - H4 MPDB board - * SBNOR - Sibley NOR - * ONNAND - Samsung One NAND - * - * include/configs/file.h contains the defn - for all CS we are interested - * #define OMAP44XX_GPMC_CSx PART - * #define OMAP44XX_GPMC_CSx_SIZE Size - * #define OMAP44XX_GPMC_CSx_MAP Map - * Where: - * x - CS number - * PART - Part Name as defined above - * SIZE - how big is the mapping to be - * GPMC_SIZE_128M - 0x8 - * GPMC_SIZE_64M - 0xC - * GPMC_SIZE_32M - 0xE - * GPMC_SIZE_16M - 0xF - * MAP - Map this CS to which address(GPMC address space)- Absolute address - * >>24 before being used. - */ -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#if defined(L3_100MHZ) -# define SMNAND_GPMC_CONFIG1 0x0 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x00000A80 - -# define M_NAND_GPMC_CONFIG1 0x00001800 -# define M_NAND_GPMC_CONFIG2 0x00141400 -# define M_NAND_GPMC_CONFIG3 0x00141400 -# define M_NAND_GPMC_CONFIG4 0x0F010F01 -# define M_NAND_GPMC_CONFIG5 0x010C1414 -# define M_NAND_GPMC_CONFIG6 0x1f0f0A80 - -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x000f0f01 -# define STNOR_GPMC_CONFIG3 0x00050502 -# define STNOR_GPMC_CONFIG4 0x0C060C06 -# define STNOR_GPMC_CONFIG5 0x01131F1F -# define STNOR_GPMC_CONFIG6 0x1F0F0000 - -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001F1F00 -# define MPDB_GPMC_CONFIG3 0x00080802 -# define MPDB_GPMC_CONFIG4 0x1C091C09 -# define MPDB_GPMC_CONFIG5 0x031A1F1F -# define MPDB_GPMC_CONFIG6 0x000003C2 -#endif - -#if defined(L3_133MHZ) -# define SMNAND_GPMC_CONFIG1 0x00000800 -# define SMNAND_GPMC_CONFIG2 0x00141400 -# define SMNAND_GPMC_CONFIG3 0x00141400 -# define SMNAND_GPMC_CONFIG4 0x0F010F01 -# define SMNAND_GPMC_CONFIG5 0x010C1414 -# define SMNAND_GPMC_CONFIG6 0x1F0F0A80 -# define SMNAND_GPMC_CONFIG7 0x00000C44 - -# define M_NAND_GPMC_CONFIG1 0x00001800 /* might reuse smnand, with |= 1000 */ -# define M_NAND_GPMC_CONFIG2 0x00141400 -# define M_NAND_GPMC_CONFIG3 0x00141400 -# define M_NAND_GPMC_CONFIG4 0x0F010F01 -# define M_NAND_GPMC_CONFIG5 0x010C1414 -# define M_NAND_GPMC_CONFIG6 0x1F0F0A80 -# define M_NAND_GPMC_CONFIG7 0x00000C44 - -# define STNOR_GPMC_CONFIG1 0x1203 -# define STNOR_GPMC_CONFIG2 0x00151501 -# define STNOR_GPMC_CONFIG3 0x00060602 -# define STNOR_GPMC_CONFIG4 0x10081008 -# define STNOR_GPMC_CONFIG5 0x01131F1F -# define STNOR_GPMC_CONFIG6 0x1F0F04c4 - -# define SIBNOR_GPMC_CONFIG1 0x1200 -# define SIBNOR_GPMC_CONFIG2 0x001f1f00 -# define SIBNOR_GPMC_CONFIG3 0x00080802 -# define SIBNOR_GPMC_CONFIG4 0x1C091C09 -# define SIBNOR_GPMC_CONFIG5 0x01131F1F -# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 - -/* ES1 SDP and ES1 chip Debug FPGA */ -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001f1f01 -# define MPDB_GPMC_CONFIG3 0x00080803 -# define MPDB_GPMC_CONFIG4 0x1C091C09 -# define MPDB_GPMC_CONFIG5 0x041f1F1F -# define MPDB_GPMC_CONFIG6 0x000004C4 - -/* ES2 SDP and ES2 chip Debug FPGA */ -# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 -# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 -# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 -# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 -# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F -# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 - -# define P2_GPMC_CONFIG1 0x0 -# define P2_GPMC_CONFIG2 0x0 -# define P2_GPMC_CONFIG3 0x0 -# define P2_GPMC_CONFIG4 0x0 -# define P2_GPMC_CONFIG5 0x0 -# define P2_GPMC_CONFIG6 0x0 - -# define ONENAND_GPMC_CONFIG1 0x00001200 -# define ONENAND_GPMC_CONFIG2 0x000c0c01 -# define ONENAND_GPMC_CONFIG3 0x00030301 -# define ONENAND_GPMC_CONFIG4 0x0c040c04 -# define ONENAND_GPMC_CONFIG5 0x010C1010 -# define ONENAND_GPMC_CONFIG6 0x1F060000 - -#endif /* endif L3_133MHZ */ - -#if defined(L3_165MHZ) -# define SMNAND_GPMC_CONFIG1 0x00000800 -# define SMNAND_GPMC_CONFIG2 0x00060600 -# define SMNAND_GPMC_CONFIG3 0x00060401 -# define SMNAND_GPMC_CONFIG4 0x05010801 -# define SMNAND_GPMC_CONFIG5 0x00090B0B -# define SMNAND_GPMC_CONFIG6 0x050001C0 -# define SMNAND_GPMC_CONFIG7 0x00000C44 - -# define M_NAND_GPMC_CONFIG1 0x00001800 -# define M_NAND_GPMC_CONFIG2 0x00141400 -# define M_NAND_GPMC_CONFIG3 0x00141400 -# define M_NAND_GPMC_CONFIG4 0x0F010F01 -# define M_NAND_GPMC_CONFIG5 0x010C1414 -# define M_NAND_GPMC_CONFIG6 0x1F0F0A80 -# define M_NAND_GPMC_CONFIG7 0x00000C44 - -# define STNOR_GPMC_CONFIG1 0x3 -# define STNOR_GPMC_CONFIG2 0x00151501 -# define STNOR_GPMC_CONFIG3 0x00060602 -# define STNOR_GPMC_CONFIG4 0x11091109 -# define STNOR_GPMC_CONFIG5 0x01141F1F -# define STNOR_GPMC_CONFIG6 0x1F0F04c4 - -# define SIBNOR_GPMC_CONFIG1 0x1200 -# define SIBNOR_GPMC_CONFIG2 0x001f1f00 -# define SIBNOR_GPMC_CONFIG3 0x00080802 -# define SIBNOR_GPMC_CONFIG4 0x1C091C09 -# define SIBNOR_GPMC_CONFIG5 0x01131F1F -# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 - -# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 -# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 -# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 -# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 -# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F -# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 - -# define MPDB_GPMC_CONFIG1 0x00011000 -# define MPDB_GPMC_CONFIG2 0x001f1f01 -# define MPDB_GPMC_CONFIG3 0x00080803 -# define MPDB_GPMC_CONFIG4 0x1c0b1c0a -# define MPDB_GPMC_CONFIG5 0x041f1F1F -# define MPDB_GPMC_CONFIG6 0x1F0F04C4 - -# define LAB_ENET_GPMC_CONFIG1 0x00611000 -# define LAB_ENET_GPMC_CONFIG2 0x001F1F01 -# define LAB_ENET_GPMC_CONFIG3 0x00080803 -# define LAB_ENET_GPMC_CONFIG4 0x1D091D09 -# define LAB_ENET_GPMC_CONFIG5 0x041D1F1F -# define LAB_ENET_GPMC_CONFIG6 0x1D0904C4 - -# define P2_GPMC_CONFIG1 0x0 -# define P2_GPMC_CONFIG2 0x0 -# define P2_GPMC_CONFIG3 0x0 -# define P2_GPMC_CONFIG4 0x0 -# define P2_GPMC_CONFIG5 0x0 -# define P2_GPMC_CONFIG6 0x0 - -# define ONENAND_GPMC_CONFIG1 0x00001200 -# define ONENAND_GPMC_CONFIG2 0x000F0F01 -# define ONENAND_GPMC_CONFIG3 0x00030301 -# define ONENAND_GPMC_CONFIG4 0x0F040F04 -# define ONENAND_GPMC_CONFIG5 0x010F1010 -# define ONENAND_GPMC_CONFIG6 0x1F060000 - -#endif - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#define PISMO1_NOR 1 -#define PISMO1_NAND 2 -#define PISMO2_CS0 3 -#define PISMO2_CS1 4 -#define PISMO1_ONENAND 5 -#define DBG_MPDB 6 -#define PISMO2_NAND_CS0 7 -#define PISMO2_NAND_CS1 8 - -/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE NAND_BASE -#define PISMO2_CS0_BASE PISMO2_MAP1 -#define PISMO1_ONEN_BASE ONENAND_MAP -#define DBG_MPDB_BASE DEBUG_BASE - -#endif /* endif _OMAP44XX_MEM_H_ */ diff --git a/x-loader/include/asm/arch-omap4/mmc.h b/x-loader/include/asm/arch-omap4/mmc.h deleted file mode 100644 index 8631aae..0000000 --- a/x-loader/include/asm/arch-omap4/mmc.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_H -#define MMC_H - -#include "mmc_host_def.h" - -/* Responses */ -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK) -#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) -#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) -#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) - -/* All supported commands */ -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD7_DESELECT (INDEX(7) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE) -#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) -#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) -#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) -#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) - -#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16) -#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16) -#define MMC_DSR_DEFAULT (0x0404) -#define SD_CMD8_CHECK_PATTERN (0xAA) -#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8) - -/* Clock Configurations and Macros */ - -#define MMC_CLOCK_REFERENCE (96) -#define MMC_RELATIVE_CARD_ADDRESS (0x1234) -#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80) -#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400) -#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1) -#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u)) - -#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29) -#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29) -#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29) - -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30) -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30) -#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30) - -#define MMC_SD2_CSD_C_SIZE_LSB_MASK (0xFFFF) -#define MMC_SD2_CSD_C_SIZE_MSB_MASK (0x003F) -#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET (16) -#define MMC_CSD_C_SIZE_LSB_MASK (0x0003) -#define MMC_CSD_C_SIZE_MSB_MASK (0x03FF) -#define MMC_CSD_C_SIZE_MSB_OFFSET (2) - -#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0) -#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3) -#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0) -#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3) -#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3) - -typedef struct { - unsigned not_used:1; - unsigned crc:7; - unsigned ecc:2; - unsigned file_format:2; - unsigned tmp_write_protect:1; - unsigned perm_write_protect:1; - unsigned copy:1; - unsigned file_format_grp:1; - unsigned content_prot_app:1; - unsigned reserved_1:4; - unsigned write_bl_partial:1; - unsigned write_bl_len:4; - unsigned r2w_factor:3; - unsigned default_ecc:2; - unsigned wp_grp_enable:1; - unsigned wp_grp_size:5; - unsigned erase_grp_mult:5; - unsigned erase_grp_size:5; - unsigned c_size_mult:3; - unsigned vdd_w_curr_max:3; - unsigned vdd_w_curr_min:3; - unsigned vdd_r_curr_max:3; - unsigned vdd_r_curr_min:3; - unsigned c_size_lsb:2; - unsigned c_size_msb:10; - unsigned reserved_2:2; - unsigned dsr_imp:1; - unsigned read_blk_misalign:1; - unsigned write_blk_misalign:1; - unsigned read_bl_partial:1; - unsigned read_bl_len:4; - unsigned ccc:12; - unsigned tran_speed:8; - unsigned nsac:8; - unsigned taac:8; - unsigned reserved_3:2; - unsigned spec_vers:4; - unsigned csd_structure:2; -} mmc_csd_reg_t; - -/* csd for sd2.0 */ -typedef struct { - unsigned not_used:1; - unsigned crc:7; - unsigned reserved_1:2; - unsigned file_format:2; - unsigned tmp_write_protect:1; - unsigned perm_write_protect:1; - unsigned copy:1; - unsigned file_format_grp:1; - unsigned reserved_2:5; - unsigned write_bl_partial:1; - unsigned write_bl_len:4; - unsigned r2w_factor:3; - unsigned reserved_3:2; - unsigned wp_grp_enable:1; - unsigned wp_grp_size:7; - unsigned sector_size:7; - unsigned erase_blk_len:1; - unsigned reserved_4:1; - unsigned c_size_lsb:16; - unsigned c_size_msb:6; - unsigned reserved_5:6; - unsigned dsr_imp:1; - unsigned read_blk_misalign:1; - unsigned write_blk_misalign:1; - unsigned read_bl_partial:1; - unsigned read_bl_len:4; - unsigned ccc:12; - unsigned tran_speed:8; - unsigned nsac:8; - unsigned taac:8; - unsigned reserved_6:6; - unsigned csd_structure:2; -} mmc_sd2_csd_reg_t; - -/* extended csd - 512 bytes long */ -typedef struct { - unsigned char reserved_1[181]; - unsigned char erasedmemorycontent; - unsigned char reserved_2; - unsigned char buswidthmode; - unsigned char reserved_3; - unsigned char highspeedinterfacetiming; - unsigned char reserved_4; - unsigned char powerclass; - unsigned char reserved_5; - unsigned char commandsetrevision; - unsigned char reserved_6; - unsigned char commandset; - unsigned char extendedcsdrevision; - unsigned char reserved_7; - unsigned char csdstructureversion; - unsigned char reserved_8; - unsigned char cardtype; - unsigned char reserved_9[3]; - unsigned char powerclass_52mhz_1_95v; - unsigned char powerclass_26mhz_1_95v; - unsigned char powerclass_52mhz_3_6v; - unsigned char powerclass_26mhz_3_6v; - unsigned char reserved_10; - unsigned char minreadperf_4b_26mhz; - unsigned char minwriteperf_4b_26mhz; - unsigned char minreadperf_8b_26mhz_4b_52mhz; - unsigned char minwriteperf_8b_26mhz_4b_52mhz; - unsigned char minreadperf_8b_52mhz; - unsigned char minwriteperf_8b_52mhz; - unsigned char reserved_11; - unsigned int sectorcount; - unsigned char reserved_12[288]; - unsigned char supportedcommandsets; - unsigned char reserved_13[7]; -} mmc_extended_csd_reg_t; - -/* mmc sd responce */ -typedef struct { - unsigned int ocr; -} mmc_resp_r3; - -typedef struct { - unsigned short cardstatus; - unsigned short newpublishedrca; -} mmc_resp_r6; - -extern mmc_card_data mmc_dev; - -unsigned char mmc_lowlevel_init(void); -unsigned char mmc_send_command(unsigned int cmd, unsigned int arg, - unsigned int *response); -unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd); -unsigned char mmc_set_opendrain(unsigned char state); -unsigned char mmc_read_data(unsigned int *output_buf); - -#endif /* MMC_H */ diff --git a/x-loader/include/asm/arch-omap4/mmc_host_def.h b/x-loader/include/asm/arch-omap4/mmc_host_def.h deleted file mode 100644 index 0abc841..0000000 --- a/x-loader/include/asm/arch-omap4/mmc_host_def.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_HOST_DEFINITIONS_H -#define MMC_HOST_DEFINITIONS_H - -#define OMAP_HSMMC1_BASE 0x4809C100 -#define OMAP_HSMMC2_BASE 0x480B4100 - -/* - * OMAP HSMMC register definitions - */ - -#define OMAP_HSMMC_SYSCONFIG (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x010)) -#define OMAP_HSMMC_SYSSTATUS (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x014)) -#define OMAP_HSMMC_CON (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x02C)) -#define OMAP_HSMMC_BLK (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x104)) -#define OMAP_HSMMC_ARG (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x108)) -#define OMAP_HSMMC_CMD (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x10C)) -#define OMAP_HSMMC_RSP10 (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x110)) -#define OMAP_HSMMC_RSP32 (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x114)) -#define OMAP_HSMMC_RSP54 (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x118)) -#define OMAP_HSMMC_RSP76 (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x11C)) -#define OMAP_HSMMC_DATA (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x120)) -#define OMAP_HSMMC_PSTATE (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x124)) -#define OMAP_HSMMC_HCTL (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x128)) -#define OMAP_HSMMC_SYSCTL (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x12C)) -#define OMAP_HSMMC_STAT (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x130)) -#define OMAP_HSMMC_IE (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x134)) -#define OMAP_HSMMC_CAPA (*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x140)) - -/* T2 Register definitions */ -#define CONTROL_PBIAS_LITE (*(volatile unsigned int *) 0x4A100600) -#define CONTROL_CONF_MMC1 (*(volatile unsigned int *) 0x4A100628) - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define DATI_CMDDIS (0x1 << 1) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE (512) -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -typedef struct { - unsigned int card_type; - unsigned int version; - unsigned int mode; - unsigned int size; - unsigned int RCA; -} mmc_card_data; - -#define mmc_reg_out(addr, mask, val) \ - (addr) = (((addr)) & (~(mask)) ) | ( (val) & (mask)); - -#endif /* MMC_HOST_DEFINITIONS_H */ diff --git a/x-loader/include/asm/arch-omap4/mux.h b/x-loader/include/asm/arch-omap4/mux.h deleted file mode 100644 index d6505bf..0000000 --- a/x-loader/include/asm/arch-omap4/mux.h +++ /dev/null @@ -1,392 +0,0 @@ -/* Copyright 2009 - * Texas Instruments, - * Syed Rafiuddin - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP4430_MUX_H_ -#define _OMAP4430_MUX_H_ - -/* - * OFF_PD - Off mode pull type down - * OFF_PU - Off mode pull type up - * OFF_OUT_PTD - Off Mode Mux low for OUT - * OFF_OUT_PTU - Off Mode Mux high for OUT - * OFF_IN - Off Mode Mux set to IN - * OFF_OUT - Off Mode Mux set to OUT - * OFF_EN - Off Mode Mux Enable - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - */ -#ifdef CONFIG_OFF_PADCONF -#define OFF_PD (1 << 12) -#define OFF_PU (3 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (2 << 10) -#define OFF_IN (1 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) -#else -#define OFF_PD (0 << 12) -#define OFF_PU (0 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (0 << 10) -#define OFF_IN (0 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (0 << 9) -#endif - -#define IEN (1 << 8) -#define IDIS (0 << 8) -#define PTU (3 << 3) -#define PTD (1 << 3) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -#ifdef CONFIG_OFF_PADCONF -#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) -#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) -#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) -#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) -#else -#define OFF_IN_PD 0 -#define OFF_IN_PU 0 -#define OFF_OUT_PD 0 -#define OFF_OUT_PU 0 -#endif /* #ifdef CONFIG_OFF_PADCONF */ - -/* - * To get the actual address the offset has to added - * with OMAP44XX_CTRL_BASE to get the actual address - */ - -/* OMAP4 SPECIFIC PADCONF REGISTERS */ - -#define CONTROL_PADCONF_CORE_REVISION 0x0000 -#define CONTROL_PADCONF_CORE_HWINFO 0x0004 -#define CONTROL_PADCONF_CORE_SYSCONFIG 0x0010 -#define CONTROL_PADCONF_GPMC_AD0 0x0040 -#define CONTROL_PADCONF_GPMC_AD1 0x0042 -#define CONTROL_PADCONF_GPMC_AD2 0x0044 -#define CONTROL_PADCONF_GPMC_AD3 0x0046 -#define CONTROL_PADCONF_GPMC_AD4 0x0048 -#define CONTROL_PADCONF_GPMC_AD5 0x004A -#define CONTROL_PADCONF_GPMC_AD6 0x004C -#define CONTROL_PADCONF_GPMC_AD7 0x004E -#define CONTROL_PADCONF_GPMC_AD8 0x0050 -#define CONTROL_PADCONF_GPMC_AD9 0x0052 -#define CONTROL_PADCONF_GPMC_AD10 0x0054 -#define CONTROL_PADCONF_GPMC_AD11 0x0056 -#define CONTROL_PADCONF_GPMC_AD12 0x0058 -#define CONTROL_PADCONF_GPMC_AD13 0x005A -#define CONTROL_PADCONF_GPMC_AD14 0x005C -#define CONTROL_PADCONF_GPMC_AD15 0x005E -#define CONTROL_PADCONF_GPMC_A16 0x0060 -#define CONTROL_PADCONF_GPMC_A17 0x0062 -#define CONTROL_PADCONF_GPMC_A18 0x0064 -#define CONTROL_PADCONF_GPMC_A19 0x0066 -#define CONTROL_PADCONF_GPMC_A20 0x0068 -#define CONTROL_PADCONF_GPMC_A21 0x006A -#define CONTROL_PADCONF_GPMC_A22 0x006C -#define CONTROL_PADCONF_GPMC_A23 0x006E -#define CONTROL_PADCONF_GPMC_A24 0x0070 -#define CONTROL_PADCONF_GPMC_A25 0x0072 -#define CONTROL_PADCONF_GPMC_NCS0 0x0074 -#define CONTROL_PADCONF_GPMC_NCS1 0x0076 -#define CONTROL_PADCONF_GPMC_NCS2 0x0078 -#define CONTROL_PADCONF_GPMC_NCS3 0x007A -#define CONTROL_PADCONF_GPMC_NWP 0x007C -#define CONTROL_PADCONF_GPMC_CLK 0x007E -#define CONTROL_PADCONF_GPMC_NADV_ALE 0x0080 -#define CONTROL_PADCONF_GPMC_NOE 0x0082 -#define CONTROL_PADCONF_GPMC_NWE 0x0084 -#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x0086 -#define CONTROL_PADCONF_GPMC_NBE1 0x0088 -#define CONTROL_PADCONF_GPMC_WAIT0 0x008A -#define CONTROL_PADCONF_GPMC_WAIT1 0x008C -#define CONTROL_PADCONF_C2C_DATA11 0x008E -#define CONTROL_PADCONF_C2C_DATA12 0x0090 -#define CONTROL_PADCONF_C2C_DATA13 0x0092 -#define CONTROL_PADCONF_C2C_DATA14 0x0094 -#define CONTROL_PADCONF_C2C_DATA15 0x0096 -#define CONTROL_PADCONF_HDMI_HPD 0x0098 -#define CONTROL_PADCONF_HDMI_CEC 0x009A -#define CONTROL_PADCONF_HDMI_DDC_SCL 0x009C -#define CONTROL_PADCONF_HDMI_DDC_SDA 0x009E -#define CONTROL_PADCONF_CSI21_DX0 0x00A0 -#define CONTROL_PADCONF_CSI21_DY0 0x00A2 -#define CONTROL_PADCONF_CSI21_DX1 0x00A4 -#define CONTROL_PADCONF_CSI21_DY1 0x00A6 -#define CONTROL_PADCONF_CSI21_DX2 0x00A8 -#define CONTROL_PADCONF_CSI21_DY2 0x00AA -#define CONTROL_PADCONF_CSI21_DX3 0x00AC -#define CONTROL_PADCONF_CSI21_DY3 0x00AE -#define CONTROL_PADCONF_CSI21_DX4 0x00B0 -#define CONTROL_PADCONF_CSI21_DY4 0x00B2 -#define CONTROL_PADCONF_CSI22_DX0 0x00B4 -#define CONTROL_PADCONF_CSI22_DY0 0x00B6 -#define CONTROL_PADCONF_CSI22_DX1 0x00B8 -#define CONTROL_PADCONF_CSI22_DY1 0x00BA -#define CONTROL_PADCONF_CAM_SHUTTER 0x00BC -#define CONTROL_PADCONF_CAM_STROBE 0x00BE -#define CONTROL_PADCONF_CAM_GLOBALRESET 0x00C0 -#define CONTROL_PADCONF_USBB1_ULPITLL_CLK 0x00C2 -#define CONTROL_PADCONF_USBB1_ULPITLL_STP 0x00C4 -#define CONTROL_PADCONF_USBB1_ULPITLL_DIR 0x00C6 -#define CONTROL_PADCONF_USBB1_ULPITLL_NXT 0x00C8 -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT0 0x00CA -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT1 0x00CC -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT2 0x00CE -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT3 0x00D0 -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT4 0x00D2 -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT5 0x00D4 -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT6 0x00D6 -#define CONTROL_PADCONF_USBB1_ULPITLL_DAT7 0x00D8 -#define CONTROL_PADCONF_USBB1_HSIC_DATA 0x00DA -#define CONTROL_PADCONF_USBB1_HSIC_STROBE 0x00DC -#define CONTROL_PADCONF_USBC1_ICUSB_DP 0x00DE -#define CONTROL_PADCONF_USBC1_ICUSB_DM 0x00E0 -#define CONTROL_PADCONF_SDMMC1_CLK 0x00E2 -#define CONTROL_PADCONF_SDMMC1_CMD 0x00E4 -#define CONTROL_PADCONF_SDMMC1_DAT0 0x00E6 -#define CONTROL_PADCONF_SDMMC1_DAT1 0x00E8 -#define CONTROL_PADCONF_SDMMC1_DAT2 0x00EA -#define CONTROL_PADCONF_SDMMC1_DAT3 0x00EC -#define CONTROL_PADCONF_SDMMC1_DAT4 0x00EE -#define CONTROL_PADCONF_SDMMC1_DAT5 0x00F0 -#define CONTROL_PADCONF_SDMMC1_DAT6 0x00F2 -#define CONTROL_PADCONF_SDMMC1_DAT7 0x00F4 -#define CONTROL_PADCONF_ABE_MCBSP2_CLKX 0x00F6 -#define CONTROL_PADCONF_ABE_MCBSP2_DR 0x00F8 -#define CONTROL_PADCONF_ABE_MCBSP2_DX 0x00FA -#define CONTROL_PADCONF_ABE_MCBSP2_FSX 0x00FC -#define CONTROL_PADCONF_ABE_MCBSP1_CLKX 0x00FE -#define CONTROL_PADCONF_ABE_MCBSP1_DR 0x0100 -#define CONTROL_PADCONF_ABE_MCBSP1_DX 0x0102 -#define CONTROL_PADCONF_ABE_MCBSP1_FSX 0x0104 -#define CONTROL_PADCONF_ABE_PDM_UL_DATA 0x0106 -#define CONTROL_PADCONF_ABE_PDM_DL_DATA 0x0108 -#define CONTROL_PADCONF_ABE_PDM_FRAME 0x010A -#define CONTROL_PADCONF_ABE_PDM_LB_CLK 0x010C -#define CONTROL_PADCONF_ABE_CLKS 0x010E -#define CONTROL_PADCONF_ABE_DMIC_CLK1 0x0110 -#define CONTROL_PADCONF_ABE_DMIC_DIN1 0x0112 -#define CONTROL_PADCONF_ABE_DMIC_DIN2 0x0114 -#define CONTROL_PADCONF_ABE_DMIC_DIN3 0x0116 -#define CONTROL_PADCONF_UART2_CTS 0x0118 -#define CONTROL_PADCONF_UART2_RTS 0x011A -#define CONTROL_PADCONF_UART2_RX 0x011C -#define CONTROL_PADCONF_UART2_TX 0x011E -#define CONTROL_PADCONF_HDQ_SIO 0x0120 -#define CONTROL_PADCONF_I2C1_SCL 0x0122 -#define CONTROL_PADCONF_I2C1_SDA 0x0124 -#define CONTROL_PADCONF_I2C2_SCL 0x0126 -#define CONTROL_PADCONF_I2C2_SDA 0x0128 -#define CONTROL_PADCONF_I2C3_SCL 0x012A -#define CONTROL_PADCONF_I2C3_SDA 0x012C -#define CONTROL_PADCONF_I2C4_SCL 0x012E -#define CONTROL_PADCONF_I2C4_SDA 0x0130 -#define CONTROL_PADCONF_MCSPI1_CLK 0x0132 -#define CONTROL_PADCONF_MCSPI1_SOMI 0x0134 -#define CONTROL_PADCONF_MCSPI1_SIMO 0x0136 -#define CONTROL_PADCONF_MCSPI1_CS0 0x0138 -#define CONTROL_PADCONF_MCSPI1_CS1 0x013A -#define CONTROL_PADCONF_MCSPI1_CS2 0x013C -#define CONTROL_PADCONF_MCSPI1_CS3 0x013E -#define CONTROL_PADCONF_UART3_CTS_RCTX 0x0140 -#define CONTROL_PADCONF_UART3_RTS_SD 0x0142 -#define CONTROL_PADCONF_UART3_RX_IRRX 0x0144 -#define CONTROL_PADCONF_UART3_TX_IRTX 0x0146 -#define CONTROL_PADCONF_SDMMC5_CLK 0x0148 -#define CONTROL_PADCONF_SDMMC5_CMD 0x014A -#define CONTROL_PADCONF_SDMMC5_DAT0 0x014C -#define CONTROL_PADCONF_SDMMC5_DAT1 0x014E -#define CONTROL_PADCONF_SDMMC5_DAT2 0x0150 -#define CONTROL_PADCONF_SDMMC5_DAT3 0x0152 -#define CONTROL_PADCONF_MCSPI4_CLK 0x0154 -#define CONTROL_PADCONF_MCSPI4_SIMO 0x0156 -#define CONTROL_PADCONF_MCSPI4_SOMI 0x0158 -#define CONTROL_PADCONF_MCSPI4_CS0 0x015A -#define CONTROL_PADCONF_UART4_RX 0x015C -#define CONTROL_PADCONF_UART4_TX 0x015E -#define CONTROL_PADCONF_USBB2_ULPITLL_CLK 0x0160 -#define CONTROL_PADCONF_USBB2_ULPITLL_STP 0x0162 -#define CONTROL_PADCONF_USBB2_ULPITLL_DIR 0x0164 -#define CONTROL_PADCONF_USBB2_ULPITLL_NXT 0x0166 -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT0 0x0168 -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT1 0x016A -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT2 0x016C -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT3 0x016E -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT4 0x0170 -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT5 0x0172 -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT6 0x0174 -#define CONTROL_PADCONF_USBB2_ULPITLL_DAT7 0x0176 -#define CONTROL_PADCONF_USBB2_HSIC_DATA 0x0178 -#define CONTROL_PADCONF_USBB2_HSIC_STROBE 0x017A -#define CONTROL_PADCONF_UNIPRO_TX0 0x017C -#define CONTROL_PADCONF_UNIPRO_TY0 0x017E -#define CONTROL_PADCONF_UNIPRO_TX1 0x0180 -#define CONTROL_PADCONF_UNIPRO_TY1 0x0182 -#define CONTROL_PADCONF_UNIPRO_TX2 0x0184 -#define CONTROL_PADCONF_UNIPRO_TY2 0x0186 -#define CONTROL_PADCONF_UNIPRO_RX0 0x0188 -#define CONTROL_PADCONF_UNIPRO_RY0 0x018A -#define CONTROL_PADCONF_UNIPRO_RX1 0x018C -#define CONTROL_PADCONF_UNIPRO_RY1 0x018E -#define CONTROL_PADCONF_UNIPRO_RX2 0x0190 -#define CONTROL_PADCONF_UNIPRO_RY2 0x0192 -#define CONTROL_PADCONF_USBA0_OTG_CE 0x0194 -#define CONTROL_PADCONF_USBA0_OTG_DP 0x0196 -#define CONTROL_PADCONF_USBA0_OTG_DM 0x0198 -#define CONTROL_PADCONF_FREF_CLK1_OUT 0x019A -#define CONTROL_PADCONF_FREF_CLK2_OUT 0x019C -#define CONTROL_PADCONF_SYS_NIRQ1 0x019E -#define CONTROL_PADCONF_SYS_NIRQ2 0x01A0 -#define CONTROL_PADCONF_SYS_BOOT0 0x01A2 -#define CONTROL_PADCONF_SYS_BOOT1 0x01A4 -#define CONTROL_PADCONF_SYS_BOOT2 0x01A6 -#define CONTROL_PADCONF_SYS_BOOT3 0x01A8 -#define CONTROL_PADCONF_SYS_BOOT4 0x01AA -#define CONTROL_PADCONF_SYS_BOOT5 0x01AC -#define CONTROL_PADCONF_DPM_EMU0 0x01AE -#define CONTROL_PADCONF_DPM_EMU1 0x01B0 -#define CONTROL_PADCONF_DPM_EMU2 0x01B2 -#define CONTROL_PADCONF_DPM_EMU3 0x01B4 -#define CONTROL_PADCONF_DPM_EMU4 0x01B6 -#define CONTROL_PADCONF_DPM_EMU5 0x01B8 -#define CONTROL_PADCONF_DPM_EMU6 0x01BA -#define CONTROL_PADCONF_DPM_EMU7 0x01BC -#define CONTROL_PADCONF_DPM_EMU8 0x01BE -#define CONTROL_PADCONF_DPM_EMU9 0x01C0 -#define CONTROL_PADCONF_DPM_EMU10 0x01C2 -#define CONTROL_PADCONF_DPM_EMU11 0x01C4 -#define CONTROL_PADCONF_DPM_EMU12 0x01C6 -#define CONTROL_PADCONF_DPM_EMU13 0x01C8 -#define CONTROL_PADCONF_DPM_EMU14 0x01CA -#define CONTROL_PADCONF_DPM_EMU15 0x01CC -#define CONTROL_PADCONF_DPM_EMU16 0x01CE -#define CONTROL_PADCONF_DPM_EMU17 0x01D0 -#define CONTROL_PADCONF_DPM_EMU18 0x01D2 -#define CONTROL_PADCONF_DPM_EMU19 0x01D4 -#define CONTROL_PADCONF_WAKEUPEVENT_0 0x01D8 -#define CONTROL_PADCONF_WAKEUPEVENT_1 0x01DC -#define CONTROL_PADCONF_WAKEUPEVENT_2 0x01E0 -#define CONTROL_PADCONF_WAKEUPEVENT_3 0x01E4 -#define CONTROL_PADCONF_WAKEUPEVENT_4 0x01E8 -#define CONTROL_PADCONF_WAKEUPEVENT_5 0x01EC -#define CONTROL_PADCONF_WAKEUPEVENT_6 0x01F0 - -#define CONTROL_PADCONF_GLOBAL 0x05A2 -#define CONTROL_PADCONF_MODE 0x05A4 -#define CONTROL_SMART1IO_PADCONF_0 0x05A8 -#define CONTROL_SMART1IO_PADCONF_1 0x05AC -#define CONTROL_SMART2IO_PADCONF_0 0x05B0 -#define CONTROL_SMART2IO_PADCONF_1 0x05B4 -#define CONTROL_SMART3IO_PADCONF_0 0x05B8 -#define CONTROL_SMART3IO_PADCONF_1 0x05BC -#define CONTROL_SMART3IO_PADCONF_2 0x05C0 -#define CONTROL_USBB_HSIC 0x05C4 -#define CONTROL_SLIMBUS 0x05C8 -#define CONTROL_PBIASLITE 0x0600 -#define CONTROL_I2C_0 0x0604 -#define CONTROL_CAMERA_RX 0x0608 -#define CONTROL_AVDAC 0x060C -#define CONTROL_HDMI_TX_PHY 0x0610 -#define CONTROL_MMC2 0x0614 -#define CONTROL_DSIPHY 0x0618 -#define CONTROL_MCBSPLP 0x061C -#define CONTROL_USB2PHYCORE 0x0620 -#define CONTROL_I2C_1 0x0624 -#define CONTROL_MMC1 0x0628 -#define CONTROL_HSI 0x062C -#define CONTROL_USB 0x0630 -#define CONTROL_HDQ 0x0634 -#define CONTROL_LPDDR2IO1_0 0x0638 -#define CONTROL_LPDDR2IO1_1 0x063C -#define CONTROL_LPDDR2IO1_2 0x0640 -#define CONTROL_LPDDR2IO1_3 0x0644 -#define CONTROL_LPDDR2IO2_0 0x0648 -#define CONTROL_LPDDR2IO2_1 0x064C -#define CONTROL_LPDDR2IO2_2 0x0650 -#define CONTROL_LPDDR2IO2_3 0x0654 -#define CONTROL_BUS_HOLD 0x0658 -#define CONTROL_C2C 0x065C -#define CONTROL_CORE_CONTROL_SPARE_RW 0x0660 -#define CONTROL_CORE_CONTROL_SPARE_R 0x0664 -#define CONTROL_CORE_CONTROL_SPARE_R_C0 0x0668 -#define CONTROL_EFUSE_1 0x0700 -#define CONTROL_EFUSE_2 0x0704 -#define CONTROL_EFUSE_3 0x0708 -#define CONTROL_EFUSE_4 0x070C - -#define CONTROL_PADCONF_WKUP_REVISION 0x0000 -#define CONTROL_PADCONF_WKUP_HWINFO 0x0004 -#define CONTROL_PADCONF_WKUP_SYSCONFIG 0x0010 -#define CONTROL_WKUP_PAD0_SIM_IO 0x0040 -#define CONTROL_WKUP_PAD1_SIM_CLK 0x0042 -#define CONTROL_WKUP_PAD0_SIM_RESET 0x0044 -#define CONTROL_WKUP_PAD1_SIM_CD 0x0046 -#define CONTROL_WKUP_PAD0_SIM_PWRCTRL 0x0048 -#define CONTROL_WKUP_PAD1_SR_SCL 0x004A -#define CONTROL_WKUP_PAD0_SR_SDA 0x004C -#define CONTROL_WKUP_PAD1_FREF_XTAL_IN 0x004E -#define CONTROL_WKUP_PAD0_FREF_SLICER_IN 0x0050 -#define CONTROL_WKUP_PAD1_FREF_CLK_IOREQ 0x0052 -#define CONTROL_WKUP_PAD0_FREF_CLK0_OUT 0x0054 -#define CONTROL_WKUP_PAD1_FREF_CLK3_REQ 0x0056 -#define CONTROL_WKUP_PAD0_FREF_CLK3_OUT 0x0058 -#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x005A -#define CONTROL_WKUP_PAD0_FREF_CLK4_OUT 0x005C -#define CONTROL_WKUP_PAD1_SYS_32K 0x005E -#define CONTROL_WKUP_PAD0_SYS_NRESPWRON 0x0060 -#define CONTROL_WKUP_PAD1_SYS_NRESWARM 0x0062 -#define CONTROL_WKUP_PAD0_SYS_PWR_REQ 0x0064 -#define CONTROL_WKUP_PAD1_SYS_PWRON_RESET 0x0066 -#define CONTROL_WKUP_PAD0_SYS_BOOT6 0x0068 -#define CONTROL_WKUP_PAD1_SYS_BOOT7 0x006A -#define CONTROL_WKUP_PAD0_JTAG_NTRST 0x006C -#define CONTROL_WKUP_PAD1_JTAG_TCK 0x006D -#define CONTROL_WKUP_PAD0_JTAG_RTCK 0x0070 -#define CONTROL_WKUP_PAD1_JTAG_TMS_TMSC 0x0072 -#define CONTROL_WKUP_PAD0_JTAG_TDI 0x0074 -#define CONTROL_WKUP_PAD1_JTAG_TDO 0x0076 -#define CONTROL_PADCONF_WAKEUPEVENT_0 0x007C -#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 -#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 -#define CONTROL_PADCONF_MODE 0x05A8 -#define CONTROL_XTAL_OSCILLATOR 0x05AC -#define CONTROL_CONTROL_I2C_2 0x0604 -#define CONTROL_CONTROL_JTAG 0x0608 -#define CONTROL_CONTROL_SYS 0x060C -#define CONTROL_WKUP_CONTROL_SPARE_RW 0x0614 -#define CONTROL_WKUP_CONTROL_SPARE_R 0x0618 -#define CONTROL_WKUP_CONTROL_SPARE_R_C0 0x061C - -#endif diff --git a/x-loader/include/asm/arch-omap4/omap4430.h b/x-loader/include/asm/arch-omap4/omap4430.h deleted file mode 100644 index 2f83621..0000000 --- a/x-loader/include/asm/arch-omap4/omap4430.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, - * Richard Woodruff - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP4430_SYS_H_ -#define _OMAP4430_SYS_H_ - -#include - -/* - * 4430 specific Section - */ - -/* Stuff on L3 Interconnect */ -#define SMX_APE_BASE 0x68000000 - -/* L3 Firewall */ -#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048) -#define A_READPERM0 (SMX_APE_BASE + 0x05050) -#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058) - -/* GPMC */ -#define OMAP44XX_GPMC_BASE (0x50000000) - -/* DMM */ -#define OMAP44XX_DMM_BASE 0x4E000000 - -/* SMS */ -#define OMAP44XX_SMS_BASE 0x6C000000 - -/* SDRC */ -#define OMAP44XX_SDRC_BASE 0x6D000000 - - -/* - * L4 Peripherals - L4 Wakeup and L4 Core now - */ -#define OMAP44XX_CORE_L4_IO_BASE 0x4A000000 - -#define OMAP44XX_WAKEUP_L4_IO_BASE 0x4A300000 - -#define OMAP44XX_L4_PER 0x48000000 - -#define OMAP44XX_L4_IO_BASE OMAP44XX_CORE_L4_IO_BASE - -/* CONTROL */ -//#define OMAP44XX_CTRL_BASE (OMAP44XX_L4_IO_BASE+0x2000) -#define OMAP44XX_CTRL_BASE 0x4a100000 - -/* TAP information dont know for 3430*/ -#define OMAP44XX_TAP_BASE (0x49000000) /*giving some junk for virtio */ - -/* UART */ -#define OMAP44XX_UART1 (OMAP44XX_L4_PER+0x6a000) -#define OMAP44XX_UART2 (OMAP44XX_L4_PER+0x6c000) -#define OMAP44XX_UART3 (OMAP44XX_L4_PER+0x20000) - -/* General Purpose Timers */ -#define OMAP44XX_GPT1 0x48318000 -#define OMAP44XX_GPT2 0x48032000 -#define OMAP44XX_GPT3 0x48034000 -#define OMAP44XX_GPT4 0x48036000 -#define OMAP44XX_GPT5 0x40138000 -#define OMAP44XX_GPT6 0x4013A000 -#define OMAP44XX_GPT7 0x4013C000 -#define OMAP44XX_GPT8 0x4013E000 -#define OMAP44XX_GPT9 0x48040000 -#define OMAP44XX_GPT10 0x48086000 -#define OMAP44XX_GPT11 0x48088000 -#define OMAP44XX_GPT12 0x48304000 - -/* WatchDog Timers (1 secure, 3 GP) */ -#define WD1_BASE (0x4A322000) -#define WD2_BASE (0x4A314000) -#define WD3_BASE (0x40130000) - -/* 32KTIMER */ -#define SYNC_32KTIMER_BASE (0x48320000) -#define S32K_CR (SYNC_32KTIMER_BASE+0x10) - -/* - * SDP4430 specific Section - */ - -/* - * The 443x's chip selects are programmable. The mask ROM - * does configure CS0 to 0x08000000 before dispatch. So, if - * you want your code to live below that address, you have to - * be prepared to jump though hoops, to reset the base address. - * Same as in SDP4430 - */ -#ifdef CONFIG_OMAP44XX -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_OFFSET0 0x40000000 -#define SRAM_OFFSET1 0x00300000 -#define SRAM_OFFSET2 0x0000D000 -#define SRAM_OFFSET3 0x00000800 -#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2|SRAM_OFFSET3) -#define LOW_LEVEL_SRAM_STACK 0x4030DFFC -#endif - -#if defined(CONFIG_4430SDP) -/* FPGA on Debug board.*/ -# define ETH_CONTROL_REG (DEBUG_BASE+0x30b) -# define LAN_RESET_REGISTER (DEBUG_BASE+0x1c) - -# define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60) -# define LED_REGISTER (DEBUG_BASE+0x40) -# define FPGA_REV_REGISTER (DEBUG_BASE+0x10) -# define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800) -# define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900) -# define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00) -# define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00) -# define ENHANCED_UI_EE_NAME "750-2075" -#endif - -#endif /* _OMAP4430_SYS_H_ */ diff --git a/x-loader/include/asm/arch-omap4/rev.h b/x-loader/include/asm/arch-omap4/rev.h deleted file mode 100644 index 18498bb..0000000 --- a/x-loader/include/asm/arch-omap4/rev.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, - * - * Richard Woodruff - * Syed Mohammed Khasim - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP44XX_REV_H_ -#define _OMAP44XX_REV_H_ - -#define CDB_DDR_COMBO /* combo part on cpu daughter card */ -#define CDB_DDR_IPDB /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_4430 0x4430 - -#define CPU_4430_ES1 1 - -#endif diff --git a/x-loader/include/asm/arch-omap4/sizes.h b/x-loader/include/asm/arch-omap4/sizes.h deleted file mode 100644 index f4e57f5..0000000 --- a/x-loader/include/asm/arch-omap4/sizes.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_31M 0x01F00000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif /* __sizes_h */ diff --git a/x-loader/include/asm/arch-omap4/sys_info.h b/x-loader/include/asm/arch-omap4/sys_info.h deleted file mode 100644 index bd90397..0000000 --- a/x-loader/include/asm/arch-omap4/sys_info.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _OMAP44XX_SYS_INFO_H_ -#define _OMAP44XX_SYS_INFO_H_ - -#define XDR_POP 5 /* package on package part */ -#define SDR_DISCRETE 4 /* 128M memory SDR module*/ -#define DDR_STACKED 3 /* stacked part on 2422 */ -#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ -#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ - -#define DDR_100 100 /* type found on most mem d-boards */ -#define DDR_111 111 /* some combo parts */ -#define DDR_133 133 /* most combo, some mem d-boards */ -#define DDR_165 165 /* future parts */ - -#define CPU_4430 0x4430 - -/* 343x real hardware: - * ES1 = rev 0 - */ - -/* 343x code defines: - * ES1 = 0+1 = 1 - * ES1 = 1+1 = 1 - */ -#define CPU_4430_ES1 1 - -/* Currently Virtio models this one */ -#define CPU_4430_CHIPID 0x0B68A000 - -#define GPMC_MUXED 1 -#define GPMC_NONMUXED 0 - -#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ -#define TYPE_NOR 0x000 -#define TYPE_ONENAND 0x800 - -#define WIDTH_8BIT 0x0000 -#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ - -#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ -#define I2C_TRITON2 0x4B /* addres of power group */ - -#define BOOT_FAST_XIP 0x1f - -/* SDP definitions according to FPGA Rev. Is this OK?? */ -#define SDP_4430_VIRTIO 0x1 -#define SDP_4430_V1 0x2 - -#define BOARD_4430_LABRADOR 0x80 -#define BOARD_4430_LABRADOR_V1 0x1 - -#endif diff --git a/x-loader/include/asm/arch-omap4/sys_proto.h b/x-loader/include/asm/arch-omap4/sys_proto.h deleted file mode 100644 index eda9c5e..0000000 --- a/x-loader/include/asm/arch-omap4/sys_proto.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments, - * Richard Woodruff - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _OMAP44XX_SYS_PROTO_H_ -#define _OMAP44XX_SYS_PROTO_H_ - -void prcm_init(void); -void per_clocks_enable(void); -void configure_core_dpll_no_lock(void); -void lock_core_dpll(void); -void lock_core_dpll_shadow(void); - -void memif_init(void); -void sdrc_init(void); -void do_sdrc_init(u32, u32); -void gpmc_init(void); - -void ether_init(void); -void watchdog_init(void); -void set_muxconf_regs(void); - -u32 get_cpu_type(void); -u32 get_cpu_rev(void); -u32 get_mem_type(void); -u32 get_sysboot_value(void); -u32 get_gpmc0_base(void); -u32 is_gpmc_muxed(void); -u32 get_gpmc0_type(void); -u32 get_gpmc0_width(void); -u32 get_board_type(void); -void display_board_info(u32); -void update_mux(u32, u32); -u32 get_sdr_cs_size(u32 offset); -u32 running_in_sdram(void); -u32 running_in_sram(void); -u32 running_in_flash(void); -u32 running_from_internal_boot(void); -u32 get_device_type(void); - -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value); -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); -void sdelay(unsigned long loops); - -#endif diff --git a/x-loader/include/asm/atomic.h b/x-loader/include/asm/atomic.h deleted file mode 100644 index ba9e4b7..0000000 --- a/x-loader/include/asm/atomic.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * linux/include/asm-arm/atomic.h - * - * Copyright (c) 1996 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 27-06-1996 RMK Created - * 13-04-1997 RMK Made functions atomic! - * 07-12-1997 RMK Upgraded for v2.1. - * 26-08-1998 PJB Added #ifdef __KERNEL__ - */ -#ifndef __ASM_ARM_ATOMIC_H -#define __ASM_ARM_ATOMIC_H - -#include - -#ifdef CONFIG_SMP -#error SMP not supported -#endif - -typedef struct { volatile int counter; } atomic_t; - -#define ATOMIC_INIT(i) { (i) } - -#ifdef __KERNEL__ -#include - -#define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) - -static inline void atomic_add(int i, volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter += i; - local_irq_restore(flags); -} - -static inline void atomic_sub(int i, volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter -= i; - local_irq_restore(flags); -} - -static inline void atomic_inc(volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter += 1; - local_irq_restore(flags); -} - -static inline void atomic_dec(volatile atomic_t *v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter -= 1; - local_irq_restore(flags); -} - -static inline int atomic_dec_and_test(volatile atomic_t *v) -{ - unsigned long flags; - int val; - - local_irq_save(flags); - val = v->counter; - v->counter = val -= 1; - local_irq_restore(flags); - - return val == 0; -} - -static inline int atomic_add_negative(int i, volatile atomic_t *v) -{ - unsigned long flags; - int val; - - local_irq_save(flags); - val = v->counter; - v->counter = val += i; - local_irq_restore(flags); - - return val < 0; -} - -static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) -{ - unsigned long flags; - - local_irq_save(flags); - *addr &= ~mask; - local_irq_restore(flags); -} - -/* Atomic operations are already serializing on ARM */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - -#endif -#endif diff --git a/x-loader/include/asm/byteorder.h b/x-loader/include/asm/byteorder.h deleted file mode 100755 index c3489f1..0000000 --- a/x-loader/include/asm/byteorder.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * linux/include/asm-arm/byteorder.h - * - * ARM Endian-ness. In little endian mode, the data bus is connected such - * that byte accesses appear as: - * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 - * and word accesses (data or instruction) appear as: - * d0...d31 - * - * When in big endian mode, byte accesses appear as: - * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 - * and word accesses (data or instruction) appear as: - * d0...d31 - */ -#ifndef __ASM_ARM_BYTEORDER_H -#define __ASM_ARM_BYTEORDER_H - - -#include - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#ifdef __ARMEB__ -#include -#else -#include -#endif - -#endif diff --git a/x-loader/include/asm/errno.h b/x-loader/include/asm/errno.h deleted file mode 100644 index 39dc515..0000000 --- a/x-loader/include/asm/errno.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * U-boot - errno.h Error number defines - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _GENERIC_ERRNO_H -#define _GENERIC_ERRNO_H - -#define EPERM 1 /* Operation not permitted */ -#define ENOENT 2 /* No such file or directory */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define E2BIG 7 /* Argument list too long */ -#define ENOEXEC 8 /* Exec format error */ -#define EBADF 9 /* Bad file number */ -#define ECHILD 10 /* No child processes */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* Out of memory */ -#define EACCES 13 /* Permission denied */ -#define EFAULT 14 /* Bad address */ -#define ENOTBLK 15 /* Block device required */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENFILE 23 /* File table overflow */ -#define EMFILE 24 /* Too many open files */ -#define ENOTTY 25 /* Not a typewriter */ -#define ETXTBSY 26 /* Text file busy */ -#define EFBIG 27 /* File too large */ -#define ENOSPC 28 /* No space left on device */ -#define ESPIPE 29 /* Illegal seek */ -#define EROFS 30 /* Read-only file system */ -#define EMLINK 31 /* Too many links */ -#define EPIPE 32 /* Broken pipe */ -#define EDOM 33 /* Math argument out of domain of func */ -#define ERANGE 34 /* Math result not representable */ -#define EDEADLK 35 /* Resource deadlock would occur */ -#define ENAMETOOLONG 36 /* File name too long */ -#define ENOLCK 37 /* No record locks available */ -#define ENOSYS 38 /* Function not implemented */ -#define ENOTEMPTY 39 /* Directory not empty */ -#define ELOOP 40 /* Too many symbolic links encountered */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define ENOMSG 42 /* No message of desired type */ -#define EIDRM 43 /* Identifier removed */ -#define ECHRNG 44 /* Channel number out of range */ -#define EL2NSYNC 45 /* Level 2 not synchronized */ -#define EL3HLT 46 /* Level 3 halted */ -#define EL3RST 47 /* Level 3 reset */ -#define ELNRNG 48 /* Link number out of range */ -#define EUNATCH 49 /* Protocol driver not attached */ -#define ENOCSI 50 /* No CSI structure available */ -#define EL2HLT 51 /* Level 2 halted */ -#define EBADE 52 /* Invalid exchange */ -#define EBADR 53 /* Invalid request descriptor */ -#define EXFULL 54 /* Exchange full */ -#define ENOANO 55 /* No anode */ -#define EBADRQC 56 /* Invalid request code */ -#define EBADSLT 57 /* Invalid slot */ - -#define EDEADLOCK EDEADLK - -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EMULTIHOP 72 /* Multihop attempted */ -#define EDOTDOT 73 /* RFS specific error */ -#define EBADMSG 74 /* Not a data message */ -#define EOVERFLOW 75 /* Value too large for defined data type */ -#define ENOTUNIQ 76 /* Name not unique on network */ -#define EBADFD 77 /* File descriptor in bad state */ -#define EREMCHG 78 /* Remote address changed */ -#define ELIBACC 79 /* Can not access a needed shared library */ -#define ELIBBAD 80 /* Accessing a corrupted shared library */ -#define ELIBSCN 81 /* .lib section in a.out corrupted */ -#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 83 /* Cannot exec a shared library directly */ -#define EILSEQ 84 /* Illegal byte sequence */ -#define ERESTART 85 /* Interrupted system call should be restarted */ -#define ESTRPIPE 86 /* Streams pipe error */ -#define EUSERS 87 /* Too many users */ -#define ENOTSOCK 88 /* Socket operation on non-socket */ -#define EDESTADDRREQ 89 /* Destination address required */ -#define EMSGSIZE 90 /* Message too long */ -#define EPROTOTYPE 91 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 92 /* Protocol not available */ -#define EPROTONOSUPPORT 93 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ -#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 96 /* Protocol family not supported */ -#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ -#define EADDRINUSE 98 /* Address already in use */ -#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ -#define ENETDOWN 100 /* Network is down */ -#define ENETUNREACH 101 /* Network is unreachable */ -#define ENETRESET 102 /* Network dropped connection because of reset */ -#define ECONNABORTED 103 /* Software caused connection abort */ -#define ECONNRESET 104 /* Connection reset by peer */ -#define ENOBUFS 105 /* No buffer space available */ -#define EISCONN 106 /* Transport endpoint is already connected */ -#define ENOTCONN 107 /* Transport endpoint is not connected */ -#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 109 /* Too many references: cannot splice */ -#define ETIMEDOUT 110 /* Connection timed out */ -#define ECONNREFUSED 111 /* Connection refused */ -#define EHOSTDOWN 112 /* Host is down */ -#define EHOSTUNREACH 113 /* No route to host */ -#define EALREADY 114 /* Operation already in progress */ -#define EINPROGRESS 115 /* Operation now in progress */ -#define ESTALE 116 /* Stale NFS file handle */ -#define EUCLEAN 117 /* Structure needs cleaning */ -#define ENOTNAM 118 /* Not a XENIX named type file */ -#define ENAVAIL 119 /* No XENIX semaphores available */ -#define EISNAM 120 /* Is a named type file */ -#define EREMOTEIO 121 /* Remote I/O error */ -#define EDQUOT 122 /* Quota exceeded */ -#define ENOMEDIUM 123 /* No medium found */ -#define EMEDIUMTYPE 124 /* Wrong medium type */ - -#endif diff --git a/x-loader/include/asm/io.h b/x-loader/include/asm/io.h deleted file mode 100644 index f4ae307..0000000 --- a/x-loader/include/asm/io.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - * linux/include/asm-arm/io.h - * - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Modifications: - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions - */ -#ifndef __ASM_ARM_IO_H -#define __ASM_ARM_IO_H - -#ifdef __KERNEL__ - -#include -#include -#include -#if 0 /* XXX###XXX */ -#include -#endif /* XXX###XXX */ - -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -/* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); -extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); -extern void __raw_writesl(unsigned int addr, const void *data, int longlen); - -extern void __raw_readsb(unsigned int addr, void *data, int bytelen); -extern void __raw_readsw(unsigned int addr, void *data, int wordlen); -extern void __raw_readsl(unsigned int addr, void *data, int longlen); - -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -#define writeb(v,a) __arch_putb(v,a) -#define writew(v,a) __arch_putw(v,a) -#define writel(v,a) __arch_putl(v,a) - -#define readb(a) __arch_getb(a) -#define readw(a) __arch_getw(a) -#define readl(a) __arch_getl(a) - -/* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) -#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) -#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) - -#define __raw_base_readb(base,off) __arch_base_getb(base,off) -#define __raw_base_readw(base,off) __arch_base_getw(base,off) -#define __raw_base_readl(base,off) __arch_base_getl(base,off) - -/* - * Now, pick up the machine-defined IO definitions - */ -#if 0 /* XXX###XXX */ -#include -#endif /* XXX###XXX */ - -/* - * IO port access primitives - * ------------------------- - * - * The ARM doesn't have special IO access instructions; all IO is memory - * mapped. Note that these are defined to perform little endian accesses - * only. Their primary purpose is to access PCI and ISA peripherals. - * - * Note that for a big endian machine, this implies that the following - * big endian mode connectivity is in place, as described by numerous - * ARM documents: - * - * PCI: D0-D7 D8-D15 D16-D23 D24-D31 - * ARM: D24-D31 D16-D23 D8-D15 D0-D7 - * - * The machine specific io.h include defines __io to translate an "IO" - * address to a memory address. - * - * Note that we prevent GCC re-ordering or caching values in expressions - * by introducing sequence points into the in*() definitions. Note that - * __raw_* do not guarantee this behaviour. - * - * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. - */ -#ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) - -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) - -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) - -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) -#endif - -#define outb_p(val,port) outb((val),(port)) -#define outw_p(val,port) outw((val),(port)) -#define outl_p(val,port) outl((val),(port)) -#define inb_p(port) inb((port)) -#define inw_p(port) inw((port)) -#define inl_p(port) inl((port)) - -#define outsb_p(port,from,len) outsb(port,from,len) -#define outsw_p(port,from,len) outsw(port,from,len) -#define outsl_p(port,from,len) outsl(port,from,len) -#define insb_p(port,to,len) insb(port,to,len) -#define insw_p(port,to,len) insw(port,to,len) -#define insl_p(port,to,len) insl(port,to,len) - -/* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * linux/Documentation/IO-mapping.txt. If you want a - * physical address, use __ioremap instead. - */ -extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); -extern void __iounmap(void *addr); - -/* - * Generic ioremap support. - * - * Define: - * iomem_valid_addr(off,size) - * iomem_to_phys(off) - */ -#ifdef iomem_valid_addr -#define __arch_ioremap(off,sz,nocache) \ - ({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off),_size,0); \ - _ret; \ - }) - -#define __arch_iounmap __iounmap -#endif - -#define ioremap(off,sz) __arch_ioremap((off),(sz),0) -#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) -#define iounmap(_addr) __arch_iounmap(_addr) - -/* - * DMA-consistent mapping functions. These allocate/free a region of - * uncached, unwrite-buffered mapped memory space for use with DMA - * devices. This is the "generic" version. The PCI specific version - * is in pci.h - */ -extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); -extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); -extern void consistent_sync(void *vaddr, size_t size, int rw); - -/* - * String version of IO memory access ops: - */ -extern void _memcpy_fromio(void *, unsigned long, size_t); -extern void _memcpy_toio(unsigned long, const void *, size_t); -extern void _memset_io(unsigned long, int, size_t); - -extern void __readwrite_bug(const char *fn); - -/* - * If this architecture has PCI memory IO, then define the read/write - * macros. These should only be used with the cookie passed from - * ioremap. - */ -#ifdef __mem_pci - -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) - -#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) - -#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) -#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) -#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) - -#define eth_io_copy_and_sum(s,c,l,b) \ - eth_copy_and_sum((s),__mem_pci(c),(l),(b)) - -static inline int -check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#elif !defined(readb) - -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") - -#define check_signature(io,sig,len) (0) - -#endif /* __mem_pci */ - -/* - * If this architecture has ISA IO, then define the isa_read/isa_write - * macros. - */ -#ifdef __mem_isa - -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) -#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) -#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - eth_copy_and_sum((a),__mem_isa(b),(c),(d)) - -static inline int -isa_check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (isa_readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#else /* __mem_isa */ - -#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) -#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) -#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) -#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") -#define isa_writew(val,addr) __readwrite_bug("isa_writew") -#define isa_writel(val,addr) __readwrite_bug("isa_writel") -#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") -#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") -#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - __readwrite_bug("isa_eth_io_copy_and_sum") - -#define isa_check_signature(io,sig,len) (0) - -#endif /* __mem_isa */ -#endif /* __KERNEL__ */ -#endif /* __ASM_ARM_IO_H */ diff --git a/x-loader/include/asm/memory.h b/x-loader/include/asm/memory.h deleted file mode 100644 index c3b2afd..0000000 --- a/x-loader/include/asm/memory.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * linux/include/asm-arm/memory.h - * - * Copyright (C) 2000-2002 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Note: this file should not be included by non-asm/.h files - */ -#ifndef __ASM_ARM_MEMORY_H -#define __ASM_ARM_MEMORY_H - -#if 0 /* XXX###XXX */ - -#include -#include - -/* - * PFNs are used to describe any physical page; this means - * PFN 0 == physical address 0. - * - * This is the PFN of the first RAM page in the kernel - * direct-mapped view. We assume this is the first page - * of RAM in the mem_map as well. - */ -#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) - -/* - * These are *only* valid on the kernel direct mapped RAM memory. - */ -static inline unsigned long virt_to_phys(void *x) -{ - return __virt_to_phys((unsigned long)(x)); -} - -static inline void *phys_to_virt(unsigned long x) -{ - return (void *)(__phys_to_virt((unsigned long)(x))); -} - -#define __pa(x) __virt_to_phys((unsigned long)(x)) -#define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) - -/* - * Virtual <-> DMA view memory address translations - * Again, these are *only* valid on the kernel direct mapped RAM - * memory. Use of these is *depreciated*. - */ -#define virt_to_bus(x) (__virt_to_bus((unsigned long)(x))) -#define bus_to_virt(x) ((void *)(__bus_to_virt((unsigned long)(x)))) - -/* - * Conversion between a struct page and a physical address. - * - * Note: when converting an unknown physical address to a - * struct page, the resulting pointer must be validated - * using VALID_PAGE(). It must return an invalid struct page - * for any physical address not corresponding to a system - * RAM address. - * - * page_to_pfn(page) convert a struct page * to a PFN number - * pfn_to_page(pfn) convert a _valid_ PFN number to struct page * - * pfn_valid(pfn) indicates whether a PFN number is valid - * - * virt_to_page(k) convert a _valid_ virtual address to struct page * - * virt_addr_valid(k) indicates whether a virtual address is valid - */ -#ifndef CONFIG_DISCONTIGMEM - -#define page_to_pfn(page) (((page) - mem_map) + PHYS_PFN_OFFSET) -#define pfn_to_page(pfn) ((mem_map + (pfn)) - PHYS_PFN_OFFSET) -#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) - -#define virt_to_page(kaddr) (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)) -#define virt_addr_valid(kaddr) ((kaddr) >= PAGE_OFFSET && (kaddr) < (unsigned long)high_memory) - -#define PHYS_TO_NID(addr) (0) - -#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) - -#else - -/* - * This is more complex. We have a set of mem_map arrays spread - * around in memory. - */ -#define page_to_pfn(page) \ - (((page) - page_zone(page)->zone_mem_map) \ - + (page_zone(page)->zone_start_paddr >> PAGE_SHIFT)) - -#define pfn_to_page(pfn) \ - (PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT)) - -#define pfn_valid(pfn) \ - ({ \ - unsigned int node = PFN_TO_NID(pfn); \ - struct pglist_data *nd = NODE_DATA(node); \ - ((node < NR_NODES) && \ - ((pfn - (nd->node_start_paddr >> PAGE_SHIFT)) < nd->node_size));\ - }) - -#define virt_to_page(kaddr) \ - (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) - -#define virt_addr_valid(kaddr) (KVADDR_TO_NID(kaddr) < NR_NODES) - -/* - * Common discontigmem stuff. - * PHYS_TO_NID is used by the ARM kernel/setup.c - */ -#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT) - -/* - * 2.4 compatibility - * - * VALID_PAGE returns a non-zero value if given page pointer is valid. - * This assumes all node's mem_maps are stored within the node they - * refer to. This is actually inherently buggy. - */ -#define VALID_PAGE(page) \ -({ unsigned int node = KVADDR_TO_NID(page); \ - ((node < NR_NODES) && \ - ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size)); \ -}) - -#endif - -/* - * We should really eliminate virt_to_bus() here - it's depreciated. - */ -#define page_to_bus(page) (virt_to_bus(page_address(page))) - -#endif /* XXX###XXX */ - -#endif /* __ASM_ARM_MEMORY_H */ diff --git a/x-loader/include/asm/posix_types.h b/x-loader/include/asm/posix_types.h deleted file mode 100644 index c412486..0000000 --- a/x-loader/include/asm/posix_types.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * linux/include/asm-arm/posix_types.h - * - * Copyright (C) 1996-1998 Russell King. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Changelog: - * 27-06-1996 RMK Created - */ -#ifndef __ARCH_ARM_POSIX_TYPES_H -#define __ARCH_ARM_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) - -#undef __FD_CLR -#define __FD_CLR(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) - -#undef __FD_ISSET -#define __FD_ISSET(fd, fdsetp) \ - ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) \ - (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) - -#endif - -#endif diff --git a/x-loader/include/asm/setup.h b/x-loader/include/asm/setup.h deleted file mode 100644 index 89df4dc..0000000 --- a/x-loader/include/asm/setup.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * linux/include/asm/setup.h - * - * Copyright (C) 1997-1999 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Structure passed to kernel to tell it about the - * hardware it's running on. See linux/Documentation/arm/Setup - * for more info. - * - * NOTE: - * This file contains two ways to pass information from the boot - * loader to the kernel. The old struct param_struct is deprecated, - * but it will be kept in the kernel for 5 years from now - * (2001). This will allow boot loaders to convert to the new struct - * tag way. - */ -#ifndef __ASMARM_SETUP_H -#define __ASMARM_SETUP_H - -/* - * Usage: - * - do not go blindly adding fields, add them at the end - * - when adding fields, don't rely on the address until - * a patch from me has been released - * - unused fields should be zero (for future expansion) - * - this structure is relatively short-lived - only - * guaranteed to contain useful data in setup_arch() - */ -#define COMMAND_LINE_SIZE 1024 - -/* This is the old deprecated way to pass parameters to the kernel */ -struct param_struct { - union { - struct { - unsigned long page_size; /* 0 */ - unsigned long nr_pages; /* 4 */ - unsigned long ramdisk_size; /* 8 */ - unsigned long flags; /* 12 */ -#define FLAG_READONLY 1 -#define FLAG_RDLOAD 4 -#define FLAG_RDPROMPT 8 - unsigned long rootdev; /* 16 */ - unsigned long video_num_cols; /* 20 */ - unsigned long video_num_rows; /* 24 */ - unsigned long video_x; /* 28 */ - unsigned long video_y; /* 32 */ - unsigned long memc_control_reg; /* 36 */ - unsigned char sounddefault; /* 40 */ - unsigned char adfsdrives; /* 41 */ - unsigned char bytes_per_char_h; /* 42 */ - unsigned char bytes_per_char_v; /* 43 */ - unsigned long pages_in_bank[4]; /* 44 */ - unsigned long pages_in_vram; /* 60 */ - unsigned long initrd_start; /* 64 */ - unsigned long initrd_size; /* 68 */ - unsigned long rd_start; /* 72 */ - unsigned long system_rev; /* 76 */ - unsigned long system_serial_low; /* 80 */ - unsigned long system_serial_high; /* 84 */ - unsigned long mem_fclk_21285; /* 88 */ - } s; - char unused[256]; - } u1; - union { - char paths[8][128]; - struct { - unsigned long magic; - char n[1024 - sizeof(unsigned long)]; - } s; - } u2; - char commandline[COMMAND_LINE_SIZE]; -}; - - -/* - * The new way of passing information: a list of tagged entries - */ - -/* The list ends with an ATAG_NONE node. */ -#define ATAG_NONE 0x00000000 - -struct tag_header { - u32 size; - u32 tag; -}; - -/* The list must start with an ATAG_CORE node */ -#define ATAG_CORE 0x54410001 - -struct tag_core { - u32 flags; /* bit 0 = read-only */ - u32 pagesize; - u32 rootdev; -}; - -/* it is allowed to have multiple ATAG_MEM nodes */ -#define ATAG_MEM 0x54410002 - -struct tag_mem32 { - u32 size; - u32 start; /* physical start address */ -}; - -/* VGA text type displays */ -#define ATAG_VIDEOTEXT 0x54410003 - -struct tag_videotext { - u8 x; - u8 y; - u16 video_page; - u8 video_mode; - u8 video_cols; - u16 video_ega_bx; - u8 video_lines; - u8 video_isvga; - u16 video_points; -}; - -/* describes how the ramdisk will be used in kernel */ -#define ATAG_RAMDISK 0x54410004 - -struct tag_ramdisk { - u32 flags; /* bit 0 = load, bit 1 = prompt */ - u32 size; /* decompressed ramdisk size in _kilo_ bytes */ - u32 start; /* starting block of floppy-based RAM disk image */ -}; - -/* describes where the compressed ramdisk image lives (virtual address) */ -/* - * this one accidentally used virtual addresses - as such, - * its depreciated. - */ -#define ATAG_INITRD 0x54410005 - -/* describes where the compressed ramdisk image lives (physical address) */ -#define ATAG_INITRD2 0x54420005 - -struct tag_initrd { - u32 start; /* physical start address */ - u32 size; /* size of compressed ramdisk image in bytes */ -}; - -/* board serial number. "64 bits should be enough for everybody" */ -#define ATAG_SERIAL 0x54410006 - -struct tag_serialnr { - u32 low; - u32 high; -}; - -/* board revision */ -#define ATAG_REVISION 0x54410007 - -struct tag_revision { - u32 rev; -}; - -/* initial values for vesafb-type framebuffers. see struct screen_info - * in include/linux/tty.h - */ -#define ATAG_VIDEOLFB 0x54410008 - -struct tag_videolfb { - u16 lfb_width; - u16 lfb_height; - u16 lfb_depth; - u16 lfb_linelength; - u32 lfb_base; - u32 lfb_size; - u8 red_size; - u8 red_pos; - u8 green_size; - u8 green_pos; - u8 blue_size; - u8 blue_pos; - u8 rsvd_size; - u8 rsvd_pos; -}; - -/* command line: \0 terminated string */ -#define ATAG_CMDLINE 0x54410009 - -struct tag_cmdline { - char cmdline[1]; /* this is the minimum size */ -}; - -/* acorn RiscPC specific information */ -#define ATAG_ACORN 0x41000101 - -struct tag_acorn { - u32 memc_control_reg; - u32 vram_pages; - u8 sounddefault; - u8 adfsdrives; -}; - -/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ -#define ATAG_MEMCLK 0x41000402 - -struct tag_memclk { - u32 fmemclk; -}; - -struct tag { - struct tag_header hdr; - union { - struct tag_core core; - struct tag_mem32 mem; - struct tag_videotext videotext; - struct tag_ramdisk ramdisk; - struct tag_initrd initrd; - struct tag_serialnr serialnr; - struct tag_revision revision; - struct tag_videolfb videolfb; - struct tag_cmdline cmdline; - - /* - * Acorn specific - */ - struct tag_acorn acorn; - - /* - * DC21285 specific - */ - struct tag_memclk memclk; - } u; -}; - -struct tagtable { - u32 tag; - int (*parse)(const struct tag *); -}; - -#define __tag __attribute__((unused, __section__(".taglist"))) -#define __tagtable(tag, fn) \ -static struct tagtable __tagtable_##fn __tag = { tag, fn } - -#define tag_member_present(tag,member) \ - ((unsigned long)(&((struct tag *)0L)->member + 1) \ - <= (tag)->hdr.size * 4) - -#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) - -#define for_each_tag(t,base) \ - for (t = base; t->hdr.size; t = tag_next(t)) - -/* - * Memory map description - */ -#define NR_BANKS 8 - -struct meminfo { - int nr_banks; - unsigned long end; - struct { - unsigned long start; - unsigned long size; - int node; - } bank[NR_BANKS]; -}; - -extern struct meminfo meminfo; - -#endif diff --git a/x-loader/include/asm/sizes.h b/x-loader/include/asm/sizes.h deleted file mode 100644 index f8d92ca..0000000 --- a/x-loader/include/asm/sizes.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -/* DO NOT EDIT!! - this file automatically generated - * from .s file by awk -f s2h.awk - */ -/* Size defintions - * Copyright (C) ARM Limited 1998. All rights reserved. - */ - -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_1K 0x00000400 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif - -/* END */ diff --git a/x-loader/include/asm/string.h b/x-loader/include/asm/string.h deleted file mode 100644 index c3ea582..0000000 --- a/x-loader/include/asm/string.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef __ASM_ARM_STRING_H -#define __ASM_ARM_STRING_H - -/* - * We don't do inline string functions, since the - * optimised inline asm versions are not small. - */ - -#undef __HAVE_ARCH_STRRCHR -extern char * strrchr(const char * s, int c); - -#undef __HAVE_ARCH_STRCHR -extern char * strchr(const char * s, int c); - -#undef __HAVE_ARCH_MEMCPY -extern void * memcpy(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMMOVE -extern void * memmove(void *, const void *, __kernel_size_t); - -#undef __HAVE_ARCH_MEMCHR -extern void * memchr(const void *, int, __kernel_size_t); - -#undef __HAVE_ARCH_MEMZERO -#undef __HAVE_ARCH_MEMSET -extern void * memset(void *, int, __kernel_size_t); - -#if 0 -extern void __memzero(void *ptr, __kernel_size_t n); - -#define memset(p,v,n) \ - ({ \ - if ((n) != 0) { \ - if (__builtin_constant_p((v)) && (v) == 0) \ - __memzero((p),(n)); \ - else \ - memset((p),(v),(n)); \ - } \ - (p); \ - }) - -#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); }) -#else -extern void memzero(void *ptr, __kernel_size_t n); -#endif - -#endif diff --git a/x-loader/include/asm/types.h b/x-loader/include/asm/types.h deleted file mode 100644 index efc3052..0000000 --- a/x-loader/include/asm/types.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef __ASM_ARM_TYPES_H -#define __ASM_ARM_TYPES_H - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; -typedef unsigned long phys_addr_t; - -#endif /* __KERNEL__ */ - -#endif diff --git a/x-loader/include/asm/x-load-arm.h b/x-loader/include/asm/x-load-arm.h deleted file mode 100644 index eef268e..0000000 --- a/x-loader/include/asm/x-load-arm.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _X_LOAD_ARM_H_ -#define _X_LOAD_ARM_H_ 1 - -/* for the following variables, see start.S */ -extern ulong _armboot_start; /* code start */ -extern ulong _bss_start; /* code + data end == BSS start */ -extern ulong _bss_end; /* BSS end */ - -#endif /* _X_LOAD_ARM_H_ */ diff --git a/x-loader/include/command.h b/x-loader/include/command.h deleted file mode 100644 index a2936ad..0000000 --- a/x-loader/include/command.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Definitions for Command Processor - */ -#ifndef __COMMAND_H -#define __COMMAND_H - -#ifndef NULL -#define NULL 0 -#endif - -#ifndef __ASSEMBLY__ -/* - * Monitor Command Table - */ - -struct cmd_tbl_s { - char *name; /* Command Name */ - int maxargs; /* maximum number of arguments */ - int repeatable; /* autorepeat allowed? */ - /* Implementation function */ - int (*cmd)(struct cmd_tbl_s *, int, int, char *[]); - char *usage; /* Usage message (short) */ -#ifdef CFG_LONGHELP - char *help; /* Help message (long) */ -#endif -#ifdef CONFIG_AUTO_COMPLETE - /* do auto completion on the arguments */ - int (*complete)(int argc, char *argv[], char last_char, int maxv, char *cmdv[]); -#endif -}; - -typedef struct cmd_tbl_s cmd_tbl_t; - -extern cmd_tbl_t __u_boot_cmd_start; -extern cmd_tbl_t __u_boot_cmd_end; - - -/* common/command.c */ -cmd_tbl_t *find_cmd(const char *cmd); - -#ifdef CONFIG_AUTO_COMPLETE -extern void install_auto_complete(void); -extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp); -#endif - -/* - * Monitor Command - * - * All commands use a common argument format: - * - * void function (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - */ - -typedef void command_t (cmd_tbl_t *, int, int, char *[]); - -#endif /* __ASSEMBLY__ */ - -/* - * Command Flags: - */ -#define CMD_FLAG_REPEAT 0x0001 /* repeat last command */ -#define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */ - -/* - * Configurable monitor commands definitions have been moved - * to include/cmd_confdefs.h - */ - - -#define Struct_Section __attribute__ ((unused,section (".u_boot_cmd"))) - -#ifdef CFG_LONGHELP - -#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \ -cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage, help} - -#else /* no long help info */ - -#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \ -cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage} - -#endif /* CFG_LONGHELP */ - -#endif /* __COMMAND_H */ diff --git a/x-loader/include/common.h b/x-loader/include/common.h deleted file mode 100644 index 5a6f4c9..0000000 --- a/x-loader/include/common.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __COMMON_H_ -#define __COMMON_H_ 1 - -#undef _LINUX_CONFIG_H -#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ - -typedef unsigned char uchar; -typedef volatile unsigned long vu_long; -typedef volatile unsigned short vu_short; -typedef volatile unsigned char vu_char; - -#include -#include -#include - -#ifdef CONFIG_ARM -#define asmlinkage /* nothing */ -#endif - - -#ifdef CONFIG_ARM -# include -# include /* ARM version to be fixed! */ -#endif /* CONFIG_ARM */ - -#ifdef CFG_PRINTF -#define printf(fmt,args...) serial_printf (fmt ,##args) -#define getc() serial_getc() -#else -#define printf(fmt,args...) -#define getc() ' ' -#endif /* CFG_PRINTF */ - -/* board/$(BOARD)/$(BOARD).c */ -int board_init (void); -int nand_init (void); -int mmc_boot (unsigned char *buf); -void board_hang (void); - -/* cpu/$(CPU)/cpu.c */ -int cpu_init (void); -#ifdef CFG_UDELAY -void udelay (unsigned long usec); -#endif - -/* nand driver */ -#define NAND_CMD_READ0 0 -#define NAND_CMD_READ1 1 -#define NAND_CMD_READOOB 0x50 -#define NAND_CMD_STATUS 0x70 -#define NAND_CMD_READID 0x90 -#define NAND_CMD_RESET 0xff - -/* Extended Commands for Large page devices */ -#define NAND_CMD_READSTART 0x30 - -int nand_chip(void); -int nand_read_block(uchar *buf, ulong block_addr); - -int onenand_chip(void); -int onenand_read_block(unsigned char *buf, ulong block); - - -#ifdef CFG_PRINTF - -/* serial driver */ -int serial_init (void); -void serial_setbrg (void); -void serial_putc (const char); -void serial_puts (const char *); -int serial_getc (void); -int serial_tstc (void); - -/* lib/printf.c */ -void serial_printf (const char *fmt, ...); -#endif - -/* lib/crc.c */ -void nand_calculate_ecc (const u_char *dat, u_char *ecc_code); -int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc); - -/* lib/board.c */ -void hang (void) __attribute__ ((noreturn)); -#endif /* __COMMON_H_ */ diff --git a/x-loader/include/configs/omap2420h4.h b/x-loader/include/configs/omap2420h4.h deleted file mode 100644 index 7495d7f..0000000 --- a/x-loader/include/configs/omap2420h4.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (C) 2004 - 2005 Texas Instruments. - * - * X-Loader Configuation settings for the TI OMAP H4 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* serial printf facility takes about 3.5K */ -#define CFG_PRINTF -//#undef CFG_PRINTF - -/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ -//#define CFG_UDELAY - -/* - * High Level Configuration Options - */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP2420 1 /* which is in a 2420 */ -#define CONFIG_OMAP2420H4 1 /* and on a H4 board */ - -#define CONFIG_OMAP242X - -#define PRCM_CONFIG_II 1 -//#define PRCM_CONFIG_III 1 -#define CONFIG_PARTIAL_SRAM 1 - -//#define CFG_SDRAM_DDR 1 -#define CFG_SDRAM_COMBO 2 -//#define CFG_SDRAM_SDR 3 -//#define CFG_SDRAM_STACKED 4 - -/* Chipselect and NAND information : - Since we share the mem.h from u-boot, we define few macros here - so as to pick the right gpmc values from there for the macros in mem.h -*/ -/* NAND fixed at CS5 */ -#define OMAP24XX_GPMC_CS0 SMNAND -#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_64M -#define OMAP24XX_GPMC_CS0_MAP CFG_FLASH_BASE -#define CFG_NAND_BOOT -#define NAND_LEGACY - -#include /* get chip and board defs */ - -#define V_SCLK 12000000 -/* input clock of PLL */ -/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ -#define CONFIG_SYS_CLK_FREQ V_SCLK - -#ifdef CFG_PRINTF - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 OMAP2420_UART1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* UART1 on H4 */ - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_PBSIZE 256 - -#endif /* CFG_PRINTF */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LOADADDR 0x80000000 - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -/*----------------------------------------------------------------------- - * Board NAND Info. - */ -#define CFG_NAND_K9K1216 /* Samsung 16-bit 64MB chip */ - -#define NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/ - -/* H4 NAND is partitioned: - * 0x0000000 - 0x0010000 Booting Image - * 0x0010000 - 0x0050000 U-Boot Image - * 0x0050000 - 0x0080000 U-Boot Env Data (X-loader doesn't care) - * 0x0080000 - 0x4000000 depends on application - */ -#define NAND_UBOOT_START 0x0040000 -#define NAND_UBOOT_END 0x0080000 -#define NAND_BLOCK_SIZE 0x4000 - -#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0) -#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0) -#define READ_NAND(adr) (*(volatile u16 *)0x6800A084) - -#define NAND_WAIT_READY() - -#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0) -#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0) - -#define NAND_CTL_CLRALE(adr) -#define NAND_CTL_SETALE(adr) -#define NAND_CTL_CLRCLE(adr) -#define NAND_CTL_SETCLE(adr) -#define NAND_DISABLE_CE() -#define NAND_ENABLE_CE() - - -#endif /* __CONFIG_H */ diff --git a/x-loader/include/configs/omap2430sdp.h b/x-loader/include/configs/omap2430sdp.h deleted file mode 100644 index 3fda61f..0000000 --- a/x-loader/include/configs/omap2430sdp.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * (C) Copyright 2004 Texas Instruments. - * - * X-Loader Configuation settings for the TI OMAP H4 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* serial printf facility takes about 3.5K */ -#define CFG_PRINTF -//#undef CFG_PRINTF - -/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ -//#define CFG_UDELAY - -/* - * High Level Configuration Options - */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP2430H4 1 /* and on a H4 board */ - -#define CONFIG_OMAP243X 1 - -//#define PRCM_CONFIG_5A 1 -#define PRCM_CONFIG_2 1 /* 2430 ES2+330ARM+DDR-165-PISMO */ - -#define OMAP2430_SQUARE_CLOCK_INPUT 1 - -/* Memory type */ -//#define CFG_SDRAM_DDR 1 /* not tested */ -//#define CFG_SDRAM_COMBO 2 /* not tested */ -#define CFG_2430SDRAM_DDR 3 -//#define CFG_SDRAM_STACKED 4 /* not tested */ - -/* The actual register values are defined in u-boot- mem.h */ -/* SDRAM Bank Allocation method */ -//#define SDRC_B_R_C 1 -//#define SDRC_B1_R_B0_C 1 -#define SDRC_R_B_C 1 - -/* Boot type */ -//#define CFG_NAND 1 -#define CFG_ONENAND 1 - -# define NAND_BASE 0x0C000000 /* NAND flash */ -# define ONENAND_BASE 0x20000000 /* OneNand flash */ - -#ifdef CFG_NAND -#define NAND_LEGACY -#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_64M -#define OMAP24XX_GPMC_CS0_MAP NAND_BASE -#else -#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_128M -#define OMAP24XX_GPMC_CS0_MAP ONENAND_BASE -#define ONENAND_ADDR ONENAND_BASE /* physical address to access OneNAND at CS0*/ -#endif - -/* Another dependency on u-boot */ -#define sdelay delay - -#include /* get chip and board defs */ - -#define V_SCLK 13000000 -/* input clock of PLL */ -/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ -#define CONFIG_SYS_CLK_FREQ V_SCLK - -#ifdef CFG_PRINTF - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CFG_NS16550_COM1 OMAP2430_UART1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* UART1 on 2430SDP */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CFG_PBSIZE 256 - -#endif /* CFG_PRINTF */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LOADADDR 0x80008000 - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -#ifdef CFG_NAND - -/*----------------------------------------------------------------------- - * Board NAND Info. - */ -#define CFG_NAND_K9K1216 /* Samsung 16-bit 64MB chip */ - -/* NAND is partitioned: - * 0x0000000 - 0x0010000 Booting Image - * 0x0010000 - 0x0050000 U-Boot Image - * 0x0050000 - 0x0080000 U-Boot Env Data (X-loader doesn't care) - * 0x0080000 - 0x00B0000 Kernel Image - * 0x00B0000 - 0x4000000 depends on application - */ -#define NAND_UBOOT_START 0x0040000 -#define NAND_UBOOT_END 0x0080000 -#define NAND_BLOCK_SIZE 0x4000 - -#define GPMC_CONFIG (OMAP24XX_GPMC_BASE+0x50) -#define GPMC_NAND_COMMAND_0 (OMAP24XX_GPMC_BASE+0x7C) -#define GPMC_NAND_ADDRESS_0 (OMAP24XX_GPMC_BASE+0x80) -#define GPMC_NAND_DATA_0 (OMAP24XX_GPMC_BASE+0x84) - -#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0) -#define WRITE_NAND(d, adr) do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0) -#define READ_NAND(adr) (*(volatile u16 *)GPMC_NAND_DATA_0) -#define NAND_WAIT_READY() -#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) -#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) - -#define NAND_CTL_CLRALE(adr) -#define NAND_CTL_SETALE(adr) -#define NAND_CTL_CLRCLE(adr) -#define NAND_CTL_SETCLE(adr) -#define NAND_DISABLE_CE() -#define NAND_ENABLE_CE() - -#else -/*----------------------------------------------------------------------- - * Board oneNAND Info. - */ -#define CFG_SYNC_BURST_READ 1 - -/* OneNAND is partitioned: - * 0x0000000 - 0x0080000 X-Loader - * 0x0080000 - 0x00c0000 U-boot Image - * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care) - * 0x00e0000 - 0x0120000 Kernel Image - * 0x0120000 - 0x4000000 depends on application - */ - -#define ONENAND_START_BLOCK 4 -#define ONENAND_END_BLOCK 6 -#define ONENAND_PAGE_SIZE 2048 /* 2KB */ -#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ - -#endif // oneNAND -#endif /* __CONFIG_H */ diff --git a/x-loader/include/configs/omap3430labrador.h b/x-loader/include/configs/omap3430labrador.h deleted file mode 100644 index b5a9c54..0000000 --- a/x-loader/include/configs/omap3430labrador.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments - * Richard Woodruff - * - * X-Loader Configuation settings for the TI OMAP SDP3430 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* configure for GTA04 with DM3730 */ -#define CONFIG_OMAP36XX 1 /* or 36XX (DM3730) */ -#define PRCM_CLK_CFG2_400MHZ 1 - -/* serial printf facility takes about 3.5K */ -#define CFG_PRINTF -//#undef CFG_PRINTF - -/* - * High Level Configuration Options - */ -#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ -#define CONFIG_3430LABRADOR 1 /* working on Labrador */ -//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ - -#include /* get chip and board defs */ - -/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ -//#define CFG_UDELAY - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ - -#if (V_OSCK > 19200000) -#define V_SCLK (V_OSCK >> 1) -#else -#define V_SCLK V_OSCK -#endif - -#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ -//#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ -#define PRCM_PCLK_OPP2 1 /* ARM=500MHz - VDD1=1.20v */ - -/* Memory type */ -#define CFG_3430SDRAM_DDR 1 - -/* The actual register values are defined in u-boot- mem.h */ -/* SDRAM Bank Allocation method */ -//#define SDRC_B_R_C 1 -//#define SDRC_B1_R_B0_C 1 -#define SDRC_R_B_C 1 - -/* Boot type */ -#define CFG_NAND 1 -//#define CFG_ONENAND 1 - -# define NAND_BASE_ADR NAND_BASE /* NAND flash */ -# define ONENAND_BASE ONENAND_MAP /* OneNand flash */ - -#ifdef CFG_NAND -#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M /* u = ofdon't need so much for nand port */ -#define OMAP34XX_GPMC_CS0_MAP NAND_BASE_ADR -#else -#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M -#define OMAP34XX_GPMC_CS0_MAP ONENAND_BASE -#define ONENAND_ADDR ONENAND_BASE /* physical address of OneNAND at CS0*/ -#endif - - -#ifdef CFG_PRINTF - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (48000000) -#define CFG_NS16550_COM3 OMAP34XX_UART3 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL3 3 /* UART3 on board */ -#define CONFIG_CONS_INDEX 3 - -#define CONFIG_BAUDRATE 115200 -#define CFG_PBSIZE 256 - -#endif /* CFG_PRINTF */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LOADADDR 0x80008000 - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -#ifdef CFG_NAND - -/*----------------------------------------------------------------------- - * Board NAND Info. - */ - - -#define CFG_NAND_K9F1G08R0A /* Micron 16-bit 256MB chip large page NAND chip*/ -#define NAND_16BIT - -/* NAND is partitioned: - * 0x00000000 - 0x0007FFFF Booting Image - * 0x00080000 - 0x000BFFFF U-Boot Image - * 0x000C0000 - 0x000FFFFF U-Boot Env Data (X-loader doesn't care) - * 0x00100000 - 0x002FFFFF Kernel Image - * 0x00300000 - 0x08000000 depends on application - */ -#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */ -#define NAND_UBOOT_END 0x00C0000 /* Giving a space of 2 blocks = 256KB */ -#define NAND_BLOCK_SIZE 0x20000 - -#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) -#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) -#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) -#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) - -#ifdef NAND_16BIT -#define WRITE_NAND_COMMAND(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0) -#define WRITE_NAND(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0) -#define READ_NAND(adr) \ - (*(volatile u16 *)GPMC_NAND_DATA_0) -#define NAND_WAIT_READY() -#define NAND_WP_OFF() \ - do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) -#define NAND_WP_ON() \ - do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) - -#else /* to support 8-bit NAND devices */ -#define WRITE_NAND_COMMAND(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d;} while(0) -#define WRITE_NAND(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_DATA_0 = d;} while(0) -#define READ_NAND(adr) \ - (*(volatile u8 *)GPMC_NAND_DATA_0); -#define NAND_WAIT_READY() -#define NAND_WP_OFF() \ - do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) -#define NAND_WP_ON() \ - do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) - -#endif - -#define NAND_CTL_CLRALE(adr) -#define NAND_CTL_SETALE(adr) -#define NAND_CTL_CLRCLE(adr) -#define NAND_CTL_SETCLE(adr) -#define NAND_DISABLE_CE() -#define NAND_ENABLE_CE() - -#else -/*----------------------------------------------------------------------- - * Board oneNAND Info. - */ -#define CFG_SYNC_BURST_READ 1 - -/* OneNAND is partitioned: - * 0x0000000 - 0x0080000 X-Loader - * 0x0080000 - 0x00c0000 U-boot Image - * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care) - * 0x00e0000 - 0x0120000 Kernel Image - * 0x0120000 - 0x4000000 depends on application - */ - -#define ONENAND_START_BLOCK 4 -#define ONENAND_END_BLOCK 6 -#define ONENAND_PAGE_SIZE 2048 /* 2KB */ -#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ - -#endif /* oneNAND */ -#endif /* __CONFIG_H */ - diff --git a/x-loader/include/configs/omap3430sdp.h b/x-loader/include/configs/omap3430sdp.h deleted file mode 100644 index ad880ed..0000000 --- a/x-loader/include/configs/omap3430sdp.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments - * Richard Woodruff - * - * X-Loader Configuation settings for the TI OMAP SDP3430 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* serial printf facility takes about 3.5K */ -#define CFG_PRINTF -//#undef CFG_PRINTF - -/* - * High Level Configuration Options - */ -#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ -#define CONFIG_3430SDP 1 /* working with SDP */ -//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ - -/* Enable the below macro if MMC boot support is required */ -//#define CONFIG_MMC 1 -#if defined(CONFIG_MMC) - #define CFG_CMD_MMC 1 - #define CFG_CMD_FAT 1 -#endif - -#include /* get chip and board defs */ - -/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ -//#define CFG_UDELAY - -/* Clock Defines */ -#define V_OSCK 19200000 /* Clock output from T2 */ - -#if (V_OSCK > 19200000) -#define V_SCLK (V_OSCK >> 1) -#else -#define V_SCLK V_OSCK -#endif - -//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ -#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ -#define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */ - -/* Memory type */ -#define CFG_3430SDRAM_DDR 1 - -/* The actual register values are defined in u-boot- mem.h */ -/* SDRAM Bank Allocation method */ -//#define SDRC_B_R_C 1 -//#define SDRC_B1_R_B0_C 1 -#define SDRC_R_B_C 1 - -/* Boot type */ -#define CFG_NAND 1 -//#define CFG_ONENAND 1 - -# define NAND_BASE_ADR NAND_BASE /* NAND flash */ -# define ONENAND_BASE ONENAND_MAP /* OneNand flash */ - -#ifdef CFG_NAND -#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M -#define OMAP34XX_GPMC_CS0_MAP NAND_BASE_ADR -#else -#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M -#define OMAP34XX_GPMC_CS0_MAP ONENAND_BASE -#define ONENAND_ADDR ONENAND_BASE /* physical address of OneNAND at CS0*/ -#endif - -#ifdef CFG_PRINTF - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (48000000) -#define CFG_NS16550_COM1 OMAP34XX_UART1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* UART1 on 3430SDP */ -#define CONFIG_CONS_INDEX 1 - -#define CONFIG_BAUDRATE 115200 -#define CFG_PBSIZE 256 - -#endif /* CFG_PRINTF */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LOADADDR 0x80008000 - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -#ifdef CFG_NAND - -/*----------------------------------------------------------------------- - * Board NAND Info. - */ - - -#define CFG_NAND_K9F1G08R0A /* Samsung 8-bit 128MB chip large page NAND chip*/ -#define NAND_8BIT - -/* NAND is partitioned: - * 0x00000000 - 0x0007FFFF Booting Image - * 0x00080000 - 0x000BFFFF U-Boot Image - * 0x000C0000 - 0x000FFFFF U-Boot Env Data (X-loader doesn't care) - * 0x00100000 - 0x002FFFFF Kernel Image - * 0x00300000 - 0x08000000 depends on application - */ -#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */ -#define NAND_UBOOT_END 0x00C0000 /* Giving a space of 2 blocks = 256KB */ -#define NAND_BLOCK_SIZE 0x20000 - -#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) -#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) -#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) -#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) - -#ifdef NAND_16BIT -#define WRITE_NAND_COMMAND(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0) -#define WRITE_NAND(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0) -#define READ_NAND(adr) \ - (*(volatile u16 *)GPMC_NAND_DATA_0) -#define NAND_WAIT_READY() -#define NAND_WP_OFF() \ - do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) -#define NAND_WP_ON() \ - do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) - -#else /* to support 8-bit NAND devices */ -#define WRITE_NAND_COMMAND(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d;} while(0) -#define WRITE_NAND(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_DATA_0 = d;} while(0) -#define READ_NAND(adr) \ - (*(volatile u8 *)GPMC_NAND_DATA_0); -#define NAND_WAIT_READY() -#define NAND_WP_OFF() \ - do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) -#define NAND_WP_ON() \ - do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) - -#endif - -#define NAND_CTL_CLRALE(adr) -#define NAND_CTL_SETALE(adr) -#define NAND_CTL_CLRCLE(adr) -#define NAND_CTL_SETCLE(adr) -#define NAND_DISABLE_CE() -#define NAND_ENABLE_CE() - -#else -/*----------------------------------------------------------------------- - * Board oneNAND Info. - */ -#define CFG_SYNC_BURST_READ 1 - -/* OneNAND is partitioned: - * 0x0000000 - 0x0080000 X-Loader - * 0x0080000 - 0x00c0000 U-boot Image - * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care) - * 0x00e0000 - 0x0120000 Kernel Image - * 0x0120000 - 0x4000000 depends on application - */ - -#define ONENAND_START_BLOCK 4 -#define ONENAND_END_BLOCK 6 -#define ONENAND_PAGE_SIZE 2048 /* 2KB */ -#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ - -#endif /* oneNAND */ -#endif /* __CONFIG_H */ - diff --git a/x-loader/include/configs/omap3530beagle.h b/x-loader/include/configs/omap3530beagle.h deleted file mode 100644 index 5625417..0000000 --- a/x-loader/include/configs/omap3530beagle.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments - * Richard Woodruff - * - * X-Loader Configuation settings for the TI OMAP SDP3430 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* serial printf facility takes about 3.5K */ -#define CFG_PRINTF -//#undef CFG_PRINTF - -/* - * High Level Configuration Options - */ -#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ -#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ - -#define CONFIG_BEAGLE_REV2 1 - -/* Enable the below macro if MMC boot support is required */ -#define CONFIG_MMC 1 -#if defined(CONFIG_MMC) - #define CFG_CMD_MMC 1 - #define CFG_CMD_FAT 1 - #define CFG_I2C_SPEED 100000 - #define CFG_I2C_SLAVE 1 - #define CFG_I2C_BUS 0 - #define CFG_I2C_BUS_SELECT 1 - #define CONFIG_DRIVER_OMAP34XX_I2C 1 -#endif - -#include /* get chip and board defs */ - -/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ -//#define CFG_UDELAY - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ - -#if (V_OSCK > 19200000) -#define V_SCLK (V_OSCK >> 1) -#else -#define V_SCLK V_OSCK -#endif - -//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ -#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ -#define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */ - -/* Memory type */ -#define CFG_3430SDRAM_DDR 1 - -/* The actual register values are defined in u-boot- mem.h */ -/* SDRAM Bank Allocation method */ -//#define SDRC_B_R_C 1 -//#define SDRC_B1_R_B0_C 1 -#define SDRC_R_B_C 1 - -#define NAND_BASE_ADR NAND_BASE -#define ONENAND_BASE ONENAND_MAP -#define ONENAND_ADDR ONENAND_BASE - -#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M - -#ifdef CFG_PRINTF - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE -4 -#define CFG_NS16550_CLK 48000000 -#define CFG_NS16550_COM3 OMAP34XX_UART3 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 3 /* use UART3 */ -#define CONFIG_CONS_INDEX 3 - -#define CONFIG_BAUDRATE 115200 -#define CFG_PBSIZE 256 - -#endif /* CFG_PRINTF */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LOADADDR 0x80008000 - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -/*----------------------------------------------------------------------- - * Board NAND Info. - */ - - -#define CFG_NAND_K9F1G08R0A -#define NAND_16BIT - -/* NAND is partitioned: - * 0x00000000 - 0x0007FFFF Booting Image - * 0x00080000 - 0x000BFFFF U-Boot Image - * 0x000C0000 - 0x000FFFFF U-Boot Env Data (X-loader doesn't care) - * 0x00100000 - 0x002FFFFF Kernel Image - * 0x00300000 - 0x08000000 depends on application - */ -#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */ -#define NAND_UBOOT_END 0x0160000 /* Giving a space of 2 blocks = 256KB */ -#define NAND_BLOCK_SIZE 0x20000 - -#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) -#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) -#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) -#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) - -#ifdef NAND_16BIT -#define WRITE_NAND_COMMAND(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0) -#define WRITE_NAND_ADDRESS(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0) -#define WRITE_NAND(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0) -#define READ_NAND(adr) \ - (*(volatile u16 *)GPMC_NAND_DATA_0) -#define NAND_WAIT_READY() -#define NAND_WP_OFF() \ - do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) -#define NAND_WP_ON() \ - do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) - -#else /* to support 8-bit NAND devices */ -#define WRITE_NAND_COMMAND(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0) -#define WRITE_NAND_ADDRESS(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0) -#define WRITE_NAND(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0) -#define READ_NAND(adr) \ - (*(volatile u8 *)GPMC_NAND_DATA_0); -#define NAND_WAIT_READY() -#define NAND_WP_OFF() \ - do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) -#define NAND_WP_ON() \ - do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) - -#endif - -#define NAND_CTL_CLRALE(adr) -#define NAND_CTL_SETALE(adr) -#define NAND_CTL_CLRCLE(adr) -#define NAND_CTL_SETCLE(adr) -#define NAND_DISABLE_CE() -#define NAND_ENABLE_CE() - -/*----------------------------------------------------------------------- - * Board oneNAND Info. - */ -#define CFG_SYNC_BURST_READ 1 - -/* OneNAND is partitioned: - * 0x0000000 - 0x0080000 X-Loader - * 0x0080000 - 0x00c0000 U-boot Image - * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care) - * 0x00e0000 - 0x0120000 Kernel Image - * 0x0120000 - 0x4000000 depends on application - */ - -#define ONENAND_START_BLOCK 4 -#define ONENAND_END_BLOCK 6 -#define ONENAND_PAGE_SIZE 2048 /* 2KB */ -#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ - -#endif /* __CONFIG_H */ - diff --git a/x-loader/include/configs/omap3530gta04.h b/x-loader/include/configs/omap3530gta04.h deleted file mode 100644 index 3e6ef21..0000000 --- a/x-loader/include/configs/omap3530gta04.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments - * Richard Woodruff - * - * X-Loader Configuation settings for the TI OMAP SDP3430 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* configure for GTA04 with DM3730 */ -#define CONFIG_OMAP36XX 1 /* or 36XX (DM3730) */ -#define PRCM_CLK_CFG2_400MHZ 1 - -/* serial printf facility takes about 3.5K */ -#define CFG_PRINTF -//#undef CFG_PRINTF - -/* - * High Level Configuration Options - */ -#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -//#define CONFIG_OMAP3430 1 /* which is in a 3430 */ -#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ - -#define CONFIG_BEAGLE_REV2 1 - -/* Enable the below macro if MMC boot support is required */ -//#define CONFIG_MMC 1 -#if defined(CONFIG_MMC) - #define CFG_CMD_MMC 1 - #define CFG_CMD_FAT 1 - #define CFG_I2C_SPEED 100000 - #define CFG_I2C_SLAVE 1 - #define CFG_I2C_BUS 0 - #define CFG_I2C_BUS_SELECT 1 - #define CONFIG_DRIVER_OMAP34XX_I2C 1 -#endif - -#include /* get chip and board defs */ - -/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ -//#define CFG_UDELAY - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ - -#if (V_OSCK > 19200000) -#define V_SCLK (V_OSCK >> 1) -#else -#define V_SCLK V_OSCK -#endif - -//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ -#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ -#define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */ - -/* Memory type */ -#define CFG_3430SDRAM_DDR 1 - -/* The actual register values are defined in u-boot- mem.h */ -/* SDRAM Bank Allocation method */ -//#define SDRC_B_R_C 1 -//#define SDRC_B1_R_B0_C 1 -#define SDRC_R_B_C 1 - -/* Enable the below macro if NAND boot support is required */ -//#define CONFIG_NAND 1 - -#define NAND_BASE_ADR NAND_BASE -#define ONENAND_BASE ONENAND_MAP -#define ONENAND_ADDR ONENAND_BASE - -#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M - -#ifdef CFG_PRINTF - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE -4 -#define CFG_NS16550_CLK 48000000 -#define CFG_NS16550_COM3 OMAP34XX_UART3 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 3 /* use UART3 */ -#define CONFIG_CONS_INDEX 3 - -#define CONFIG_BAUDRATE 115200 -#define CFG_PBSIZE 256 - -#endif /* CFG_PRINTF */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LOADADDR 0x80008000 - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -#if defined(CONFIG_NAND) - -/*----------------------------------------------------------------------- - * Board NAND Info. - */ - - -#define CFG_NAND_K9F1G08R0A -#define NAND_16BIT - -/* NAND is partitioned: - * 0x00000000 - 0x0007FFFF Booting Image - * 0x00080000 - 0x000BFFFF U-Boot Image - * 0x000C0000 - 0x000FFFFF U-Boot Env Data (X-loader doesn't care) - * 0x00100000 - 0x002FFFFF Kernel Image - * 0x00300000 - 0x08000000 depends on application - */ -#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */ -#define NAND_UBOOT_END 0x0160000 /* Giving a space of 2 blocks = 256KB */ -#define NAND_BLOCK_SIZE 0x20000 - -#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) -#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) -#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) -#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) - -#ifdef NAND_16BIT -#define WRITE_NAND_COMMAND(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0) -#define WRITE_NAND_ADDRESS(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0) -#define WRITE_NAND(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0) -#define READ_NAND(adr) \ - (*(volatile u16 *)GPMC_NAND_DATA_0) -#define NAND_WAIT_READY() -#define NAND_WP_OFF() \ - do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) -#define NAND_WP_ON() \ - do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) - -#else /* to support 8-bit NAND devices */ -#define WRITE_NAND_COMMAND(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0) -#define WRITE_NAND_ADDRESS(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0) -#define WRITE_NAND(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0) -#define READ_NAND(adr) \ - (*(volatile u8 *)GPMC_NAND_DATA_0); -#define NAND_WAIT_READY() -#define NAND_WP_OFF() \ - do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) -#define NAND_WP_ON() \ - do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) - -#endif - -#define NAND_CTL_CLRALE(adr) -#define NAND_CTL_SETALE(adr) -#define NAND_CTL_CLRCLE(adr) -#define NAND_CTL_SETCLE(adr) -#define NAND_DISABLE_CE() -#define NAND_ENABLE_CE() - -/*----------------------------------------------------------------------- - * Board oneNAND Info. - */ -#define CFG_SYNC_BURST_READ 1 - -/* OneNAND is partitioned: - * 0x0000000 - 0x0080000 X-Loader - * 0x0080000 - 0x00c0000 U-boot Image - * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care) - * 0x00e0000 - 0x0120000 Kernel Image - * 0x0120000 - 0x4000000 depends on application - */ - -#define ONENAND_START_BLOCK 4 -#define ONENAND_END_BLOCK 6 -#define ONENAND_PAGE_SIZE 2048 /* 2KB */ -#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ - -#endif - -#endif /* __CONFIG_H */ - diff --git a/x-loader/include/configs/omap3evm.h b/x-loader/include/configs/omap3evm.h deleted file mode 100644 index 10e48ba..0000000 --- a/x-loader/include/configs/omap3evm.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (C) 2007 Mistral Solutions Pvt Ltd. - * - * X-Loader Configuation settings for the OMAP3EVM board. - * - * Derived from /include/configs/omap3430sdp.h - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* serial printf facility takes about 3.5K */ -#define CFG_PRINTF -//#undef CFG_PRINTF - -/* - * High Level Configuration Options - */ -#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ -//#define CONFIG_3430SDP 1 /* working with SDP */ -//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ - -#define CONFIG_OMAP3EVM 1 /* working with EVM */ - -/* Enable the below macro if MMC boot support is required */ -#define CONFIG_MMC 1 -#if defined(CONFIG_MMC) - #define CFG_CMD_MMC 1 - #define CFG_CMD_FAT 1 - #define CFG_I2C_SPEED 100000 - #define CFG_I2C_SLAVE 1 - #define CFG_I2C_BUS 0 - #define CFG_I2C_BUS_SELECT 1 - #define CONFIG_DRIVER_OMAP34XX_I2C 1 -#endif - -#include /* get chip and board defs */ - -/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ -//#define CFG_UDELAY - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ - -#if (V_OSCK > 19200000) -#define V_SCLK (V_OSCK >> 1) -#else -#define V_SCLK V_OSCK -#endif - -//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ -#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ -#define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */ - -/* Memory type */ -#define CFG_3430SDRAM_DDR 1 - -/* The actual register values are defined in u-boot- mem.h */ -/* SDRAM Bank Allocation method */ -//#define SDRC_B_R_C 1 -//#define SDRC_B1_R_B0_C 1 -#define SDRC_R_B_C 1 - - -# define NAND_BASE_ADR NAND_BASE /* NAND flash */ -# define ONENAND_BASE ONENAND_MAP /* OneNand flash */ - -#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M -#define ONENAND_ADDR ONENAND_BASE /* physical address of OneNAND at CS0*/ - -#ifdef CFG_PRINTF - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (48000000) -#define CFG_NS16550_COM1 OMAP34XX_UART1 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* UART1 on OMAP3EVM */ -#define CONFIG_CONS_INDEX 1 - -#define CONFIG_BAUDRATE 115200 -#define CFG_PBSIZE 256 - -#endif /* CFG_PRINTF */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LOADADDR 0x80008000 - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -/*----------------------------------------------------------------------- - * Board NAND Info. - */ - - -#define CFG_NAND_K9F1G08R0A /* Samsung 8-bit 128MB chip large page NAND chip*/ -#define NAND_16BIT - -/* NAND is partitioned: - * 0x00000000 - 0x0007FFFF Booting Image - * 0x00080000 - 0x0023FFFF U-Boot Image - * 0x00240000 - 0x0027FFFF U-Boot Env Data (X-loader doesn't care) - * 0x00280000 - 0x0077FFFF Kernel Image - * 0x00780000 - 0x08000000 depends on application - */ -#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */ -#define NAND_UBOOT_END 0x0240000 /* Giving a space of 2 blocks = 256KB */ -#define NAND_BLOCK_SIZE 0x20000 - -#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) -#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) -#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) -#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) - -#ifdef NAND_16BIT -#define WRITE_NAND_COMMAND(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0) -#define WRITE_NAND(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0) -#define READ_NAND(adr) \ - (*(volatile u16 *)GPMC_NAND_DATA_0) -#define NAND_WAIT_READY() -#define NAND_WP_OFF() \ - do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) -#define NAND_WP_ON() \ - do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) - -#else /* to support 8-bit NAND devices */ -#define WRITE_NAND_COMMAND(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d;} while(0) -#define WRITE_NAND(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_DATA_0 = d;} while(0) -#define READ_NAND(adr) \ - (*(volatile u8 *)GPMC_NAND_DATA_0); -#define NAND_WAIT_READY() -#define NAND_WP_OFF() \ - do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) -#define NAND_WP_ON() \ - do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) - -#endif - -#define NAND_CTL_CLRALE(adr) -#define NAND_CTL_SETALE(adr) -#define NAND_CTL_CLRCLE(adr) -#define NAND_CTL_SETCLE(adr) -#define NAND_DISABLE_CE() -#define NAND_ENABLE_CE() - -/*----------------------------------------------------------------------- - * Board oneNAND Info. - */ -#define CFG_SYNC_BURST_READ 1 - -/* OneNAND is partitioned: - * 0x0000000 - 0x0080000 X-Loader - * 0x0080000 - 0x0240000 U-boot Image - * 0x0240000 - 0x0280000 U-Boot Env Data (X-loader doesn't care) - * 0x0280000 - 0x0780000 Kernel Image - * 0x0780000 - 0x8000000 depends on application - */ - -#define ONENAND_START_BLOCK 4 -#define ONENAND_END_BLOCK 18 -#define ONENAND_PAGE_SIZE 2048 /* 2KB */ -#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ - -#endif /* __CONFIG_H */ - diff --git a/x-loader/include/configs/omap4430panda.h b/x-loader/include/configs/omap4430panda.h deleted file mode 100644 index 74e2f42..0000000 --- a/x-loader/include/configs/omap4430panda.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments - * Richard Woodruff - * - * X-Loader Configuation settings for the TI OMAP SDP3430 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* serial printf facility takes about 3.5K */ -#define CFG_PRINTF -//#undef CFG_PRINTF - -/* - * High Level Configuration Options - */ -#define CONFIG_ARMCORTEXA9 1 /* This is an ARM V7 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP44XX 1 /* which is a 34XX */ -#define CONFIG_OMAP4430 1 /* which is in a 3430 */ -#define CONFIG_4430PANDA 1 /* working with SDP */ - -/* Keep Default @ 33MHz at boot loader level - * On Phoenix board vlotage needs to be bumped up - * before scaling the MPU up - */ -#define CONFIG_MPU_600 1 -#define CORE_190MHZ 1 -/* Enable the below macro if MMC boot support is required */ -#define CONFIG_MMC 1 -#if defined(CONFIG_MMC) - /* To Enable MMC boot for OMAP4430 Panda */ - //#define CONFIG_MMC1 1 - /* To Enable EMMC boot for OMAP4430 Panda */ - #define CONFIG_MMC2 1 - #define CFG_CMD_MMC 1 - #define CFG_CMD_FAT 1 -#endif - -#include /* get chip and board defs */ - -/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ -//#define CFG_UDELAY - -/* Clock Defines */ -#define V_OSCK 19200000 /* Clock output from T2 */ -#define V_SCLK V_OSCK - -/* Memory type */ -#define CFG_4430SDRAM_DDR 1 - -#ifdef CFG_PRINTF - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK (48000000) -#define CFG_NS16550_COM3 OMAP44XX_UART3 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* UART1 on 3430SDP */ -#define CONFIG_CONS_INDEX 3 - -#define CONFIG_BAUDRATE 115200 -#define CFG_PBSIZE 256 - -#endif /* CFG_PRINTF */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LOADADDR 0x80e80000 - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_ENV_SIZE 0x100 -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -#endif /* __CONFIG_H */ - diff --git a/x-loader/include/configs/overo.h b/x-loader/include/configs/overo.h deleted file mode 100644 index 70e3683..0000000 --- a/x-loader/include/configs/overo.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * (C) Copyright 2006 - * Texas Instruments - * Richard Woodruff - * - * X-Loader Configuation settings for the overo board. - * - * Derived from /include/configs/omap3evm.h - * Steve Sakoman - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* serial printf facility takes about 3.5K */ -#define CFG_PRINTF -//#undef CFG_PRINTF - -/* - * High Level Configuration Options - */ -#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ -#define CONFIG_OVERO 1 /* working with overo */ - -/* Enable the below macro if MMC boot support is required */ -#define CONFIG_MMC 1 -#if defined(CONFIG_MMC) - #define CFG_CMD_MMC 1 - #define CFG_CMD_FAT 1 - #define CFG_I2C_SPEED 100000 - #define CFG_I2C_SLAVE 1 - #define CFG_I2C_BUS 0 - #define CFG_I2C_BUS_SELECT 1 - #define CONFIG_DRIVER_OMAP34XX_I2C 1 -#endif - -#include /* get chip and board defs */ - -/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ -//#define CFG_UDELAY - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ - -#if (V_OSCK > 19200000) -#define V_SCLK (V_OSCK >> 1) -#else -#define V_SCLK V_OSCK -#endif - -//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ -#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ -#define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */ - -/* Memory type */ -#define CFG_3430SDRAM_DDR 1 - -/* The actual register values are defined in u-boot- mem.h */ -/* SDRAM Bank Allocation method */ -//#define SDRC_B_R_C 1 -//#define SDRC_B1_R_B0_C 1 -#define SDRC_R_B_C 1 - -#define NAND_BASE_ADR NAND_BASE -#define ONENAND_BASE ONENAND_MAP -#define ONENAND_ADDR ONENAND_BASE - -#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M - -#ifdef CFG_PRINTF - -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE -4 -#define CFG_NS16550_CLK 48000000 -#define CFG_NS16550_COM3 OMAP34XX_UART3 - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 3 /* use UART3 */ -#define CONFIG_CONS_INDEX 3 - -#define CONFIG_BAUDRATE 115200 -#define CFG_PBSIZE 256 - -#endif /* CFG_PRINTF */ - -/* - * Miscellaneous configurable options - */ -#define CFG_LOADADDR 0x80008000 - -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -/*----------------------------------------------------------------------- - * Board NAND Info. - */ - -#define CFG_NAND_K9F1G08R0A -#define NAND_16BIT - -/* NAND is partitioned: - * 0x00000000 - 0x0007FFFF Booting Image - * 0x00080000 - 0x0023FFFF U-Boot Image - * 0x00240000 - 0x0027FFFF U-Boot Env Data (X-loader doesn't care) - * 0x00280000 - 0x0077FFFF Kernel Image - * 0x00780000 - 0x08000000 depends on application - */ -#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */ -#define NAND_UBOOT_END 0x0240000 /* Giving a space of 2 blocks = 256KB */ -#define NAND_BLOCK_SIZE 0x20000 - -#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) -#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) -#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) -#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) - -#ifdef NAND_16BIT -#define WRITE_NAND_COMMAND(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0) -#define WRITE_NAND_ADDRESS(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0) -#define WRITE_NAND(d, adr) \ - do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0) -#define READ_NAND(adr) \ - (*(volatile u16 *)GPMC_NAND_DATA_0) -#define NAND_WAIT_READY() -#define NAND_WP_OFF() \ - do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) -#define NAND_WP_ON() \ - do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) - -#else /* to support 8-bit NAND devices */ -#define WRITE_NAND_COMMAND(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0) -#define WRITE_NAND_ADDRESS(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0) -#define WRITE_NAND(d, adr) \ - do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0) -#define READ_NAND(adr) \ - (*(volatile u8 *)GPMC_NAND_DATA_0); -#define NAND_WAIT_READY() -#define NAND_WP_OFF() \ - do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0) -#define NAND_WP_ON() \ - do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0) - -#endif - -#define NAND_CTL_CLRALE(adr) -#define NAND_CTL_SETALE(adr) -#define NAND_CTL_CLRCLE(adr) -#define NAND_CTL_SETCLE(adr) -#define NAND_DISABLE_CE() -#define NAND_ENABLE_CE() - -/*----------------------------------------------------------------------- - * Board oneNAND Info. - */ -#define CFG_SYNC_BURST_READ 1 - -/* OneNAND is partitioned: - * 0x0000000 - 0x0080000 X-Loader - * 0x0080000 - 0x0240000 U-boot Image - * 0x0240000 - 0x0280000 U-Boot Env Data (X-loader doesn't care) - * 0x0280000 - 0x0780000 Kernel Image - * 0x0780000 - 0x8000000 depends on application - */ - -#define ONENAND_START_BLOCK 4 -#define ONENAND_END_BLOCK 18 -#define ONENAND_PAGE_SIZE 2048 /* 2KB */ -#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ - -#endif /* __CONFIG_H */ - diff --git a/x-loader/include/fat.h b/x-loader/include/fat.h deleted file mode 100644 index 4f70981..0000000 --- a/x-loader/include/fat.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg - * - * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6 - * 2003-03-10 - kharris@nexus-tech.net - ported to u-boot - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _FAT_H_ -#define _FAT_H_ - -#include - -#define CONFIG_SUPPORT_VFAT - -#define SECTOR_SIZE FS_BLOCK_SIZE - -#define FS_BLOCK_SIZE 512 - -#if FS_BLOCK_SIZE != SECTOR_SIZE -#error FS_BLOCK_SIZE != SECTOR_SIZE - This code needs to be fixed! -#endif - -#define MAX_CLUSTSIZE 65536 -#define DIRENTSPERBLOCK (FS_BLOCK_SIZE/sizeof(dir_entry)) -#define DIRENTSPERCLUST ((mydata->clust_size*SECTOR_SIZE)/sizeof(dir_entry)) - -#define FATBUFBLOCKS 6 -#define FATBUFSIZE (FS_BLOCK_SIZE*FATBUFBLOCKS) -#define FAT12BUFSIZE ((FATBUFSIZE*2)/3) -#define FAT16BUFSIZE (FATBUFSIZE/2) -#define FAT32BUFSIZE (FATBUFSIZE/4) - - -/* Filesystem identifiers */ -#define FAT12_SIGN "FAT12 " -#define FAT16_SIGN "FAT16 " -#define FAT32_SIGN "FAT32 " -#define SIGNLEN 8 - -/* File attributes */ -#define ATTR_RO 1 -#define ATTR_HIDDEN 2 -#define ATTR_SYS 4 -#define ATTR_VOLUME 8 -#define ATTR_DIR 16 -#define ATTR_ARCH 32 - -#define ATTR_VFAT (ATTR_RO | ATTR_HIDDEN | ATTR_SYS | ATTR_VOLUME) - -#define DELETED_FLAG ((char)0xe5) /* Marks deleted files when in name[0] */ -#define aRING 0x05 /* Used to represent 'å' in name[0] */ - -/* Indicates that the entry is the last long entry in a set of long - * dir entries - */ -#define LAST_LONG_ENTRY_MASK 0x40 - -/* Flags telling whether we should read a file or list a directory */ -#define LS_NO 0 -#define LS_YES 1 -#define LS_DIR 1 -#define LS_ROOT 2 - -#ifdef DEBUG -#define FAT_DPRINT(args...) printf(args) -#else -#define FAT_DPRINT(args...) -#endif -#define FAT_ERROR(args...) printf(args) - -#define ISDIRDELIM(c) ((c) == '/' || (c) == '\\') - -#define FSTYPE_NONE (-1) - -#if defined(__linux__) && defined(__KERNEL__) -#define FAT2CPU16 le16_to_cpu -#define FAT2CPU32 le32_to_cpu -#else -#if __LITTLE_ENDIAN -#define FAT2CPU16(x) (x) -#define FAT2CPU32(x) (x) -#else -#define FAT2CPU16(x) ((((x) & 0x00ff) << 8) | (((x) & 0xff00) >> 8)) -#define FAT2CPU32(x) ((((x) & 0x000000ff) << 24) | \ - (((x) & 0x0000ff00) << 8) | \ - (((x) & 0x00ff0000) >> 8) | \ - (((x) & 0xff000000) >> 24)) -#endif -#endif - -#define TOLOWER(c) if((c) >= 'A' && (c) <= 'Z'){(c)+=('a' - 'A');} -#define START(dent) (FAT2CPU16((dent)->start) \ - + (mydata->fatsize != 32 ? 0 : \ - (FAT2CPU16((dent)->starthi) << 16))) - - -typedef struct boot_sector { - __u8 ignored[3]; /* Bootstrap code */ - char system_id[8]; /* Name of fs */ - __u8 sector_size[2]; /* Bytes/sector */ - __u8 cluster_size; /* Sectors/cluster */ - __u16 reserved; /* Number of reserved sectors */ - __u8 fats; /* Number of FATs */ - __u8 dir_entries[2]; /* Number of root directory entries */ - __u8 sectors[2]; /* Number of sectors */ - __u8 media; /* Media code */ - __u16 fat_length; /* Sectors/FAT */ - __u16 secs_track; /* Sectors/track */ - __u16 heads; /* Number of heads */ - __u32 hidden; /* Number of hidden sectors */ - __u32 total_sect; /* Number of sectors (if sectors == 0) */ - - /* FAT32 only */ - __u32 fat32_length; /* Sectors/FAT */ - __u16 flags; /* Bit 8: fat mirroring, low 4: active fat */ - __u8 version[2]; /* Filesystem version */ - __u32 root_cluster; /* First cluster in root directory */ - __u16 info_sector; /* Filesystem info sector */ - __u16 backup_boot; /* Backup boot sector */ - __u16 reserved2[6]; /* Unused */ -} boot_sector; - -typedef struct volume_info -{ - __u8 drive_number; /* BIOS drive number */ - __u8 reserved; /* Unused */ - __u8 ext_boot_sign; /* 0x29 if fields below exist (DOS 3.3+) */ - __u8 volume_id[4]; /* Volume ID number */ - char volume_label[11]; /* Volume label */ - char fs_type[8]; /* Typically FAT12, FAT16, or FAT32 */ - /* Boot code comes next, all but 2 bytes to fill up sector */ - /* Boot sign comes last, 2 bytes */ -} volume_info; - -typedef struct dir_entry { - char name[8],ext[3]; /* Name and extension */ - __u8 attr; /* Attribute bits */ - __u8 lcase; /* Case for base and extension */ - __u8 ctime_ms; /* Creation time, milliseconds */ - __u16 ctime; /* Creation time */ - __u16 cdate; /* Creation date */ - __u16 adate; /* Last access date */ - __u16 starthi; /* High 16 bits of cluster in FAT32 */ - __u16 time,date,start;/* Time, date and first cluster */ - __u32 size; /* File size in bytes */ -} dir_entry; - -typedef struct dir_slot { - __u8 id; /* Sequence number for slot */ - __u8 name0_4[10]; /* First 5 characters in name */ - __u8 attr; /* Attribute byte */ - __u8 reserved; /* Unused */ - __u8 alias_checksum;/* Checksum for 8.3 alias */ - __u8 name5_10[12]; /* 6 more characters in name */ - __u16 start; /* Unused */ - __u8 name11_12[4]; /* Last 2 characters in name */ -} dir_slot; - -/* Private filesystem parameters */ -typedef struct { - int fatsize; /* Size of FAT in bits */ - __u16 fatlength; /* Length of FAT in sectors */ - __u16 fat_sect; /* Starting sector of the FAT */ - __u16 rootdir_sect; /* Start sector of root directory */ - __u16 clust_size; /* Size of clusters in sectors */ - short data_begin; /* The sector of the first cluster, can be negative */ - __u32 fatbuf[FATBUFSIZE]; /* Current FAT buffer */ - int fatbufnum; /* Used by get_fatent, init to -1 */ -} fsdata; - -typedef int (file_detectfs_func)(void); -typedef int (file_ls_func)(const char *dir); -typedef long (file_read_func)(const char *filename, void *buffer, - unsigned long maxsize); - -struct filesystem { - file_detectfs_func *detect; - file_ls_func *ls; - file_read_func *read; - const char name[12]; -}; - -/* FAT tables */ -file_detectfs_func file_fat_detectfs; -file_ls_func file_fat_ls; -file_read_func file_fat_read; - -/* Currently this doesn't check if the dir exists or is valid... */ -int file_cd(const char *path); -int file_fat_detectfs(void); -int file_fat_ls(const char *dir); -long file_fat_read(const char *filename, void *buffer, unsigned long maxsize); -const char *file_getfsname(int idx); -int fat_register_device(block_dev_desc_t *dev_desc, int part_no); - -#endif /* _FAT_H_ */ diff --git a/x-loader/include/i2c.h b/x-loader/include/i2c.h deleted file mode 100644 index a51c164..0000000 --- a/x-loader/include/i2c.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * (C) Copyright 2001 - * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * The original I2C interface was - * (C) 2000 by Paolo Scaffardi (arsenio@tin.it) - * AIRVENT SAM s.p.a - RIMINI(ITALY) - * but has been changed substantially. - */ - -#ifndef _I2C_H_ -#define _I2C_H_ - -/* - * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING - * - * The implementation MUST NOT use static or global variables if the - * I2C routines are used to read SDRAM configuration information - * because this is done before the memories are initialized. Limited - * use of stack-based variables are OK (the initial stack size is - * limited). - * - * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING - */ - -/* - * Configuration items. - */ -#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ - -#if defined(CONFIG_I2C_MULTI_BUS) -#define CFG_MAX_I2C_BUS 2 -#define I2C_GET_BUS() i2c_get_bus_num() -#define I2C_SET_BUS(a) i2c_set_bus_num(a) -#else -#define CFG_MAX_I2C_BUS 1 -#define I2C_GET_BUS() 0 -#define I2C_SET_BUS(a) -#endif - -/* define the I2C bus number for RTC and DTT if not already done */ -#if !defined(CFG_RTC_BUS_NUM) -#define CFG_RTC_BUS_NUM 0 -#endif -#if !defined(CFG_DTT_BUS_NUM) -#define CFG_DTT_BUS_NUM 0 -#endif -#if !defined(CFG_SPD_BUS_NUM) -#define CFG_SPD_BUS_NUM 0 -#endif - -/* - * Initialization, must be called once on start up, may be called - * repeatedly to change the speed and slave addresses. - */ -void i2c_init(int speed, int slaveaddr); -#ifdef CFG_I2C_INIT_BOARD -void i2c_init_board(void); -#endif - -/* - * Probe the given I2C chip address. Returns 0 if a chip responded, - * not 0 on failure. - */ -int i2c_probe(uchar chip); - -/* - * Read/Write interface: - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); - -/* - * Utility routines to read/write registers. - */ -uchar i2c_reg_read (uchar chip, uchar reg); -void i2c_reg_write(uchar chip, uchar reg, uchar val); - -/* - * Functions for setting the current I2C bus and its speed - */ - -/* - * i2c_set_bus_num: - * - * Change the active I2C bus. Subsequent read/write calls will - * go to this one. - * - * bus - bus index, zero based - * - * Returns: 0 on success, not 0 on failure - * - */ -int i2c_set_bus_num(unsigned int bus); - -/* - * i2c_get_bus_num: - * - * Returns index of currently active I2C bus. Zero-based. - */ - -unsigned int i2c_get_bus_num(void); - -/* - * i2c_set_bus_speed: - * - * Change the speed of the active I2C bus - * - * speed - bus speed in Hz - * - * Returns: 0 on success, not 0 on failure - * - */ -int i2c_set_bus_speed(unsigned int); - -/* - * i2c_get_bus_speed: - * - * Returns speed of currently active I2C bus in Hz - */ - -unsigned int i2c_get_bus_speed(void); - -#endif /* _I2C_H_ */ diff --git a/x-loader/include/ide.h b/x-loader/include/ide.h deleted file mode 100644 index dfef32f..0000000 --- a/x-loader/include/ide.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _IDE_H -#define _IDE_H - -#define IDE_BUS(dev) (dev >> 1) - -#ifdef CONFIG_IDE_LED - -/* - * LED Port - */ -#define LED_PORT ((uchar *)(PER8_BASE + 0x3000)) -#define LED_IDE1 0x01 -#define LED_IDE2 0x02 -#define DEVICE_LED(d) ((d & 2) | ((d & 2) == 0)) /* depends on bit positions! */ - -#endif /* CONFIG_IDE_LED */ - -#ifdef CFG_64BIT_LBA -typedef uint64_t lbaint_t; -#else -typedef ulong lbaint_t; -#endif - -/* - * Function Prototypes - */ - -void ide_init (void); -ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer); -ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer); - -#endif /* _IDE_H */ diff --git a/x-loader/include/linux/byteorder/big_endian.h b/x-loader/include/linux/byteorder/big_endian.h deleted file mode 100644 index 19b0c86..0000000 --- a/x-loader/include/linux/byteorder/big_endian.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H -#define _LINUX_BYTEORDER_BIG_ENDIAN_H - -#ifndef __BIG_ENDIAN -#define __BIG_ENDIAN 4321 -#endif -#ifndef __BIG_ENDIAN_BITFIELD -#define __BIG_ENDIAN_BITFIELD -#endif -#define __BYTE_ORDER __BIG_ENDIAN - -#include - -#define __constant_htonl(x) ((__u32)(x)) -#define __constant_ntohl(x) ((__u32)(x)) -#define __constant_htons(x) ((__u16)(x)) -#define __constant_ntohs(x) ((__u16)(x)) -#define __constant_cpu_to_le64(x) ___swab64((x)) -#define __constant_le64_to_cpu(x) ___swab64((x)) -#define __constant_cpu_to_le32(x) ___swab32((x)) -#define __constant_le32_to_cpu(x) ___swab32((x)) -#define __constant_cpu_to_le16(x) ___swab16((x)) -#define __constant_le16_to_cpu(x) ___swab16((x)) -#define __constant_cpu_to_be64(x) ((__u64)(x)) -#define __constant_be64_to_cpu(x) ((__u64)(x)) -#define __constant_cpu_to_be32(x) ((__u32)(x)) -#define __constant_be32_to_cpu(x) ((__u32)(x)) -#define __constant_cpu_to_be16(x) ((__u16)(x)) -#define __constant_be16_to_cpu(x) ((__u16)(x)) -#define __cpu_to_le64(x) __swab64((x)) -#define __le64_to_cpu(x) __swab64((x)) -#define __cpu_to_le32(x) __swab32((x)) -#define __le32_to_cpu(x) __swab32((x)) -#define __cpu_to_le16(x) __swab16((x)) -#define __le16_to_cpu(x) __swab16((x)) -#define __cpu_to_be64(x) ((__u64)(x)) -#define __be64_to_cpu(x) ((__u64)(x)) -#define __cpu_to_be32(x) ((__u32)(x)) -#define __be32_to_cpu(x) ((__u32)(x)) -#define __cpu_to_be16(x) ((__u16)(x)) -#define __be16_to_cpu(x) ((__u16)(x)) -#define __cpu_to_le64p(x) __swab64p((x)) -#define __le64_to_cpup(x) __swab64p((x)) -#define __cpu_to_le32p(x) __swab32p((x)) -#define __le32_to_cpup(x) __swab32p((x)) -#define __cpu_to_le16p(x) __swab16p((x)) -#define __le16_to_cpup(x) __swab16p((x)) -#define __cpu_to_be64p(x) (*(__u64*)(x)) -#define __be64_to_cpup(x) (*(__u64*)(x)) -#define __cpu_to_be32p(x) (*(__u32*)(x)) -#define __be32_to_cpup(x) (*(__u32*)(x)) -#define __cpu_to_be16p(x) (*(__u16*)(x)) -#define __be16_to_cpup(x) (*(__u16*)(x)) -#define __cpu_to_le64s(x) __swab64s((x)) -#define __le64_to_cpus(x) __swab64s((x)) -#define __cpu_to_le32s(x) __swab32s((x)) -#define __le32_to_cpus(x) __swab32s((x)) -#define __cpu_to_le16s(x) __swab16s((x)) -#define __le16_to_cpus(x) __swab16s((x)) -#define __cpu_to_be64s(x) do {} while (0) -#define __be64_to_cpus(x) do {} while (0) -#define __cpu_to_be32s(x) do {} while (0) -#define __be32_to_cpus(x) do {} while (0) -#define __cpu_to_be16s(x) do {} while (0) -#define __be16_to_cpus(x) do {} while (0) - -#include - -#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */ diff --git a/x-loader/include/linux/byteorder/generic.h b/x-loader/include/linux/byteorder/generic.h deleted file mode 100644 index cff850f..0000000 --- a/x-loader/include/linux/byteorder/generic.h +++ /dev/null @@ -1,180 +0,0 @@ -#ifndef _LINUX_BYTEORDER_GENERIC_H -#define _LINUX_BYTEORDER_GENERIC_H - -/* - * linux/byteorder_generic.h - * Generic Byte-reordering support - * - * Francois-Rene Rideau 19970707 - * gathered all the good ideas from all asm-foo/byteorder.h into one file, - * cleaned them up. - * I hope it is compliant with non-GCC compilers. - * I decided to put __BYTEORDER_HAS_U64__ in byteorder.h, - * because I wasn't sure it would be ok to put it in types.h - * Upgraded it to 2.1.43 - * Francois-Rene Rideau 19971012 - * Upgraded it to 2.1.57 - * to please Linus T., replaced huge #ifdef's between little/big endian - * by nestedly #include'd files. - * Francois-Rene Rideau 19971205 - * Made it to 2.1.71; now a facelift: - * Put files under include/linux/byteorder/ - * Split swab from generic support. - * - * TODO: - * = Regular kernel maintainers could also replace all these manual - * byteswap macros that remain, disseminated among drivers, - * after some grep or the sources... - * = Linus might want to rename all these macros and files to fit his taste, - * to fit his personal naming scheme. - * = it seems that a few drivers would also appreciate - * nybble swapping support... - * = every architecture could add their byteswap macro in asm/byteorder.h - * see how some architectures already do (i386, alpha, ppc, etc) - * = cpu_to_beXX and beXX_to_cpu might some day need to be well - * distinguished throughout the kernel. This is not the case currently, - * since little endian, big endian, and pdp endian machines needn't it. - * But this might be the case for, say, a port of Linux to 20/21 bit - * architectures (and F21 Linux addict around?). - */ - -/* - * The following macros are to be defined by : - * - * Conversion of long and short int between network and host format - * ntohl(__u32 x) - * ntohs(__u16 x) - * htonl(__u32 x) - * htons(__u16 x) - * It seems that some programs (which? where? or perhaps a standard? POSIX?) - * might like the above to be functions, not macros (why?). - * if that's true, then detect them, and take measures. - * Anyway, the measure is: define only ___ntohl as a macro instead, - * and in a separate file, have - * unsigned long inline ntohl(x){return ___ntohl(x);} - * - * The same for constant arguments - * __constant_ntohl(__u32 x) - * __constant_ntohs(__u16 x) - * __constant_htonl(__u32 x) - * __constant_htons(__u16 x) - * - * Conversion of XX-bit integers (16- 32- or 64-) - * between native CPU format and little/big endian format - * 64-bit stuff only defined for proper architectures - * cpu_to_[bl]eXX(__uXX x) - * [bl]eXX_to_cpu(__uXX x) - * - * The same, but takes a pointer to the value to convert - * cpu_to_[bl]eXXp(__uXX x) - * [bl]eXX_to_cpup(__uXX x) - * - * The same, but change in situ - * cpu_to_[bl]eXXs(__uXX x) - * [bl]eXX_to_cpus(__uXX x) - * - * See asm-foo/byteorder.h for examples of how to provide - * architecture-optimized versions - * - */ - - -#if defined(__KERNEL__) -/* - * inside the kernel, we can use nicknames; - * outside of it, we must avoid POSIX namespace pollution... - */ -#define cpu_to_le64 __cpu_to_le64 -#define le64_to_cpu __le64_to_cpu -#define cpu_to_le32 __cpu_to_le32 -#define le32_to_cpu __le32_to_cpu -#define cpu_to_le16 __cpu_to_le16 -#define le16_to_cpu __le16_to_cpu -#define cpu_to_be64 __cpu_to_be64 -#define be64_to_cpu __be64_to_cpu -#define cpu_to_be32 __cpu_to_be32 -#define be32_to_cpu __be32_to_cpu -#define cpu_to_be16 __cpu_to_be16 -#define be16_to_cpu __be16_to_cpu -#define cpu_to_le64p __cpu_to_le64p -#define le64_to_cpup __le64_to_cpup -#define cpu_to_le32p __cpu_to_le32p -#define le32_to_cpup __le32_to_cpup -#define cpu_to_le16p __cpu_to_le16p -#define le16_to_cpup __le16_to_cpup -#define cpu_to_be64p __cpu_to_be64p -#define be64_to_cpup __be64_to_cpup -#define cpu_to_be32p __cpu_to_be32p -#define be32_to_cpup __be32_to_cpup -#define cpu_to_be16p __cpu_to_be16p -#define be16_to_cpup __be16_to_cpup -#define cpu_to_le64s __cpu_to_le64s -#define le64_to_cpus __le64_to_cpus -#define cpu_to_le32s __cpu_to_le32s -#define le32_to_cpus __le32_to_cpus -#define cpu_to_le16s __cpu_to_le16s -#define le16_to_cpus __le16_to_cpus -#define cpu_to_be64s __cpu_to_be64s -#define be64_to_cpus __be64_to_cpus -#define cpu_to_be32s __cpu_to_be32s -#define be32_to_cpus __be32_to_cpus -#define cpu_to_be16s __cpu_to_be16s -#define be16_to_cpus __be16_to_cpus -#endif - - -/* - * Handle ntohl and suches. These have various compatibility - * issues - like we want to give the prototype even though we - * also have a macro for them in case some strange program - * wants to take the address of the thing or something.. - * - * Note that these used to return a "long" in libc5, even though - * long is often 64-bit these days.. Thus the casts. - * - * They have to be macros in order to do the constant folding - * correctly - if the argument passed into a inline function - * it is no longer constant according to gcc.. - */ - -#undef ntohl -#undef ntohs -#undef htonl -#undef htons - -/* - * Do the prototypes. Somebody might want to take the - * address or some such sick thing.. - */ -#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2) -extern __u32 ntohl(__u32); -extern __u32 htonl(__u32); -#else -extern unsigned long int ntohl(unsigned long int); -extern unsigned long int htonl(unsigned long int); -#endif -extern unsigned short int ntohs(unsigned short int); -extern unsigned short int htons(unsigned short int); - - -#if defined(__GNUC__) && (__GNUC__ >= 2) - -#define ___htonl(x) __cpu_to_be32(x) -#define ___htons(x) __cpu_to_be16(x) -#define ___ntohl(x) __be32_to_cpu(x) -#define ___ntohs(x) __be16_to_cpu(x) - -#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2) -#define htonl(x) ___htonl(x) -#define ntohl(x) ___ntohl(x) -#else -#define htonl(x) ((unsigned long)___htonl(x)) -#define ntohl(x) ((unsigned long)___ntohl(x)) -#endif -#define htons(x) ___htons(x) -#define ntohs(x) ___ntohs(x) - -#endif /* OPTIMIZE */ - - -#endif /* _LINUX_BYTEORDER_GENERIC_H */ diff --git a/x-loader/include/linux/byteorder/little_endian.h b/x-loader/include/linux/byteorder/little_endian.h deleted file mode 100644 index a46f3ec..0000000 --- a/x-loader/include/linux/byteorder/little_endian.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H -#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H - -#ifndef __LITTLE_ENDIAN -#define __LITTLE_ENDIAN 1234 -#endif -#ifndef __LITTLE_ENDIAN_BITFIELD -#define __LITTLE_ENDIAN_BITFIELD -#endif -#define __BYTE_ORDER __LITTLE_ENDIAN - -#include - -#define __constant_htonl(x) ___constant_swab32((x)) -#define __constant_ntohl(x) ___constant_swab32((x)) -#define __constant_htons(x) ___constant_swab16((x)) -#define __constant_ntohs(x) ___constant_swab16((x)) -#define __constant_cpu_to_le64(x) ((__u64)(x)) -#define __constant_le64_to_cpu(x) ((__u64)(x)) -#define __constant_cpu_to_le32(x) ((__u32)(x)) -#define __constant_le32_to_cpu(x) ((__u32)(x)) -#define __constant_cpu_to_le16(x) ((__u16)(x)) -#define __constant_le16_to_cpu(x) ((__u16)(x)) -#define __constant_cpu_to_be64(x) ___constant_swab64((x)) -#define __constant_be64_to_cpu(x) ___constant_swab64((x)) -#define __constant_cpu_to_be32(x) ___constant_swab32((x)) -#define __constant_be32_to_cpu(x) ___constant_swab32((x)) -#define __constant_cpu_to_be16(x) ___constant_swab16((x)) -#define __constant_be16_to_cpu(x) ___constant_swab16((x)) -#define __cpu_to_le64(x) ((__u64)(x)) -#define __le64_to_cpu(x) ((__u64)(x)) -#define __cpu_to_le32(x) ((__u32)(x)) -#define __le32_to_cpu(x) ((__u32)(x)) -#define __cpu_to_le16(x) ((__u16)(x)) -#define __le16_to_cpu(x) ((__u16)(x)) -#define __cpu_to_be64(x) __swab64((x)) -#define __be64_to_cpu(x) __swab64((x)) -#define __cpu_to_be32(x) __swab32((x)) -#define __be32_to_cpu(x) __swab32((x)) -#define __cpu_to_be16(x) __swab16((x)) -#define __be16_to_cpu(x) __swab16((x)) -#define __cpu_to_le64p(x) (*(__u64*)(x)) -#define __le64_to_cpup(x) (*(__u64*)(x)) -#define __cpu_to_le32p(x) (*(__u32*)(x)) -#define __le32_to_cpup(x) (*(__u32*)(x)) -#define __cpu_to_le16p(x) (*(__u16*)(x)) -#define __le16_to_cpup(x) (*(__u16*)(x)) -#define __cpu_to_be64p(x) __swab64p((x)) -#define __be64_to_cpup(x) __swab64p((x)) -#define __cpu_to_be32p(x) __swab32p((x)) -#define __be32_to_cpup(x) __swab32p((x)) -#define __cpu_to_be16p(x) __swab16p((x)) -#define __be16_to_cpup(x) __swab16p((x)) -#define __cpu_to_le64s(x) do {} while (0) -#define __le64_to_cpus(x) do {} while (0) -#define __cpu_to_le32s(x) do {} while (0) -#define __le32_to_cpus(x) do {} while (0) -#define __cpu_to_le16s(x) do {} while (0) -#define __le16_to_cpus(x) do {} while (0) -#define __cpu_to_be64s(x) __swab64s((x)) -#define __be64_to_cpus(x) __swab64s((x)) -#define __cpu_to_be32s(x) __swab32s((x)) -#define __be32_to_cpus(x) __swab32s((x)) -#define __cpu_to_be16s(x) __swab16s((x)) -#define __be16_to_cpus(x) __swab16s((x)) - -#include - -#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */ diff --git a/x-loader/include/linux/byteorder/swab.h b/x-loader/include/linux/byteorder/swab.h deleted file mode 100644 index b1d570e..0000000 --- a/x-loader/include/linux/byteorder/swab.h +++ /dev/null @@ -1,158 +0,0 @@ -#ifndef _LINUX_BYTEORDER_SWAB_H -#define _LINUX_BYTEORDER_SWAB_H - -/* - * linux/byteorder/swab.h - * Byte-swapping, independently from CPU endianness - * swabXX[ps]?(foo) - * - * Francois-Rene Rideau 19971205 - * separated swab functions from cpu_to_XX, - * to clean up support for bizarre-endian architectures. - * - * See asm-i386/byteorder.h and suches for examples of how to provide - * architecture-dependent optimized versions - * - */ - -/* casts are necessary for constants, because we never know how for sure - * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. - */ -#define ___swab16(x) \ - ((__u16)( \ - (((__u16)(x) & (__u16)0x00ffU) << 8) | \ - (((__u16)(x) & (__u16)0xff00U) >> 8) )) -#define ___swab32(x) \ - ((__u32)( \ - (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ - (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ - (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ - (((__u32)(x) & (__u32)0xff000000UL) >> 24) )) -#define ___swab64(x) \ - ((__u64)( \ - (__u64)(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \ - (__u64)(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \ - (__u64)(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \ - (__u64)(((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \ - (__u64)(((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \ - (__u64)(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ - (__u64)(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \ - (__u64)(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56) )) - -/* - * provide defaults when no architecture-specific optimization is detected - */ -#ifndef __arch__swab16 -# define __arch__swab16(x) ___swab16(x) -#endif -#ifndef __arch__swab32 -# define __arch__swab32(x) ___swab32(x) -#endif -#ifndef __arch__swab64 -# define __arch__swab64(x) ___swab64(x) -#endif - -#ifndef __arch__swab16p -# define __arch__swab16p(x) __swab16(*(x)) -#endif -#ifndef __arch__swab32p -# define __arch__swab32p(x) __swab32(*(x)) -#endif -#ifndef __arch__swab64p -# define __arch__swab64p(x) __swab64(*(x)) -#endif - -#ifndef __arch__swab16s -# define __arch__swab16s(x) do { *(x) = __swab16p((x)); } while (0) -#endif -#ifndef __arch__swab32s -# define __arch__swab32s(x) do { *(x) = __swab32p((x)); } while (0) -#endif -#ifndef __arch__swab64s -# define __arch__swab64s(x) do { *(x) = __swab64p((x)); } while (0) -#endif - - -/* - * Allow constant folding - */ -#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) -# define __swab16(x) \ -(__builtin_constant_p((__u16)(x)) ? \ - ___swab16((x)) : \ - __fswab16((x))) -# define __swab32(x) \ -(__builtin_constant_p((__u32)(x)) ? \ - ___swab32((x)) : \ - __fswab32((x))) -# define __swab64(x) \ -(__builtin_constant_p((__u64)(x)) ? \ - ___swab64((x)) : \ - __fswab64((x))) -#else -# define __swab16(x) __fswab16(x) -# define __swab32(x) __fswab32(x) -# define __swab64(x) __fswab64(x) -#endif /* OPTIMIZE */ - - -static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x) -{ - return __arch__swab16(x); -} -static __inline__ __u16 __swab16p(__u16 *x) -{ - return __arch__swab16p(x); -} -static __inline__ void __swab16s(__u16 *addr) -{ - __arch__swab16s(addr); -} - -static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x) -{ - return __arch__swab32(x); -} -static __inline__ __u32 __swab32p(__u32 *x) -{ - return __arch__swab32p(x); -} -static __inline__ void __swab32s(__u32 *addr) -{ - __arch__swab32s(addr); -} - -#ifdef __BYTEORDER_HAS_U64__ -static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x) -{ -# ifdef __SWAB_64_THRU_32__ - __u32 h = x >> 32; - __u32 l = x & ((1ULL<<32)-1); - return (((__u64)__swab32(l)) << 32) | ((__u64)(__swab32(h))); -# else - return __arch__swab64(x); -# endif -} -static __inline__ __u64 __swab64p(__u64 *x) -{ - return __arch__swab64p(x); -} -static __inline__ void __swab64s(__u64 *addr) -{ - __arch__swab64s(addr); -} -#endif /* __BYTEORDER_HAS_U64__ */ - -#if defined(__KERNEL__) -#define swab16 __swab16 -#define swab32 __swab32 -#define swab64 __swab64 -#define swab16p __swab16p -#define swab32p __swab32p -#define swab64p __swab64p -#define swab16s __swab16s -#define swab32s __swab32s -#define swab64s __swab64s -#endif - -#endif /* _LINUX_BYTEORDER_SWAB_H */ diff --git a/x-loader/include/linux/config.h b/x-loader/include/linux/config.h deleted file mode 100644 index a0194cb..0000000 --- a/x-loader/include/linux/config.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _LINUX_CONFIG_H -#define _LINUX_CONFIG_H - -/* #include */ - -#endif diff --git a/x-loader/include/linux/posix_types.h b/x-loader/include/linux/posix_types.h deleted file mode 100644 index bd37e1f..0000000 --- a/x-loader/include/linux/posix_types.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef _LINUX_POSIX_TYPES_H -#define _LINUX_POSIX_TYPES_H - -#include - -/* - * This allows for 1024 file descriptors: if NR_OPEN is ever grown - * beyond that you'll have to change this too. But 1024 fd's seem to be - * enough even for such "real" unices like OSF/1, so hopefully this is - * one limit that doesn't have to be changed [again]. - * - * Note that POSIX wants the FD_CLEAR(fd,fdsetp) defines to be in - * (and thus ) - but this is a more logical - * place for them. Solved by having dummy defines in . - */ - -/* - * Those macros may have been defined in . But we always - * use the ones here. - */ -#undef __NFDBITS -#define __NFDBITS (8 * sizeof(unsigned long)) - -#undef __FD_SETSIZE -#define __FD_SETSIZE 1024 - -#undef __FDSET_LONGS -#define __FDSET_LONGS (__FD_SETSIZE/__NFDBITS) - -#undef __FDELT -#define __FDELT(d) ((d) / __NFDBITS) - -#undef __FDMASK -#define __FDMASK(d) (1UL << ((d) % __NFDBITS)) - -typedef struct { - unsigned long fds_bits [__FDSET_LONGS]; -} __kernel_fd_set; - -/* Type of a signal handler. */ -typedef void (*__kernel_sighandler_t)(int); - -/* Type of a SYSV IPC key. */ -typedef int __kernel_key_t; - -#include - -#endif /* _LINUX_POSIX_TYPES_H */ diff --git a/x-loader/include/linux/stat.h b/x-loader/include/linux/stat.h deleted file mode 100644 index f9422cb..0000000 --- a/x-loader/include/linux/stat.h +++ /dev/null @@ -1,132 +0,0 @@ -#ifndef _LINUX_STAT_H -#define _LINUX_STAT_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define S_IFMT 00170000 /* type of file */ -#define S_IFSOCK 0140000 /* named socket */ -#define S_IFLNK 0120000 /* symbolic link */ -#define S_IFREG 0100000 /* regular */ -#define S_IFBLK 0060000 /* block special */ -#define S_IFDIR 0040000 /* directory */ -#define S_IFCHR 0020000 /* character special */ -#define S_IFIFO 0010000 /* fifo */ -#define S_ISUID 0004000 /* set user id on execution */ -#define S_ISGID 0002000 /* set group id on execution */ -#define S_ISVTX 0001000 /* save swapped text even after use */ - -#define S_ISLNK(m) (((m) & S_IFMT) == S_IFLNK) -#define S_ISREG(m) (((m) & S_IFMT) == S_IFREG) -#define S_ISDIR(m) (((m) & S_IFMT) == S_IFDIR) -#define S_ISCHR(m) (((m) & S_IFMT) == S_IFCHR) -#define S_ISBLK(m) (((m) & S_IFMT) == S_IFBLK) -#define S_ISFIFO(m) (((m) & S_IFMT) == S_IFIFO) -#define S_ISSOCK(m) (((m) & S_IFMT) == S_IFSOCK) - -#define S_IRWXU 00700 /* rwx for owner */ -#define S_IRUSR 00400 /* read permission for owner */ -#define S_IWUSR 00200 /* write permission for owner */ -#define S_IXUSR 00100 /* execute/search permission for owner */ - -#define S_IRWXG 00070 /* rwx for group */ -#define S_IRGRP 00040 /* read permission for group */ -#define S_IWGRP 00020 /* write permission for group */ -#define S_IXGRP 00010 /* execute/search permission for group */ - -#define S_IRWXO 00007 /* rwx for other */ -#define S_IROTH 00004 /* read permission for other */ -#define S_IWOTH 00002 /* read permission for other */ -#define S_IXOTH 00001 /* execute/search permission for other */ - -#ifdef __PPC__ - -struct stat { - dev_t st_dev; /* file system id */ - ino_t st_ino; /* file id */ - mode_t st_mode; /* ownership/protection */ - nlink_t st_nlink; /* number of links */ - uid_t st_uid; /* user id */ - gid_t st_gid; /* group id */ - dev_t st_rdev; - off_t st_size; /* file size in # of bytes */ - unsigned long st_blksize; /* block size */ - unsigned long st_blocks; /* file size in # of blocks */ - unsigned long st_atime; /* time file was last accessed */ - unsigned long __unused1; - unsigned long st_mtime; /* time file was last modified */ - unsigned long __unused2; - unsigned long st_ctime; /* time file status was last changed */ - unsigned long __unused3; - unsigned long __unused4; - unsigned long __unused5; -}; - -#endif /* __PPC__ */ - -#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__) - -struct stat { - unsigned short st_dev; - unsigned short __pad1; - unsigned long st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned short __pad2; - unsigned long st_size; - unsigned long st_blksize; - unsigned long st_blocks; - unsigned long st_atime; - unsigned long __unused1; - unsigned long st_mtime; - unsigned long __unused2; - unsigned long st_ctime; - unsigned long __unused3; - unsigned long __unused4; - unsigned long __unused5; -}; - -#endif /* __ARM__ */ - -#if defined (__MIPS__) - -struct stat { - dev_t st_dev; - long st_pad1[3]; - ino_t st_ino; - mode_t st_mode; - nlink_t st_nlink; - uid_t st_uid; - gid_t st_gid; - dev_t st_rdev; - long st_pad2[2]; - off_t st_size; - long st_pad3; - /* - * Actually this should be timestruc_t st_atime, st_mtime and st_ctime - * but we don't have it under Linux. - */ - time_t st_atime; - long reserved0; - time_t st_mtime; - long reserved1; - time_t st_ctime; - long reserved2; - long st_blksize; - long st_blocks; - long st_pad4[14]; -}; - -#endif /* __MIPS__ */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/x-loader/include/linux/stddef.h b/x-loader/include/linux/stddef.h deleted file mode 100644 index 81e34c2..0000000 --- a/x-loader/include/linux/stddef.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _LINUX_STDDEF_H -#define _LINUX_STDDEF_H - -#undef NULL -#if defined(__cplusplus) -#define NULL 0 -#else -#define NULL ((void *)0) -#endif - -#ifndef _SIZE_T -#include -#endif - -#undef offsetof -#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) - -#endif diff --git a/x-loader/include/linux/time.h b/x-loader/include/linux/time.h deleted file mode 100644 index bf12b99..0000000 --- a/x-loader/include/linux/time.h +++ /dev/null @@ -1,158 +0,0 @@ -#ifndef _LINUX_TIME_H -#define _LINUX_TIME_H - -#include - -#define _DEFUN(a,b,c) a(c) -#define _CONST const -#define _AND , - -#define _REENT_ONLY - -#define SECSPERMIN 60L -#define MINSPERHOUR 60L -#define HOURSPERDAY 24L -#define SECSPERHOUR (SECSPERMIN * MINSPERHOUR) -#define SECSPERDAY (SECSPERHOUR * HOURSPERDAY) -#define DAYSPERWEEK 7 -#define MONSPERYEAR 12 - -#define YEAR_BASE 1900 -#define EPOCH_YEAR 1970 -#define EPOCH_WDAY 4 - -#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0) - - -/* Used by other time functions. */ -struct tm { - int tm_sec; /* Seconds. [0-60] (1 leap second) */ - int tm_min; /* Minutes. [0-59] */ - int tm_hour; /* Hours. [0-23] */ - int tm_mday; /* Day. [1-31] */ - int tm_mon; /* Month. [0-11] */ - int tm_year; /* Year - 1900. */ - int tm_wday; /* Day of week. [0-6] */ - int tm_yday; /* Days in year.[0-365] */ - int tm_isdst; /* DST. [-1/0/1]*/ - -# ifdef __USE_BSD - long int tm_gmtoff; /* Seconds east of UTC. */ - __const char *tm_zone; /* Timezone abbreviation. */ -# else - long int __tm_gmtoff; /* Seconds east of UTC. */ - __const char *__tm_zone; /* Timezone abbreviation. */ -# endif -}; - -static inline char * -_DEFUN (asctime_r, (tim_p, result), - _CONST struct tm *tim_p _AND - char *result) -{ - static _CONST char day_name[7][3] = { - "Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat" - }; - static _CONST char mon_name[12][3] = { - "Jan", "Feb", "Mar", "Apr", "May", "Jun", - "Jul", "Aug", "Sep", "Oct", "Nov", "Dec" - }; - - sprintf (result, "%.3s %.3s %.2d %.2d:%.2d:%.2d %d\n", - day_name[tim_p->tm_wday], - mon_name[tim_p->tm_mon], - tim_p->tm_mday, tim_p->tm_hour, tim_p->tm_min, - tim_p->tm_sec, 1900 + tim_p->tm_year); - return result; -} - -static inline struct tm * -_DEFUN (localtime_r, (tim_p, res), - _CONST time_t * tim_p _AND - struct tm *res) -{ - static _CONST int mon_lengths[2][MONSPERYEAR] = { - {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}, - {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31} - } ; - - static _CONST int year_lengths[2] = { - 365, - 366 - } ; - - long days, rem; - int y; - int yleap; - _CONST int *ip; - - days = ((long) *tim_p) / SECSPERDAY; - rem = ((long) *tim_p) % SECSPERDAY; - while (rem < 0) - { - rem += SECSPERDAY; - --days; - } - while (rem >= SECSPERDAY) - { - rem -= SECSPERDAY; - ++days; - } - - /* compute hour, min, and sec */ - res->tm_hour = (int) (rem / SECSPERHOUR); - rem %= SECSPERHOUR; - res->tm_min = (int) (rem / SECSPERMIN); - res->tm_sec = (int) (rem % SECSPERMIN); - - /* compute day of week */ - if ((res->tm_wday = ((EPOCH_WDAY + days) % DAYSPERWEEK)) < 0) - res->tm_wday += DAYSPERWEEK; - - /* compute year & day of year */ - y = EPOCH_YEAR; - if (days >= 0) - { - for (;;) - { - yleap = isleap(y); - if (days < year_lengths[yleap]) - break; - y++; - days -= year_lengths[yleap]; - } - } - else - { - do - { - --y; - yleap = isleap(y); - days += year_lengths[yleap]; - } while (days < 0); - } - - res->tm_year = y - YEAR_BASE; - res->tm_yday = days; - ip = mon_lengths[yleap]; - for (res->tm_mon = 0; days >= ip[res->tm_mon]; ++res->tm_mon) - days -= ip[res->tm_mon]; - res->tm_mday = days + 1; - - /* set daylight saving time flag */ - res->tm_isdst = -1; - - return (res); -} - -static inline char * -_DEFUN (ctime_r, (tim_p, result), - _CONST time_t * tim_p _AND - char * result) - -{ - struct tm tm; - return asctime_r (localtime_r (tim_p, &tm), result); -} - -#endif diff --git a/x-loader/include/linux/types.h b/x-loader/include/linux/types.h deleted file mode 100644 index df4808f..0000000 --- a/x-loader/include/linux/types.h +++ /dev/null @@ -1,130 +0,0 @@ -#ifndef _LINUX_TYPES_H -#define _LINUX_TYPES_H - -#ifdef __KERNEL__ -#include -#endif - -#include -#include - -#ifndef __KERNEL_STRICT_NAMES - -typedef __kernel_fd_set fd_set; -typedef __kernel_dev_t dev_t; -typedef __kernel_ino_t ino_t; -typedef __kernel_mode_t mode_t; -typedef __kernel_nlink_t nlink_t; -typedef __kernel_off_t off_t; -typedef __kernel_pid_t pid_t; -typedef __kernel_daddr_t daddr_t; -typedef __kernel_key_t key_t; -typedef __kernel_suseconds_t suseconds_t; - -#ifdef __KERNEL__ -typedef __kernel_uid32_t uid_t; -typedef __kernel_gid32_t gid_t; -typedef __kernel_uid16_t uid16_t; -typedef __kernel_gid16_t gid16_t; - -#ifdef CONFIG_UID16 -/* This is defined by include/asm-{arch}/posix_types.h */ -typedef __kernel_old_uid_t old_uid_t; -typedef __kernel_old_gid_t old_gid_t; -#endif /* CONFIG_UID16 */ - -/* libc5 includes this file to define uid_t, thus uid_t can never change - * when it is included by non-kernel code - */ -#else -typedef __kernel_uid_t uid_t; -typedef __kernel_gid_t gid_t; -#endif /* __KERNEL__ */ - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __kernel_loff_t loff_t; -#endif - -/* - * The following typedefs are also protected by individual ifdefs for - * historical reasons: - */ -#ifndef _SIZE_T -#define _SIZE_T -typedef __kernel_size_t size_t; -#endif - -#ifndef _SSIZE_T -#define _SSIZE_T -typedef __kernel_ssize_t ssize_t; -#endif - -#ifndef _PTRDIFF_T -#define _PTRDIFF_T -typedef __kernel_ptrdiff_t ptrdiff_t; -#endif - -#ifndef _TIME_T -#define _TIME_T -typedef __kernel_time_t time_t; -#endif - -#ifndef _CLOCK_T -#define _CLOCK_T -typedef __kernel_clock_t clock_t; -#endif - -#ifndef _CADDR_T -#define _CADDR_T -typedef __kernel_caddr_t caddr_t; -#endif - -/* bsd */ -typedef unsigned char u_char; -typedef unsigned short u_short; -typedef unsigned int u_int; -typedef unsigned long u_long; - -/* sysv */ -typedef unsigned char unchar; -typedef unsigned short ushort; -typedef unsigned int uint; -typedef unsigned long ulong; - -#ifndef __BIT_TYPES_DEFINED__ -#define __BIT_TYPES_DEFINED__ - -typedef __u8 u_int8_t; -typedef __s8 int8_t; -typedef __u16 u_int16_t; -typedef __s16 int16_t; -typedef __u32 u_int32_t; -typedef __s32 int32_t; - -#endif /* !(__BIT_TYPES_DEFINED__) */ - -typedef __u8 uint8_t; -typedef __u16 uint16_t; -typedef __u32 uint32_t; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __u64 uint64_t; -typedef __u64 u_int64_t; -typedef __s64 int64_t; -#endif - -#endif /* __KERNEL_STRICT_NAMES */ - -/* - * Below are truly Linux-specific types that should never collide with - * any application/library that wants linux/types.h. - */ - -struct ustat { - __kernel_daddr_t f_tfree; - __kernel_ino_t f_tinode; - char f_fname[6]; - char f_fpack[6]; -}; - -#endif /* _LINUX_TYPES_H */ diff --git a/x-loader/include/malloc.h b/x-loader/include/malloc.h deleted file mode 100644 index 47154b0..0000000 --- a/x-loader/include/malloc.h +++ /dev/null @@ -1,942 +0,0 @@ -/* - A version of malloc/free/realloc written by Doug Lea and released to the - public domain. Send questions/comments/complaints/performance data - to dl@cs.oswego.edu - -* VERSION 2.6.6 Sun Mar 5 19:10:03 2000 Doug Lea (dl at gee) - - Note: There may be an updated version of this malloc obtainable at - ftp://g.oswego.edu/pub/misc/malloc.c - Check before installing! - -* Why use this malloc? - - This is not the fastest, most space-conserving, most portable, or - most tunable malloc ever written. However it is among the fastest - while also being among the most space-conserving, portable and tunable. - Consistent balance across these factors results in a good general-purpose - allocator. For a high-level description, see - http://g.oswego.edu/dl/html/malloc.html - -* Synopsis of public routines - - (Much fuller descriptions are contained in the program documentation below.) - - malloc(size_t n); - Return a pointer to a newly allocated chunk of at least n bytes, or null - if no space is available. - free(Void_t* p); - Release the chunk of memory pointed to by p, or no effect if p is null. - realloc(Void_t* p, size_t n); - Return a pointer to a chunk of size n that contains the same data - as does chunk p up to the minimum of (n, p's size) bytes, or null - if no space is available. The returned pointer may or may not be - the same as p. If p is null, equivalent to malloc. Unless the - #define REALLOC_ZERO_BYTES_FREES below is set, realloc with a - size argument of zero (re)allocates a minimum-sized chunk. - memalign(size_t alignment, size_t n); - Return a pointer to a newly allocated chunk of n bytes, aligned - in accord with the alignment argument, which must be a power of - two. - valloc(size_t n); - Equivalent to memalign(pagesize, n), where pagesize is the page - size of the system (or as near to this as can be figured out from - all the includes/defines below.) - pvalloc(size_t n); - Equivalent to valloc(minimum-page-that-holds(n)), that is, - round up n to nearest pagesize. - calloc(size_t unit, size_t quantity); - Returns a pointer to quantity * unit bytes, with all locations - set to zero. - cfree(Void_t* p); - Equivalent to free(p). - malloc_trim(size_t pad); - Release all but pad bytes of freed top-most memory back - to the system. Return 1 if successful, else 0. - malloc_usable_size(Void_t* p); - Report the number usable allocated bytes associated with allocated - chunk p. This may or may not report more bytes than were requested, - due to alignment and minimum size constraints. - malloc_stats(); - Prints brief summary statistics on stderr. - mallinfo() - Returns (by copy) a struct containing various summary statistics. - mallopt(int parameter_number, int parameter_value) - Changes one of the tunable parameters described below. Returns - 1 if successful in changing the parameter, else 0. - -* Vital statistics: - - Alignment: 8-byte - 8 byte alignment is currently hardwired into the design. This - seems to suffice for all current machines and C compilers. - - Assumed pointer representation: 4 or 8 bytes - Code for 8-byte pointers is untested by me but has worked - reliably by Wolfram Gloger, who contributed most of the - changes supporting this. - - Assumed size_t representation: 4 or 8 bytes - Note that size_t is allowed to be 4 bytes even if pointers are 8. - - Minimum overhead per allocated chunk: 4 or 8 bytes - Each malloced chunk has a hidden overhead of 4 bytes holding size - and status information. - - Minimum allocated size: 4-byte ptrs: 16 bytes (including 4 overhead) - 8-byte ptrs: 24/32 bytes (including, 4/8 overhead) - - When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte - ptrs but 4 byte size) or 24 (for 8/8) additional bytes are - needed; 4 (8) for a trailing size field - and 8 (16) bytes for free list pointers. Thus, the minimum - allocatable size is 16/24/32 bytes. - - Even a request for zero bytes (i.e., malloc(0)) returns a - pointer to something of the minimum allocatable size. - - Maximum allocated size: 4-byte size_t: 2^31 - 8 bytes - 8-byte size_t: 2^63 - 16 bytes - - It is assumed that (possibly signed) size_t bit values suffice to - represent chunk sizes. `Possibly signed' is due to the fact - that `size_t' may be defined on a system as either a signed or - an unsigned type. To be conservative, values that would appear - as negative numbers are avoided. - Requests for sizes with a negative sign bit when the request - size is treaded as a long will return null. - - Maximum overhead wastage per allocated chunk: normally 15 bytes - - Alignnment demands, plus the minimum allocatable size restriction - make the normal worst-case wastage 15 bytes (i.e., up to 15 - more bytes will be allocated than were requested in malloc), with - two exceptions: - 1. Because requests for zero bytes allocate non-zero space, - the worst case wastage for a request of zero bytes is 24 bytes. - 2. For requests >= mmap_threshold that are serviced via - mmap(), the worst case wastage is 8 bytes plus the remainder - from a system page (the minimal mmap unit); typically 4096 bytes. - -* Limitations - - Here are some features that are NOT currently supported - - * No user-definable hooks for callbacks and the like. - * No automated mechanism for fully checking that all accesses - to malloced memory stay within their bounds. - * No support for compaction. - -* Synopsis of compile-time options: - - People have reported using previous versions of this malloc on all - versions of Unix, sometimes by tweaking some of the defines - below. It has been tested most extensively on Solaris and - Linux. It is also reported to work on WIN32 platforms. - People have also reported adapting this malloc for use in - stand-alone embedded systems. - - The implementation is in straight, hand-tuned ANSI C. Among other - consequences, it uses a lot of macros. Because of this, to be at - all usable, this code should be compiled using an optimizing compiler - (for example gcc -O2) that can simplify expressions and control - paths. - - __STD_C (default: derived from C compiler defines) - Nonzero if using ANSI-standard C compiler, a C++ compiler, or - a C compiler sufficiently close to ANSI to get away with it. - DEBUG (default: NOT defined) - Define to enable debugging. Adds fairly extensive assertion-based - checking to help track down memory errors, but noticeably slows down - execution. - REALLOC_ZERO_BYTES_FREES (default: NOT defined) - Define this if you think that realloc(p, 0) should be equivalent - to free(p). Otherwise, since malloc returns a unique pointer for - malloc(0), so does realloc(p, 0). - HAVE_MEMCPY (default: defined) - Define if you are not otherwise using ANSI STD C, but still - have memcpy and memset in your C library and want to use them. - Otherwise, simple internal versions are supplied. - USE_MEMCPY (default: 1 if HAVE_MEMCPY is defined, 0 otherwise) - Define as 1 if you want the C library versions of memset and - memcpy called in realloc and calloc (otherwise macro versions are used). - At least on some platforms, the simple macro versions usually - outperform libc versions. - HAVE_MMAP (default: defined as 1) - Define to non-zero to optionally make malloc() use mmap() to - allocate very large blocks. - HAVE_MREMAP (default: defined as 0 unless Linux libc set) - Define to non-zero to optionally make realloc() use mremap() to - reallocate very large blocks. - malloc_getpagesize (default: derived from system #includes) - Either a constant or routine call returning the system page size. - HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined) - Optionally define if you are on a system with a /usr/include/malloc.h - that declares struct mallinfo. It is not at all necessary to - define this even if you do, but will ensure consistency. - INTERNAL_SIZE_T (default: size_t) - Define to a 32-bit type (probably `unsigned int') if you are on a - 64-bit machine, yet do not want or need to allow malloc requests of - greater than 2^31 to be handled. This saves space, especially for - very small chunks. - INTERNAL_LINUX_C_LIB (default: NOT defined) - Defined only when compiled as part of Linux libc. - Also note that there is some odd internal name-mangling via defines - (for example, internally, `malloc' is named `mALLOc') needed - when compiling in this case. These look funny but don't otherwise - affect anything. - WIN32 (default: undefined) - Define this on MS win (95, nt) platforms to compile in sbrk emulation. - LACKS_UNISTD_H (default: undefined if not WIN32) - Define this if your system does not have a . - LACKS_SYS_PARAM_H (default: undefined if not WIN32) - Define this if your system does not have a . - MORECORE (default: sbrk) - The name of the routine to call to obtain more memory from the system. - MORECORE_FAILURE (default: -1) - The value returned upon failure of MORECORE. - MORECORE_CLEARS (default 1) - True (1) if the routine mapped to MORECORE zeroes out memory (which - holds for sbrk). - DEFAULT_TRIM_THRESHOLD - DEFAULT_TOP_PAD - DEFAULT_MMAP_THRESHOLD - DEFAULT_MMAP_MAX - Default values of tunable parameters (described in detail below) - controlling interaction with host system routines (sbrk, mmap, etc). - These values may also be changed dynamically via mallopt(). The - preset defaults are those that give best performance for typical - programs/systems. - USE_DL_PREFIX (default: undefined) - Prefix all public routines with the string 'dl'. Useful to - quickly avoid procedure declaration conflicts and linker symbol - conflicts with existing memory allocation routines. - - -*/ - - - - -/* Preliminaries */ - -#ifndef __STD_C -#ifdef __STDC__ -#define __STD_C 1 -#else -#if __cplusplus -#define __STD_C 1 -#else -#define __STD_C 0 -#endif /*__cplusplus*/ -#endif /*__STDC__*/ -#endif /*__STD_C*/ - -#ifndef Void_t -#if (__STD_C || defined(WIN32)) -#define Void_t void -#else -#define Void_t char -#endif -#endif /*Void_t*/ - -#if __STD_C -#include /* for size_t */ -#else -#include -#endif /* __STD_C */ - -#ifdef __cplusplus -extern "C" { -#endif - -#if 0 /* not for U-Boot */ -#include /* needed for malloc_stats */ -#endif - - -/* - Compile-time options -*/ - - -/* - Debugging: - - Because freed chunks may be overwritten with link fields, this - malloc will often die when freed memory is overwritten by user - programs. This can be very effective (albeit in an annoying way) - in helping track down dangling pointers. - - If you compile with -DDEBUG, a number of assertion checks are - enabled that will catch more memory errors. You probably won't be - able to make much sense of the actual assertion errors, but they - should help you locate incorrectly overwritten memory. The - checking is fairly extensive, and will slow down execution - noticeably. Calling malloc_stats or mallinfo with DEBUG set will - attempt to check every non-mmapped allocated and free chunk in the - course of computing the summmaries. (By nature, mmapped regions - cannot be checked very much automatically.) - - Setting DEBUG may also be helpful if you are trying to modify - this code. The assertions in the check routines spell out in more - detail the assumptions and invariants underlying the algorithms. - -*/ - -#ifdef DEBUG -/* #include */ -#define assert(x) ((void)0) -#else -#define assert(x) ((void)0) -#endif - - -/* - INTERNAL_SIZE_T is the word-size used for internal bookkeeping - of chunk sizes. On a 64-bit machine, you can reduce malloc - overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int' - at the expense of not being able to handle requests greater than - 2^31. This limitation is hardly ever a concern; you are encouraged - to set this. However, the default version is the same as size_t. -*/ - -#ifndef INTERNAL_SIZE_T -#define INTERNAL_SIZE_T size_t -#endif - -/* - REALLOC_ZERO_BYTES_FREES should be set if a call to - realloc with zero bytes should be the same as a call to free. - Some people think it should. Otherwise, since this malloc - returns a unique pointer for malloc(0), so does realloc(p, 0). -*/ - - -/* #define REALLOC_ZERO_BYTES_FREES */ - - -/* - WIN32 causes an emulation of sbrk to be compiled in - mmap-based options are not currently supported in WIN32. -*/ - -/* #define WIN32 */ -#ifdef WIN32 -#define MORECORE wsbrk -#define HAVE_MMAP 0 - -#define LACKS_UNISTD_H -#define LACKS_SYS_PARAM_H - -/* - Include 'windows.h' to get the necessary declarations for the - Microsoft Visual C++ data structures and routines used in the 'sbrk' - emulation. - - Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft - Visual C++ header files are included. -*/ -#define WIN32_LEAN_AND_MEAN -#include -#endif - - -/* - HAVE_MEMCPY should be defined if you are not otherwise using - ANSI STD C, but still have memcpy and memset in your C library - and want to use them in calloc and realloc. Otherwise simple - macro versions are defined here. - - USE_MEMCPY should be defined as 1 if you actually want to - have memset and memcpy called. People report that the macro - versions are often enough faster than libc versions on many - systems that it is better to use them. - -*/ - -#define HAVE_MEMCPY - -#ifndef USE_MEMCPY -#ifdef HAVE_MEMCPY -#define USE_MEMCPY 1 -#else -#define USE_MEMCPY 0 -#endif -#endif - -#if (__STD_C || defined(HAVE_MEMCPY)) - -#if __STD_C -void* memset(void*, int, size_t); -void* memcpy(void*, const void*, size_t); -#else -#ifdef WIN32 -/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */ -/* 'windows.h' */ -#else -Void_t* memset(); -Void_t* memcpy(); -#endif -#endif -#endif - -#if USE_MEMCPY - -/* The following macros are only invoked with (2n+1)-multiples of - INTERNAL_SIZE_T units, with a positive integer n. This is exploited - for fast inline execution when n is small. */ - -#define MALLOC_ZERO(charp, nbytes) \ -do { \ - INTERNAL_SIZE_T mzsz = (nbytes); \ - if(mzsz <= 9*sizeof(mzsz)) { \ - INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp); \ - if(mzsz >= 5*sizeof(mzsz)) { *mz++ = 0; \ - *mz++ = 0; \ - if(mzsz >= 7*sizeof(mzsz)) { *mz++ = 0; \ - *mz++ = 0; \ - if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0; \ - *mz++ = 0; }}} \ - *mz++ = 0; \ - *mz++ = 0; \ - *mz = 0; \ - } else memset((charp), 0, mzsz); \ -} while(0) - -#define MALLOC_COPY(dest,src,nbytes) \ -do { \ - INTERNAL_SIZE_T mcsz = (nbytes); \ - if(mcsz <= 9*sizeof(mcsz)) { \ - INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src); \ - INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest); \ - if(mcsz >= 5*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ - *mcdst++ = *mcsrc++; \ - if(mcsz >= 7*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ - *mcdst++ = *mcsrc++; \ - if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ - *mcdst++ = *mcsrc++; }}} \ - *mcdst++ = *mcsrc++; \ - *mcdst++ = *mcsrc++; \ - *mcdst = *mcsrc ; \ - } else memcpy(dest, src, mcsz); \ -} while(0) - -#else /* !USE_MEMCPY */ - -/* Use Duff's device for good zeroing/copying performance. */ - -#define MALLOC_ZERO(charp, nbytes) \ -do { \ - INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp); \ - long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ - if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ - switch (mctmp) { \ - case 0: for(;;) { *mzp++ = 0; \ - case 7: *mzp++ = 0; \ - case 6: *mzp++ = 0; \ - case 5: *mzp++ = 0; \ - case 4: *mzp++ = 0; \ - case 3: *mzp++ = 0; \ - case 2: *mzp++ = 0; \ - case 1: *mzp++ = 0; if(mcn <= 0) break; mcn--; } \ - } \ -} while(0) - -#define MALLOC_COPY(dest,src,nbytes) \ -do { \ - INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src; \ - INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest; \ - long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \ - if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \ - switch (mctmp) { \ - case 0: for(;;) { *mcdst++ = *mcsrc++; \ - case 7: *mcdst++ = *mcsrc++; \ - case 6: *mcdst++ = *mcsrc++; \ - case 5: *mcdst++ = *mcsrc++; \ - case 4: *mcdst++ = *mcsrc++; \ - case 3: *mcdst++ = *mcsrc++; \ - case 2: *mcdst++ = *mcsrc++; \ - case 1: *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; } \ - } \ -} while(0) - -#endif - - -/* - Define HAVE_MMAP to optionally make malloc() use mmap() to - allocate very large blocks. These will be returned to the - operating system immediately after a free(). -*/ - -/*** -#ifndef HAVE_MMAP -#define HAVE_MMAP 1 -#endif -***/ -#undef HAVE_MMAP /* Not available for U-Boot */ - -/* - Define HAVE_MREMAP to make realloc() use mremap() to re-allocate - large blocks. This is currently only possible on Linux with - kernel versions newer than 1.3.77. -*/ - -/*** -#ifndef HAVE_MREMAP -#ifdef INTERNAL_LINUX_C_LIB -#define HAVE_MREMAP 1 -#else -#define HAVE_MREMAP 0 -#endif -#endif -***/ -#undef HAVE_MREMAP /* Not available for U-Boot */ - -#if HAVE_MMAP - -#include -#include -#include - -#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON) -#define MAP_ANONYMOUS MAP_ANON -#endif - -#endif /* HAVE_MMAP */ - -/* - Access to system page size. To the extent possible, this malloc - manages memory from the system in page-size units. - - The following mechanics for getpagesize were adapted from - bsd/gnu getpagesize.h -*/ - -#define LACKS_UNISTD_H /* Shortcut for U-Boot */ -#define malloc_getpagesize 4096 - -#ifndef LACKS_UNISTD_H -# include -#endif - -#ifndef malloc_getpagesize -# ifdef _SC_PAGESIZE /* some SVR4 systems omit an underscore */ -# ifndef _SC_PAGE_SIZE -# define _SC_PAGE_SIZE _SC_PAGESIZE -# endif -# endif -# ifdef _SC_PAGE_SIZE -# define malloc_getpagesize sysconf(_SC_PAGE_SIZE) -# else -# if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE) - extern size_t getpagesize(); -# define malloc_getpagesize getpagesize() -# else -# ifdef WIN32 -# define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */ -# else -# ifndef LACKS_SYS_PARAM_H -# include -# endif -# ifdef EXEC_PAGESIZE -# define malloc_getpagesize EXEC_PAGESIZE -# else -# ifdef NBPG -# ifndef CLSIZE -# define malloc_getpagesize NBPG -# else -# define malloc_getpagesize (NBPG * CLSIZE) -# endif -# else -# ifdef NBPC -# define malloc_getpagesize NBPC -# else -# ifdef PAGESIZE -# define malloc_getpagesize PAGESIZE -# else -# define malloc_getpagesize (4096) /* just guess */ -# endif -# endif -# endif -# endif -# endif -# endif -# endif -#endif - - -/* - - This version of malloc supports the standard SVID/XPG mallinfo - routine that returns a struct containing the same kind of - information you can get from malloc_stats. It should work on - any SVID/XPG compliant system that has a /usr/include/malloc.h - defining struct mallinfo. (If you'd like to install such a thing - yourself, cut out the preliminary declarations as described above - and below and save them in a malloc.h file. But there's no - compelling reason to bother to do this.) - - The main declaration needed is the mallinfo struct that is returned - (by-copy) by mallinfo(). The SVID/XPG malloinfo struct contains a - bunch of fields, most of which are not even meaningful in this - version of malloc. Some of these fields are are instead filled by - mallinfo() with other numbers that might possibly be of interest. - - HAVE_USR_INCLUDE_MALLOC_H should be set if you have a - /usr/include/malloc.h file that includes a declaration of struct - mallinfo. If so, it is included; else an SVID2/XPG2 compliant - version is declared below. These must be precisely the same for - mallinfo() to work. - -*/ - -/* #define HAVE_USR_INCLUDE_MALLOC_H */ - -#if HAVE_USR_INCLUDE_MALLOC_H -#include "/usr/include/malloc.h" -#else - -/* SVID2/XPG mallinfo structure */ - -struct mallinfo { - int arena; /* total space allocated from system */ - int ordblks; /* number of non-inuse chunks */ - int smblks; /* unused -- always zero */ - int hblks; /* number of mmapped regions */ - int hblkhd; /* total space in mmapped regions */ - int usmblks; /* unused -- always zero */ - int fsmblks; /* unused -- always zero */ - int uordblks; /* total allocated space */ - int fordblks; /* total non-inuse space */ - int keepcost; /* top-most, releasable (via malloc_trim) space */ -}; - -/* SVID2/XPG mallopt options */ - -#define M_MXFAST 1 /* UNUSED in this malloc */ -#define M_NLBLKS 2 /* UNUSED in this malloc */ -#define M_GRAIN 3 /* UNUSED in this malloc */ -#define M_KEEP 4 /* UNUSED in this malloc */ - -#endif - -/* mallopt options that actually do something */ - -#define M_TRIM_THRESHOLD -1 -#define M_TOP_PAD -2 -#define M_MMAP_THRESHOLD -3 -#define M_MMAP_MAX -4 - - -#ifndef DEFAULT_TRIM_THRESHOLD -#define DEFAULT_TRIM_THRESHOLD (128 * 1024) -#endif - -/* - M_TRIM_THRESHOLD is the maximum amount of unused top-most memory - to keep before releasing via malloc_trim in free(). - - Automatic trimming is mainly useful in long-lived programs. - Because trimming via sbrk can be slow on some systems, and can - sometimes be wasteful (in cases where programs immediately - afterward allocate more large chunks) the value should be high - enough so that your overall system performance would improve by - releasing. - - The trim threshold and the mmap control parameters (see below) - can be traded off with one another. Trimming and mmapping are - two different ways of releasing unused memory back to the - system. Between these two, it is often possible to keep - system-level demands of a long-lived program down to a bare - minimum. For example, in one test suite of sessions measuring - the XF86 X server on Linux, using a trim threshold of 128K and a - mmap threshold of 192K led to near-minimal long term resource - consumption. - - If you are using this malloc in a long-lived program, it should - pay to experiment with these values. As a rough guide, you - might set to a value close to the average size of a process - (program) running on your system. Releasing this much memory - would allow such a process to run in memory. Generally, it's - worth it to tune for trimming rather tham memory mapping when a - program undergoes phases where several large chunks are - allocated and released in ways that can reuse each other's - storage, perhaps mixed with phases where there are no such - chunks at all. And in well-behaved long-lived programs, - controlling release of large blocks via trimming versus mapping - is usually faster. - - However, in most programs, these parameters serve mainly as - protection against the system-level effects of carrying around - massive amounts of unneeded memory. Since frequent calls to - sbrk, mmap, and munmap otherwise degrade performance, the default - parameters are set to relatively high values that serve only as - safeguards. - - The default trim value is high enough to cause trimming only in - fairly extreme (by current memory consumption standards) cases. - It must be greater than page size to have any useful effect. To - disable trimming completely, you can set to (unsigned long)(-1); - - -*/ - - -#ifndef DEFAULT_TOP_PAD -#define DEFAULT_TOP_PAD (0) -#endif - -/* - M_TOP_PAD is the amount of extra `padding' space to allocate or - retain whenever sbrk is called. It is used in two ways internally: - - * When sbrk is called to extend the top of the arena to satisfy - a new malloc request, this much padding is added to the sbrk - request. - - * When malloc_trim is called automatically from free(), - it is used as the `pad' argument. - - In both cases, the actual amount of padding is rounded - so that the end of the arena is always a system page boundary. - - The main reason for using padding is to avoid calling sbrk so - often. Having even a small pad greatly reduces the likelihood - that nearly every malloc request during program start-up (or - after trimming) will invoke sbrk, which needlessly wastes - time. - - Automatic rounding-up to page-size units is normally sufficient - to avoid measurable overhead, so the default is 0. However, in - systems where sbrk is relatively slow, it can pay to increase - this value, at the expense of carrying around more memory than - the program needs. - -*/ - - -#ifndef DEFAULT_MMAP_THRESHOLD -#define DEFAULT_MMAP_THRESHOLD (128 * 1024) -#endif - -/* - - M_MMAP_THRESHOLD is the request size threshold for using mmap() - to service a request. Requests of at least this size that cannot - be allocated using already-existing space will be serviced via mmap. - (If enough normal freed space already exists it is used instead.) - - Using mmap segregates relatively large chunks of memory so that - they can be individually obtained and released from the host - system. A request serviced through mmap is never reused by any - other request (at least not directly; the system may just so - happen to remap successive requests to the same locations). - - Segregating space in this way has the benefit that mmapped space - can ALWAYS be individually released back to the system, which - helps keep the system level memory demands of a long-lived - program low. Mapped memory can never become `locked' between - other chunks, as can happen with normally allocated chunks, which - menas that even trimming via malloc_trim would not release them. - - However, it has the disadvantages that: - - 1. The space cannot be reclaimed, consolidated, and then - used to service later requests, as happens with normal chunks. - 2. It can lead to more wastage because of mmap page alignment - requirements - 3. It causes malloc performance to be more dependent on host - system memory management support routines which may vary in - implementation quality and may impose arbitrary - limitations. Generally, servicing a request via normal - malloc steps is faster than going through a system's mmap. - - All together, these considerations should lead you to use mmap - only for relatively large requests. - - -*/ - - -#ifndef DEFAULT_MMAP_MAX -#if HAVE_MMAP -#define DEFAULT_MMAP_MAX (64) -#else -#define DEFAULT_MMAP_MAX (0) -#endif -#endif - -/* - M_MMAP_MAX is the maximum number of requests to simultaneously - service using mmap. This parameter exists because: - - 1. Some systems have a limited number of internal tables for - use by mmap. - 2. In most systems, overreliance on mmap can degrade overall - performance. - 3. If a program allocates many large regions, it is probably - better off using normal sbrk-based allocation routines that - can reclaim and reallocate normal heap memory. Using a - small value allows transition into this mode after the - first few allocations. - - Setting to 0 disables all use of mmap. If HAVE_MMAP is not set, - the default value is 0, and attempts to set it to non-zero values - in mallopt will fail. -*/ - - -/* - USE_DL_PREFIX will prefix all public routines with the string 'dl'. - Useful to quickly avoid procedure declaration conflicts and linker - symbol conflicts with existing memory allocation routines. - -*/ - -/* #define USE_DL_PREFIX */ - - -/* - - Special defines for linux libc - - Except when compiled using these special defines for Linux libc - using weak aliases, this malloc is NOT designed to work in - multithreaded applications. No semaphores or other concurrency - control are provided to ensure that multiple malloc or free calls - don't run at the same time, which could be disasterous. A single - semaphore could be used across malloc, realloc, and free (which is - essentially the effect of the linux weak alias approach). It would - be hard to obtain finer granularity. - -*/ - - -#ifdef INTERNAL_LINUX_C_LIB - -#if __STD_C - -Void_t * __default_morecore_init (ptrdiff_t); -Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init; - -#else - -Void_t * __default_morecore_init (); -Void_t *(*__morecore)() = __default_morecore_init; - -#endif - -#define MORECORE (*__morecore) -#define MORECORE_FAILURE 0 -#define MORECORE_CLEARS 1 - -#else /* INTERNAL_LINUX_C_LIB */ - -#if __STD_C -extern Void_t* sbrk(ptrdiff_t); -#else -extern Void_t* sbrk(); -#endif - -#ifndef MORECORE -#define MORECORE sbrk -#endif - -#ifndef MORECORE_FAILURE -#define MORECORE_FAILURE -1 -#endif - -#ifndef MORECORE_CLEARS -#define MORECORE_CLEARS 1 -#endif - -#endif /* INTERNAL_LINUX_C_LIB */ - -#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__) - -#define cALLOc __libc_calloc -#define fREe __libc_free -#define mALLOc __libc_malloc -#define mEMALIGn __libc_memalign -#define rEALLOc __libc_realloc -#define vALLOc __libc_valloc -#define pvALLOc __libc_pvalloc -#define mALLINFo __libc_mallinfo -#define mALLOPt __libc_mallopt - -#pragma weak calloc = __libc_calloc -#pragma weak free = __libc_free -#pragma weak cfree = __libc_free -#pragma weak malloc = __libc_malloc -#pragma weak memalign = __libc_memalign -#pragma weak realloc = __libc_realloc -#pragma weak valloc = __libc_valloc -#pragma weak pvalloc = __libc_pvalloc -#pragma weak mallinfo = __libc_mallinfo -#pragma weak mallopt = __libc_mallopt - -#else - -#ifdef USE_DL_PREFIX -#define cALLOc dlcalloc -#define fREe dlfree -#define mALLOc dlmalloc -#define mEMALIGn dlmemalign -#define rEALLOc dlrealloc -#define vALLOc dlvalloc -#define pvALLOc dlpvalloc -#define mALLINFo dlmallinfo -#define mALLOPt dlmallopt -#else /* USE_DL_PREFIX */ -#define cALLOc calloc -#define fREe free -#define mALLOc malloc -#define mEMALIGn memalign -#define rEALLOc realloc -#define vALLOc valloc -#define pvALLOc pvalloc -#define mALLINFo mallinfo -#define mALLOPt mallopt -#endif /* USE_DL_PREFIX */ - -#endif - -/* Public routines */ - -#if __STD_C - -Void_t* mALLOc(size_t); -void fREe(Void_t*); -Void_t* rEALLOc(Void_t*, size_t); -Void_t* mEMALIGn(size_t, size_t); -Void_t* vALLOc(size_t); -Void_t* pvALLOc(size_t); -Void_t* cALLOc(size_t, size_t); -void cfree(Void_t*); -int malloc_trim(size_t); -size_t malloc_usable_size(Void_t*); -void malloc_stats(void); -int mALLOPt(int, int); -struct mallinfo mALLINFo(void); -#else -Void_t* mALLOc(); -void fREe(); -Void_t* rEALLOc(); -Void_t* mEMALIGn(); -Void_t* vALLOc(); -Void_t* pvALLOc(); -Void_t* cALLOc(); -void cfree(); -int malloc_trim(); -size_t malloc_usable_size(); -void malloc_stats(); -int mALLOPt(); -struct mallinfo mALLINFo(); -#endif - - -#ifdef __cplusplus -}; /* end of extern "C" */ -#endif diff --git a/x-loader/include/mmc.h b/x-loader/include/mmc.h deleted file mode 100644 index 19c76fe..0000000 --- a/x-loader/include/mmc.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _MMC_H_ -#define _MMC_H_ -#include - -/* MMC command numbers */ -#define MMC_CMD_GO_IDLE_STATE 0 -#define MMC_CMD_SEND_OP_COND 1 -#define MMC_CMD_ALL_SEND_CID 2 -#define MMC_CMD_SET_RELATIVE_ADDR 3 -#define MMC_CMD_SET_DSR 4 -#define MMC_CMD_SELECT_CARD 7 -#define MMC_CMD_SEND_CSD 9 -#define MMC_CMD_SEND_CID 10 -#define MMC_CMD_SEND_STATUS 13 -#define MMC_CMD_SET_BLOCKLEN 16 -#define MMC_CMD_READ_SINGLE_BLOCK 17 -#define MMC_CMD_READ_MULTIPLE_BLOCK 18 -#define MMC_CMD_WRITE_BLOCK 24 -#define MMC_CMD_APP_CMD 55 - -/* SD Card command numbers */ -#define SD_CMD_SEND_RELATIVE_ADDR 3 -#define SD_CMD_SWITCH 6 -#define SD_CMD_SEND_IF_COND 8 - -#define SD_CMD_APP_SET_BUS_WIDTH 6 -#define SD_CMD_APP_SEND_OP_COND 41 - -int mmc_init(int verbose); -int mmc_read(ulong src, uchar *dst, int size); -int mmc_write(uchar *src, ulong dst, int size); -int mmc2info(ulong addr); - -#endif /* _MMC_H_ */ diff --git a/x-loader/include/ns16550.h b/x-loader/include/ns16550.h deleted file mode 100644 index 36d2d40..0000000 --- a/x-loader/include/ns16550.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - *This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * NS16550 Serial Port - * originally from linux source (arch/ppc/boot/ns16550.h) - * modified slightly to - * have addresses as offsets from CFG_ISA_BASE - * added a few more definitions - * added prototypes for ns16550.c - * reduced no of com ports to 2 - * modifications (c) Rob Taylor, Flying Pig Systems. 2000. - */ - -#if (CFG_NS16550_REG_SIZE == 1) -struct NS16550 { - unsigned char rbr; /* 0 */ - unsigned char ier; /* 1 */ - unsigned char fcr; /* 2 */ - unsigned char lcr; /* 3 */ - unsigned char mcr; /* 4 */ - unsigned char lsr; /* 5 */ - unsigned char msr; /* 6 */ - unsigned char scr; /* 7 */ -} __attribute__ ((packed)); -#elif (CFG_NS16550_REG_SIZE == 2) -struct NS16550 { - unsigned short rbr; /* 0 */ - unsigned short ier; /* 1 */ - unsigned short fcr; /* 2 */ - unsigned short lcr; /* 3 */ - unsigned short mcr; /* 4 */ - unsigned short lsr; /* 5 */ - unsigned short msr; /* 6 */ - unsigned short scr; /* 7 */ -} __attribute__ ((packed)); -#elif (CFG_NS16550_REG_SIZE == 4) -struct NS16550 { - unsigned long rbr; /* 0 */ - unsigned long ier; /* 1 */ - unsigned long fcr; /* 2 */ - unsigned long lcr; /* 3 */ - unsigned long mcr; /* 4 */ - unsigned long lsr; /* 5 */ - unsigned long msr; /* 6 */ - unsigned long scr; /* 7 */ -} __attribute__ ((packed)); -#elif (CFG_NS16550_REG_SIZE == -4) -struct NS16550 { - unsigned char rbr; /* 0 */ - int pad1:24; - unsigned char ier; /* 1 */ - int pad2:24; - unsigned char fcr; /* 2 */ - int pad3:24; - unsigned char lcr; /* 3 */ - int pad4:24; - unsigned char mcr; /* 4 */ - int pad5:24; - unsigned char lsr; /* 5 */ - int pad6:24; - unsigned char msr; /* 6 */ - int pad7:24; - unsigned char scr; /* 7 */ - int pad8:24; -#if defined(CONFIG_OMAP) - unsigned char mdr1; /* mode select reset TL16C750*/ -#endif -#ifdef CONFIG_OMAP1510 - int pad9:24; - unsigned long pad[10]; - unsigned char osc_12m_sel; - int pad10:24; -#endif -} __attribute__ ((packed)); -#else -#error "Please define NS16550 registers size." -#endif - -#define thr rbr -#define iir fcr -#define dll rbr -#define dlm ier - -typedef volatile struct NS16550 *NS16550_t; - -#define FCR_FIFO_EN 0x01 /* Fifo enable */ -#define FCR_RXSR 0x02 /* Receiver soft reset */ -#define FCR_TXSR 0x04 /* Transmitter soft reset */ - -#define MCR_DTR 0x01 -#define MCR_RTS 0x02 -#define MCR_DMA_EN 0x04 -#define MCR_TX_DFR 0x08 - -#define LCR_WLS_MSK 0x03 /* character length slect mask */ -#define LCR_WLS_5 0x00 /* 5 bit character length */ -#define LCR_WLS_6 0x01 /* 6 bit character length */ -#define LCR_WLS_7 0x02 /* 7 bit character length */ -#define LCR_WLS_8 0x03 /* 8 bit character length */ -#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define LCR_PEN 0x08 /* Parity eneble */ -#define LCR_EPS 0x10 /* Even Parity Select */ -#define LCR_STKP 0x20 /* Stick Parity */ -#define LCR_SBRK 0x40 /* Set Break */ -#define LCR_BKSE 0x80 /* Bank select enable */ - -#define LSR_DR 0x01 /* Data ready */ -#define LSR_OE 0x02 /* Overrun */ -#define LSR_PE 0x04 /* Parity error */ -#define LSR_FE 0x08 /* Framing error */ -#define LSR_BI 0x10 /* Break */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define LSR_TEMT 0x40 /* Xmitter empty */ -#define LSR_ERR 0x80 /* Error */ - -#ifdef CONFIG_OMAP1510 -#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */ -#endif - -/* useful defaults for LCR */ -#define LCR_8N1 0x03 - -void NS16550_init (NS16550_t com_port, int baud_divisor); -void NS16550_putc (NS16550_t com_port, char c); -char NS16550_getc (NS16550_t com_port); -int NS16550_tstc (NS16550_t com_port); -void NS16550_reinit (NS16550_t com_port, int baud_divisor); diff --git a/x-loader/include/part.h b/x-loader/include/part.h deleted file mode 100644 index 318aa3c..0000000 --- a/x-loader/include/part.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _PART_H -#define _PART_H -#include - -typedef struct block_dev_desc { - int if_type; /* type of the interface */ - int dev; /* device number */ - unsigned char part_type; /* partition type */ - unsigned char target; /* target SCSI ID */ - unsigned char lun; /* target LUN */ - unsigned char type; /* device type */ - unsigned char removable; /* removable device */ -#ifdef CONFIG_LBA48 - unsigned char lba48; /* device can use 48bit addr (ATA/ATAPI v7) */ -#endif - lbaint_t lba; /* number of blocks */ - unsigned long blksz; /* block size */ - unsigned char vendor [40+1]; /* IDE model, SCSI Vendor */ - unsigned char product[20+1]; /* IDE Serial no, SCSI product */ - unsigned char revision[8+1]; /* firmware revision */ - unsigned long (*block_read)(int dev, - unsigned long start, - lbaint_t blkcnt, - unsigned long *buffer); -}block_dev_desc_t; - -/* Interface types: */ -#define IF_TYPE_UNKNOWN 0 -#define IF_TYPE_IDE 1 -#define IF_TYPE_SCSI 2 -#define IF_TYPE_ATAPI 3 -#define IF_TYPE_USB 4 -#define IF_TYPE_DOC 5 -#define IF_TYPE_MMC 6 - -/* Part types */ -#define PART_TYPE_UNKNOWN 0x00 -#define PART_TYPE_MAC 0x01 -#define PART_TYPE_DOS 0x02 -#define PART_TYPE_ISO 0x03 -#define PART_TYPE_AMIGA 0x04 - -/* - * Type string for U-Boot bootable partitions - */ -#define BOOT_PART_TYPE "U-Boot" /* primary boot partition type */ -#define BOOT_PART_COMP "PPCBoot" /* PPCBoot compatibility type */ - -/* device types */ -#define DEV_TYPE_UNKNOWN 0xff /* not connected */ -#define DEV_TYPE_HARDDISK 0x00 /* harddisk */ -#define DEV_TYPE_TAPE 0x01 /* Tape */ -#define DEV_TYPE_CDROM 0x05 /* CD-ROM */ -#define DEV_TYPE_OPDISK 0x07 /* optical disk */ - -typedef struct disk_partition { - ulong start; /* # of first block in partition */ - ulong size; /* number of blocks in partition */ - ulong blksz; /* block size in bytes */ - uchar name[32]; /* partition name */ - uchar type[32]; /* string type description */ -} disk_partition_t; - -/* disk/part.c */ -int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); -void print_part (block_dev_desc_t *dev_desc); -void init_part (block_dev_desc_t *dev_desc); -void dev_print(block_dev_desc_t *dev_desc); - - -#ifdef CONFIG_MAC_PARTITION -/* disk/part_mac.c */ -int get_partition_info_mac (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); -void print_part_mac (block_dev_desc_t *dev_desc); -int test_part_mac (block_dev_desc_t *dev_desc); -#endif - -#ifdef CONFIG_DOS_PARTITION -/* disk/part_dos.c */ -int get_partition_info_dos (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); -void print_part_dos (block_dev_desc_t *dev_desc); -int test_part_dos (block_dev_desc_t *dev_desc); -#endif - -#ifdef CONFIG_ISO_PARTITION -/* disk/part_iso.c */ -int get_partition_info_iso (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); -void print_part_iso (block_dev_desc_t *dev_desc); -int test_part_iso (block_dev_desc_t *dev_desc); -#endif - -#ifdef CONFIG_AMIGA_PARTITION -/* disk/part_amiga.c */ -int get_partition_info_amiga (block_dev_desc_t * dev_desc, int part, disk_partition_t *info); -void print_part_amiga (block_dev_desc_t *dev_desc); -int test_part_amiga (block_dev_desc_t *dev_desc); -#endif - -#endif /* _PART_H */ diff --git a/x-loader/lib/Makefile b/x-loader/lib/Makefile deleted file mode 100644 index 32b3798..0000000 --- a/x-loader/lib/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -# -# (C) Copyright 2004 Texas Instruments -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(ARCH).a - -SOBJS = _udivsi3.o _umodsi3.o - -COBJS = board.o ecc.o printf.o div0.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) crv $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/x-loader/lib/_udivsi3.S b/x-loader/lib/_udivsi3.S deleted file mode 100644 index 2cdcd48..0000000 --- a/x-loader/lib/_udivsi3.S +++ /dev/null @@ -1,77 +0,0 @@ -/* # 1 "libgcc1.S" */ -@ libgcc1 routines for ARM cpu. -@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) -dividend .req r0 -divisor .req r1 -result .req r2 -curbit .req r3 -/* ip .req r12 */ -/* sp .req r13 */ -/* lr .req r14 */ -/* pc .req r15 */ - .text - .globl __udivsi3 - .type __udivsi3 ,function - .align 0 - __udivsi3 : - cmp divisor, #0 - beq Ldiv0 - mov curbit, #1 - mov result, #0 - cmp dividend, divisor - bcc Lgot_result -Loop1: - @ Unless the divisor is very big, shift it up in multiples of - @ four bits, since this is the amount of unwinding in the main - @ division loop. Continue shifting until the divisor is - @ larger than the dividend. - cmp divisor, #0x10000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #4 - movcc curbit, curbit, lsl #4 - bcc Loop1 -Lbignum: - @ For very big divisors, we must shift it a bit at a time, or - @ we will be in danger of overflowing. - cmp divisor, #0x80000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #1 - movcc curbit, curbit, lsl #1 - bcc Lbignum -Loop3: - @ Test for possible subtractions, and note which bits - @ are done in the result. On the final pass, this may subtract - @ too much from the dividend, but the result will be ok, since the - @ "bit" will have been shifted out at the bottom. - cmp dividend, divisor - subcs dividend, dividend, divisor - orrcs result, result, curbit - cmp dividend, divisor, lsr #1 - subcs dividend, dividend, divisor, lsr #1 - orrcs result, result, curbit, lsr #1 - cmp dividend, divisor, lsr #2 - subcs dividend, dividend, divisor, lsr #2 - orrcs result, result, curbit, lsr #2 - cmp dividend, divisor, lsr #3 - subcs dividend, dividend, divisor, lsr #3 - orrcs result, result, curbit, lsr #3 - cmp dividend, #0 @ Early termination? - movnes curbit, curbit, lsr #4 @ No, any more bits to do? - movne divisor, divisor, lsr #4 - bne Loop3 -Lgot_result: - mov r0, result - mov pc, lr -Ldiv0: - str lr, [sp, #-4]! - bl __div0 (PLT) - mov r0, #0 @ about as wrong as it could be - ldmia sp!, {pc} - .size __udivsi3 , . - __udivsi3 -/* # 235 "libgcc1.S" */ -/* # 320 "libgcc1.S" */ -/* # 421 "libgcc1.S" */ -/* # 433 "libgcc1.S" */ -/* # 456 "libgcc1.S" */ -/* # 500 "libgcc1.S" */ -/* # 580 "libgcc1.S" */ diff --git a/x-loader/lib/_umodsi3.S b/x-loader/lib/_umodsi3.S deleted file mode 100644 index e4aebe8..0000000 --- a/x-loader/lib/_umodsi3.S +++ /dev/null @@ -1,88 +0,0 @@ -/* # 1 "libgcc1.S" */ -@ libgcc1 routines for ARM cpu. -@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) -/* # 145 "libgcc1.S" */ -dividend .req r0 -divisor .req r1 -overdone .req r2 -curbit .req r3 -/* ip .req r12 */ -/* sp .req r13 */ -/* lr .req r14 */ -/* pc .req r15 */ - .text - .globl __umodsi3 - .type __umodsi3 ,function - .align 0 - __umodsi3 : - cmp divisor, #0 - beq Ldiv0 - mov curbit, #1 - cmp dividend, divisor - movcc pc, lr -Loop1: - @ Unless the divisor is very big, shift it up in multiples of - @ four bits, since this is the amount of unwinding in the main - @ division loop. Continue shifting until the divisor is - @ larger than the dividend. - cmp divisor, #0x10000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #4 - movcc curbit, curbit, lsl #4 - bcc Loop1 -Lbignum: - @ For very big divisors, we must shift it a bit at a time, or - @ we will be in danger of overflowing. - cmp divisor, #0x80000000 - cmpcc divisor, dividend - movcc divisor, divisor, lsl #1 - movcc curbit, curbit, lsl #1 - bcc Lbignum -Loop3: - @ Test for possible subtractions. On the final pass, this may - @ subtract too much from the dividend, so keep track of which - @ subtractions are done, we can fix them up afterwards... - mov overdone, #0 - cmp dividend, divisor - subcs dividend, dividend, divisor - cmp dividend, divisor, lsr #1 - subcs dividend, dividend, divisor, lsr #1 - orrcs overdone, overdone, curbit, ror #1 - cmp dividend, divisor, lsr #2 - subcs dividend, dividend, divisor, lsr #2 - orrcs overdone, overdone, curbit, ror #2 - cmp dividend, divisor, lsr #3 - subcs dividend, dividend, divisor, lsr #3 - orrcs overdone, overdone, curbit, ror #3 - mov ip, curbit - cmp dividend, #0 @ Early termination? - movnes curbit, curbit, lsr #4 @ No, any more bits to do? - movne divisor, divisor, lsr #4 - bne Loop3 - @ Any subtractions that we should not have done will be recorded in - @ the top three bits of "overdone". Exactly which were not needed - @ are governed by the position of the bit, stored in ip. - @ If we terminated early, because dividend became zero, - @ then none of the below will match, since the bit in ip will not be - @ in the bottom nibble. - ands overdone, overdone, #0xe0000000 - moveq pc, lr @ No fixups needed - tst overdone, ip, ror #3 - addne dividend, dividend, divisor, lsr #3 - tst overdone, ip, ror #2 - addne dividend, dividend, divisor, lsr #2 - tst overdone, ip, ror #1 - addne dividend, dividend, divisor, lsr #1 - mov pc, lr -Ldiv0: - str lr, [sp, #-4]! - bl __div0 (PLT) - mov r0, #0 @ about as wrong as it could be - ldmia sp!, {pc} - .size __umodsi3 , . - __umodsi3 -/* # 320 "libgcc1.S" */ -/* # 421 "libgcc1.S" */ -/* # 433 "libgcc1.S" */ -/* # 456 "libgcc1.S" */ -/* # 500 "libgcc1.S" */ -/* # 580 "libgcc1.S" */ diff --git a/x-loader/lib/board.c b/x-loader/lib/board.c deleted file mode 100644 index fc6e86b..0000000 --- a/x-loader/lib/board.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (C) 2005 Texas Instruments. - * - * (C) Copyright 2004 - * Jian Zhang, Texas Instruments, jzhang@ti.com. - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -const char version_string[] = - "Texas Instruments X-Loader 1.4.4ss modified for GTA04 (" __DATE__ " - " __TIME__ ")"; - -int print_info(void) -{ -#ifdef CFG_PRINTF - printf("\n\n%s\n", version_string); -#endif - return 0; -} - -static int init_func_i2c (void) -{ -#ifdef CONFIG_MMC -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); -#endif -#endif - return 0; -} - -typedef int (init_fnc_t) (void); - -init_fnc_t *init_sequence[] = { - cpu_init, /* basic cpu dependent setup */ - board_init, /* basic board dependent setup */ -#ifdef CFG_NS16550_SERIAL - serial_init, /* serial communications setup */ -#endif - print_info, - nand_init, /* board specific nand init */ -#ifdef CONFIG_MMC -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - init_func_i2c, -#endif -#endif - NULL, -}; - -void start_armboot (void) -{ - init_fnc_t **init_fnc_ptr; - int i, size; - uchar *buf; - int *first_instruction; - block_dev_desc_t *dev_desc = NULL; - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - if ((*init_fnc_ptr)() != 0) { - hang (); - } - } - - misc_init_r(); - - buf = (uchar*) CFG_LOADADDR; - *(int *)buf = 0xffffffff; - -#ifdef CONFIG_MMC - /* first try mmc */ - if (mmc_init(1)) { - size = file_fat_read("u-boot.bin", buf, 0); - if (size > 0) { -#ifdef CFG_PRINTF - printf("Loading u-boot.bin (%i bytes) from mmc/sd\n", size); -#endif - buf += size; - } - } -#endif - -#ifdef CONFIG_NAND - - if (buf == (uchar *)CFG_LOADADDR) { - /* if no u-boot on mmc, try onenand or nand, depending upon sysboot */ - if (get_mem_type() == GPMC_ONENAND){ -#ifdef CFG_ONENAND -#ifdef CFG_PRINTF - printf("Loading u-boot.bin from onenand\n"); -#endif - for (i = ONENAND_START_BLOCK; i < ONENAND_END_BLOCK; i++){ - if (!onenand_read_block(buf, i)) - buf += ONENAND_BLOCK_SIZE; - } -#endif - } else if (get_mem_type() == GPMC_NAND){ -#ifdef CFG_NAND_K9F1G08R0A -#ifdef CFG_PRINTF - printf("Loading u-boot.bin from nand\n"); -#endif - for (i = NAND_UBOOT_START; i < NAND_UBOOT_END; i+= NAND_BLOCK_SIZE){ - if (!nand_read_block(buf, i)) - buf += NAND_BLOCK_SIZE; /* advance buf ptr */ - } -#endif - } - } -#endif - - /* if u-boot not found on mmc or - * nand read result is erased data - * then serial boot - */ - first_instruction = (int *)CFG_LOADADDR; - if((buf == (uchar *)CFG_LOADADDR) || (*first_instruction == 0xffffffff)) { - extern int do_load_serial_bin (ulong offset, int baudrate); - printf("u-boot.bin not found or blank nand contents - attempting serial boot . . .\n"); - do_load_serial_bin(CFG_LOADADDR, 115200); - } - - /* go run U-Boot and never return */ - ((init_fnc_t *)CFG_LOADADDR)(); - - /* should never come here */ -} - -void hang (void) -{ - /* call board specific hang function */ - board_hang(); - - /* if board_hang() returns, hang here */ -#ifdef CFG_PRINTF - printf("X-Loader hangs\n"); -#endif - for (;;); -} diff --git a/x-loader/lib/div0.c b/x-loader/lib/div0.c deleted file mode 100644 index 6267bf1..0000000 --- a/x-loader/lib/div0.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Replacement (=dummy) for GNU/Linux division-by zero handler */ -void __div0 (void) -{ - extern void hang (void); - - hang(); -} diff --git a/x-loader/lib/ecc.c b/x-loader/lib/ecc.c deleted file mode 100644 index 28fc40d..0000000 --- a/x-loader/lib/ecc.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * (C) Copyright 2000 Texas Instruments - * - * This file os based on the following u-boot file: - * common/cmd_nand.c - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* - * Pre-calculated 256-way 1 byte column parity - */ -static const u_char nand_ecc_precalc_table[] = { - 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, - 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, - 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, - 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, - 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, - 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, - 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, - 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, - 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, - 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, - 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, - 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, - 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, - 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, - 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, - 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 -}; - - -/* - * Creates non-inverted ECC code from line parity - */ -static void nand_trans_result(u_char reg2, u_char reg3, - u_char *ecc_code) -{ - u_char a, b, i, tmp1, tmp2; - - /* Initialize variables */ - a = b = 0x80; - tmp1 = tmp2 = 0; - - /* Calculate first ECC byte */ - for (i = 0; i < 4; i++) { - if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */ - tmp1 |= b; - b >>= 1; - if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */ - tmp1 |= b; - b >>= 1; - a >>= 1; - } - - /* Calculate second ECC byte */ - b = 0x80; - for (i = 0; i < 4; i++) { - if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */ - tmp2 |= b; - b >>= 1; - if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */ - tmp2 |= b; - b >>= 1; - a >>= 1; - } - - /* Store two of the ECC bytes */ - ecc_code[0] = tmp1; - ecc_code[1] = tmp2; -} - -/* - * Calculate 3 byte ECC code for 256 byte block - */ -/* ECC Calculation is different between NAND and NAND Legacy code - * in U-Boot. If NAND_LEGACY is enabled in u-boot it should be - * enabled in the config file in x-loader also - */ -#ifdef NAND_LEGACY -void nand_calculate_ecc (const u_char *dat, u_char *ecc_code) -{ - u_char idx, reg1, reg3; - int j; - - /* Initialize variables */ - reg1 = reg3 = 0; - ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; - - /* Build up column parity */ - for(j = 0; j < 256; j++) { - - /* Get CP0 - CP5 from table */ - idx = nand_ecc_precalc_table[dat[j]]; - reg1 ^= idx; - - /* All bit XOR = 1 ? */ - if (idx & 0x40) { - reg3 ^= (u_char) j; - } - } - - /* Create non-inverted ECC code from line parity */ - nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code); - - /* Calculate final ECC code */ - ecc_code[0] = ~ecc_code[0]; - ecc_code[1] = ~ecc_code[1]; - ecc_code[2] = ((~reg1) << 2) | 0x03; -} -#else -void nand_calculate_ecc (const u_char *dat, u_char *ecc_code) -{ - u_char idx, reg1, reg2, reg3; - int j; - - /* Initialize variables */ - reg1 = reg2 = reg3 = 0; - ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; - - /* Build up column parity */ - for(j = 0; j < 256; j++) { - - /* Get CP0 - CP5 from table */ - idx = nand_ecc_precalc_table[dat[j]]; - reg1 ^= (idx & 0x3f); - - /* All bit XOR = 1 ? */ - if (idx & 0x40) { - reg3 ^= (u_char) j; - reg2 ^= ~((u_char) j); - } - } - - /* Create non-inverted ECC code from line parity */ - nand_trans_result(reg2, reg3, ecc_code); - - /* Calculate final ECC code */ - ecc_code[0] = ~ecc_code[0]; - ecc_code[1] = ~ecc_code[1]; - ecc_code[2] = ((~reg1) << 2) | 0x03; -} -#endif -/* - * Detect and correct a 1 bit error for 256 byte block - */ -int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc) -{ - u_char a, b, c, d1, d2, d3, add, bit, i; - - /* Do error detection */ - d1 = calc_ecc[0] ^ read_ecc[0]; - d2 = calc_ecc[1] ^ read_ecc[1]; - d3 = calc_ecc[2] ^ read_ecc[2]; - - if ((d1 | d2 | d3) == 0) { - /* No errors */ - return 0; - } - else { - a = (d1 ^ (d1 >> 1)) & 0x55; - b = (d2 ^ (d2 >> 1)) & 0x55; - c = (d3 ^ (d3 >> 1)) & 0x54; - - /* Found and will correct single bit error in the data */ - if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { - c = 0x80; - add = 0; - a = 0x80; - for (i=0; i<4; i++) { - if (d1 & c) - add |= a; - c >>= 2; - a >>= 1; - } - c = 0x80; - for (i=0; i<4; i++) { - if (d2 & c) - add |= a; - c >>= 2; - a >>= 1; - } - bit = 0; - b = 0x04; - c = 0x80; - for (i=0; i<3; i++) { - if (d3 & c) - bit |= b; - c >>= 2; - b >>= 1; - } - b = 0x01; - a = dat[add]; - a ^= (b << bit); - dat[add] = a; - return 1; - } - else { - i = 0; - while (d1) { - if (d1 & 0x01) - ++i; - d1 >>= 1; - } - while (d2) { - if (d2 & 0x01) - ++i; - d2 >>= 1; - } - while (d3) { - if (d3 & 0x01) - ++i; - d3 >>= 1; - } - if (i == 1) { - /* ECC Code Error Correction */ - read_ecc[0] = calc_ecc[0]; - read_ecc[1] = calc_ecc[1]; - read_ecc[2] = calc_ecc[2]; - return 2; - } - else { - /* Uncorrectable Error */ - return -1; - } - } - } - - /* Should never happen */ - return -1; -} - diff --git a/x-loader/lib/printf.c b/x-loader/lib/printf.c deleted file mode 100644 index 91d22fc..0000000 --- a/x-loader/lib/printf.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * (C) Copyright 2004 Texas Instruments - * - * Based on the following file: - * linux/lib/vsprintf.c - * - * Copyright (C) 1991, 1992 Linus Torvalds - */ - -/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */ -/* - * Wirzenius wrote this portably, Torvalds fucked it up :-) - */ - -#include -#include - -#ifdef CFG_PRINTF - -/* we use this so that we can do without the ctype library */ -#define is_digit(c) ((c) >= '0' && (c) <= '9') - -size_t strnlen(const char * s, size_t count) -{ - const char *sc; - - for (sc = s; count-- && *sc != '\0'; ++sc) - /* nothing */; - return sc - s; -} - -static int skip_atoi(const char **s) -{ - int i=0; - - while (is_digit(**s)) - i = i*10 + *((*s)++) - '0'; - return i; -} - -#define ZEROPAD 1 /* pad with zero */ -#define SIGN 2 /* unsigned/signed long */ -#define PLUS 4 /* show plus */ -#define SPACE 8 /* space if plus */ -#define LEFT 16 /* left justified */ -#define SPECIAL 32 /* 0x */ -#define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ - -#define do_div(n,base) ({ \ -int __res; \ -__res = ((unsigned long) n) % (unsigned) base; \ -n = ((unsigned long) n) / (unsigned) base; \ -__res; }) - -static char * number(char * str, long num, int base, int size, int precision - ,int type) -{ - char c,sign,tmp[66]; - const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; - int i; - - if (type & LARGE) - digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; - if (type & LEFT) - type &= ~ZEROPAD; - if (base < 2 || base > 36) - return 0; - c = (type & ZEROPAD) ? '0' : ' '; - sign = 0; - if (type & SIGN) { - if (num < 0) { - sign = '-'; - num = -num; - size--; - } else if (type & PLUS) { - sign = '+'; - size--; - } else if (type & SPACE) { - sign = ' '; - size--; - } - } - if (type & SPECIAL) { - if (base == 16) - size -= 2; - else if (base == 8) - size--; - } - i = 0; - if (num == 0) - tmp[i++]='0'; - else while (num != 0) - tmp[i++] = digits[do_div(num,base)]; - if (i > precision) - precision = i; - size -= precision; - if (!(type&(ZEROPAD+LEFT))) - while(size-->0) - *str++ = ' '; - if (sign) - *str++ = sign; - if (type & SPECIAL) { - if (base==8) - *str++ = '0'; - else if (base==16) { - *str++ = '0'; - *str++ = digits[33]; - } - } - if (!(type & LEFT)) - while (size-- > 0) - *str++ = c; - while (i < precision--) - *str++ = '0'; - while (i-- > 0) - *str++ = tmp[i]; - while (size-- > 0) - *str++ = ' '; - return str; -} - - -static int vsprintf(char *buf, const char *fmt, va_list args) -{ - int len; - unsigned long num; - int i, base; - char * str; - const char *s; - - int flags; /* flags to number() */ - - int field_width; /* width of output field */ - int precision; /* min. # of digits for integers; max - number of chars for from string */ - int qualifier; /* 'h', 'l', or 'L' for integer fields */ - - for (str=buf ; *fmt ; ++fmt) { - if (*fmt != '%') { - *str++ = *fmt; - continue; - } - - /* process flags */ - flags = 0; - repeat: - ++fmt; /* this also skips first '%' */ - switch (*fmt) { - case '-': flags |= LEFT; goto repeat; - case '+': flags |= PLUS; goto repeat; - case ' ': flags |= SPACE; goto repeat; - case '#': flags |= SPECIAL; goto repeat; - case '0': flags |= ZEROPAD; goto repeat; - } - - /* get field width */ - field_width = -1; - if (is_digit(*fmt)) - field_width = skip_atoi(&fmt); - else if (*fmt == '*') { - ++fmt; - /* it's the next argument */ - field_width = va_arg(args, int); - if (field_width < 0) { - field_width = -field_width; - flags |= LEFT; - } - } - - /* get the precision */ - precision = -1; - if (*fmt == '.') { - ++fmt; - if (is_digit(*fmt)) - precision = skip_atoi(&fmt); - else if (*fmt == '*') { - ++fmt; - /* it's the next argument */ - precision = va_arg(args, int); - } - if (precision < 0) - precision = 0; - } - - /* get the conversion qualifier */ - qualifier = -1; - if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') { - qualifier = *fmt; - ++fmt; - } - - /* default base */ - base = 10; - - switch (*fmt) { - case 'c': - if (!(flags & LEFT)) - while (--field_width > 0) - *str++ = ' '; - *str++ = (unsigned char) va_arg(args, int); - while (--field_width > 0) - *str++ = ' '; - continue; - - case 's': - s = va_arg(args, char *); - if (!s) - s = ""; - - len = strnlen(s, precision); - - if (!(flags & LEFT)) - while (len < field_width--) - *str++ = ' '; - for (i = 0; i < len; ++i) - *str++ = *s++; - while (len < field_width--) - *str++ = ' '; - continue; - - case 'p': - if (field_width == -1) { - field_width = 2*sizeof(void *); - flags |= ZEROPAD; - } - str = number(str, - (unsigned long) va_arg(args, void *), 16, - field_width, precision, flags); - continue; - - - case 'n': - if (qualifier == 'l') { - long * ip = va_arg(args, long *); - *ip = (str - buf); - } else { - int * ip = va_arg(args, int *); - *ip = (str - buf); - } - continue; - - case '%': - *str++ = '%'; - continue; - - /* integer number formats - set up the flags and "break" */ - case 'o': - base = 8; - break; - - case 'X': - flags |= LARGE; - case 'x': - base = 16; - break; - - case 'd': - case 'i': - flags |= SIGN; - case 'u': - break; - - default: - *str++ = '%'; - if (*fmt) - *str++ = *fmt; - else - --fmt; - continue; - } - if (qualifier == 'l') - num = va_arg(args, unsigned long); - else if (qualifier == 'h') { - num = (unsigned short) va_arg(args, int); - if (flags & SIGN) - num = (short) num; - } else if (flags & SIGN) - num = va_arg(args, int); - else - num = va_arg(args, unsigned int); - str = number(str, num, base, field_width, precision, flags); - } - *str = '\0'; - return str-buf; -} - -void serial_printf (const char *fmt, ...) -{ - va_list args; - uint i; - char printbuffer[CFG_PBSIZE]; - - va_start (args, fmt); - - /* For this to work, printbuffer must be larger than - * anything we ever want to print. - */ - i = vsprintf (printbuffer, fmt, args); - va_end (args); - - /* Print the string */ - serial_puts (printbuffer); -} -#endif diff --git a/x-loader/mkconfig b/x-loader/mkconfig deleted file mode 100755 index 54c5268..0000000 --- a/x-loader/mkconfig +++ /dev/null @@ -1,63 +0,0 @@ -#!/bin/sh -e - -# Script to create header files and links to configure -# X-Loader for a specific board. -# -# Parameters: Target Architecture CPU Board -# -# (C) 2004 Texas Instruments -# (C) 2002 DENX Software Engineering, Wolfgang Denk -# - -APPEND=no # Default: Create new config file - -while [ $# -gt 0 ] ; do - case "$1" in - --) shift ; break ;; - -a) shift ; APPEND=yes ;; - *) break ;; - esac -done - -[ $# -lt 4 ] && exit 1 -[ $# -gt 5 ] && exit 1 - -echo "Configuring for $1 board..." - -# -# Create link to architecture specific headers -# -if [ "$SRCTREE" != "$OBJTREE" ] ; then - mkdir -p ${OBJTREE}/include - cd ${OBJTREE}/include - mkdir -p asm - rm -f asm/arch - ln -s ${SRCTREE}/include/asm/arch-$3 asm/arch -else - cd ./include - rm -f asm/arch - ln -s arch-$3 asm/arch -fi - -# -# Create include file for Make -# -echo "ARCH = $2" > config.mk -echo "CPU = $3" >> config.mk -echo "BOARD = $4" >> config.mk - -[ "$5" ] && echo "VENDOR = $5" >> config.mk - -# -# Create board specific header file -# -if [ "$APPEND" = "yes" ] # Append to existing config file -then - echo >> config.h -else - > config.h # Create new config file -fi -echo "/* Automatically generated - do not edit */" >>config.h -echo "#include " >>config.h - -exit 0 diff --git a/x-loader/rules.mk b/x-loader/rules.mk deleted file mode 100644 index 107f2a3..0000000 --- a/x-loader/rules.mk +++ /dev/null @@ -1,35 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -######################################################################### - -_depend: $(obj).depend - -$(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(SRCS) - @rm -f $@ - @for f in $(SRCS); do \ - g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \ - $(CC) -M $(HOST_CFLAGS) $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \ - done - -######################################################################### diff --git a/x-loader/scripts/mkoneboot.sh b/x-loader/scripts/mkoneboot.sh deleted file mode 100644 index f0862a5..0000000 --- a/x-loader/scripts/mkoneboot.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh - -IMAGE1=x-load.bin.ift -IMAGE2=x-load-signed.ift -TMP=oneloader -PAGESIZE=2048 - -size=`ls -la $IMAGE1 | awk -F' ' '{ printf $5}'` -let remain=$PAGESIZE-$size -dd if=/dev/zero of=$IMAGE2 bs=1 count=512 -#dd if=/dev/zero of=zerofile bs=$remain count=1 > /dev/null 2> /dev/null -cat $IMAGE1>>$IMAGE2 - -rm -f $IMAGE1 - -echo "Create $IMAGE2 completed..." diff --git a/x-loader/scripts/signGP.c b/x-loader/scripts/signGP.c deleted file mode 100644 index 963a937..0000000 --- a/x-loader/scripts/signGP.c +++ /dev/null @@ -1,300 +0,0 @@ -/** - * signGP.c - Read the x-load.bin file and write out the x-load.bin.ift file - * - * The signed image is the original pre-pended with the size of the image - * and the load address. If not entered on command line, file name is - * assumed to be x-load.bin in current directory and load address is - * 0x40200800. - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 of - * the License as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include -#include - -#undef CH_WITH_CHRAM -struct chsettings { - __u32 section_key; - __u8 valid; - __u8 version; - __u16 reserved; - __u32 flags; -} __attribute__ ((__packed__)); - -/* __u32 cm_clksel_core; - __u32 reserved1; - __u32 cm_autoidle_dpll_mpu; - __u32 cm_clksel_dpll_mpu; - __u32 cm_div_m2_dpll_mpu; - __u32 cm_autoidle_dpll_core; - __u32 cm_clksel_dpll_core; - __u32 cm_div_m2_dpll_core; - __u32 cm_div_m3_dpll_core; - __u32 cm_div_m4_dpll_core; - __u32 cm_div_m5_dpll_core; - __u32 cm_div_m6_dpll_core; - __u32 cm_div_m7_dpll_core; - __u32 cm_autoidle_dpll_per; - __u32 cm_clksel_dpll_per; - __u32 cm_div_m2_dpll_per; - __u32 cm_div_m3_dpll_per; - __u32 cm_div_m4_dpll_per; - __u32 cm_div_m5_dpll_per; - __u32 cm_div_m6_dpll_per; - __u32 cm_div_m7_dpll_per; - __u32 cm_autoidle_dpll_usb; - __u32 cm_clksel_dpll_usb; - __u32 cm_div_m2_dpll_usb; -}*/ - -struct gp_header { - __u32 size; - __u32 load_addr; -} __attribute__ ((__packed__)); - -struct ch_toc { - __u32 section_offset; - __u32 section_size; - __u8 unused[12]; - __u8 section_name[12]; -} __attribute__ ((__packed__)); - -struct chram { - /* CHRAM */ - __u32 section_key_chr; - __u8 section_disable_chr; - __u8 pad_chr[3]; - /* EMIF1 */ - __u32 config_emif1; - __u32 refresh_emif1; - __u32 tim1_emif1; - __u32 tim2_emif1; - __u32 tim3_emif1; - __u32 pwrControl_emif1; - __u32 phy_cntr1_emif1; - __u32 phy_cntr2_emif1; - __u8 modereg1_emif1; - __u8 modereg2_emif1; - __u8 modereg3_emif1; - __u8 pad_emif1; - /* EMIF2 */ - __u32 config_emif2; - __u32 refresh_emif2; - __u32 tim1_emif2; - __u32 tim2_emif2; - __u32 tim3_emif2; - __u32 pwrControl_emif2; - __u32 phy_cntr1_emif2; - __u32 phy_cntr2_emif2; - __u8 modereg1_emif2; - __u8 modereg2_emif2; - __u8 modereg3_emif2; - __u8 pad_emif2; - - __u32 dmm_lisa_map; - __u8 flags; - __u8 pad[3]; -} __attribute__ ((__packed__)); - - -struct ch_chsettings_chram { - struct ch_toc toc_chsettings; - struct ch_toc toc_chram; - struct ch_toc toc_terminator; - struct chsettings section_chsettings; - struct chram section_chram; - __u8 padding1[512 - - (sizeof(struct ch_toc) * 3 + - sizeof(struct chsettings) + sizeof(struct chram))]; - /* struct gp_header gpheader; */ -} __attribute__ ((__packed__)); - -struct ch_chsettings_nochram { - struct ch_toc toc_chsettings; - struct ch_toc toc_terminator; - struct chsettings section_chsettings; - __u8 padding1[512 - - (sizeof(struct ch_toc) * 2 + - sizeof(struct chsettings))]; - /* struct gp_header gpheader; */ -} __attribute__ ((__packed__)); - - -#ifdef CH_WITH_CHRAM -static const struct ch_chsettings_chram config_header = { - /* CHSETTINGS TOC */ - {sizeof(struct ch_toc) * 4, - sizeof(struct chsettings), - "", - {"CHSETTINGS"} - }, - /* CHRAM TOC */ - {sizeof(struct ch_toc) * 4 + sizeof(struct chsettings), - sizeof(struct chram), - "", - {"CHRAM"} - }, - /* toc terminator */ - {0xFFFFFFFF, - 0xFFFFFFFF, - {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF}, - {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF} - }, - /* CHSETTINGS section */ - { - 0xC0C0C0C1, - 0, - 1, - 0, - 0}, - /* CHRAM section */ - { - 0xc0c0c0c2, - 0x01, - {0x00, 0x00, 0x00}, - - /* EMIF1 */ - 0x80800eb2, - 0x00000010, - 0x110d1624, - 0x3058161b, - 0x030060b2, - 0x00000200, - 0x901ff416, - 0x00000000, - 0x23, - 0x01, - 0x02, - 0x00, - - /* EMIF2 */ - 0x80800eb2, - 0x000002ba, - 0x110d1624, - 0x3058161b, - 0x03006542, - 0x00000200, - 0x901ff416, - 0x00000000, - 0x23, - 0x01, - 0x02, - 0x00, - - /* LISA map */ - 0x80700100, - 0x05, - {0x00, 0x00, 0x00}, - }, - "" -}; -#else -static struct ch_chsettings_nochram config_header - __attribute__((section(".config_header"))) = { - /* CHSETTINGS TOC */ - {(sizeof(struct ch_toc)) * 2, - sizeof(struct chsettings), - "", - {"CHSETTINGS"} - }, - /* toc terminator */ - {0xFFFFFFFF, - 0xFFFFFFFF, - {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF}, - {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF} - }, - /* CHSETTINGS section */ - { - 0xC0C0C0C1, - 0, - 1, - 0, - 0}, - "" -}; -#endif - - -int main(int argc, char *argv[]) -{ - int i; - char ifname[FILENAME_MAX], ofname[FILENAME_MAX], ch; - FILE *ifile, *ofile; - unsigned long loadaddr, len; - struct stat sinfo; - - - /* Default to x-load.bin and 0x40200800. */ - strcpy(ifname, "x-load.bin"); - loadaddr = 0x40200800; - - if ((argc == 2) || (argc == 3)) - strcpy(ifname, argv[1]); - - if (argc == 3) - loadaddr = strtoul(argv[2], NULL, 16); - - /* Form the output file name. */ - strcpy(ofname, ifname); - strcat(ofname, ".ift"); - - /* Open the input file. */ - ifile = fopen(ifname, "rb"); - if (ifile == NULL) { - printf("Cannot open %s\n", ifname); - return 1; - } - - /* Get file length. */ - stat(ifname, &sinfo); - len = sinfo.st_size; - - /* Open the output file and write it. */ - ofile = fopen(ofname, "wb"); - if (ofile == NULL) { - printf("Cannot open %s\n", ofname); - fclose(ifile); - return 1; - } - - /* Pad 1 sector of zeroes. */ -#if 0 - ch = 0x00; - for (i = 0; i < 0x200; i++) - fwrite(&ch, 1, 1, ofile); -#endif - - fwrite(&config_header, 1, 512, ofile); - fwrite(&len, 1, 4, ofile); - fwrite(&loadaddr, 1, 4, ofile); - for (i = 0; i < len; i++) { - fread(&ch, 1, 1, ifile); - fwrite(&ch, 1, 1, ofile); - } - - fclose(ifile); - fclose(ofile); - - return 0; -} -- cgit v1.1