From e1bbb64ec2ca8ddf1dec91ae1e08ef96ee53639a Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Tue, 11 Jan 2011 17:31:17 +0100 Subject: fixed issue with submodules --- uart-loader | 1 - uart-loader/.gitignore | 50 ++ uart-loader/Makefile | 222 +++++ uart-loader/README | 152 ++++ uart-loader/arm_config.mk | 24 + uart-loader/board/omap3430labrador/Makefile | 47 ++ uart-loader/board/omap3430labrador/config.mk | 22 + .../board/omap3430labrador/omap3430labrador.c | 875 +++++++++++++++++++ uart-loader/board/omap3430labrador/platform.S | 218 +++++ uart-loader/common/Makefile | 48 ++ uart-loader/common/cmd_load.c | 829 ++++++++++++++++++ uart-loader/config.mk | 175 ++++ uart-loader/cpu/omap3/Makefile | 43 + uart-loader/cpu/omap3/config.mk | 32 + uart-loader/cpu/omap3/cpu.c | 51 ++ uart-loader/cpu/omap3/mmc.c | 1 + uart-loader/cpu/omap3/mmc_host_def.h | 1 + uart-loader/cpu/omap3/mmc_protocol.h | 1 + uart-loader/cpu/omap3/start.S | 230 +++++ uart-loader/cpu/omap3/sys_info.c | 82 ++ uart-loader/disk/Makefile | 44 + uart-loader/disk/part.c | 273 ++++++ uart-loader/drivers/Makefile | 70 ++ uart-loader/drivers/k9f1g08r0a.c | 512 ++++++++++++ uart-loader/drivers/k9f5616.c | 229 +++++ uart-loader/drivers/k9k1216.c | 258 ++++++ uart-loader/drivers/ns16550.c | 69 ++ uart-loader/drivers/onenand.c | 203 +++++ uart-loader/drivers/onenand_regs.h | 167 ++++ uart-loader/drivers/serial.c | 119 +++ uart-loader/fs/Makefile | 29 + uart-loader/fs/fat/Makefile | 46 + uart-loader/fs/fat/fat.c | 927 +++++++++++++++++++++ uart-loader/fs/fat/file.c | 208 +++++ uart-loader/include/asm/arch-arm1136/bits.h | 49 ++ uart-loader/include/asm/arch-arm1136/clocks.h | 1 + uart-loader/include/asm/arch-arm1136/clocks242x.h | 1 + uart-loader/include/asm/arch-arm1136/clocks243x.h | 1 + uart-loader/include/asm/arch-arm1136/mem.h | 1 + uart-loader/include/asm/arch-arm1136/omap2420.h | 223 +++++ uart-loader/include/asm/arch-arm1136/omap2430.h | 255 ++++++ uart-loader/include/asm/arch-arm1136/sizes.h | 50 ++ uart-loader/include/asm/arch-arm1136/sys_info.h | 139 +++ uart-loader/include/asm/arch-arm926ejs/sizes.h | 51 ++ uart-loader/include/asm/arch-omap3/bits.h | 1 + uart-loader/include/asm/arch-omap3/clocks.h | 1 + uart-loader/include/asm/arch-omap3/clocks343x.h | 1 + uart-loader/include/asm/arch-omap3/cpu.h | 1 + .../include/asm/arch-omap3/dpll_table_34xx.S | 1 + .../include/asm/arch-omap3/dpll_table_36xx.S | 1 + uart-loader/include/asm/arch-omap3/mem.h | 1 + uart-loader/include/asm/arch-omap3/mmc.h | 187 +++++ uart-loader/include/asm/arch-omap3/mux.h | 1 + uart-loader/include/asm/arch-omap3/omap3430.h | 1 + uart-loader/include/asm/arch-omap3/rev.h | 1 + uart-loader/include/asm/arch-omap3/sizes.h | 1 + uart-loader/include/asm/arch-omap3/sys_info.h | 1 + uart-loader/include/asm/arch-omap3/sys_proto.h | 1 + uart-loader/include/asm/atomic.h | 113 +++ uart-loader/include/asm/byteorder.h | 1 + uart-loader/include/asm/posix_types.h | 79 ++ uart-loader/include/asm/setup.h | 269 ++++++ uart-loader/include/asm/sizes.h | 52 ++ uart-loader/include/asm/string.h | 47 ++ uart-loader/include/asm/types.h | 50 ++ uart-loader/include/asm/x-load-arm.h | 40 + uart-loader/include/command.h | 1 + uart-loader/include/common.h | 110 +++ uart-loader/include/configs/omap3430labrador.h | 220 +++++ uart-loader/include/fat.h | 1 + uart-loader/include/ide.h | 1 + uart-loader/include/linux/byteorder | 1 + uart-loader/include/linux/config.h | 6 + uart-loader/include/linux/posix_types.h | 48 ++ uart-loader/include/linux/stat.h | 1 + uart-loader/include/linux/stddef.h | 18 + uart-loader/include/linux/time.h | 1 + uart-loader/include/linux/types.h | 130 +++ uart-loader/include/malloc.h | 1 + uart-loader/include/mmc.h | 1 + uart-loader/include/ns16550.h | 130 +++ uart-loader/include/part.h | 1 + uart-loader/lib/Makefile | 46 + uart-loader/lib/_udivsi3.S | 77 ++ uart-loader/lib/_umodsi3.S | 88 ++ uart-loader/lib/board.c | 242 ++++++ uart-loader/lib/div0.c | 30 + uart-loader/lib/ecc_256.c | 329 ++++++++ uart-loader/lib/ecc_512.c | 420 ++++++++++ uart-loader/lib/printf.c | 304 +++++++ uart-loader/mkconfig | 61 ++ uart-loader/scripts/mkoneboot.sh | 16 + uart-loader/scripts/signGP.c | 73 ++ 93 files changed, 10236 insertions(+), 1 deletion(-) delete mode 160000 uart-loader create mode 100644 uart-loader/.gitignore create mode 100644 uart-loader/Makefile create mode 100644 uart-loader/README create mode 100644 uart-loader/arm_config.mk create mode 100644 uart-loader/board/omap3430labrador/Makefile create mode 100644 uart-loader/board/omap3430labrador/config.mk create mode 100644 uart-loader/board/omap3430labrador/omap3430labrador.c create mode 100644 uart-loader/board/omap3430labrador/platform.S create mode 100644 uart-loader/common/Makefile create mode 100644 uart-loader/common/cmd_load.c create mode 100644 uart-loader/config.mk create mode 100644 uart-loader/cpu/omap3/Makefile create mode 100644 uart-loader/cpu/omap3/config.mk create mode 100644 uart-loader/cpu/omap3/cpu.c create mode 120000 uart-loader/cpu/omap3/mmc.c create mode 120000 uart-loader/cpu/omap3/mmc_host_def.h create mode 120000 uart-loader/cpu/omap3/mmc_protocol.h create mode 100644 uart-loader/cpu/omap3/start.S create mode 100644 uart-loader/cpu/omap3/sys_info.c create mode 100644 uart-loader/disk/Makefile create mode 100644 uart-loader/disk/part.c create mode 100644 uart-loader/drivers/Makefile create mode 100644 uart-loader/drivers/k9f1g08r0a.c create mode 100644 uart-loader/drivers/k9f5616.c create mode 100644 uart-loader/drivers/k9k1216.c create mode 100644 uart-loader/drivers/ns16550.c create mode 100644 uart-loader/drivers/onenand.c create mode 100644 uart-loader/drivers/onenand_regs.h create mode 100644 uart-loader/drivers/serial.c create mode 100644 uart-loader/fs/Makefile create mode 100644 uart-loader/fs/fat/Makefile create mode 100644 uart-loader/fs/fat/fat.c create mode 100644 uart-loader/fs/fat/file.c create mode 100644 uart-loader/include/asm/arch-arm1136/bits.h create mode 120000 uart-loader/include/asm/arch-arm1136/clocks.h create mode 120000 uart-loader/include/asm/arch-arm1136/clocks242x.h create mode 120000 uart-loader/include/asm/arch-arm1136/clocks243x.h create mode 120000 uart-loader/include/asm/arch-arm1136/mem.h create mode 100644 uart-loader/include/asm/arch-arm1136/omap2420.h create mode 100644 uart-loader/include/asm/arch-arm1136/omap2430.h create mode 100644 uart-loader/include/asm/arch-arm1136/sizes.h create mode 100644 uart-loader/include/asm/arch-arm1136/sys_info.h create mode 100644 uart-loader/include/asm/arch-arm926ejs/sizes.h create mode 120000 uart-loader/include/asm/arch-omap3/bits.h create mode 120000 uart-loader/include/asm/arch-omap3/clocks.h create mode 120000 uart-loader/include/asm/arch-omap3/clocks343x.h create mode 120000 uart-loader/include/asm/arch-omap3/cpu.h create mode 120000 uart-loader/include/asm/arch-omap3/dpll_table_34xx.S create mode 120000 uart-loader/include/asm/arch-omap3/dpll_table_36xx.S create mode 120000 uart-loader/include/asm/arch-omap3/mem.h create mode 100644 uart-loader/include/asm/arch-omap3/mmc.h create mode 120000 uart-loader/include/asm/arch-omap3/mux.h create mode 120000 uart-loader/include/asm/arch-omap3/omap3430.h create mode 120000 uart-loader/include/asm/arch-omap3/rev.h create mode 120000 uart-loader/include/asm/arch-omap3/sizes.h create mode 120000 uart-loader/include/asm/arch-omap3/sys_info.h create mode 120000 uart-loader/include/asm/arch-omap3/sys_proto.h create mode 100644 uart-loader/include/asm/atomic.h create mode 120000 uart-loader/include/asm/byteorder.h create mode 100644 uart-loader/include/asm/posix_types.h create mode 100644 uart-loader/include/asm/setup.h create mode 100644 uart-loader/include/asm/sizes.h create mode 100644 uart-loader/include/asm/string.h create mode 100644 uart-loader/include/asm/types.h create mode 100644 uart-loader/include/asm/x-load-arm.h create mode 120000 uart-loader/include/command.h create mode 100644 uart-loader/include/common.h create mode 100644 uart-loader/include/configs/omap3430labrador.h create mode 120000 uart-loader/include/fat.h create mode 120000 uart-loader/include/ide.h create mode 120000 uart-loader/include/linux/byteorder create mode 100644 uart-loader/include/linux/config.h create mode 100644 uart-loader/include/linux/posix_types.h create mode 120000 uart-loader/include/linux/stat.h create mode 100644 uart-loader/include/linux/stddef.h create mode 120000 uart-loader/include/linux/time.h create mode 100644 uart-loader/include/linux/types.h create mode 120000 uart-loader/include/malloc.h create mode 120000 uart-loader/include/mmc.h create mode 100644 uart-loader/include/ns16550.h create mode 120000 uart-loader/include/part.h create mode 100644 uart-loader/lib/Makefile create mode 100644 uart-loader/lib/_udivsi3.S create mode 100644 uart-loader/lib/_umodsi3.S create mode 100644 uart-loader/lib/board.c create mode 100644 uart-loader/lib/div0.c create mode 100644 uart-loader/lib/ecc_256.c create mode 100644 uart-loader/lib/ecc_512.c create mode 100644 uart-loader/lib/printf.c create mode 100755 uart-loader/mkconfig create mode 100644 uart-loader/scripts/mkoneboot.sh create mode 100644 uart-loader/scripts/signGP.c (limited to 'uart-loader') diff --git a/uart-loader b/uart-loader deleted file mode 160000 index eb8b047..0000000 --- a/uart-loader +++ /dev/null @@ -1 +0,0 @@ -Subproject commit eb8b047c29a2027fbdd841cd1289fa27ddb22d72 diff --git a/uart-loader/.gitignore b/uart-loader/.gitignore new file mode 100644 index 0000000..5bc6dd2 --- /dev/null +++ b/uart-loader/.gitignore @@ -0,0 +1,50 @@ +# +# NOTE! Don't add files that are generated in specific +# subdirectories here. Add them in the ".gitignore" file +# in that subdirectory instead. +# +# Normal rules +# +.* +*.o +*.o.* +*.a +*.s +*.ko +*.so +*.so.dbg +*.mod.c +*.i +*.lst +*.symtypes + +# +# Top-level generic files +# +x-load +x-load.* +System.map +include/asm/arch +include/asm/proc +include/config.h +include/config.mk +!.gitignore +signGP +MLO + +# +# Generated include files +# + +# stgit generated dirs +patches-* + +# quilt's files +patches +series + +# cscope files +cscope.* + +*.orig +*.rej diff --git a/uart-loader/Makefile b/uart-loader/Makefile new file mode 100644 index 0000000..73f82ec --- /dev/null +++ b/uart-loader/Makefile @@ -0,0 +1,222 @@ +# +# (C) Copyright 2004-2006, Texas Instruments, +# Jian Zhang +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +HOSTARCH := $(shell uname -m | \ + sed -e s/i.86/i386/ \ + -e s/sun4u/sparc64/ \ + -e s/arm.*/arm/ \ + -e s/sa110/arm/ \ + -e s/powerpc/ppc/ \ + -e s/macppc/ppc/) + +HOSTOS := $(shell uname -s | tr A-Z a-z | \ + sed -e 's/\(cygwin\).*/cygwin/') + +export HOSTARCH + +# Deal with colliding definitions from tcsh etc. +VENDOR= + +######################################################################### + +TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi) +export TOPDIR + +ifeq (include/config.mk,$(wildcard include/config.mk)) +# load ARCH, BOARD, and CPU configuration +include include/config.mk +export ARCH CPU BOARD VENDOR +# load other configuration +include $(TOPDIR)/config.mk + +ifndef CROSS_COMPILE +CROSS_COMPILE = arm-none-linux-gnueabi- +#CROSS_COMPILE = arm-linux- +export CROSS_COMPILE +endif + +######################################################################### +# X-LOAD objects....order is important (i.e. start must be first) + +OBJS = cpu/$(CPU)/start.o + + +LIBS += board/$(BOARDDIR)/lib$(BOARD).a +LIBS += cpu/$(CPU)/lib$(CPU).a +LIBS += lib/lib$(ARCH).a +LIBS += fs/fat/libfat.a +LIBS += disk/libdisk.a +LIBS += drivers/libdrivers.a +LIBS += common/libcommon.a +.PHONY : $(LIBS) + +# Add GCC lib +PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc + +SUBDIRS = +######################################################################### +######################################################################### + +ALL = x-load.bin System.map + +all: $(ALL) + +ift: $(ALL) x-load.bin.ift + +x-load.bin.ift: signGP System.map x-load.bin + TEXT_BASE=`grep -w _start System.map|cut -d ' ' -f1` + ./signGP x-load.bin $(TEXT_BASE) + cp x-load.bin.ift MLO + +x-load.bin: x-load + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +x-load: $(OBJS) $(LIBS) $(LDSCRIPT) + UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ + $(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \ + --start-group $(LIBS) --end-group $(PLATFORM_LIBS) \ + -Map x-load.map -o x-load + +$(LIBS): + $(MAKE) -C `dirname $@` + + +System.map: x-load + @$(NM) $< | \ + grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > System.map + +oneboot: x-load.bin + scripts/mkoneboot.sh + +signGP: scripts/signGP.c + gcc -O3 -o signGP $< + +######################################################################### +else +all install x-load x-load.srec oneboot depend dep: + @echo "System not configured - see README" >&2 + @ exit 1 +endif + +######################################################################### + +unconfig: + rm -f include/config.h include/config.mk + +#======================================================================== +# ARM +#======================================================================== +######################################################################### +## OMAP1 (ARM92xT) Systems +######################################################################### + +omap1710h3_config : unconfig + @./mkconfig $(@:_config=) arm arm926ejs omap1710h3 + +######################################################################### +## OMAP2 (ARM1136) Systems +######################################################################### + +omap2420h4_config : unconfig + @./mkconfig $(@:_config=) arm arm1136 omap2420h4 + +omap2430sdp_config : unconfig + @./mkconfig $(@:_config=) arm arm1136 omap2430sdp + +######################################################################### +## OMAP3 (ARM-CortexA8) Systems +######################################################################### +omap3430sdp_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3430sdp +omap3430labrador_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3430labrador + +omap3430labradordownload_config : unconfig + @./mkconfig omap3430labrador arm omap3 omap3430labrador; \ + echo "#define START_LOADB_DOWNLOAD" >> ./include/config-2.h; \ + cat ./include/config.h >> ./include/config-2.h; \ + mv ./include/config-2.h ./include/config.h + +omap3430zoom2_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3430labrador + +omap3430zoom2_512m_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3430labrador + sed -e ' s/CONFIG_3430ZOOM2/CONFIG_3430ZOOM2_512M/ ' < \ + ./include/configs/omap3430zoom2.h | \ + sed -e ' s/#define CFG_NAND 1/#undef CFG_NAND/ ' \ + >> ./include/config-2.h; \ + mv ./include/config-2.h ./include/config.h + +omap3630zoom3_config : omap3630zoom3_1G_config + +omap3630zoom3_512m_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3430labrador + sed s/omap3630zoom3_512m/omap3630zoom3/ < \ + ./include/config.h > ./include/config-2.h; \ + mv ./include/config-2.h ./include/config.h + +omap3630zoom3_1G_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3430labrador + sed s/CONFIG_3630ZOOM3/CONFIG_3630ZOOM3_1G/ < \ + ./include/configs/omap3630zoom3.h > ./include/config-2.h; \ + mv ./include/config-2.h ./include/config.h + +omap3630sdp_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3430labrador + +omap3630sdp_1G_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3430labrador + sed s/CONFIG_3630SDP/CONFIG_3630SDP_1G/ < \ + ./include/configs/omap3630sdp.h > ./include/config-2.h; \ + mv ./include/config-2.h ./include/config.h +######################################################################### + +clean: + find . -type f \ + \( -name 'core' -o -name '*.bak' -o -name '*~' \ + -o -name '*.o' -o -name '*.a' \) -print \ + | xargs rm -f + +clobber: clean + find . -type f \ + \( -name .depend -o -name '*.srec' -o -name '*.bin' \) \ + -print \ + | xargs rm -f + rm -f $(OBJS) *.bak tags TAGS + rm -fr *.*~ + rm -f x-load x-load.map $(ALL) x-load.bin.ift signGP MLO + rm -f include/asm/proc include/asm/arch + +mrproper \ +distclean: clobber unconfig + +backup: + F=`basename $(TOPDIR)` ; cd .. ; \ + gtar --force-local -zcvf `date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F + +######################################################################### diff --git a/uart-loader/README b/uart-loader/README new file mode 100644 index 0000000..ae2662a --- /dev/null +++ b/uart-loader/README @@ -0,0 +1,152 @@ +# +# (C) Copyright 2004-2006 Texas Instruments +# +# Some cut/paste from U-Boot README +# (C) Copyright 2000 - 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +Summary: +======== + +This directory contains the source code for X-Loader, an initial program +loader for Embedded boards based on OMAP processors. X-Loader can be +signed by Texas Instruments IFT and installed to Nand flash to achieve +Nand booting. + + +Status: +======= + +The support for Texas Instruments H3 board (OMAP1710) has been implemented +and tested. (May 2004) +The support for Texas Instruments H4 board (OMAP2420) has been implemented +and tested. (Nov 2004) +The support for Texas Instruments 2430SDP board (OMAP2430) has been implemented +and tested. (Jul 2006) +The support for Texas Instruments 3430SDP board (OMAP3430) has been implemented +and tested. (Dec 2006) + + +Support for other OMAP boards can be added. + + +Directory Hierarchy: +==================== + +- board Board dependent files +- cpu CPU specific files +- drivers Commonly used device drivers +- lib Libraries + +- cpu/arm926ejs Files specific to ARM 926 CPUs +- cpu/arm1136 Files specific to ARM 1136 CPUs +- cpu/omap3 Files specific to ARM CortexA8 CPU + + +- board/omap1710h3 + Files specific to OMAP 1710 H3 boards +- board/omap2420h4 + Files specific to OMAP 2420 H4 boards +- board/omap2430sdp + Files specific to OMAP 2430 2430sdp boards +- board/omap3430sdp + Files specific to OMAP 3420sdp boards + + +Software Configuration: +======================= + +Configuration is usually done using C preprocessor defines. Configuration +depends on the combination of board and CPU type; all such information is +kept in a configuration file "include/configs/.h". + +Example: For a H3 module, all configuration settings are in +"include/configs/omap1710h3.h". + +For all supported boards there are ready-to-use default +configurations available; just type "make _config". + +Example: For a H3 module type: + + cd x-load + make omap1710h3_config + +After a board has been configured, type "make" to build it supposing the +needed cross tools are in your path. + + +Image Format: +============= + +X-Loader expects OS boot loader (e.g. U-Boot) in Nand flash using +JFFS2 style ECC. + + +Prepare Booting Nand Flash: +=========================== + +After you have built x-load.bin for your board, you need to do the +followings to get it into Nand flash: + +1. Use Texas Instruments IFT to sign x-load.bin. This results in a +signed image called x-load.bin.ift. +2. Use Texas Instruments FlashPrep to generate a .out file using +FlashWriterNand and specifying 0 as nand target address. +3. Use Texas instrumnets Code Composer Studio to run the .out file +which flashes x-load.bin.ift to Nand flash. + +Next you need to get your OS boot loader to Nand at the address your +X-Loader expects. For the H3 example, you can use U-Boot to flash U-Boot. +You can't use FlashWriterNand because it uses ROM code ECC style. + + +More Information +================ + +OMAP1710 NAND Booting Design Document has more information. + +Implemenation notes: +==================== +H3, H4 support NAND flash booting +2430sdp & 3430sdp support OneNAND booting + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/uart-loader/arm_config.mk b/uart-loader/arm_config.mk new file mode 100644 index 0000000..73d9625 --- /dev/null +++ b/uart-loader/arm_config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ diff --git a/uart-loader/board/omap3430labrador/Makefile b/uart-loader/board/omap3430labrador/Makefile new file mode 100644 index 0000000..c03134c --- /dev/null +++ b/uart-loader/board/omap3430labrador/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := omap3430labrador.o +SOBJS := platform.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/uart-loader/board/omap3430labrador/config.mk b/uart-loader/board/omap3430labrador/config.mk new file mode 100644 index 0000000..d6ad6c5 --- /dev/null +++ b/uart-loader/board/omap3430labrador/config.mk @@ -0,0 +1,22 @@ +# +# (C) Copyright 2006 +# Texas Instruments, +# +# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# SDP3430 has 1 bank of 32MB or 128MB mDDR-SDRAM on CS0 +# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000'0000 (bank1) - re-mappable below CS1 + +# For use if you want X-Loader to relocate from SRAM to DDR +#TEXT_BASE = 0x80e80000 + +# For XIP in 64K of SRAM or debug (GP device has it all availabe) +# SRAM 40200000-4020FFFF base +# initial stack at 0x4020fffc used in s_init (below xloader). +# The run time stack is (above xloader, 2k below) +# If any globals exist there needs to be room for them also +TEXT_BASE = 0x40208800 diff --git a/uart-loader/board/omap3430labrador/omap3430labrador.c b/uart-loader/board/omap3430labrador/omap3430labrador.c new file mode 100644 index 0000000..33361f4 --- /dev/null +++ b/uart-loader/board/omap3430labrador/omap3430labrador.c @@ -0,0 +1,875 @@ +/* + * (C) Copyright 2006-2009 + * Texas Instruments, + * Jian Zhang + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Used to index into DPLL parameter tables */ +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +}; + +#ifdef CONFIG_OMAP36XX +struct dpll_per_param { + unsigned int sys_clk; + unsigned int m; + unsigned int n; + unsigned int clkin; + unsigned int sd; + unsigned int dco; + unsigned int m2; + unsigned int m3; + unsigned int m4; + unsigned int m5; + unsigned int m6; + unsigned int m2div; +}; +typedef struct dpll_per_param dpll_per_param; +#define MAX_SIL_INDEX 1 +#else +typedef struct dpll_param dpll_per_param; +#define MAX_SIL_INDEX 3 +#endif + +typedef struct dpll_param dpll_param; + +/* Following functions are exported from lowlevel_init.S */ +extern dpll_param * get_mpu_dpll_param(void); +extern dpll_param * get_core_dpll_param(void); +extern dpll_param * get_per_dpll_param(void); + +#define __raw_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init (void) +{ + return 0; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return(mode >>= 8); +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = __raw_readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + __raw_writel(tmp, addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return (1); + if (i == bound) + return (0); + } while (1); +} + +#ifdef CFG_3430SDRAM_DDR +/********************************************************************* + * config_3430sdram_ddr() - Init DDR on 3430SDP dev board. + *********************************************************************/ +void config_3430sdram_ddr(void) +{ + /* check if its h/w or s/w reset for warm reset workaround */ + if (__raw_readl(PRM_RSTTST) & 0x2) { + /* Enable SDRC clock & wait SDRC idle status to access*/ + sr32(CM_ICLKEN1_CORE, 1, 1, 0x1); + wait_on_value(BIT1, 0, CM_IDLEST1_CORE, LDELAY); + } else { + /* do a SDRC reset between types to clear regs */ + __raw_writel(SOFTRESET, SDRC_SYSCONFIG);/* reset sdrc */ + /* wait on reset */ + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); + __raw_writel(0, SDRC_SYSCONFIG);/* clear soft reset */ + } + /* Clear reset sources */ + __raw_writel(0xfff, PRM_RSTTST); + + /* setup sdrc to ball mux */ + __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); + + /* Configure the first chip select */ + /* set mdcfg */ + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0); + + /* set timing */ + __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); + __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); + __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL_0); + + /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0); + delay(5000); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0); + + /* set mr0 */ + __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0); +#ifdef CONFIG_2GBDDR + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1); + + /* set timing */ + __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_1); + __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1); + __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL_1); + + /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ + __raw_writel(CMD_NOP, SDRC_MANUAL_1); + delay(5000); + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1); + + /* set mr0 */ + __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1); + + /* Configure cs1 to be just behind cs0 - 128meg boundary */ +#if defined(CONFIG_3430ZOOM2_512M) || \ + defined(CONFIG_3630ZOOM3) || defined(CONFIG_3630SDP) + /* 2 * 128M = 256M for cs1 */ + __raw_writel(0x2, SDRC_CS_CFG); +#elif defined(CONFIG_3630SDP_1G) || defined(CONFIG_3630ZOOM3_1G) + /* 4 * 128M = 512M for cs1 */ + __raw_writel(0x4, SDRC_CS_CFG); +#else + /* 1 * 128M = 128M for cs1 */ + __raw_writel(0x1, SDRC_CS_CFG); +#endif + + /* set up dllB-CS1 */ + __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); + delay(0x2000); /* give time to lock */ +#endif + + /* set up dllA-CS0 */ + __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); + delay(0x2000); /* give time to lock */ + +} +#endif // CFG_3430SDRAM_DDR + +/************************************************************* + * get_sys_clk_speed - determine reference oscillator speed + * based on known 32kHz clock and gptimer. + *************************************************************/ +u32 get_osc_clk_speed(void) +{ + u32 start, cstart, cend, cdiff, val; + + val = __raw_readl(PRM_CLKSRC_CTRL); + /* If SYS_CLK is being divided by 2, remove for now */ + val = (val & (~BIT7)) | BIT6; + __raw_writel(val, PRM_CLKSRC_CTRL); + + /* enable timer2 */ + val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; + __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ + + /* Enable I and F Clocks for GPT1 */ + val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; + __raw_writel(val, CM_ICLKEN_WKUP); + val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; + __raw_writel(val, CM_FCLKEN_WKUP); + + __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ + __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ + /* enable 32kHz source *//* enabled out of reset */ + /* determine sys_clk via gauging */ + + start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ + while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ + cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ + while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ + cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ + cdiff = cend - cstart; /* get elapsed ticks */ + + /* based on number of ticks assign speed */ + if (cdiff > 19000) + return (S38_4M); + else if (cdiff > 15200) + return (S26M); + else if (cdiff > 13000) + return (S24M); + else if (cdiff > 9000) + return (S19_2M); + else if (cdiff > 7600) + return (S13M); + else + return (S12M); +} + +/****************************************************************************** + * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on + * -- input oscillator clock frequency. + * + *****************************************************************************/ +void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) +{ + if(osc_clk == S38_4M) + *sys_clkin_sel= 4; + else if(osc_clk == S26M) + *sys_clkin_sel = 3; + else if(osc_clk == S19_2M) + *sys_clkin_sel = 2; + else if(osc_clk == S13M) + *sys_clkin_sel = 1; + else if(osc_clk == S12M) + *sys_clkin_sel = 0; +} + +static dpll_per_param *_get_per_dpll(int clk_index) +{ + dpll_per_param *ret = (dpll_per_param *)get_per_dpll_param(); + ret += clk_index; + return ret; +} + +static dpll_param *_get_mpu_dpll(int clk_index, int sil_index) +{ + dpll_param *ret = (dpll_param *)get_mpu_dpll_param(); + ret += (MAX_SIL_INDEX * clk_index) + sil_index; + return ret; +} + +#ifdef CONFIG_OMAP36XX + +#define PER_M_BITS 12 +#define PER_M2_BITS 5 +#define PER_M3_BITS 6 +#define PER_M4_BITS 6 +#define PER_M5_BITS 6 +#define PER_M6_BITS 6 + +static void per_dpll_init_36XX(int clk_index) +{ + dpll_per_param *per; + + per = _get_per_dpll(clk_index); + + sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); + wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); + + sr32(CM_CLKSEL2_PLL, 8, PER_M_BITS, per->m); + sr32(CM_CLKSEL2_PLL, 0, 7, per->n); + sr32(PRM_CLKSRC_CTRL, 8, 1, per->clkin); + sr32(CM_CLKSEL2_PLL, 24, 7, per->sd); + sr32(CM_CLKSEL2_PLL, 21, 3, per->dco); + sr32(CM_CLKSEL3_PLL, 0, PER_M2_BITS, per->m2); + sr32(CM_CLKSEL_DSS, 8, PER_M3_BITS, per->m3); + sr32(CM_CLKSEL_DSS, 0, PER_M4_BITS, per->m4); + sr32(CM_CLKSEL_CAM, 0, PER_M5_BITS, per->m5); + sr32(CM_CLKSEL1_EMU, 24, PER_M6_BITS, per->m6); + sr32(CM_CLKSEL_CORE, 12, 2, per->m2div); + + sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); +} + +static void mpu_dpll_init_36XX(int clk_index, int sil_index) +{ + dpll_param *mpu; + + mpu = _get_mpu_dpll(clk_index, sil_index); + + /* MPU DPLL (unlocked already) */ + sr32(CM_CLKSEL1_PLL_MPU, 8, 11, mpu->m); + sr32(CM_CLKSEL1_PLL_MPU, 0, 7, mpu->n); + sr32(CM_CLKSEL2_PLL_MPU, 0, 5, mpu->m2); + + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); +} + +#else /* 34xx */ + +#define PER_M_BITS 11 +#define PER_M2_BITS 5 +#define PER_M3_BITS 5 +#define PER_M4_BITS 5 +#define PER_M5_BITS 5 +#define PER_M6_BITS 5 + +static void per_dpll_init_34XX(int clk_index) +{ + dpll_per_param *dpll_param_p; + + /* Getting the base address to PER DPLL param table*/ + dpll_param_p = (dpll_param *)get_per_dpll_param(); + /* Moving it to the right sysclk base */ + dpll_param_p = dpll_param_p + clk_index; + /* PER DPLL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); + wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ + sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ + sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); +} + +static void mpu_dpll_init_34XX(int clk_index, int sil_index) +{ + dpll_param *dpll_param_p; + + /* Getting the base address to MPU DPLL param table*/ + dpll_param_p = (dpll_param *)get_mpu_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + /* MPU DPLL (unlocked already) */ + sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); +} + +#endif + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * -- called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + u32 osc_clk=0, sys_clkin_sel; + dpll_param *dpll_param_p; + u32 clk_index, sil_index; + + /* Gauge the input clock speed and find out the sys_clkin_sel + * value corresponding to the input clock. + */ + osc_clk = get_osc_clk_speed(); + get_sys_clkin_sel(osc_clk, &sys_clkin_sel); + + sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ + +/* Using 26MHz divider straight into OMAP saves ~2ms on OFF mode restore */ +#if 0 + /* If the input clock is greater than 19.2M always divide/2 */ + if(sys_clkin_sel > 2) { + sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */ + clk_index = sys_clkin_sel/2; + } else +#endif + { + sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */ + clk_index = sys_clkin_sel; + } + + sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ + + /* The DPLL tables are defined according to sysclk value and + * silicon revision. The clk_index value will be used to get + * the values for that input sysclk from the DPLL param table + * and sil_index will get the values for that SysClk for the + * appropriate silicon rev. + */ +#ifdef CONFIG_OMAP36XX + sil_index = 0; +#else + if(cpu_is_3410()) + sil_index = 2; + else { + if(get_cpu_rev() == CPU_3XX_ES10) + sil_index = 0; + else if(get_cpu_rev() >= CPU_3XX_ES20) + sil_index = 1; + } +#endif + + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address of Core DPLL param table*/ + dpll_param_p = (dpll_param *)get_core_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + /* CORE DPLL */ + /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); + /* For 3430 ES1.0 Errata 1.50, default value directly doesnt + work. write another value and then default value. */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ + sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ + sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ + sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb ES1 only */ + sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ + sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ + sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ + sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ + sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); + + /* PER DPLL */ +#ifdef CONFIG_OMAP36XX + per_dpll_init_36XX(clk_index); + mpu_dpll_init_36XX(clk_index, sil_index); +#else + per_dpll_init_34XX(clk_index); + mpu_dpll_init_34XX(clk_index, sil_index); +#endif + + /* Set up GPTimers to sys_clk source only */ + sr32(CM_CLKSEL_PER, 0, 8, 0xff); + sr32(CM_CLKSEL_WKUP, 0, 1, 1); + + delay(5000); +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) { + secure_unlock(); + } + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called at time when only stack is available. + **********************************************************/ + +void s_init(void) +{ + watchdog_init(); +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP); +#endif + try_unlock_memory(); + set_muxconf_regs(); + delay(100); + prcm_init(); + per_clocks_enable(); + config_3430sdram_ddr(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r (void) +{ + return(0); +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init (void) +{ + return 0; +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +void per_clocks_enable(void) +{ + /* Enable GP2 timer. */ + sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ + sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ + sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ + +#ifdef CFG_NS16550 +////#ifdef CONFIG_SERIAL3 + sr32(CM_FCLKEN_PER, 11, 1, 0x1); + sr32(CM_ICLKEN_PER, 11, 1, 0x1); +////#else + /* Enable UART1 clocks */ + sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); + sr32(CM_ICLKEN1_CORE, 13, 5, 0x1); +////#endif +#endif + // hns: enable clock for GPIO2-6 http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/p/65520/236545.aspx + sr32(CM_FCLKEN_PER, 13, 5, 0x1f); + sr32(CM_ICLKEN_PER, 13, 5, 0x1f); + // hns: and GPIO1 + sr32(CM_FCLKEN_WKUP, 3, 1, 0x1); + sr32(CM_ICLKEN_WKUP, 3, 1, 0x1); + delay(1000); +} + +/* Set MUX for UART, GPMC, SDRC, GPIO */ + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4 lab*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5 lab*/\ +MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | EN | M4)) /*GPT_PWM11/GPIO57*/\ + MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_IO_DIR lab*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1 lab*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ + MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ + MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ + MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ + MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ + MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ + MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ + MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ + MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ + MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ + MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ + MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/\ +MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ +MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/ +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT(); +#ifdef CONFIG_2GBDDR + MUX_VAL(CP(sdrc_cke1), (IDIS | PTU | EN | M0)) /*sdrc_cke1 */ +#endif +} + +/********************************************************** + * Routine: nand+_init + * Description: Set up nand for nand and jffs2 commands + *********************************************************/ +int nand_init(void) +{ + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */ +#ifdef CFG_NAND + __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ +#endif + + /* setup CS0 for Micron NAND, leave other CS's to u-boot */ + __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); + delay(1000); + +#ifdef CFG_NAND + __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); + +#elif CFG_ONENAND /* CFG_ONENAND */ + __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0); + __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0); +#endif + + /* Enable the GPMC Mapping */ + __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) | + ((OMAP34XX_GPMC_CS0_MAP>>24) & 0x3F) | + (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0)); + delay(2000); + +#ifdef CFG_NAND + if (nand_chip()){ +#ifdef CFG_PRINTF + printf("Unsupported Chip!\n"); +#endif + return 1; + } +#elif CFG_ONENAND + if (onenand_chip()){ +#ifdef CFG_PRINTF + printf("OneNAND Unsupported !\n"); +#endif + return 1; + } +#endif + return 0; +} + +/* optionally do something like blinking LED */ +void board_hang (void) +{ + while (1) { + printf("X-Loader hangs\n"); + } +} diff --git a/uart-loader/board/omap3430labrador/platform.S b/uart-loader/board/omap3430labrador/platform.S new file mode 100644 index 0000000..42dfc72 --- /dev/null +++ b/uart-loader/board/omap3430labrador/platform.S @@ -0,0 +1,218 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * NOTE: 3430 X-loader currently does not use this code. +* It could be removed its is kept for compatabily with u-boot. + * + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = CM_CLKEN_PLL-bypass value + * R1 = CM_CLKSEL1_PLL-m, n, and divider values + * R2 = CM_CLKSEL_CORE-divider values + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + * + * Note: If core unlocks/relocks and SDRAM is running fast already it gets + * confused. A reset of the controller gets it back. Taking away its + * L3 when its not in self refresh seems bad for it. Normally, this code + * runs from flash before SDR is init so that should be ok. + ******************************************************************************/ +.global go_to_speed + go_to_speed: + stmfd sp!, {r4-r6} + + /* move into fast relock bypass */ + ldr r4, pll_ctl_add + str r0, [r4] +wait1: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + beq wait1 /* if lock, loop */ + + /* set new dpll dividers _after_ in bypass */ + ldr r5, pll_div_add1 + str r1, [r5] /* set m, n, m2 */ + ldr r5, pll_div_add2 + str r2, [r5] /* set l3/l4/.. dividers*/ + ldr r5, pll_div_add3 /* wkup */ + ldr r2, pll_div_val3 /* rsm val */ + str r2, [r5] + ldr r5, pll_div_add4 /* gfx */ + ldr r2, pll_div_val4 + str r2, [r5] + ldr r5, pll_div_add5 /* emu */ + ldr r2, pll_div_val5 + str r2, [r5] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r5, flash_cfg3_addr + ldr r2, flash_cfg3_val + str r2, [r5] + ldr r5, flash_cfg4_addr + ldr r2, flash_cfg4_val + str r2, [r5] + ldr r5, flash_cfg5_addr + ldr r2, flash_cfg5_val + str r2, [r5] + ldr r5, flash_cfg1_addr + ldr r2, [r5] + orr r2, r2, #0x3 /* up gpmc divider */ + str r2, [r5] + + /* lock DPLL3 and wait a bit */ + orr r0, r0, #0x7 /* set up for lock mode */ + str r0, [r4] /* lock */ + nop /* ARM slow at this point working at sys_clk */ + nop + nop + nop +wait2: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + bne wait2 /* if lock, loop */ + nop + nop + nop + nop + ldmfd sp!, {r4-r6} + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_div_add1: + .word CM_CLKSEL1_PLL +pll_div_add2: + .word CM_CLKSEL_CORE +pll_div_add3: + .word CM_CLKSEL_WKUP +pll_div_val3: + .word (WKUP_RSM << 1) +pll_div_add4: + .word CM_CLKSEL_GFX +pll_div_val4: + .word (GFX_DIV << 0) +pll_div_add5: + .word CM_CLKSEL1_EMU +pll_div_val5: + .word CLSEL1_EMU_VAL + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + +.globl get_mpu_dpll_param +get_mpu_dpll_param: + adr r0, mpu_dpll_param + mov pc, lr + +.globl get_iva_dpll_param +get_iva_dpll_param: + adr r0, iva_dpll_param + mov pc, lr + +.globl get_core_dpll_param +get_core_dpll_param: + adr r0, core_dpll_param + mov pc, lr + +.globl get_per_dpll_param +get_per_dpll_param: + adr r0, per_dpll_param + mov pc, lr + +#if defined(CONFIG_OMAP36XX) +#include +#elif defined(CONFIG_OMAP34XX) +#include +#else +#error "DPLL Table is undefined" +#endif \ No newline at end of file diff --git a/uart-loader/common/Makefile b/uart-loader/common/Makefile new file mode 100644 index 0000000..de856cf --- /dev/null +++ b/uart-loader/common/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libcommon.a + +AOBJS = + +COBJS = cmd_load.o + +OBJS = $(AOBJS) $(COBJS) + +CPPFLAGS += -I.. + +all: $(LIB) $(AOBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/uart-loader/common/cmd_load.c b/uart-loader/common/cmd_load.c new file mode 100644 index 0000000..872833d --- /dev/null +++ b/uart-loader/common/cmd_load.c @@ -0,0 +1,829 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Serial up- and download support + */ +#include +#include + +#define putc serial_putc +#define tstc serial_tstc + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} +static inline void udelay(unsigned long us) +{ + delay(us * 200); /* approximate */ +} + +static gpio_t *blocks[]={ // GPIO1 .. 6 + OMAP34XX_GPIO1_BASE, + OMAP34XX_GPIO2_BASE, + OMAP34XX_GPIO3_BASE, + OMAP34XX_GPIO4_BASE, + OMAP34XX_GPIO5_BASE, + OMAP34XX_GPIO6_BASE +}; + +static inline int gpio_get(int n) +{ + int bit=n % 32; + gpio_t *base=blocks[n/32]; + return (base->datain >> bit)&1; +} + +static inline int gpio_is_input(int n) +{ // geht nicht richtig + int bit=n % 32; + gpio_t *base=blocks[n/32]; + return (base->oe >> bit)&1; +} + +#ifdef CFG_CMD_FAT +extern void * memcpy(void * dest,const void *src,size_t count); +#else +void * memcpy(void * dest,const void *src,size_t count) +{ + char *tmp = (char *) dest, *s = (char *) src; + + while (count--) + *tmp++ = *s++; + + return dest; +} +#endif + +/* -------------------------------------------------------------------- */ + +#define XON_CHAR 17 +#define XOFF_CHAR 19 +#define START_CHAR 0x01 +#define ETX_CHAR 0x03 +#define END_CHAR 0x0D +#define SPACE 0x20 +#define K_ESCAPE 0x23 +#define SEND_TYPE 'S' +#define DATA_TYPE 'D' +#define ACK_TYPE 'Y' +#define NACK_TYPE 'N' +#define BREAK_TYPE 'B' +#define tochar(x) ((char) (((x) + SPACE) & 0xff)) +#define untochar(x) ((int) (((x) - SPACE) & 0xff)) + +extern int os_data_count; +extern int os_data_header[8]; + +static void set_kerm_bin_mode(unsigned long *); +static int k_recv(void); +static ulong load_serial_bin (ulong offset); + + +char his_eol; /* character he needs at end of packet */ +int his_pad_count; /* number of pad chars he needs */ +char his_pad_char; /* pad chars he needs */ +char his_quote; /* quote chars he'll use */ + +int strcmp(char *s1, char *s2) +{ + while(*s1 == *s2) { + if(*s1 == 0) + return 0; // same + s1++; + s2++; + } + return *s1 > *s2?1:-1; +} + +long xtol(char *s) +{ + long val=0; + while(1) + { + if(*s >= '0' && *s <= '9') + val=16*val+(*s++-'0'); + else if(*s >= 'A' && *s <= 'F') + val=16*val+(*s++-'A'+10); + else if(*s >= 'a' && *s <= 'f') + val=16*val+(*s++-'a'+10); + else + break; + } + return val; +} + +static char *addr=(char *) CFG_LOADADDR; +static char line[100]; +static char *argv[10]; + +#define __raw_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) + +#define MUX_VAL(OFFSET,VALUE)\ +__raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) + +void testfn(void) +{ // code can be copied to SDRAM (assuming that it is position-independent!) + int i; + for(i=0; i<10; i++) { + if(i & 1) + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | EN | M4)) /*GPT_PWM11/GPIO57*/ + else + MUX_VAL(CP(GPMC_nCS6), (IEN | PTU | EN | M4)) /*GPT_PWM11/GPIO57*/ + udelay(500*1000); + } +} + +int do_comand_line(void) +{ // add testing code here + printf ("Welcome to uart-loader\n"); + while(1) { + char *c; + int argc=0; + int pos=0; + printf ("$ "); + while(1) { + line[pos]=getc(); + switch(line[pos]) { + case '\b': + case 0x7f: + if(pos > 0) { + putc('\b'); + pos--; + } + continue; + case 0: + case '\n': + continue; // ignore + case '\r': + break; // command + default: + if(pos < sizeof(line)/sizeof(line[0])) { + putc(line[pos]); + pos++; + } + continue; + } + line[pos]=0; + printf("\n"); + break; + } + c=line; + while(argc < sizeof(argv)/sizeof(argv[0])) { + while (*c == ' ' || *c == '\t') + c++; + if(*c == 0) + break; + argv[argc]=c; + while(*c != 0 && *c != '\t' && *c != ' ') + c++; + argc++; + if(*c == 0) + break; + *c=0; // substitute + c++; + } + if(argc == 0) + continue; // empty line +// printf("argc=%d argv[0]=%s\n", argc, argv[0]); + if(strcmp(argv[0], "c") == 0) { // c - copy test function to SDRAM and execute + void (*fn)(void) = &testfn; + size_t cnt = 0x1000; + addr=(char *) CFG_LOADADDR; + printf("%08x (%d) --> %08x\n", fn, cnt, addr); + memcpy(addr, fn, cnt); + (*fn)(); + } + else if(strcmp(argv[0], "x") == 0) { // x [addr] - execute code + void (*fn)(void) = addr; + if(argc > 1) + fn = (void *) xtol(argv[1]); + (*fn)(); + } + else if(strcmp(argv[0], "l") == 0) { // l - loop + int d=1; + while(1) + printf ("Welcome to uart-monitor (%d)\n", d++), udelay(500*1000); + } + else if(strcmp(argv[0], "ram") == 0) { + int val=0x55; + if(argc == 2) + val=xtol(argv[1]); + for(addr=(char *) CFG_LOADADDR; addr < 256+(char *) CFG_LOADADDR; addr++) { + *addr=val++; + } + addr=(char *) CFG_LOADADDR; + } + else if(strcmp(argv[0], "a") == 0) { // a [addr] + if(argc > 1) + addr=(char *) xtol(argv[1]); + printf("%08x\n", addr); + } + else if(strcmp(argv[0], "r") == 0) { // r [size] + int i; + int n=1; + if(argc > 1) + n=xtol(argv[1]); + printf("%08x:", addr); + for(i=0; i 1) + n=xtol(argv[1]); + printf("%08x:", addr); + for(i=0; i 1) + val=xtol(argv[1]); + if(argc > 2) + n=xtol(argv[2]); + for(i=0; i datain); + printf("%03d:", 0); + for(i=0; i>= 16; + } + if(addr == 0x48002264) { + addr=0x480025DC; + printf("\n%08x", addr); + cols=0; + } + else { + addr+=4; + if(++cols == 8) + printf("\n%08x", addr), cols=0; + } + } + printf("\n"); + } + else + printf("uart-loader unknown command: %s\n", argv[0]); + } + return 0; +} + +int do_load_serial_bin (ulong offset, int baudrate) +{ + ulong addr; + int rcode = 0; + + printf ("## Ready for binary (kermit) download " + "to 0x%08lX at %d bps...\n", + offset, + baudrate); + addr = load_serial_bin (offset); + + udelay(3*1000*1000); + + if (addr == ~0) { + printf ("## Binary (kermit) download aborted\n"); + rcode = 1; + } else { + printf ("## Start Addr = 0x%08lX\n", addr); +#if 0 + udelay(3*1000*1000); + { + int i; + int n=256; + char *a=(char *) addr; + printf("%08x:", a); + for(i=0; i 0) + putc (his_pad_char); +} + +/* converts escaped kermit char to binary char */ +char ktrans (char in) +{ + if ((in & 0x60) == 0x40) { + return (char) (in & ~0x40); + } else if ((in & 0x7f) == 0x3f) { + return (char) (in | 0x40); + } else + return in; +} + +int chk1 (char *buffer) +{ + int total = 0; + + while (*buffer) { + total += *buffer++; + } + return (int) ((total + ((total >> 6) & 0x03)) & 0x3f); +} + +void s1_sendpacket (char *packet) +{ + send_pad (); + while (*packet) { + putc (*packet++); + } +} + +static char a_b[24]; +void send_ack (int n) +{ + a_b[0] = START_CHAR; + a_b[1] = tochar (3); + a_b[2] = tochar (n); + a_b[3] = ACK_TYPE; + a_b[4] = '\0'; + a_b[4] = tochar (chk1 (&a_b[1])); + a_b[5] = his_eol; + a_b[6] = '\0'; + s1_sendpacket (a_b); +} + +void send_nack (int n) +{ + a_b[0] = START_CHAR; + a_b[1] = tochar (3); + a_b[2] = tochar (n); + a_b[3] = NACK_TYPE; + a_b[4] = '\0'; + a_b[4] = tochar (chk1 (&a_b[1])); + a_b[5] = his_eol; + a_b[6] = '\0'; + s1_sendpacket (a_b); +} + + +/* os_data_* takes an OS Open image and puts it into memory, and + puts the boot header in an array named os_data_header + + if image is binary, no header is stored in os_data_header. +*/ +void (*os_data_init) (void); +void (*os_data_char) (char new_char); +static int os_data_state, os_data_state_saved; +int os_data_count; +static int os_data_count_saved; +static char *os_data_addr, *os_data_addr_saved; +static char *bin_start_address; +int os_data_header[8]; +static void bin_data_init (void) +{ + os_data_state = 0; + os_data_count = 0; + os_data_addr = bin_start_address; +} +static void os_data_save (void) +{ + os_data_state_saved = os_data_state; + os_data_count_saved = os_data_count; + os_data_addr_saved = os_data_addr; +} +static void os_data_restore (void) +{ + os_data_state = os_data_state_saved; + os_data_count = os_data_count_saved; + os_data_addr = os_data_addr_saved; +} +static void bin_data_char (char new_char) +{ + switch (os_data_state) { + case 0: /* data */ + *os_data_addr++ = new_char; + --os_data_count; + break; + } +} +static void set_kerm_bin_mode (unsigned long *addr) +{ + bin_start_address = (char *) addr; + os_data_init = bin_data_init; + os_data_char = bin_data_char; +} + + +/* k_data_* simply handles the kermit escape translations */ +static int k_data_escape, k_data_escape_saved; +void k_data_init (void) +{ + k_data_escape = 0; + os_data_init (); +} +void k_data_save (void) +{ + k_data_escape_saved = k_data_escape; + os_data_save (); +} +void k_data_restore (void) +{ + k_data_escape = k_data_escape_saved; + os_data_restore (); +} +void k_data_char (char new_char) +{ + if (k_data_escape) { + /* last char was escape - translate this character */ + os_data_char (ktrans (new_char)); + k_data_escape = 0; + } else { + if (new_char == his_quote) { + /* this char is escape - remember */ + k_data_escape = 1; + } else { + /* otherwise send this char as-is */ + os_data_char (new_char); + } + } +} + +#define SEND_DATA_SIZE 20 +char send_parms[SEND_DATA_SIZE]; +char *send_ptr; + +/* handle_send_packet interprits the protocol info and builds and + sends an appropriate ack for what we can do */ +void handle_send_packet (int n) +{ + int length = 3; + int bytes; + + /* initialize some protocol parameters */ + his_eol = END_CHAR; /* default end of line character */ + his_pad_count = 0; + his_pad_char = '\0'; + his_quote = K_ESCAPE; + + /* ignore last character if it filled the buffer */ + if (send_ptr == &send_parms[SEND_DATA_SIZE - 1]) + --send_ptr; + bytes = send_ptr - send_parms; /* how many bytes we'll process */ + do { + if (bytes-- <= 0) + break; + /* handle MAXL - max length */ + /* ignore what he says - most I'll take (here) is 94 */ + a_b[++length] = tochar (94); + if (bytes-- <= 0) + break; + /* handle TIME - time you should wait for my packets */ + /* ignore what he says - don't wait for my ack longer than 1 second */ + a_b[++length] = tochar (1); + if (bytes-- <= 0) + break; + /* handle NPAD - number of pad chars I need */ + /* remember what he says - I need none */ + his_pad_count = untochar (send_parms[2]); + a_b[++length] = tochar (0); + if (bytes-- <= 0) + break; + /* handle PADC - pad chars I need */ + /* remember what he says - I need none */ + his_pad_char = ktrans (send_parms[3]); + a_b[++length] = 0x40; /* He should ignore this */ + if (bytes-- <= 0) + break; + /* handle EOL - end of line he needs */ + /* remember what he says - I need CR */ + his_eol = untochar (send_parms[4]); + a_b[++length] = tochar (END_CHAR); + if (bytes-- <= 0) + break; + /* handle QCTL - quote control char he'll use */ + /* remember what he says - I'll use '#' */ + his_quote = send_parms[5]; + a_b[++length] = '#'; + if (bytes-- <= 0) + break; + /* handle QBIN - 8-th bit prefixing */ + /* ignore what he says - I refuse */ + a_b[++length] = 'N'; + if (bytes-- <= 0) + break; + /* handle CHKT - the clock check type */ + /* ignore what he says - I do type 1 (for now) */ + a_b[++length] = '1'; + if (bytes-- <= 0) + break; + /* handle REPT - the repeat prefix */ + /* ignore what he says - I refuse (for now) */ + a_b[++length] = 'N'; + if (bytes-- <= 0) + break; + /* handle CAPAS - the capabilities mask */ + /* ignore what he says - I only do long packets - I don't do windows */ + a_b[++length] = tochar (2); /* only long packets */ + a_b[++length] = tochar (0); /* no windows */ + a_b[++length] = tochar (94); /* large packet msb */ + a_b[++length] = tochar (94); /* large packet lsb */ + } while (0); + + a_b[0] = START_CHAR; + a_b[1] = tochar (length); + a_b[2] = tochar (n); + a_b[3] = ACK_TYPE; + a_b[++length] = '\0'; + a_b[length] = tochar (chk1 (&a_b[1])); + a_b[++length] = his_eol; + a_b[++length] = '\0'; + s1_sendpacket (a_b); +} + +/* k_recv receives a OS Open image file over kermit line */ +static int k_recv (void) +{ + char new_char; + char k_state, k_state_saved; + int sum; + int done; + int length; + int n, last_n; + int z = 0; + int len_lo, len_hi; + + /* initialize some protocol parameters */ + his_eol = END_CHAR; /* default end of line character */ + his_pad_count = 0; + his_pad_char = '\0'; + his_quote = K_ESCAPE; + + /* initialize the k_recv and k_data state machine */ + done = 0; + k_state = 0; + k_data_init (); + k_state_saved = k_state; + k_data_save (); + n = 0; /* just to get rid of a warning */ + last_n = -1; + + /* expect this "type" sequence (but don't check): + S: send initiate + F: file header + D: data (multiple) + Z: end of file + B: break transmission + */ + + /* enter main loop */ + while (!done) { + /* set the send packet pointer to begining of send packet parms */ + send_ptr = send_parms; + + /* With each packet, start summing the bytes starting with the length. + Save the current sequence number. + Note the type of the packet. + If a character less than SPACE (0x20) is received - error. + */ + +#if 0 + /* OLD CODE, Prior to checking sequence numbers */ + /* first have all state machines save current states */ + k_state_saved = k_state; + k_data_save (); +#endif + + /* get a packet */ + /* wait for the starting character or ^C */ + for (;;) { + switch (getc ()) { + case START_CHAR: /* start packet */ + goto START; + case ETX_CHAR: /* ^C waiting for packet */ + return (0); + default: + ; + } + } +START: + /* get length of packet */ + sum = 0; + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + length = untochar (new_char); + /* get sequence number */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + n = untochar (new_char); + --length; + + /* NEW CODE - check sequence numbers for retried packets */ + /* Note - this new code assumes that the sequence number is correctly + * received. Handling an invalid sequence number adds another layer + * of complexity that may not be needed - yet! At this time, I'm hoping + * that I don't need to buffer the incoming data packets and can write + * the data into memory in real time. + */ + if (n == last_n) { + /* same sequence number, restore the previous state */ + k_state = k_state_saved; + k_data_restore (); + } else { + /* new sequence number, checkpoint the download */ + last_n = n; + k_state_saved = k_state; + k_data_save (); + } + /* END NEW CODE */ + + /* get packet type */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + k_state = new_char; + --length; + /* check for extended length */ + if (length == -2) { + /* (length byte was 0, decremented twice) */ + /* get the two length bytes */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + len_hi = untochar (new_char); + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + len_lo = untochar (new_char); + length = len_hi * 95 + len_lo; + /* check header checksum */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + if (new_char != tochar ((sum + ((sum >> 6) & 0x03)) & 0x3f)) + goto packet_error; + sum += new_char & 0xff; +/* --length; */ /* new length includes only data and block check to come */ + } + /* bring in rest of packet */ + while (length > 1) { + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + sum += new_char & 0xff; + --length; + if (k_state == DATA_TYPE) { + /* pass on the data if this is a data packet */ + k_data_char (new_char); + } else if (k_state == SEND_TYPE) { + /* save send pack in buffer as is */ + *send_ptr++ = new_char; + /* if too much data, back off the pointer */ + if (send_ptr >= &send_parms[SEND_DATA_SIZE]) + --send_ptr; + } + } + /* get and validate checksum character */ + new_char = getc (); + if ((new_char & 0xE0) == 0) + goto packet_error; + if (new_char != tochar ((sum + ((sum >> 6) & 0x03)) & 0x3f)) + goto packet_error; + /* get END_CHAR */ + new_char = getc (); + if (new_char != END_CHAR) { + packet_error: + /* restore state machines */ + k_state = k_state_saved; + k_data_restore (); + /* send a negative acknowledge packet in */ + send_nack (n); + } else if (k_state == SEND_TYPE) { + /* crack the protocol parms, build an appropriate ack packet */ + handle_send_packet (n); + } else { + /* send simple acknowledge packet in */ + send_ack (n); + /* quit if end of transmission */ + if (k_state == BREAK_TYPE) + done = 1; + } + ++z; + } + return ((ulong) os_data_addr - (ulong) bin_start_address); +} diff --git a/uart-loader/config.mk b/uart-loader/config.mk new file mode 100644 index 0000000..1365b9d --- /dev/null +++ b/uart-loader/config.mk @@ -0,0 +1,175 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +# clean the slate ... +PLATFORM_RELFLAGS = +PLATFORM_CPPFLAGS = +PLATFORM_LDFLAGS = + +# +# When cross-compiling on NetBSD, we have to define __PPC__ or else we +# will pick up a va_list declaration that is incompatible with the +# actual argument lists emitted by the compiler. +# +# [Tested on NetBSD/i386 1.5 + cross-powerpc-netbsd-1.3] + +ifeq ($(ARCH),ppc) +ifeq ($(CROSS_COMPILE),powerpc-netbsd-) +PLATFORM_CPPFLAGS+= -D__PPC__ +endif +ifeq ($(CROSS_COMPILE),powerpc-openbsd-) +PLATFORM_CPPFLAGS+= -D__PPC__ +endif +endif + +ifeq ($(ARCH),arm) +ifeq ($(CROSS_COMPILE),powerpc-netbsd-) +PLATFORM_CPPFLAGS+= -D__ARM__ +endif +ifeq ($(CROSS_COMPILE),powerpc-openbsd-) +PLATFORM_CPPFLAGS+= -D__ARM__ +endif +endif + +ifdef ARCH +sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules +endif +ifdef CPU +sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules +endif +ifdef VENDOR +BOARDDIR = $(VENDOR)/$(BOARD) +else +BOARDDIR = $(BOARD) +endif +ifdef BOARD +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk # include board specific rules +endif + +######################################################################### + +CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ + else if [ -x /bin/bash ]; then echo /bin/bash; \ + else echo sh; fi ; fi) + +ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +HOSTCC = cc +else +HOSTCC = gcc +endif +HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer +HOSTSTRIP = strip + +######################################################################### +# +# Option checker (courtesy linux kernel) to ensure +# only supported compiler options are used +# +cc-option = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \ + > /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;) + +# +# Include the make variables (CC, etc...) +# +AS = $(CROSS_COMPILE)as +LD = $(CROSS_COMPILE)ld +CC = $(CROSS_COMPILE)gcc +CPP = $(CC) -E +AR = $(CROSS_COMPILE)ar +NM = $(CROSS_COMPILE)nm +STRIP = $(CROSS_COMPILE)strip +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump +RANLIB = $(CROSS_COMPILE)RANLIB + +RELFLAGS= $(PLATFORM_RELFLAGS) +DBGFLAGS= -g # -DDEBUG +OPTFLAGS= -Os #-fomit-frame-pointer +ifndef LDSCRIPT +#LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/x-load.lds.debug +LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/x-load.lds +endif +OBJCFLAGS += --gap-fill=0xff + +gccincdir := $(shell $(CC) -print-file-name=include) + +CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ + -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \ + -I$(TOPDIR)/include \ + -fno-builtin -ffreestanding -nostdinc -isystem \ + $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) + +ifdef BUILD_TAG +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \ + -DBUILD_TAG='"$(BUILD_TAG)"' +else +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes +endif + +AFLAGS_DEBUG := -Wa,-gstabs +AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) + +LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) + +# Location of a usable BFD library, where we define "usable" as +# "built for ${HOST}, supports ${TARGET}". Sensible values are +# - When cross-compiling: the root of the cross-environment +# - Linux/ppc (native): /usr +# - NetBSD/ppc (native): you lose ... (must extract these from the +# binutils build directory, plus the native and U-Boot include +# files don't like each other) +# +# So far, this is used only by tools/gdb/Makefile. + +ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +BFD_ROOT_DIR = /usr/local/tools +else +ifeq ($(HOSTARCH),$(ARCH)) +# native +BFD_ROOT_DIR = /usr +else +#BFD_ROOT_DIR = /LinuxPPC/CDK # Linux/i386 +#BFD_ROOT_DIR = /usr/pkg/cross # NetBSD/i386 +BFD_ROOT_DIR = /opt/powerpc +endif +endif + +######################################################################### + +export CONFIG_SHELL HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \ + AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP \ + MAKE +export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS + +######################################################################### + +%.s: %.S + $(CPP) $(AFLAGS) -o $@ $(CURDIR)/$< +%.o: %.S + $(CC) $(AFLAGS) -c -o $@ $(CURDIR)/$< +%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< + +######################################################################### diff --git a/uart-loader/cpu/omap3/Makefile b/uart-loader/cpu/omap3/Makefile new file mode 100644 index 0000000..fca0dad --- /dev/null +++ b/uart-loader/cpu/omap3/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o +OBJS = cpu.o mmc.o sys_info.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/uart-loader/cpu/omap3/config.mk b/uart-loader/cpu/omap3/config.mk new file mode 100644 index 0000000..71547f3 --- /dev/null +++ b/uart-loader/cpu/omap3/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 + +# PLATFORM_CPPFLAGS += -march=armv7-a +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/uart-loader/cpu/omap3/cpu.c b/uart-loader/cpu/omap3/cpu.c new file mode 100644 index 0000000..1cf422a --- /dev/null +++ b/uart-loader/cpu/omap3/cpu.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2004-2006 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ +#include + +/* See also ARM Ref. Man. */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ +#define C1_WB (1<<3) /* merging write buffer on/off */ +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ +#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ + +int cpu_init (void) +{ + return 0; +} + diff --git a/uart-loader/cpu/omap3/mmc.c b/uart-loader/cpu/omap3/mmc.c new file mode 120000 index 0000000..ca45f14 --- /dev/null +++ b/uart-loader/cpu/omap3/mmc.c @@ -0,0 +1 @@ +../../../u-boot/cpu/omap3/mmc.c \ No newline at end of file diff --git a/uart-loader/cpu/omap3/mmc_host_def.h b/uart-loader/cpu/omap3/mmc_host_def.h new file mode 120000 index 0000000..d40a0a1 --- /dev/null +++ b/uart-loader/cpu/omap3/mmc_host_def.h @@ -0,0 +1 @@ +../../../u-boot/cpu/omap3/mmc_host_def.h \ No newline at end of file diff --git a/uart-loader/cpu/omap3/mmc_protocol.h b/uart-loader/cpu/omap3/mmc_protocol.h new file mode 120000 index 0000000..f79c007 --- /dev/null +++ b/uart-loader/cpu/omap3/mmc_protocol.h @@ -0,0 +1 @@ +../../../u-boot/cpu/omap3/mmc_protocol.h \ No newline at end of file diff --git a/uart-loader/cpu/omap3/start.S b/uart-loader/cpu/omap3/start.S new file mode 100644 index 0000000..142c425 --- /dev/null +++ b/uart-loader/cpu/omap3/start.S @@ -0,0 +1,230 @@ +/* + * armboot - Startup Code for OMP2420/ARM1136 CPU-core + * + * Copyright (c) 2004-2006 Texas Instruments + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2003 Richard Woodruff + * Copyright (c) 2003 Kshitij + * Copyright (c) 2004 Jian Zhang + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +.globl _start +_start: + b reset + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + +_hang: + .word do_hang + + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 /* now 16*4=64 */ + +.global _end_vect +_end_vect: + + .balignl 16,0xdeadbeef +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +/* + * the actual reset code + */ + +reset: + ldr r4, scratchpad /* r4 <- scratchpad reg address */ + ldr r5, [r0, #0x4] /* r5 <- value of boot device */ + str r5, [r4] /* store r5 in scratchpad reg */ + + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* Copy vectors to mask ROM indirect addr */ + adr r0, _start /* r0 <- current position of code */ + add r0, r0, #4 /* skip reset vector */ + mov r2, #64 /* r2 <- size to copy */ + add r2, r0, r2 /* r2 <- source end address */ + mov r1, #SRAM_OFFSET0 /* build vect addr */ + mov r3, #SRAM_OFFSET1 + add r1, r1, r3 + mov r3, #SRAM_OFFSET2 + add r1, r1, r3 +next: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next /* loop until equal */ + + bl cpy_clk_code /* put dpll adjust code behind vectors */ + + /* the mask ROM code should have PLL and others stable */ + bl cpu_init_crit + +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* no need to relocate if XIP */ + beq stack_setup /* skip txt cpy if XIP(SRAM, SDRAM) */ + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub sp, r0, #128 /* leave 32 words for abort-stack */ + and sp, sp, #~7 /* 8 byte alinged for (ldr/str)d */ + + /* Clear BSS (if any). Is below tx (watch load addr - need space) */ +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear value */ +clbss_l: + str r2, [r0] /* clear BSS location */ + cmp r0, r1 /* are we at the end yet */ + add r0, r0, #4 /* increment clear index pointer */ + bne clbss_l /* keep clearing till at end */ + + ldr pc, _start_armboot /* jump to C code */ + +_start_armboot: .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +cpu_init_crit: + /* + * Invalidate L1 I/D + */ + mov r0, #0 /* set up for MCR */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr p15, 0, r0, c7, c5, 1 /* invalidate icache */ + + /* Invalide L2 cache (gp device call point) + * - warning, this may have issues on EMU/HS devices + * this call can corrupt r0-r5 + */ + mov r12, #0x1 @ set up to invalide L2 +smi: .word 0xE1600070 @ Call SMI monitor + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002000 @ clear bits 13 (--V-) + bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) + orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align +#ifndef CONFIG_ICACHE_OFF + orr r0, r0, #0x00001800 @ set bit 11,12 (---I Z---) BTB,I-Cache +#endif + mcr p15, 0, r0, c1, c0, 0 + + /* + * Jump to board specific initialization... The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle wake up conditions. + */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* pass on info about skipping some init portions */ + moveq r0,#0x1 /* flag to skip prcm and sdrc setup */ + movne r0,#0x0 + + mov ip, lr /* persevere link reg across call */ + bl lowlevel_init /* go setup pll,mux,memory */ + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ + +/* + * exception handler + */ + .align 5 +do_hang: + ldr sp, _TEXT_BASE /* use 32 words abort stack */ + bl hang /* hang and never return */ + +scratchpad: + .word 0x480029c0 diff --git a/uart-loader/cpu/omap3/sys_info.c b/uart-loader/cpu/omap3/sys_info.c new file mode 100644 index 0000000..9a14d0e --- /dev/null +++ b/uart-loader/cpu/omap3/sys_info.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * Derived from board specific omap code by + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + +/* + * get_cpu_rev(void) - extract version info + */ +u32 get_cpu_rev(void) +{ + u32 cpuid = 0; + ctrl_id_t *id_base; + /* + * On ES1.0 the IDCODE register is not exposed on L4 + * so using CPU ID to differentiate between ES1.0 and > ES1.0. + */ + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); + if ((cpuid & 0xf) == 0x0) + return CPU_3XX_ES10; + else { + /* Decode the IDs on > ES1.0 */ + id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE; + + cpuid = (__raw_readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf; + + /* Some early ES2.0 seem to report ID 0, fix this */ + if (cpuid == 0) + cpuid = CPU_3XX_ES20; + + return cpuid; + } +} + +/* + * cpu_is_3410(void) - returns true for 3410 + */ +u32 cpu_is_3410(void) +{ + int status; + if(get_cpu_rev() < CPU_3XX_ES20) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + diff --git a/uart-loader/disk/Makefile b/uart-loader/disk/Makefile new file mode 100644 index 0000000..7da4624 --- /dev/null +++ b/uart-loader/disk/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +#CFLAGS += -DET_DEBUG -DDEBUG + +LIB = libdisk.a + +OBJS = part.o + +all: $(LIB) + +$(LIB): $(START) $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/uart-loader/disk/part.c b/uart-loader/disk/part.c new file mode 100644 index 0000000..a367f13 --- /dev/null +++ b/uart-loader/disk/part.c @@ -0,0 +1,273 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#undef PART_DEBUG + +#ifdef PART_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + defined(CONFIG_MMC) || \ + defined(CONFIG_SYSTEMACE) ) + +/* ------------------------------------------------------------------------- */ +/* + * reports device info to the user + */ +void dev_print (block_dev_desc_t *dev_desc) +{ +#ifdef CONFIG_LBA48 + uint64_t lba512; /* number of blocks if 512bytes block size */ +#else + lbaint_t lba512; +#endif + + if (dev_desc->type==DEV_TYPE_UNKNOWN) { + return; + } + if (dev_desc->if_type==IF_TYPE_SCSI) { + printf ("(%d:%d) ", dev_desc->target,dev_desc->lun); + } + if (dev_desc->if_type==IF_TYPE_IDE) { + printf ("Model: %s Firm: %s Ser#: %s\n", + dev_desc->vendor, + dev_desc->revision, + dev_desc->product); + } else { + printf ("Vendor: %s Prod.: %s Rev: %s\n", + dev_desc->vendor, + dev_desc->product, + dev_desc->revision); + } + printf (" Type: "); + switch (dev_desc->type & 0x1F) { + case DEV_TYPE_HARDDISK: printf ("Hard Disk"); + break; + case DEV_TYPE_CDROM: printf ("CD ROM"); + break; + case DEV_TYPE_OPDISK: printf ("Optical Device"); + break; + case DEV_TYPE_TAPE: printf ("Tape"); + break; + default: printf ("# %02X #", dev_desc->type & 0x1F); + break; + } + if ((dev_desc->lba * dev_desc->blksz)>0L) { + ulong mb, mb_quot, mb_rem, gb, gb_quot, gb_rem; + lbaint_t lba; + + lba = dev_desc->lba; + + lba512 = (lba * (dev_desc->blksz/512)); + mb = (10 * lba512) / 2048; /* 2048 = (1024 * 1024) / 512 MB */ + /* round to 1 digit */ + mb_quot = mb / 10; + mb_rem = mb - (10 * mb_quot); + + gb = mb / 1024; + gb_quot = gb / 10; + gb_rem = gb - (10 * gb_quot); +#ifdef CONFIG_LBA48 + if (dev_desc->lba48) + printf (" Supports 48-bit addressing\n"); +#endif +#if defined(CFG_64BIT_LBA) && defined(CFG_64BIT_VSPRINTF) + printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%qd x %ld)\n", + mb_quot, mb_rem, + gb_quot, gb_rem, + lba, + dev_desc->blksz); +#else + printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\n", + mb_quot, mb_rem, + gb_quot, gb_rem, + (ulong)lba, + dev_desc->blksz); +#endif + } else { + printf (" Capacity: not available\n"); + } +} +#endif /* CFG_CMD_IDE || CFG_CMD_SCSI || CFG_CMD_USB || CONFIG_MMC */ + +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + (CONFIG_COMMANDS & CFG_CMD_MMC) || \ + defined(CONFIG_SYSTEMACE) ) + +#if defined(CONFIG_MAC_PARTITION) || \ + defined(CONFIG_DOS_PARTITION) || \ + defined(CONFIG_ISO_PARTITION) || \ + defined(CONFIG_AMIGA_PARTITION) + +void init_part (block_dev_desc_t * dev_desc) +{ +#ifdef CONFIG_ISO_PARTITION + if (test_part_iso(dev_desc) == 0) { + dev_desc->part_type = PART_TYPE_ISO; + return; + } +#endif + +#ifdef CONFIG_MAC_PARTITION + if (test_part_mac(dev_desc) == 0) { + dev_desc->part_type = PART_TYPE_MAC; + return; + } +#endif + +#ifdef CONFIG_DOS_PARTITION + if (test_part_dos(dev_desc) == 0) { + dev_desc->part_type = PART_TYPE_DOS; + return; + } +#endif + +#ifdef CONFIG_AMIGA_PARTITION + if (test_part_amiga(dev_desc) == 0) { + dev_desc->part_type = PART_TYPE_AMIGA; + return; + } +#endif +} + + +int get_partition_info (block_dev_desc_t *dev_desc, int part, disk_partition_t *info) +{ + switch (dev_desc->part_type) { +#ifdef CONFIG_MAC_PARTITION + case PART_TYPE_MAC: + if (get_partition_info_mac(dev_desc,part,info) == 0) { + PRINTF ("## Valid MAC partition found ##\n"); + return (0); + } + break; +#endif + +#ifdef CONFIG_DOS_PARTITION + case PART_TYPE_DOS: + if (get_partition_info_dos(dev_desc,part,info) == 0) { + PRINTF ("## Valid DOS partition found ##\n"); + return (0); + } + break; +#endif + +#ifdef CONFIG_ISO_PARTITION + case PART_TYPE_ISO: + if (get_partition_info_iso(dev_desc,part,info) == 0) { + PRINTF ("## Valid ISO boot partition found ##\n"); + return (0); + } + break; +#endif + +#ifdef CONFIG_AMIGA_PARTITION + case PART_TYPE_AMIGA: + if (get_partition_info_amiga(dev_desc, part, info) == 0) + { + PRINTF ("## Valid Amiga partition found ##\n"); + return (0); + } + break; +#endif + default: + break; + } + return (-1); +} + +static void print_part_header (const char *type, block_dev_desc_t * dev_desc) +{ + switch (dev_desc->if_type) { + case IF_TYPE_IDE: printf ("IDE"); + break; + case IF_TYPE_SCSI: printf ("SCSI"); + break; + case IF_TYPE_ATAPI: printf ("ATAPI"); + break; + case IF_TYPE_USB: printf ("USB"); + break; + case IF_TYPE_DOC: printf ("DOC"); + break; + default: printf ("UNKNOWN"); + break; + } + printf (" device %d -- Partition Type: %s\n\n", + dev_desc->dev, type); +} + +void print_part (block_dev_desc_t * dev_desc) +{ + + switch (dev_desc->part_type) { +#ifdef CONFIG_MAC_PARTITION + case PART_TYPE_MAC: + PRINTF ("## Testing for valid MAC partition ##\n"); + print_part_header ("MAC", dev_desc); + print_part_mac (dev_desc); + return; +#endif +#ifdef CONFIG_DOS_PARTITION + case PART_TYPE_DOS: + PRINTF ("## Testing for valid DOS partition ##\n"); + print_part_header ("DOS", dev_desc); + print_part_dos (dev_desc); + return; +#endif + +#ifdef CONFIG_ISO_PARTITION + case PART_TYPE_ISO: + PRINTF ("## Testing for valid ISO Boot partition ##\n"); + print_part_header ("ISO", dev_desc); + print_part_iso (dev_desc); + return; +#endif + +#ifdef CONFIG_AMIGA_PARTITION + case PART_TYPE_AMIGA: + PRINTF ("## Testing for a valid Amiga partition ##\n"); + print_part_header ("AMIGA", dev_desc); + print_part_amiga (dev_desc); + return; +#endif + } +} + + +#else /* neither MAC nor DOS nor ISO partition configured */ +# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION nor CONFIG_ISO_PARTITION configured! +#endif + +#endif /* (CONFIG_COMMANDS & CFG_CMD_IDE) || CONFIG_COMMANDS & CFG_CMD_SCSI) */ diff --git a/uart-loader/drivers/Makefile b/uart-loader/drivers/Makefile new file mode 100644 index 0000000..ffc38b3 --- /dev/null +++ b/uart-loader/drivers/Makefile @@ -0,0 +1,70 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG -DDEBUG + +LIB = libdrivers.a +OBJS = serial.o ns16550.o onenand.o + +ifeq ($(BOARD), omap3430sdp) +OBJS += k9f1g08r0a.o +endif + +ifeq ($(BOARD), omap3430labrador) +OBJS += k9f1g08r0a.o +endif + +ifeq ($(BOARD), omap2420h4) +OBJS += k9k1216.o +endif + +ifeq ($(BOARD), omap2430sdp) +OBJS += k9k1216.o +endif + +ifeq ($(BOARD), omap1710h3) +OBJS += k9f5616.o +endif + + +## Disabled for now: +## cs8900.o ct69000.o dataflash.o dc2114x.o ds1722.o \ +## lan91c96.o mw_eeprom.o natsemi.o \ +## smc91111.o smiLynxEM.o spi_eeprom.o sym53c8xx.o \ +## + +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/uart-loader/drivers/k9f1g08r0a.c b/uart-loader/drivers/k9f1g08r0a.c new file mode 100644 index 0000000..f0d6452 --- /dev/null +++ b/uart-loader/drivers/k9f1g08r0a.c @@ -0,0 +1,512 @@ +/* + * (C) Copyright 2004 Texas Instruments + * Jian Zhang + * + * Samsung K9F1G08R0AQ0C NAND chip driver for an OMAP2420 board + * + * This file is based on the following u-boot file: + * common/cmd_nand.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include +#include + +#ifdef CFG_NAND_K9F1G08R0A + +#define K9F1G08R0A_MFR 0xec /* Samsung */ +#define K9F1G08R0A_ID 0xa1 /* part # */ + +/* Since Micron and Samsung parts are similar in geometry and bus width + * we can use the same driver. Need to revisit to make this file independent + * of part/manufacturer + */ +#define MT29F1G_MFR 0x2c /* Micron */ +#define MT29F1G_ID 0xa1 /* x8, 1GiB */ +#define MT29F2G_ID 0xba /* x16, 2GiB */ +#define MT29F4G_ID 0xbc /* x16, 4GiB */ + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE (ADDR_COLUMN | ADDR_PAGE) + +#define ADDR_OOB (0x4 | ADDR_COLUMN_PAGE) + +#define PAGE_SIZE 2048 +#define OOB_SIZE 64 +#define MAX_NUM_PAGES 64 + +#ifdef NAND_HW_ROMCODE_ECC_LAYOUT +#define __raw_ecc_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_ecc_writel(v, a) (*(volatile unsigned int *)(a) = (v)) +/* Register definitions */ +#define GPMC_BASE_ADDR OMAP34XX_GPMC_BASE + +#define ECCCLEAR (0x1 << 8) +#define ECCRESULTREG1 (0x1 << 0) +#define ECCSIZE512BYTE 0xFF +#define ECCSIZE1 (ECCSIZE512BYTE << 22) +#define ECCSIZE0 (ECCSIZE512BYTE << 12) +#define ECCSIZE0SEL (0x000 << 0) + +#define ECC_BLOCK_SIZE 512 +#ifdef NAND_16BIT +#define DEV_WIDTH 1 +static u_char ecc_pos[] = { 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13 +}; +#else +#define DEV_WIDTH 0 +static u_char ecc_pos[] = { 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12 +}; +#endif + +#else +#ifdef NAND_16BIT +#define DEV_WIDTH 1 +#else +#define DEV_WIDTH 0 +#endif + +#ifdef CFG_SW_ECC_512 +#define ECC_BLOCK_SIZE 512 +#else +#define ECC_BLOCK_SIZE 256 +#endif +/* JFFS2 large page layout for 3-byte ECC per 256 bytes ECC layout */ +/* This is the only SW ECC supported by u-boot. So to load u-boot + * this should be supported */ +static u_char ecc_pos[] = {40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63}; + +#endif + +#define ECC_SIZE (sizeof(ecc_pos)) +#define ECC_STEPS 3 +#define ECC_CHECK_ENABLE + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %0, #1\n" + "bne 1b" : "=r" (loops) : "0" (loops)); +} + +static int nand_read_page(u_char *buf, ulong page_addr); +static int nand_read_oob(u_char *buf, ulong page_addr); + +static unsigned long chipsize = (256 << 20); + +/* NanD_Command: Send a flash command to the flash chip */ +static int NanD_Command(unsigned char command) +{ + NAND_CTL_SETCLE(NAND_ADDR); + + WRITE_NAND_COMMAND(command, NAND_ADDR); + NAND_CTL_CLRCLE(NAND_ADDR); + + if (command == NAND_CMD_RESET) { + unsigned char ret_val; + NanD_Command(NAND_CMD_STATUS); + do { + ret_val = READ_NAND(NAND_ADDR); /* wait till ready */ + } while ((ret_val & 0x40) != 0x40); + } + + NAND_WAIT_READY(); + return 0; +} + + +/* NanD_Address: Set the current address for the flash chip */ +static int NanD_Address(unsigned int numbytes, unsigned long ofs) +{ + uchar u; + + NAND_CTL_SETALE(NAND_ADDR); + + if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE + || numbytes == ADDR_OOB) + { + ushort col = ofs; + + u = col & 0xff; + WRITE_NAND_ADDRESS(u, NAND_ADDR); + + u = (col >> 8) & 0x07; + if (numbytes == ADDR_OOB) + u = u | ((DEV_WIDTH == 1) ? (1 << 2) : (1 << 3)); + WRITE_NAND_ADDRESS(u, NAND_ADDR); + } + + if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE + || numbytes == ADDR_OOB) + { + u = (ofs >> 11) & 0xff; + WRITE_NAND_ADDRESS(u, NAND_ADDR); + u = (ofs >> 19) & 0xff; + WRITE_NAND_ADDRESS(u, NAND_ADDR); + + /* One more address cycle for devices > 128MiB */ + if (chipsize > (128 << 20)) { + u = (ofs >> 27) & 0xff; + WRITE_NAND_ADDRESS(u, NAND_ADDR); + } + } + + NAND_CTL_CLRALE(NAND_ADDR); + + NAND_WAIT_READY(); + return 0; +} + +/* read chip mfr and id + * return 0 if they match board config + * return 1 if not + */ +int nand_chip() +{ + int mfr, id; + + NAND_ENABLE_CE(); + + if (NanD_Command(NAND_CMD_RESET)) { + printf("Err: RESET\n"); + NAND_DISABLE_CE(); + return 1; + } + + if (NanD_Command(NAND_CMD_READID)) { + printf("Err: READID\n"); + NAND_DISABLE_CE(); + return 1; + } + + NanD_Address(ADDR_COLUMN, 0); + + mfr = READ_NAND(NAND_ADDR); + id = READ_NAND(NAND_ADDR); + + NAND_DISABLE_CE(); + + /* Check Micron part or Samsung part */ + if ((mfr == MT29F1G_MFR && (id == MT29F1G_ID || + id == MT29F2G_ID || id == MT29F4G_ID)) || + (mfr == K9F1G08R0A_MFR && (id == K9F1G08R0A_ID))) + return 0; + + return 1; +} + +/* read a block data to buf + * return 1 if the block is bad or ECC error can't be corrected for any page + * return 0 on sucess + */ +int nand_read_block(unsigned char *buf, ulong block_addr) +{ + int i, offset = 0; + +#ifdef ECC_CHECK_ENABLE + u8 oob_buf[OOB_SIZE]; + + /* check bad block */ + /* 0th word in spare area needs be 0xff */ + if (nand_read_oob(oob_buf, block_addr) || (oob_buf[0] & 0xff) != 0xff) { + printf("Skipped bad block at 0x%x\n", block_addr); + return 1; /* skip bad block */ + } +#endif + /* read the block page by page*/ + for (i = 0; i < MAX_NUM_PAGES; i++) { + if (nand_read_page(buf + offset, block_addr + offset)) + return 1; + offset += PAGE_SIZE; + } + + return 0; +} + +#ifdef NAND_HW_ROMCODE_ECC_LAYOUT +/* + * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in + * GPMC controller + * + */ +static void omap_hwecc_init(void) +{ + /* + * Init ECC Control Register + * Clear all ECC | Enable Reg1 + */ + __raw_ecc_writel(ECCCLEAR | ECCRESULTREG1, + GPMC_BASE_ADDR + GPMC_ECC_CONTROL); + __raw_ecc_writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, + GPMC_BASE_ADDR + GPMC_ECC_SIZE_CONFIG); + __raw_ecc_writel(0x1 | (0 << 1) | (DEV_WIDTH << 7), + GPMC_BASE_ADDR + GPMC_ECC_CONFIG); +} + +/* + * gen_true_ecc - This function will generate true ECC value, which + * can be used when correcting data read from NAND flash memory core + * + * @ecc_buf: buffer to store ecc code + * + * @return: re-formatted ECC value + */ +static uint32_t gen_true_ecc(uint8_t *ecc_buf) +{ + return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) | + ((ecc_buf[2] & 0x0F) << 8); +} + +/* + * omap_calculate_ecc - Generate non-inverted ECC bytes. + * + * Using noninverted ECC can be considered ugly since writing a blank + * page ie. padding will clear the ECC bytes. This is no problem as + * long nobody is trying to write data on the seemingly unused page. + * Reading an erased page will produce an ECC mismatch between + * generated and read ECC bytes that has to be dealt with separately. + * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC + * is used, the result of read will be 0x0 while the ECC offsets of the + * spare area will be 0xFF which will result in an ECC mismatch. + * @dat: unused + * @ecc_code: ecc_code buffer + */ +static int omap_calculate_ecc(const uint8_t *dat, uint8_t *ecc_code) +{ + u_int32_t val; + + /* Start Reading from HW ECC1_Result = 0x200 */ + val = __raw_ecc_readl(GPMC_BASE_ADDR + GPMC_ECC1_RESULT); + + ecc_code[0] = val & 0xFF; + ecc_code[1] = (val >> 16) & 0xFF; + ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); + + /* + * Stop reading anymore ECC vals and clear old results + * enable will be called if more reads are required + */ + __raw_ecc_writel(0x000, GPMC_BASE_ADDR + GPMC_ECC_CONFIG); + + return 0; +} + +static int hweight32(unsigned int val) +{ + u_char count = 0; + for ( ; val; count++) + val &= (val - 1); + return count; +} + +/* + * omap_correct_data - Compares the ecc read from nand spare area with ECC + * registers values and corrects one bit error if it has occured + * Further details can be had from OMAP TRM and the following selected links: + * http://en.wikipedia.org/wiki/Hamming_code + * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf + * + * @dat: page data + * @read_ecc: ecc read from nand flash + * @calc_ecc: ecc read from ECC registers + * + * @return 0 if data is OK or corrected, else returns -1 + */ +static int omap_correct_data(uint8_t *dat, + uint8_t *read_ecc, uint8_t *calc_ecc) +{ + uint32_t orig_ecc, new_ecc, res, hm; + uint16_t parity_bits, byte; + uint8_t bit; + + /* Regenerate the orginal ECC */ + orig_ecc = gen_true_ecc(read_ecc); + new_ecc = gen_true_ecc(calc_ecc); + /* Get the XOR of real ecc */ + res = orig_ecc ^ new_ecc; + if (res) { + /* Get the hamming width */ + hm = hweight32(res); + /* Single bit errors can be corrected! */ + if (hm == 12) { + /* Correctable data! */ + parity_bits = res >> 16; + bit = (parity_bits & 0x7); + byte = (parity_bits >> 3) & 0x1FF; + /* Flip the bit to correct */ + dat[byte] ^= (0x1 << bit); + } else if (hm == 1) { + printf("Error: Ecc is wrong\n"); + /* ECC itself is corrupted */ + return 2; + } else { + /* + * hm distance != parity pairs OR one, could mean 2 bit + * error OR potentially be on a blank page.. + * orig_ecc: contains spare area data from nand flash. + * new_ecc: generated ecc while reading data area. + * Note: if the ecc = 0, all data bits from which it was + * generated are 0xFF. + * The 3 byte(24 bits) ecc is generated per 512byte + * chunk of a page. If orig_ecc(from spare area) + * is 0xFF && new_ecc(computed now from data area)=0x0, + * this means that data area is 0xFF and spare area is + * 0xFF. A sure sign of a erased page! + */ + if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000)) + return 0; + printf("Error: Bad compare! failed\n"); + /* detected 2 bit error */ + return -1; + } + } + return 0; +} + +#define NAND_ECC_INIT() omap_hwecc_init() +#define NAND_ECC_CALC(data_buf, ecc_buf) omap_calculate_ecc(data_buf, ecc_buf) +#define NAND_ECC_CORRECT(data_buf, ecc_gen, ecc_old)\ + omap_correct_data(data_buf, ecc_gen, ecc_old) +#else +/* Software ECC APIs */ +#define NAND_ECC_INIT() +#define NAND_ECC_CALC(data_buf, ecc_buf) nand_calculate_ecc(data_buf, ecc_buf) +#define NAND_ECC_CORRECT(data_buf, ecc_gen, ecc_old)\ + nand_correct_data(data_buf, ecc_gen, ecc_old) +#endif /* NAND_HW_ROMCODE_ECC_LAYOUT */ + +/* read a page with ECC */ +static int nand_read_page(u_char *buf, ulong page_addr) +{ +#ifdef ECC_CHECK_ENABLE + u_char ecc_code[ECC_SIZE]; + u_char ecc_calc[ECC_SIZE]; + u_char oob_buf[OOB_SIZE]; +#endif + u16 val; + int cntr; + int len; + int count; + +#ifdef NAND_16BIT + u16 *p = (u16 *) buf; +#else + u_char *p = (u_char *) buf; +#endif + + NAND_ENABLE_CE(); + NanD_Command(NAND_CMD_READ0); + NanD_Address(ADDR_COLUMN_PAGE, page_addr); + NanD_Command(NAND_CMD_READSTART); + NAND_WAIT_READY(); + + /* A delay seems to be helping here. needs more investigation */ + delay(10000); + len = (DEV_WIDTH == 1) ? ECC_BLOCK_SIZE >> 1 : ECC_BLOCK_SIZE; + + /* Read in chunks of data. */ + for (count = 0; count < ECC_SIZE; count += ECC_STEPS) { + NAND_ECC_INIT(); + for (cntr = 0; cntr < len; cntr++) { + *p++ = READ_NAND(NAND_ADDR); + delay(10); + } + NAND_ECC_CALC((p - ECC_BLOCK_SIZE), &ecc_calc[count]); + } + +#ifdef ECC_CHECK_ENABLE +#ifdef NAND_16BIT + p = (u16 *) oob_buf; +#else + p = (u_char *) oob_buf; +#endif + len = (DEV_WIDTH == 1) ? OOB_SIZE >> 1 : OOB_SIZE; + for (cntr = 0; cntr < len; cntr++) { + *p++ = READ_NAND(NAND_ADDR); + delay(10); + } + count = 0; + NAND_DISABLE_CE(); /* set pin high */ + + /* Pick the ECC bytes out of the oob data */ + for (cntr = 0; cntr < ECC_SIZE; cntr++) + ecc_code[cntr] = oob_buf[ecc_pos[cntr]]; + + for (count = 0, cntr = 0; cntr < PAGE_SIZE / ECC_BLOCK_SIZE; + cntr++, count += ECC_STEPS) { + if (NAND_ECC_CORRECT(buf, &ecc_code[count], &ecc_calc[count]) + == -1) { + printf("ECC Failed, page 0x%08x\n", page_addr); + for (val = 0; val < ECC_BLOCK_SIZE; val++) + printf("%x ", buf[val]); + printf(" Hang!!!\n"); + for (;;); + return 1; + } + buf += ECC_BLOCK_SIZE; + page_addr += ECC_BLOCK_SIZE; + } +#endif + return 0; +} + +/* read from the 16 bytes of oob data that correspond to a 512 / 2048 byte page. + */ +static int nand_read_oob(u_char *buf, ulong page_addr) +{ + int cntr; + int len; + +#ifdef NAND_16BIT + u16 *p = (u16 *) buf; +#else + u_char *p = (u_char *) buf; +#endif + len = (DEV_WIDTH == 1) ? OOB_SIZE >> 1 : OOB_SIZE; + + NAND_ENABLE_CE(); /* set pin low */ + NanD_Command(NAND_CMD_READ0); + NanD_Address(ADDR_OOB, page_addr); + NanD_Command(NAND_CMD_READSTART); + NAND_WAIT_READY(); + + /* A delay seems to be helping here. needs more investigation */ + delay(10000); + for (cntr = 0; cntr < len; cntr++) + *p++ = READ_NAND(NAND_ADDR); + + NAND_WAIT_READY(); + NAND_DISABLE_CE(); /* set pin high */ + + return 0; +} + +#endif diff --git a/uart-loader/drivers/k9f5616.c b/uart-loader/drivers/k9f5616.c new file mode 100644 index 0000000..4081664 --- /dev/null +++ b/uart-loader/drivers/k9f5616.c @@ -0,0 +1,229 @@ +/* + * (C) Copyright 2004 Texas Instruments + * Jian Zhang + * + * Samsung K9F5616Q0C NAND chip driver for an OMAP16xx board + * + * This file is based on the following u-boot file: + * common/cmd_nand.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CFG_NAND_K9F5616 + +#define K9F5616_MFR 0xec +#define K9F5616_ID 0x45 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define PAGE_SIZE 512 + +static int nand_read_page(u_char *buf, ulong page_addr); +static int nand_read_oob(u_char * buf, ulong page_addr); + +/* JFFS2 512-byte-page ECC layout */ +static u_char ecc_pos[] = {0,1,2,3,6,7}; +static u_char eccvalid_pos = 4; + +/* NanD_Command: Send a flash command to the flash chip */ +static int NanD_Command(unsigned char command) +{ + NAND_CTL_SETCLE(NAND_ADDR); + WRITE_NAND_COMMAND(command, NAND_ADDR); + NAND_CTL_CLRCLE(NAND_ADDR); + + if(command == NAND_CMD_RESET){ + unsigned char ret_val; + NanD_Command(NAND_CMD_STATUS); + do{ + ret_val = READ_NAND(NAND_ADDR);/* wait till ready */ + } while((ret_val & 0x40) != 0x40); + } + + NAND_WAIT_READY(); + return 0; +} + +/* NanD_Address: Set the current address for the flash chip */ +static int NanD_Address(int numbytes, unsigned long ofs) +{ + int i; + + NAND_CTL_SETALE(NAND_ADDR); + + if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) + WRITE_NAND_ADDRESS(ofs, NAND_ADDR); + + ofs = ofs >> 8; + + if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) + for (i = 0; i < 2; i++, ofs = ofs >> 8) + WRITE_NAND_ADDRESS(ofs, NAND_ADDR); + + NAND_CTL_CLRALE(NAND_ADDR); + + NAND_WAIT_READY(); + return 0; +} + +/* read chip mfr and id + * return 0 if they match board config + * return 1 if not + */ +int nand_chip() +{ + int mfr, id; + + NAND_ENABLE_CE(); + + if (NanD_Command(NAND_CMD_RESET)) { + printf("Err: RESET\n"); + NAND_DISABLE_CE(); + return 1; + } + + if (NanD_Command(NAND_CMD_READID)) { + printf("Err: READID\n"); + NAND_DISABLE_CE(); + return 1; + } + + NanD_Address(ADDR_COLUMN, 0); + + mfr = READ_NAND(NAND_ADDR); + id = READ_NAND(NAND_ADDR); + + NAND_DISABLE_CE(); + + return (mfr != K9F5616_MFR || id != K9F5616_ID); +} + +/* read a block data to buf + * return 1 if the block is bad or ECC error can't be corrected for any page + * return 0 on sucess + */ +int nand_read_block(unsigned char *buf, ulong block_addr) +{ + int i, offset = 0; + uchar oob_buf[16]; + + /* check bad block */ + /* 0th and 5th words need be 0xffff */ + if (nand_read_oob(oob_buf, block_addr) || +// oob_buf[0] != 0xff || oob_buf[1] != 0xff || +// oob_buf[10] != 0xff || oob_buf[11] != 0xff ){ + oob_buf[5] != 0xff){ + printf("Skipped bad block at 0x%x\n", block_addr); + return 1; /* skip bad block */ + } + + /* read the block page by page*/ + for (i=0; i<32; i++){ + if (nand_read_page(buf+offset, block_addr + offset)) + return 1; + offset += PAGE_SIZE; + } + + return 0; +} + +/* read a page with ECC */ +static int nand_read_page(u_char *buf, ulong page_addr) +{ + u_char ecc_code[6]; + u_char ecc_calc[3]; + u_char oob_buf[16]; + u_char *p; + u16 val; + int cntr; + + NAND_ENABLE_CE(); + NanD_Command(NAND_CMD_READ0); + NanD_Address(ADDR_COLUMN_PAGE, page_addr>>1); + + NAND_WAIT_READY(); + p = buf; + for (cntr = 0; cntr < 256; cntr++){ + val = READ_NAND(NAND_ADDR); + *p++ = val & 0xff; + *p++ = val >> 8; + } + + p = oob_buf; + for (cntr = 0; cntr < 8; cntr++){ + val = READ_NAND(NAND_ADDR); + *p++ = val & 0xff; + *p++ = val >> 8; + } + NAND_DISABLE_CE(); /* set pin high */ + + /* Pick the ECC bytes out of the oob data */ + for (cntr = 0; cntr < 6; cntr++) + ecc_code[cntr] = oob_buf[ecc_pos[cntr]]; + + + if ((oob_buf[eccvalid_pos] & 0x0f) != 0x0f) { + nand_calculate_ecc (buf, &ecc_calc[0]); + if (nand_correct_data (buf, &ecc_code[0], &ecc_calc[0]) == -1) { + printf ("ECC Failed, page 0x%08x\n", page_addr); + return 1; + } + } + + if ((oob_buf[eccvalid_pos] & 0xf0) != 0xf0) { + nand_calculate_ecc (buf + 256, &ecc_calc[0]); + if (nand_correct_data (buf + 256, &ecc_code[3], &ecc_calc[0]) == -1) { + printf ("ECC Failed, page 0x%08x\n", page_addr+0x100); + return 1; + } + } + + return 0; +} + +/* read from the 16 bytes of oob data that correspond to a 512 byte page. + */ +static int nand_read_oob(u_char *buf, ulong page_addr) +{ + u16 val; + int cntr; + + NAND_ENABLE_CE(); /* set pin low */ + NanD_Command(NAND_CMD_READOOB); + NanD_Address(ADDR_COLUMN_PAGE, page_addr>>1); + NAND_WAIT_READY(); + + for (cntr = 0; cntr < 8; cntr++){ + val = READ_NAND(NAND_ADDR); + *buf++ = val & 0xff; + *buf++ = val >> 8; + } + + NAND_WAIT_READY(); + NAND_DISABLE_CE(); /* set pin high */ + + return 0; +} + +#endif diff --git a/uart-loader/drivers/k9k1216.c b/uart-loader/drivers/k9k1216.c new file mode 100644 index 0000000..888fb6b --- /dev/null +++ b/uart-loader/drivers/k9k1216.c @@ -0,0 +1,258 @@ +/* + * (C) Copyright 2004 Texas Instruments + * Jian Zhang + * + * Samsung K9K1216Q0C NAND chip driver for an OMAP2420 board + * + * This file is based on the following u-boot file: + * common/cmd_nand.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CFG_NAND_K9K1216 + +#define K9K1216_MFR 0xec +#define K9K1216_ID 0x46 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define PAGE_SIZE 512 +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +static int nand_read_page(u_char *buf, ulong page_addr); +static int nand_read_oob(u_char * buf, ulong page_addr); + +/* JFFS2 512-byte-page ECC layout */ +static u_char ecc_pos[] = {0,1,2,3,6,7}; +static u_char eccvalid_pos = 4; + +/* NanD_Command: Send a flash command to the flash chip */ +static int NanD_Command(unsigned char command) +{ + NAND_CTL_SETCLE(NAND_ADDR); + WRITE_NAND_COMMAND(command, NAND_ADDR); + NAND_CTL_CLRCLE(NAND_ADDR); + + if(command == NAND_CMD_RESET){ + unsigned char ret_val; + NanD_Command(NAND_CMD_STATUS); + do{ + ret_val = READ_NAND(NAND_ADDR);/* wait till ready */ + } while((ret_val & 0x40) != 0x40); + } + + NAND_WAIT_READY(); + return 0; +} + +/* NanD_Address: Set the current address for the flash chip */ +static int NanD_Address(int numbytes, unsigned long ofs) +{ + int i; + + NAND_CTL_SETALE(NAND_ADDR); + + if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) + WRITE_NAND_ADDRESS(ofs, NAND_ADDR); + + ofs = ofs >> 9; + + if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) + for (i = 0; i < 3; i++, ofs = ofs >> 8) + WRITE_NAND_ADDRESS(ofs, NAND_ADDR); + + NAND_CTL_CLRALE(NAND_ADDR); + + NAND_WAIT_READY(); + return 0; +} + +/* read chip mfr and id + * return 0 if they match board config + * return 1 if not + */ +int nand_chip() +{ + int mfr, id; + + NAND_ENABLE_CE(); + + if (NanD_Command(NAND_CMD_RESET)) { + printf("Err: RESET\n"); + NAND_DISABLE_CE(); + return 1; + } + + if (NanD_Command(NAND_CMD_READID)) { + printf("Err: READID\n"); + NAND_DISABLE_CE(); + return 1; + } + + NanD_Address(ADDR_COLUMN, 0); + + mfr = READ_NAND(NAND_ADDR); + id = READ_NAND(NAND_ADDR); + + NAND_DISABLE_CE(); + + return (mfr != K9K1216_MFR || id != K9K1216_ID); +} + +/* read a block data to buf + * return 1 if the block is bad or ECC error can't be corrected for any page + * return 0 on sucess + */ +int nand_read_block(unsigned char *buf, ulong block_addr) +{ + int i, offset = 0; + uchar oob_buf[16]; + + /* check bad block */ + /* 0th and 5th words need be 0xffff */ + if (nand_read_oob(oob_buf, block_addr) || +// oob_buf[0] != 0xff || oob_buf[1] != 0xff || +// oob_buf[10] != 0xff || oob_buf[11] != 0xff ){ + oob_buf[5] != 0xff){ + printf("Skipped bad block at 0x%x\n", block_addr); + return 1; /* skip bad block */ + } + + /* read the block page by page*/ + for (i=0; i<32; i++){ + if (nand_read_page(buf+offset, block_addr + offset)) + return 1; + offset += PAGE_SIZE; + } + + return 0; +} +static count = 0; +/* read a page with ECC */ +static int nand_read_page(u_char *buf, ulong page_addr) +{ + u_char ecc_code[6]; + u_char ecc_calc[3]; + u_char oob_buf[16]; + u_char *p; + u16 val; + int cntr; + + NAND_ENABLE_CE(); + NanD_Command(NAND_CMD_READ0); + NanD_Address(ADDR_COLUMN_PAGE, page_addr); + NAND_WAIT_READY(); + + delay(500); /* we go through NFC need a bigger delay. 200 is not enough */ + + p = buf; + for (cntr = 0; cntr < 256; cntr++){ + val = READ_NAND(NAND_ADDR); + *p++ = val & 0xff; + *p++ = val >> 8; + } + + p = oob_buf; + for (cntr = 0; cntr < 8; cntr++){ + val = READ_NAND(NAND_ADDR); + *p++ = val & 0xff; + *p++ = val >> 8; + } + count = 1; + NAND_DISABLE_CE(); /* set pin high */ + + /* Pick the ECC bytes out of the oob data */ + for (cntr = 0; cntr < 6; cntr++) + ecc_code[cntr] = oob_buf[ecc_pos[cntr]]; + + if ((oob_buf[eccvalid_pos] & 0x0f) != 0x0f) { + nand_calculate_ecc (buf, &ecc_calc[0]); + if (nand_correct_data (buf, &ecc_code[0], &ecc_calc[0]) == -1) { + printf ("ECC Failed, page 0x%08x\n", page_addr); + for (val=0; val <256; val++) + printf("%x ", buf[val]); + printf("\n"); + for (;;); + return 1; + } + } + + if ((oob_buf[eccvalid_pos] & 0xf0) != 0xf0) { + nand_calculate_ecc (buf + 256, &ecc_calc[0]); + if (nand_correct_data (buf + 256, &ecc_code[3], &ecc_calc[0]) == -1) { + printf ("ECC Failed, page 0x%08x\n", page_addr+0x100); + for (val=0; val <256; val++) + printf("%x ", buf[val+256]); + printf("\n"); + for (;;); + return 1; + } + } + + return 0; +} + +/* read from the 16 bytes of oob data that correspond to a 512 byte page. + */ +static int nand_read_oob(u_char *buf, ulong page_addr) +{ + u16 val; + int cntr; + + NAND_ENABLE_CE(); /* set pin low */ + NanD_Command(NAND_CMD_READOOB); + NanD_Address(ADDR_COLUMN_PAGE, page_addr); + NAND_WAIT_READY(); + +/* do { + *(volatile u32 *)(0x6800A07c) = NAND_CMD_STATUS; + val = *(volatile u32 *)(0x6800A084); + printf("val = %x\n", val); + } while ((val & 0x40) != 0x40); +*/ + /* the above code from OSTBoot doesn't work, we use delay */ + delay(500); /* we go through NFC need a bigger delay. 200 is not enough */ + + for (cntr = 0; cntr < 8; cntr++){ + val = READ_NAND(NAND_ADDR); + *buf++ = val & 0xff; + *buf++ = val >> 8; + } + + NAND_WAIT_READY(); + NAND_DISABLE_CE(); /* set pin high */ + + return 0; +} + +#endif diff --git a/uart-loader/drivers/ns16550.c b/uart-loader/drivers/ns16550.c new file mode 100644 index 0000000..b5a5c12 --- /dev/null +++ b/uart-loader/drivers/ns16550.c @@ -0,0 +1,69 @@ +/* + * This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * COM1 NS16550 support + * originally from linux source (arch/ppc/boot/ns16550.c) + * modified to use CFG_ISA_MEM and new defines + */ + +#include + +#ifdef CFG_PRINTF +#ifdef CFG_NS16550 + +#include + +#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ +#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */ +#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */ + +void NS16550_init (NS16550_t com_port, int baud_divisor) +{ + com_port->ier = 0x00; +#ifdef CONFIG_OMAP + com_port->mdr1 = 0x7; /* mode select reset TL16C750*/ +#endif + com_port->lcr = LCR_BKSE | LCRVAL; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCRVAL; + com_port->mcr = MCRVAL; + com_port->fcr = FCRVAL; +#if defined(CONFIG_OMAP) + com_port->mdr1 = 0; /* select uart mode */ +#endif +} + +void NS16550_reinit (NS16550_t com_port, int baud_divisor) +{ + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCRVAL; + com_port->mcr = MCRVAL; + com_port->fcr = FCRVAL; +} + +void NS16550_putc (NS16550_t com_port, char c) +{ + while ((com_port->lsr & LSR_THRE) == 0); + com_port->thr = c; +} + +char NS16550_getc (NS16550_t com_port) +{ + while ((com_port->lsr & LSR_DR) == 0); + return (com_port->rbr); +} + +int NS16550_tstc (NS16550_t com_port) +{ + return ((com_port->lsr & LSR_DR) != 0); +} + +#endif +#endif diff --git a/uart-loader/drivers/onenand.c b/uart-loader/drivers/onenand.c new file mode 100644 index 0000000..7d4e454 --- /dev/null +++ b/uart-loader/drivers/onenand.c @@ -0,0 +1,203 @@ +/* + * (C) Copyright 2005 Samsung Electronis + * Kyungmin Park + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include + +#include "onenand_regs.h" + +#define onenand_readw(a) (*(volatile unsigned short *)(a)) +#define onenand_writew(v, a) ((*(volatile unsigned short *)(a)) = (u16) (v)) + +#define SAMSUNG_MFR_ID 0xEC +#define KFM1G16Q2A_DEV_ID 0x30 +#define KFN2G16Q2A_DEV_ID 0x40 + +#ifdef CFG_ONENAND + +#define THIS_ONENAND(a) (ONENAND_ADDR + (a)) + +#define READ_INTERRUPT() \ + onenand_readw(THIS_ONENAND(ONENAND_REG_INTERRUPT)) + +#define SET_EMIFS_CS_CONFIG(v) \ + (*(volatile unsigned long *)(OMAP_EMIFS_CS_CONFIG) = (v)) + +#define onenand_block_address(block) (block) +#define onenand_sector_address(page) (page << 2) +#define onenand_buffer_address() ((1 << 3) << 8) +#define onenand_bufferram_address(block) (0) + +#if defined(CFG_SYNC_BURST_READ) && defined(CONFIG_OMAP1610) +static inline void set_sync_burst_read(void) +{ + unsigned int value; + value = 0 + | (0x1 << 15) /* Read Mode: Synchronous */ + | (0x4 << 12) /* Burst Read Latency: 4 cycles */ + | (0x4 << 9) /* Burst Length: 8 word */ + | (0x1 << 7) /* RDY signal plarity */ + | (0x1 << 6) /* INT signal plarity */ + | (0x1 << 5) /* I/O buffer enable */ + ; + onenand_writew(value, THIS_ONENAND(ONENAND_REG_SYS_CFG1)); + + value = 0 + | (4 << 16) /* Synchronous Burst Read */ + | (1 << 12) /* PGWST/WELEN */ + | (1 << 8) /* WRWST */ + | (4 << 4) /* RDWST */ + | (1 << 0) /* FCLKDIV => 48MHz */ + ; + SET_EMIFS_CS_CONFIG(value); +} + +static inline void set_async_read(void) +{ + unsigned int value; + value = 0 + | (0x0 << 15) /* Read Mode: Asynchronous */ + | (0x4 << 12) /* Burst Read Latency: 4 cycles */ + | (0x0 << 9) /* Burst Length: continuous */ + | (0x1 << 7) /* RDY signal plarity */ + | (0x1 << 6) /* INT signal plarity */ + | (0x0 << 5) /* I/O buffer disable */ + ; + onenand_writew(value, THIS_ONENAND(ONENAND_REG_SYS_CFG1)); + + value = 0 + | (0 << 16) /* Asynchronous Read */ + | (1 << 12) /* PGWST/WELEN */ + | (1 << 8) /* WRWST */ + | (3 << 4) /* RDWST */ + | (1 << 0) /* FCLKDIV => 48MHz */ + ; + SET_EMIFS_CS_CONFIG(value); +} +#else +#define set_sync_burst_read(...) do { } while (0) +#define set_async_read(...) do { } while (0) +#endif + +int +onenand_chip() +{ + unsigned short mf_id, dev_id; + mf_id = (*(volatile unsigned short *)(THIS_ONENAND(ONENAND_REG_MANUFACTURER_ID))); + dev_id = (*(volatile unsigned short *)(THIS_ONENAND(ONENAND_REG_DEVICE_ID))); + + if(mf_id == SAMSUNG_MFR_ID) { + if (dev_id == KFM1G16Q2A_DEV_ID) { + printf("Detected Samsung MuxOneNAND1G Flash \r\n"); + return 0; + } else if (dev_id == KFN2G16Q2A_DEV_ID) { + printf("Detected Samsung MuxOneNAND2G Flash \r\n"); + return 0; + } else { + printf(" ONENAND Flash unsupported\r\n"); + return 1; + } + } else { + printf("ONENAND Flash Unsupported\r\n"); + return 1; + } +} + +/* read a page with ECC */ +static inline int onenand_read_page(ulong block, ulong page, u_char *buf) +{ + unsigned long *base; + +#ifndef __HAVE_ARCH_MEMCPY32 + unsigned int offset, value; + unsigned long *p; +#endif + + onenand_writew(onenand_block_address(block), + THIS_ONENAND(ONENAND_REG_START_ADDRESS1)); + + onenand_writew(onenand_sector_address(page), + THIS_ONENAND(ONENAND_REG_START_ADDRESS8)); + + onenand_writew(onenand_buffer_address(), + THIS_ONENAND(ONENAND_REG_START_BUFFER)); + + onenand_writew(onenand_bufferram_address(block), + THIS_ONENAND(ONENAND_REG_START_ADDRESS2)); + + onenand_writew(ONENAND_INT_CLEAR, THIS_ONENAND(ONENAND_REG_INTERRUPT)); + + onenand_writew(ONENAND_CMD_READ, THIS_ONENAND(ONENAND_REG_COMMAND)); + +#ifndef __HAVE_ARCH_MEMCPY32 + p = (unsigned long *) buf; +#endif + base = (unsigned long *) (ONENAND_ADDR + ONENAND_DATARAM); + + while (!(READ_INTERRUPT() & ONENAND_INT_MASTER)) + continue; + +#ifdef __HAVE_ARCH_MEMCPY32 + /* 32 bytes boundary memory copy */ + memcpy32(buf, base, ONENAND_PAGE_SIZE); +#else + for (offset = 0; offset < (ONENAND_PAGE_SIZE >> 2); offset++) { + value = *(base + offset); + *p++ = value; + } +#endif + + return 0; +} + +#define ONENAND_START_PAGE 0 +#define ONENAND_PAGES_PER_BLOCK 64 + +/** + * onenand_read_block - Read a block data to buf + * @return 0 on sucess + */ + +int onenand_read_block(unsigned char *buf, ulong block) +{ + int page, offset = 0; + + set_sync_burst_read(); + + /* NOTE: you must read page from page 1 of block 0 */ + /* read the block page by page*/ + for (page = ONENAND_START_PAGE; + page < ONENAND_PAGES_PER_BLOCK; page++) { + + onenand_read_page(block, page, buf + offset); + + offset += ONENAND_PAGE_SIZE; + } + + set_async_read(); + + return 0; +} + +#endif /* CFG_ONENAND */ diff --git a/uart-loader/drivers/onenand_regs.h b/uart-loader/drivers/onenand_regs.h new file mode 100644 index 0000000..d8acc8c --- /dev/null +++ b/uart-loader/drivers/onenand_regs.h @@ -0,0 +1,167 @@ +/* + * linux/include/linux/mtd/onenand_regs.h + * + * OneNAND Register header file + * + * Copyright (C) 2005 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ONENAND_REG_H +#define __ONENAND_REG_H + +/* Memory Address Map Translation (Word order) */ +#define ONENAND_MEMORY_MAP(x) ((x) << 1) + +/* + * External BufferRAM area + */ +#define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000) +#define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200) +#define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010) + +/* + * OneNAND Registers + */ +#define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000) +#define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001) +#define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002) +#define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003) +#define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004) +#define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005) +#define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006) + +#define ONENAND_REG_START_ADDRESS1 ONENAND_MEMORY_MAP(0xF100) +#define ONENAND_REG_START_ADDRESS2 ONENAND_MEMORY_MAP(0xF101) +#define ONENAND_REG_START_ADDRESS3 ONENAND_MEMORY_MAP(0xF102) +#define ONENAND_REG_START_ADDRESS4 ONENAND_MEMORY_MAP(0xF103) +#define ONENAND_REG_START_ADDRESS5 ONENAND_MEMORY_MAP(0xF104) +#define ONENAND_REG_START_ADDRESS6 ONENAND_MEMORY_MAP(0xF105) +#define ONENAND_REG_START_ADDRESS7 ONENAND_MEMORY_MAP(0xF106) +#define ONENAND_REG_START_ADDRESS8 ONENAND_MEMORY_MAP(0xF107) + +#define ONENAND_REG_START_BUFFER ONENAND_MEMORY_MAP(0xF200) +#define ONENAND_REG_COMMAND ONENAND_MEMORY_MAP(0xF220) +#define ONENAND_REG_SYS_CFG1 ONENAND_MEMORY_MAP(0xF221) +#define ONENAND_REG_SYS_CFG2 ONENAND_MEMORY_MAP(0xF222) +#define ONENAND_REG_CTRL_STATUS ONENAND_MEMORY_MAP(0xF240) +#define ONENAND_REG_INTERRUPT ONENAND_MEMORY_MAP(0xF241) +#define ONENAND_REG_START_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24C) +#define ONENAND_REG_END_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24D) +#define ONENAND_REG_WP_STATUS ONENAND_MEMORY_MAP(0xF24E) + +#define ONENAND_REG_ECC_STATUS ONENAND_MEMORY_MAP(0xFF00) +#define ONENAND_REG_ECC_M0 ONENAND_MEMORY_MAP(0xFF01) +#define ONENAND_REG_ECC_S0 ONENAND_MEMORY_MAP(0xFF02) +#define ONENAND_REG_ECC_M1 ONENAND_MEMORY_MAP(0xFF03) +#define ONENAND_REG_ECC_S1 ONENAND_MEMORY_MAP(0xFF04) +#define ONENAND_REG_ECC_M2 ONENAND_MEMORY_MAP(0xFF05) +#define ONENAND_REG_ECC_S2 ONENAND_MEMORY_MAP(0xFF06) +#define ONENAND_REG_ECC_M3 ONENAND_MEMORY_MAP(0xFF07) +#define ONENAND_REG_ECC_S3 ONENAND_MEMORY_MAP(0xFF08) + +/* + * Device ID Register F001h (R) + */ +#define ONENAND_DEVICE_DENSITY_SHIFT (4) +#define ONENAND_DEVICE_IS_DDP (1 << 3) +#define ONENAND_DEVICE_IS_DEMUX (1 << 2) +#define ONENAND_DEVICE_VCC_MASK (0x3) + +#define ONENAND_DEVICE_DENSITY_512Mb (0x002) + +/* + * Version ID Register F002h (R) + */ +#define ONENAND_VERSION_PROCESS_SHIFT (8) + +/* + * Start Address 1 F100h (R/W) + */ +#define ONENAND_DDP_SHIFT (15) + +/* + * Start Address 8 F107h (R/W) + */ +#define ONENAND_FPA_MASK (0x3f) +#define ONENAND_FPA_SHIFT (2) +#define ONENAND_FSA_MASK (0x03) + +/* + * Start Buffer Register F200h (R/W) + */ +#define ONENAND_BSA_MASK (0x03) +#define ONENAND_BSA_SHIFT (8) +#define ONENAND_BSA_BOOTRAM (0 << 2) +#define ONENAND_BSA_DATARAM0 (2 << 2) +#define ONENAND_BSA_DATARAM1 (3 << 2) +#define ONENAND_BSC_MASK (0x03) + +/* + * Command Register F220h (R/W) + */ +#define ONENAND_CMD_READ (0x00) +#define ONENAND_CMD_READOOB (0x13) +#define ONENAND_CMD_PROG (0x80) +#define ONENAND_CMD_PROGOOB (0x1A) +#define ONENAND_CMD_UNLOCK (0x23) +#define ONENAND_CMD_LOCK (0x2A) +#define ONENAND_CMD_LOCK_TIGHT (0x2C) +#define ONENAND_CMD_ERASE (0x94) +#define ONENAND_CMD_RESET (0xF0) +#define ONENAND_CMD_READID (0x90) + +/* NOTE: Those are not *REAL* commands */ +#define ONENAND_CMD_BUFFERRAM (0x1978) + +/* + * System Configuration 1 Register F221h (R, R/W) + */ +#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15) +#define ONENAND_SYS_CFG1_BRL (12) +#define ONENAND_SYS_CFG1_BL (9) +#define ONENAND_SYS_CFG1_NO_ECC (1 << 8) +#define ONENAND_SYS_CFG1_RDY (1 << 7) +#define ONENAND_SYS_CFG1_INT (1 << 6) +#define ONENAND_SYS_CFG1_IOBE (1 << 5) +#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4) + +/* + * Controller Status Register F240h (R) + */ +#define ONENAND_CTRL_ONGO (1 << 15) +#define ONENAND_CTRL_LOCK (1 << 14) +#define ONENAND_CTRL_LOAD (1 << 13) +#define ONENAND_CTRL_PROGRAM (1 << 12) +#define ONENAND_CTRL_ERASE (1 << 11) +#define ONENAND_CTRL_ERROR (1 << 10) +#define ONENAND_CTRL_RSTB (1 << 7) + +/* + * Interrupt Status Register F241h (R) + */ +#define ONENAND_INT_MASTER (1 << 15) +#define ONENAND_INT_READ (1 << 7) +#define ONENAND_INT_WRITE (1 << 6) +#define ONENAND_INT_ERASE (1 << 5) +#define ONENAND_INT_RESET (1 << 4) +#define ONENAND_INT_CLEAR (0 << 0) + +/* + * NAND Flash Write Protection Status Register F24Eh (R) + */ +#define ONENAND_WP_US (1 << 2) +#define ONENAND_WP_LS (1 << 1) +#define ONENAND_WP_LTS (1 << 0) + +/* + * ECC Status Reigser FF00h (R) + */ +#define ONENAND_ECC_1BIT (1 << 0) +#define ONENAND_ECC_2BIT (1 << 1) +#define ONENAND_ECC_2BIT_ALL (0xAAAA) + +#endif /* __ONENAND_REG_H */ diff --git a/uart-loader/drivers/serial.c b/uart-loader/drivers/serial.c new file mode 100644 index 0000000..b9ecf2a --- /dev/null +++ b/uart-loader/drivers/serial.c @@ -0,0 +1,119 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CFG_PRINTF +#ifdef CFG_NS16550_SERIAL + +#include +#ifdef CFG_NS87308 +#include +#endif + +#if CONFIG_CONS_INDEX == 1 +static NS16550_t console = (NS16550_t) CFG_NS16550_COM1; +#elif CONFIG_CONS_INDEX == 2 +static NS16550_t console = (NS16550_t) CFG_NS16550_COM2; +#elif CONFIG_CONS_INDEX == 3 +static NS16550_t console = (NS16550_t) CFG_NS16550_COM3; +#elif CONFIG_CONS_INDEX == 4 +static NS16550_t console = (NS16550_t) CFG_NS16550_COM4; +#else +#error no valid console defined +#endif + +static int calc_divisor (void) +{ +// DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_OMAP1510 + /* If can't cleanly clock 115200 set div to 1 */ + if ((CFG_NS16550_CLK == 12000000) && (CONFIG_BAUDRATE == 115200)) { + console->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */ + return (1); /* return 1 for base divisor */ + } + console->osc_12m_sel = 0; /* clear if previsouly set */ +#endif +#if defined(CONFIG_OMAP1610) || defined(CONFIG_OMAP1710) + /* If can't cleanly clock 115200 set div to 1 */ + if ((CFG_NS16550_CLK == 48000000) && (CONFIG_BAUDRATE == 115200)) { + return (26); /* return 26 for base divisor */ + } +#endif + return (CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE); +} + +int serial_init (void) +{ + int clock_divisor = calc_divisor(); + +#ifdef CFG_NS87308 + initialise_ns87308(); +#endif + + NS16550_init(console, clock_divisor); + + return (0); +} + +void +serial_putc(const char c) +{ + if (c == '\n') + NS16550_putc(console, '\r'); + + NS16550_putc(console, c); +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + + +int +serial_getc(void) +{ + return NS16550_getc(console); +} + +int +serial_tstc(void) +{ + return NS16550_tstc(console); +} + +void +serial_setbrg (void) +{ + int clock_divisor; + + clock_divisor = calc_divisor(); + NS16550_reinit(console, clock_divisor); +} + +#endif +#endif diff --git a/uart-loader/fs/Makefile b/uart-loader/fs/Makefile new file mode 100644 index 0000000..f419b99 --- /dev/null +++ b/uart-loader/fs/Makefile @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000, 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# + +SUBDIRS := fat + +.depend all: + @for dir in $(SUBDIRS) ; do \ + $(MAKE) -C $$dir $@ ; done diff --git a/uart-loader/fs/fat/Makefile b/uart-loader/fs/fat/Makefile new file mode 100644 index 0000000..e462757 --- /dev/null +++ b/uart-loader/fs/fat/Makefile @@ -0,0 +1,46 @@ +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TOPDIR=../../ + +include $(TOPDIR)/config.mk + +LIB = libfat.a + +AOBJS = +COBJS = fat.o file.o + +OBJS = $(AOBJS) $(COBJS) + +all: $(LIB) $(AOBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/uart-loader/fs/fat/fat.c b/uart-loader/fs/fat/fat.c new file mode 100644 index 0000000..bad4f6c --- /dev/null +++ b/uart-loader/fs/fat/fat.c @@ -0,0 +1,927 @@ +/* + * fat.c + * + * R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg + * + * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6 + * 2003-03-10 - kharris@nexus-tech.net - ported to uboot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#ifdef CFG_CMD_FAT + +/* + * Convert a string to lowercase. + */ +static void +downcase(char *str) +{ + while (*str != '\0') { + TOLOWER(*str); + str++; + } +} + +static block_dev_desc_t *cur_dev = NULL; +static unsigned long part_offset = 0; +static int cur_part = 1; + +#define DOS_PART_TBL_OFFSET 0x1be +#define DOS_PART_MAGIC_OFFSET 0x1fe +#define DOS_FS_TYPE_OFFSET 0x52 + +int strncmp(const char * cs,const char * ct,size_t count) +{ + register signed char __res = 0; + + while (count) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + count--; + } + + return __res; +} + +char * strcpy(char * dest,const char *src) +{ + char *tmp = dest; + + while ((*dest++ = *src++) != '\0') + /* nothing */; + return tmp; +} + +int strcmp(const char * cs,const char * ct) +{ + register signed char __res; + + while (1) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + } + + return __res; +} +void * memcpy(void * dest,const void *src,size_t count) +{ + char *tmp = (char *) dest, *s = (char *) src; + + while (count--) + *tmp++ = *s++; + + return dest; +} + + +int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr) +{ + startblock += part_offset; + if (cur_dev == NULL) + return -1; + if (cur_dev->block_read) { + return cur_dev->block_read (cur_dev->dev, startblock, getsize, (unsigned long *)bufptr); + } + return -1; +} + + +int +fat_register_device(block_dev_desc_t *dev_desc, int part_no) +{ + unsigned char buffer[SECTOR_SIZE]; + + if (!dev_desc->block_read) + return -1; + cur_dev=dev_desc; + /* check if we have a MBR (on floppies we have only a PBR) */ + if (dev_desc->block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) { + printf ("** Can't read from device %d **\n", dev_desc->dev); + return -1; + } + if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || + buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) { + /* no signature found */ + return -1; + } + if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { + /* ok, we assume we are on a PBR only */ + cur_part = 1; + part_offset=0; + } + else { +#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || (CONFIG_COMMANDS & CFG_CMD_MMC) || defined(CONFIG_SYSTEMACE) + disk_partition_t info; + if(!get_partition_info(dev_desc, part_no, &info)) { + part_offset = info.start; + cur_part = part_no; + } + else { + printf ("** Partition %d not valid on device %d **\n",part_no,dev_desc->dev); + return -1; + } +#else + /* FIXME we need to determine the start block of the + * partition where the DOS FS resides. This can be done + * by using the get_partition_info routine. For this + * purpose the libpart must be included. + */ + part_offset=63; + //part_offset=0; + cur_part = 1; +#endif + } + return 0; +} + + +/* + * Get the first occurence of a directory delimiter ('/' or '\') in a string. + * Return index into string if found, -1 otherwise. + */ +static int +dirdelim(char *str) +{ + char *start = str; + + while (*str != '\0') { + if (ISDIRDELIM(*str)) return str - start; + str++; + } + return -1; +} + + +/* + * Match volume_info fs_type strings. + * Return 0 on match, -1 otherwise. + */ +static int +compare_sign(char *str1, char *str2) +{ + char *end = str1+SIGNLEN; + + while (str1 != end) { + if (*str1 != *str2) { + return -1; + } + str1++; + str2++; + } + + return 0; +} + + +/* + * Extract zero terminated short name from a directory entry. + */ +static void get_name (dir_entry *dirent, char *s_name) +{ + char *ptr; + + memcpy (s_name, dirent->name, 8); + s_name[8] = '\0'; + ptr = s_name; + while (*ptr && *ptr != ' ') + ptr++; + if (dirent->ext[0] && dirent->ext[0] != ' ') { + *ptr = '.'; + ptr++; + memcpy (ptr, dirent->ext, 3); + ptr[3] = '\0'; + while (*ptr && *ptr != ' ') + ptr++; + } + *ptr = '\0'; + if (*s_name == DELETED_FLAG) + *s_name = '\0'; + else if (*s_name == aRING) + *s_name = 'å'; + downcase (s_name); +} + +/* + * Get the entry at index 'entry' in a FAT (12/16/32) table. + * On failure 0x00 is returned. + */ +static __u32 +get_fatent(fsdata *mydata, __u32 entry) +{ + __u32 bufnum; + __u32 offset; + __u32 ret = 0x00; + + switch (mydata->fatsize) { + case 32: + bufnum = entry / FAT32BUFSIZE; + offset = entry - bufnum * FAT32BUFSIZE; + break; + case 16: + bufnum = entry / FAT16BUFSIZE; + offset = entry - bufnum * FAT16BUFSIZE; + break; + case 12: + bufnum = entry / FAT12BUFSIZE; + offset = entry - bufnum * FAT12BUFSIZE; + break; + + default: + /* Unsupported FAT size */ + return ret; + } + /* Read a new block of FAT entries into the cache. */ + if (bufnum != mydata->fatbufnum) { + int getsize = FATBUFSIZE/FS_BLOCK_SIZE; + __u8 *bufptr = mydata->fatbuf; + __u32 fatlength = mydata->fatlength; + __u32 startblock = bufnum * FATBUFBLOCKS; + unsigned long i; + + fatlength *= SECTOR_SIZE; /* We want it in bytes now */ + startblock += mydata->fat_sect; /* Offset from start of disk */ + + if (getsize > fatlength) getsize = fatlength; + if (disk_read(startblock, getsize, bufptr) < 0) { + FAT_DPRINT("Error reading FAT blocks\n"); + return ret; + } + mydata->fatbufnum = bufnum; + } + + /* Get the actual entry from the table */ + switch (mydata->fatsize) { + case 32: + ret = FAT2CPU32(((__u32*)mydata->fatbuf)[offset]); + break; + case 16: + ret = FAT2CPU16(((__u16*)mydata->fatbuf)[offset]); + break; + case 12: { + __u32 off16 = (offset*3)/4; + __u16 val1, val2; + + switch (offset & 0x3) { + case 0: + ret = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); + ret &= 0xfff; + break; + case 1: + val1 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); + val1 &= 0xf000; + val2 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16+1]); + val2 &= 0x00ff; + ret = (val2 << 4) | (val1 >> 12); + break; + case 2: + val1 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); + val1 &= 0xff00; + val2 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16+1]); + val2 &= 0x000f; + ret = (val2 << 8) | (val1 >> 8); + break; + case 3: + ret = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]);; + ret = (ret & 0xfff0) >> 4; + break; + default: + break; + } + } + break; + } + FAT_DPRINT("ret: %d, offset: %d\n", ret, offset); + + return ret; +} + + +/* + * Read at most 'size' bytes from the specified cluster into 'buffer'. + * Return 0 on success, -1 otherwise. + */ +static int +get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) +{ + int idx = 0; + __u32 startsect; + + if (clustnum > 0) { + startsect = mydata->data_begin + clustnum*mydata->clust_size; + } else { + startsect = mydata->rootdir_sect; + } + + if (disk_read(startsect, size/FS_BLOCK_SIZE , buffer) < 0) { + FAT_DPRINT("Error reading data\n"); + return -1; + } + if(size % FS_BLOCK_SIZE) { + __u8 tmpbuf[FS_BLOCK_SIZE]; + idx= size/FS_BLOCK_SIZE; + if (disk_read(startsect + idx, 1, tmpbuf) < 0) { + FAT_DPRINT("Error reading data\n"); + return -1; + } + buffer += idx*FS_BLOCK_SIZE; + + memcpy(buffer, tmpbuf, size % FS_BLOCK_SIZE); + return 0; + } + + return 0; +} + + +/* + * Read at most 'maxsize' bytes from the file associated with 'dentptr' + * into 'buffer'. + * Return the number of bytes read or -1 on fatal errors. + */ +static long +get_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, + unsigned long maxsize) +{ + unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0; + unsigned int bytesperclust = mydata->clust_size * SECTOR_SIZE; + __u32 curclust = START(dentptr); + __u32 endclust, newclust; + unsigned long actsize; + + FAT_DPRINT("Filesize: %ld bytes\n", filesize); + + if (maxsize > 0 && filesize > maxsize) filesize = maxsize; + + FAT_DPRINT("Reading: %ld bytes\n", filesize); + + actsize=bytesperclust; + endclust=curclust; + do { + /* search for consecutive clusters */ + while(actsize < filesize) { + newclust = get_fatent(mydata, endclust); + if((newclust -1)!=endclust) + goto getit; + if (newclust <= 0x0001 || newclust >= 0xfff0) { + FAT_DPRINT("curclust: 0x%x\n", newclust); + FAT_DPRINT("Invalid FAT entry\n"); + return gotsize; + } + endclust=newclust; + actsize+= bytesperclust; + } + /* actsize >= file size */ + actsize -= bytesperclust; + /* get remaining clusters */ + if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) { + FAT_ERROR("Error reading cluster\n"); + return -1; + } + /* get remaining bytes */ + gotsize += (int)actsize; + filesize -= actsize; + buffer += actsize; + actsize= filesize; + if (get_cluster(mydata, endclust, buffer, (int)actsize) != 0) { + FAT_ERROR("Error reading cluster\n"); + return -1; + } + gotsize+=actsize; + return gotsize; +getit: + if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) { + FAT_ERROR("Error reading cluster\n"); + return -1; + } + gotsize += (int)actsize; + filesize -= actsize; + buffer += actsize; + curclust = get_fatent(mydata, endclust); + if (curclust <= 0x0001 || curclust >= 0xfff0) { + FAT_DPRINT("curclust: 0x%x\n", curclust); + FAT_ERROR("Invalid FAT entry\n"); + return gotsize; + } + actsize=bytesperclust; + endclust=curclust; + } while (1); +} + + +#ifdef CONFIG_SUPPORT_VFAT +/* + * Extract the file name information from 'slotptr' into 'l_name', + * starting at l_name[*idx]. + * Return 1 if terminator (zero byte) is found, 0 otherwise. + */ +static int +slot2str(dir_slot *slotptr, char *l_name, int *idx) +{ + int j; + + for (j = 0; j <= 8; j += 2) { + l_name[*idx] = slotptr->name0_4[j]; + if (l_name[*idx] == 0x00) return 1; + (*idx)++; + } + for (j = 0; j <= 10; j += 2) { + l_name[*idx] = slotptr->name5_10[j]; + if (l_name[*idx] == 0x00) return 1; + (*idx)++; + } + for (j = 0; j <= 2; j += 2) { + l_name[*idx] = slotptr->name11_12[j]; + if (l_name[*idx] == 0x00) return 1; + (*idx)++; + } + + return 0; +} + +/* Calculate short name checksum */ +static __u8 +mkcksum(const char *str) +{ + int i; + __u8 ret = 0; + + for (i = 0; i < 11; i++) { + ret = (((ret&1)<<7)|((ret&0xfe)>>1)) + str[i]; + } + + return ret; +} +#endif + + +/* + * Get the directory entry associated with 'filename' from the directory + * starting at 'startsect' + */ + + +static dir_entry *get_dentfromdir (fsdata * mydata, int startsect, + char *filename, dir_entry * retdent, + int dols) +{ + +} + +#if 0 +__u8 get_dentfromdir_block[MAX_CLUSTSIZE]; +static dir_entry *get_dentfromdir (fsdata * mydata, int startsect, + char *filename, dir_entry * retdent, + int dols) +{ + __u16 prevcksum = 0xffff; + __u32 curclust = START (retdent); + int files = 0, dirs = 0; + + while (1) { + dir_entry *dentptr; + int i; + + if (get_cluster (mydata, curclust, get_dentfromdir_block, + mydata->clust_size * SECTOR_SIZE) != 0) { + FAT_DPRINT ("Error: reading directory block\n"); + return NULL; + } + dentptr = (dir_entry *) get_dentfromdir_block; + for (i = 0; i < DIRENTSPERCLUST; i++) { + char s_name[14], l_name[256]; + + l_name[0] = '\0'; + if (dentptr->name[0] == DELETED_FLAG) { + dentptr++; + continue; + } + if ((dentptr->attr & ATTR_VOLUME)) { + /* Volume label or VFAT entry */ + dentptr++; + continue; + } + if (dentptr->name[0] == 0) { + if (dols) { + printf ("\n%d file(s), %d dir(s)\n\n", files, dirs); + } + FAT_DPRINT ("Dentname == NULL - %d\n", i); + return NULL; + } +#ifdef CONFIG_SUPPORT_VFAT + if (dols && mkcksum (dentptr->name) == prevcksum) { + dentptr++; + continue; + } +#endif + get_name (dentptr, s_name); + if (dols) { + int isdir = (dentptr->attr & ATTR_DIR); + char dirc; + int doit = 0; + + if (isdir) { + dirs++; + dirc = '/'; + doit = 1; + } else { + dirc = ' '; + if (s_name[0] != 0) { + files++; + doit = 1; + } + } + if (doit) { + if (dirc == ' ') { + printf (" %8ld %s%c\n", + (long) FAT2CPU32 (dentptr->size), s_name, + dirc); + } else { + printf (" %s%c\n", s_name, dirc); + } + } + dentptr++; + continue; + } + if (strcmp (filename, s_name) && strcmp (filename, l_name)) { + FAT_DPRINT ("Mismatch: |%s|%s|\n", s_name, l_name); + dentptr++; + continue; + } + memcpy (retdent, dentptr, sizeof (dir_entry)); + + FAT_DPRINT ("DentName: %s", s_name); + FAT_DPRINT (", start: 0x%x", START (dentptr)); + FAT_DPRINT (", size: 0x%x %s\n", + FAT2CPU32 (dentptr->size), + (dentptr->attr & ATTR_DIR) ? "(DIR)" : ""); + + return retdent; + } + curclust = get_fatent (mydata, curclust); + if (curclust <= 0x0001 || curclust >= 0xfff0) { + FAT_DPRINT ("curclust: 0x%x\n", curclust); + FAT_ERROR ("Invalid FAT entry\n"); + return NULL; + } + } + + return NULL; +} +#endif + + +/* + * Read boot sector and volume info from a FAT filesystem + */ +static int +read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) +{ + __u8 block[FS_BLOCK_SIZE]; + volume_info *vistart; + + FAT_DPRINT("Reading boot sector\n"); + + if (disk_read(0, 1, block) < 0) { + FAT_DPRINT("Error: reading block\n"); + return -1; + } + + memcpy(bs, block, sizeof(boot_sector)); + bs->reserved = FAT2CPU16(bs->reserved); + bs->fat_length = FAT2CPU16(bs->fat_length); + bs->secs_track = FAT2CPU16(bs->secs_track); + bs->heads = FAT2CPU16(bs->heads); +#if 0 /* UNUSED */ + bs->hidden = FAT2CPU32(bs->hidden); +#endif + bs->total_sect = FAT2CPU32(bs->total_sect); + + /* FAT32 entries */ + if (bs->fat_length == 0) { + /* Assume FAT32 */ + bs->fat32_length = FAT2CPU32(bs->fat32_length); + bs->flags = FAT2CPU16(bs->flags); + bs->root_cluster = FAT2CPU32(bs->root_cluster); + bs->info_sector = FAT2CPU16(bs->info_sector); + bs->backup_boot = FAT2CPU16(bs->backup_boot); + vistart = (volume_info*) (block + sizeof(boot_sector)); + *fatsize = 32; + } else { + vistart = (volume_info*) &(bs->fat32_length); + *fatsize = 0; + } + memcpy(volinfo, vistart, sizeof(volume_info)); + + /* Terminate fs_type string. Writing past the end of vistart + is ok - it's just the buffer. */ + vistart->fs_type[8] = '\0'; + + if (*fatsize == 32) { + if (compare_sign(FAT32_SIGN, vistart->fs_type) == 0) { + return 0; + } + } else { + if (compare_sign(FAT12_SIGN, vistart->fs_type) == 0) { + *fatsize = 12; + return 0; + } + if (compare_sign(FAT16_SIGN, vistart->fs_type) == 0) { + *fatsize = 16; + return 0; + } + } + + FAT_DPRINT("Error: broken fs_type sign\n"); + return -1; +} + +#if 0 +__u8 do_fat_read_block[MAX_CLUSTSIZE]; /* Block buffer */ +#endif + +__u8 *fnamecopy = 0x80500000; +__u8 *do_fat_read_block = 0x80500880; + +boot_sector bs; +volume_info volinfo; +fsdata datablock; + +long +do_fat_read(const char *filename, void *buffer, unsigned long maxsize, + int dols) +{ +#if CONFIG_NIOS /* NIOS CPU cannot access big automatic arrays */ + static +#endif + fsdata *mydata = &datablock; + dir_entry *dentptr; + __u16 prevcksum = 0xffff; + char *subname = ""; + int rootdir_size, cursect; + int idx, isdir = 0; + int files = 0, dirs = 0; + long ret = 0; + int firsttime; + + if (read_bootsectandvi (&bs, &volinfo, &mydata->fatsize)) { + printf ("Error: reading boot sector\n"); + return -1; + } + if (mydata->fatsize == 32) { + mydata->fatlength = bs.fat32_length; + } else { + mydata->fatlength = bs.fat_length; + } + mydata->fat_sect = bs.reserved; + cursect = mydata->rootdir_sect + = mydata->fat_sect + mydata->fatlength * bs.fats; + mydata->clust_size = bs.cluster_size; + if (mydata->fatsize == 32) { + rootdir_size = mydata->clust_size; + mydata->data_begin = mydata->rootdir_sect /* + rootdir_size */ + - (mydata->clust_size * 2); + } else { + rootdir_size = ((bs.dir_entries[1] * (int) 256 + bs.dir_entries[0]) + * sizeof (dir_entry)) / SECTOR_SIZE; + mydata->data_begin = mydata->rootdir_sect + rootdir_size + - (mydata->clust_size * 2); + } + mydata->fatbufnum = -1; + + FAT_DPRINT ("FAT%d, fatlength: %d\n", mydata->fatsize, + mydata->fatlength); + FAT_DPRINT ("Rootdir begins at sector: %d, offset: %x, size: %d\n" + "Data begins at: %d\n", + mydata->rootdir_sect, mydata->rootdir_sect * SECTOR_SIZE, + rootdir_size, mydata->data_begin); + FAT_DPRINT ("Cluster size: %d\n", mydata->clust_size); + + /* "cwd" is always the root... */ + while (ISDIRDELIM (*filename)) + filename++; + /* Make a copy of the filename and convert it to lowercase */ + strcpy (fnamecopy, filename); + downcase (fnamecopy); + if (*fnamecopy == '\0') { + if (!dols){ + printf("\n not there\n"); + return -1; + } + dols = LS_ROOT; + } else if ((idx = dirdelim (fnamecopy)) >= 0) { + isdir = 1; + fnamecopy[idx] = '\0'; + subname = fnamecopy + idx + 1; + /* Handle multiple delimiters */ + while (ISDIRDELIM (*subname)) + subname++; + } else if (dols) { + isdir = 1; + } + + while (1) { + int i; + + if (disk_read (cursect, mydata->clust_size, do_fat_read_block) < 0) { + printf ("Error: reading rootdir block\n"); + return -1; + } + dentptr = (dir_entry *) do_fat_read_block; + for (i = 0; i < DIRENTSPERBLOCK; i++) { + char s_name[14], l_name[256]; + + l_name[0] = '\0'; + if ((dentptr->attr & ATTR_VOLUME)) { + /* Volume label or VFAT entry */ + dentptr++; + continue; + } else if (dentptr->name[0] == 0) { + FAT_DPRINT ("RootDentname == NULL - %d\n", i); + if (dols == LS_ROOT) { + printf ("\n%d file(s), %d dir(s)\n\n", files, dirs); + return 0; + } + return -1; + } +#ifdef CONFIG_SUPPORT_VFAT + else if (dols == LS_ROOT + && mkcksum (dentptr->name) == prevcksum) { + dentptr++; + continue; + } +#endif + get_name (dentptr, s_name); + if (dols == LS_ROOT) { + int isdir = (dentptr->attr & ATTR_DIR); + char dirc; + int doit = 0; + + if (isdir) { + dirc = '/'; + if (s_name[0] != 0) { + dirs++; + doit = 1; + } + } else { + dirc = ' '; + if (s_name[0] != 0) { + files++; + doit = 1; + } + } + if (doit) { + if (dirc == ' ') { + printf (" %8ld %s%c\n", + (long) FAT2CPU32 (dentptr->size), s_name, + dirc); + } else { + printf (" %s%c\n", s_name, dirc); + } + } + dentptr++; + continue; + } + if (strcmp (fnamecopy, s_name) && strcmp (fnamecopy, l_name)) { + FAT_DPRINT ("RootMismatch: |%s|%s|\n", s_name, l_name); + dentptr++; + continue; + } + if (isdir && !(dentptr->attr & ATTR_DIR)) + return -1; + + FAT_DPRINT ("RootName: %s", s_name); + FAT_DPRINT (", start: 0x%x", START (dentptr)); + FAT_DPRINT (", size: 0x%x %s\n", + FAT2CPU32 (dentptr->size), isdir ? "(DIR)" : ""); + + goto rootdir_done; /* We got a match */ + } + cursect++; + } + rootdir_done: + + firsttime = 1; + while (isdir) { + int startsect = mydata->data_begin + + START (dentptr) * mydata->clust_size; + dir_entry dent; + char *nextname = NULL; + + dent = *dentptr; + dentptr = &dent; + idx = dirdelim (subname); + if (idx >= 0) { + subname[idx] = '\0'; + nextname = subname + idx + 1; + /* Handle multiple delimiters */ + while (ISDIRDELIM (*nextname)) + nextname++; + if (dols && *nextname == '\0') + firsttime = 0; + } else { + if (dols && firsttime) { + firsttime = 0; + } else { + isdir = 0; + } + } + + if (get_dentfromdir (mydata, startsect, subname, dentptr, + isdir ? 0 : dols) == NULL) { + if (dols && !isdir) + return 0; + return -1; + } + + if (idx >= 0) { + if (!(dentptr->attr & ATTR_DIR)) + return -1; + subname = nextname; + } + } + ret = get_contents (mydata, dentptr, buffer, maxsize); + FAT_DPRINT ("Size: %d, got: %ld\n", FAT2CPU32 (dentptr->size), ret); + + return ret; +} + + +int +file_fat_detectfs(void) +{ + boot_sector bs; + volume_info volinfo; + int fatsize; + char vol_label[12]; + + if(cur_dev==NULL) { + printf("No current device\n"); + return 1; + } +#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || (CONFIG_MMC) + printf("Interface: "); + switch(cur_dev->if_type) { + case IF_TYPE_IDE : printf("IDE"); break; + case IF_TYPE_SCSI : printf("SCSI"); break; + case IF_TYPE_ATAPI : printf("ATAPI"); break; + case IF_TYPE_USB : printf("USB"); break; + case IF_TYPE_DOC : printf("DOC"); break; + case IF_TYPE_MMC : printf("MMC"); break; + default : printf("Unknown"); + } + printf("\n Device %d: ",cur_dev->dev); + dev_print(cur_dev); +#endif + if(read_bootsectandvi(&bs, &volinfo, &fatsize)) { + printf("\nNo valid FAT fs found\n"); + return 1; + } + memcpy (vol_label, volinfo.volume_label, 11); + vol_label[11] = '\0'; + volinfo.fs_type[5]='\0'; + printf("Partition %d: Filesystem: %s \"%s\"\n",cur_part,volinfo.fs_type,vol_label); + return 0; +} + + +int +file_fat_ls(const char *dir) +{ + return do_fat_read(dir, NULL, 0, LS_YES); +} + + +long +file_fat_read(const char *filename, void *buffer, unsigned long maxsize) +{ + long ret; + ret = do_fat_read(filename, buffer, maxsize, LS_NO); + return ret; +} + +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FAT) */ diff --git a/uart-loader/fs/fat/file.c b/uart-loader/fs/fat/file.c new file mode 100644 index 0000000..2a2354e --- /dev/null +++ b/uart-loader/fs/fat/file.c @@ -0,0 +1,208 @@ +/* + * file.c + * + * Mini "VFS" by Marcus Sundberg + * + * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6 + * 2003-03-10 - kharris@nexus-tech.net - ported to uboot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_FAT) + +/* Supported filesystems */ +static const struct filesystem filesystems[] = { + { file_fat_detectfs, file_fat_ls, file_fat_read, "FAT" }, +}; +#define NUM_FILESYS (sizeof(filesystems)/sizeof(struct filesystem)) + +/* The filesystem which was last detected */ +static int current_filesystem = FSTYPE_NONE; + +/* The current working directory */ +#define CWD_LEN 511 +char file_cwd[CWD_LEN+1] = "/"; + +const char * +file_getfsname(int idx) +{ + if (idx < 0 || idx >= NUM_FILESYS) return NULL; + + return filesystems[idx].name; +} + + +static void +pathcpy(char *dest, const char *src) +{ + char *origdest = dest; + + do { + if (dest-file_cwd >= CWD_LEN) { + *dest = '\0'; + return; + } + *(dest) = *(src); + if (*src == '\0') { + if (dest-- != origdest && ISDIRDELIM(*dest)) { + *dest = '\0'; + } + return; + } + ++dest; + if (ISDIRDELIM(*src)) { + while (ISDIRDELIM(*src)) src++; + } else { + src++; + } + } while (1); +} + + +int +file_cd(const char *path) +{ + if (ISDIRDELIM(*path)) { + while (ISDIRDELIM(*path)) path++; + strncpy(file_cwd+1, path, CWD_LEN-1); + } else { + const char *origpath = path; + char *tmpstr = file_cwd; + int back = 0; + + while (*tmpstr != '\0') tmpstr++; + do { + tmpstr--; + } while (ISDIRDELIM(*tmpstr)); + + while (*path == '.') { + path++; + while (*path == '.') { + path++; + back++; + } + if (*path != '\0' && !ISDIRDELIM(*path)) { + path = origpath; + back = 0; + break; + } + while (ISDIRDELIM(*path)) path++; + origpath = path; + } + + while (back--) { + /* Strip off path component */ + while (!ISDIRDELIM(*tmpstr)) { + tmpstr--; + } + if (tmpstr == file_cwd) { + /* Incremented again right after the loop. */ + tmpstr--; + break; + } + /* Skip delimiters */ + while (ISDIRDELIM(*tmpstr)) tmpstr--; + } + tmpstr++; + if (*path == '\0') { + if (tmpstr == file_cwd) { + *tmpstr = '/'; + tmpstr++; + } + *tmpstr = '\0'; + return 0; + } + *tmpstr = '/'; + pathcpy(tmpstr+1, path); + } + + return 0; +} + + +int +file_detectfs(void) +{ + int i; + + current_filesystem = FSTYPE_NONE; + + for (i = 0; i < NUM_FILESYS; i++) { + if (filesystems[i].detect() == 0) { + strcpy(file_cwd, "/"); + current_filesystem = i; + break; + } + } + + return current_filesystem; +} + + +int +file_ls(const char *dir) +{ + char fullpath[1024]; + const char *arg; + + if (current_filesystem == FSTYPE_NONE) { + printf("Can't list files without a filesystem!\n"); + return -1; + } + + if (ISDIRDELIM(*dir)) { + arg = dir; + } else { + sprintf(fullpath, "%s/%s", file_cwd, dir); + arg = fullpath; + } + return filesystems[current_filesystem].ls(arg); +} + + +long +file_read(const char *filename, void *buffer, unsigned long maxsize) +{ + char fullpath[1024]; + const char *arg; + + if (current_filesystem == FSTYPE_NONE) { + printf("Can't load file without a filesystem!\n"); + return -1; + } + + if (ISDIRDELIM(*filename)) { + arg = filename; + } else { + sprintf(fullpath, "%s/%s", file_cwd, filename); + arg = fullpath; + } + + return filesystems[current_filesystem].read(arg, buffer, maxsize); +} + +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FAT) */ diff --git a/uart-loader/include/asm/arch-arm1136/bits.h b/uart-loader/include/asm/arch-arm1136/bits.h new file mode 100644 index 0000000..dc3273e --- /dev/null +++ b/uart-loader/include/asm/arch-arm1136/bits.h @@ -0,0 +1,49 @@ +/* bits.h + * Copyright (c) 2004 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef __bits_h +#define __bits_h 1 + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif + diff --git a/uart-loader/include/asm/arch-arm1136/clocks.h b/uart-loader/include/asm/arch-arm1136/clocks.h new file mode 120000 index 0000000..c4b03ba --- /dev/null +++ b/uart-loader/include/asm/arch-arm1136/clocks.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-arm1136/clocks.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-arm1136/clocks242x.h b/uart-loader/include/asm/arch-arm1136/clocks242x.h new file mode 120000 index 0000000..f080726 --- /dev/null +++ b/uart-loader/include/asm/arch-arm1136/clocks242x.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-arm1136/clocks242x.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-arm1136/clocks243x.h b/uart-loader/include/asm/arch-arm1136/clocks243x.h new file mode 120000 index 0000000..703bdce --- /dev/null +++ b/uart-loader/include/asm/arch-arm1136/clocks243x.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-arm1136/clocks243x.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-arm1136/mem.h b/uart-loader/include/asm/arch-arm1136/mem.h new file mode 120000 index 0000000..dd453b2 --- /dev/null +++ b/uart-loader/include/asm/arch-arm1136/mem.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-arm1136/mem.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-arm1136/omap2420.h b/uart-loader/include/asm/arch-arm1136/omap2420.h new file mode 100644 index 0000000..2164b68 --- /dev/null +++ b/uart-loader/include/asm/arch-arm1136/omap2420.h @@ -0,0 +1,223 @@ +/* + * Copyright (C) 2005 Texas Instruments, + * + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP2420_SYS_H_ +#define _OMAP2420_SYS_H_ + +#include + + +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + + +/* + * 2420 specific Section + */ + +/* CONTROL */ +#define OMAP2420_CTRL_BASE (0x48000000) +#define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) + +/* TAP information */ +#define OMAP2420_TAP_BASE (0x48014000) +#define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) + +/* GPMC */ +#define OMAP2420_GPMC_BASE (0x6800A000) +#define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) +#define GPMC_SYSSTATUS (OMAP2420_GPMC_BASE+0x14) +#define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) +#define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) +#define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) +#define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) +#define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) +#define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) +#define GPMC_CONFIG6_0 (OMAP2420_GPMC_BASE+0x74) +#define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) +#define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) +#define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) +#define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) +#define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) +#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) +#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) +#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) + +/* SMS */ +#define OMAP2420_SMS_BASE 0x68008000 +#define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) + +/* SDRC */ +#define OMAP2420_SDRC_BASE 0x68009000 +#define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) +#define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) +#define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) +#define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) +#define SDRC_DLLA_STATUS (OMAP2420_SDRC_BASE+0x64) +#define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) +#define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) +#define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) +#define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) +#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) +#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) +#define SDRC_MCFG_1 (OMAP2420_SDRC_BASE+0xB0) +#define SDRC_MR_1 (OMAP2420_SDRC_BASE+0xB4) +#define SDRC_EMR2_1 (OMAP2420_SDRC_BASE+0xBC) +#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) +#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) +#define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) +#define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) +#define SDRC_RFR_CTRL1 (OMAP2420_SDRC_BASE+0xD4) +#define SDRC_MANUAL_1 (OMAP2420_SDRC_BASE+0xD8) + +#define OMAP2420_SDRC_CS0 0x80000000 +#define OMAP2420_SDRC_CS1 0xA0000000 + +#define LOADDLL BIT2 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET BIT1 +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + + +/* UART */ +#define OMAP2420_UART1 0x4806A000 +#define OMAP2420_UART2 0x4806C000 +#define OMAP2420_UART3 0x4806E000 + +/* General Purpose Timers */ +#define OMAP2420_GPT1 0x48028000 +#define OMAP2420_GPT2 0x4802A000 +#define OMAP2420_GPT3 0x48078000 +#define OMAP2420_GPT4 0x4807A000 +#define OMAP2420_GPT5 0x4807C000 +#define OMAP2420_GPT6 0x4807E000 +#define OMAP2420_GPT7 0x48080000 +#define OMAP2420_GPT8 0x48082000 +#define OMAP2420_GPT9 0x48084000 +#define OMAP2420_GPT10 0x48086000 +#define OMAP2420_GPT11 0x48088000 +#define OMAP2420_GPT12 0x4808A000 + +/* timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE 0x48020000 +#define WD2_BASE 0x48022000 +#define WD3_BASE 0x48024000 +#define WD4_BASE 0x48026000 +#define WWPS 0x34 /* r */ +#define WSPR 0x48 /* rw */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define OMAP2420_CM_BASE 0x48008000 +#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) +#define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) +#define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) +#define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) +#define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) +#define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) +#define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) +#define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) +#define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) +#define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) +#define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) +#define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) +#define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) +#define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) +#define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) +#define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) + +/* + * H4 specific Section + */ + +/* + * The 2420's chip selects are programmable. The mask ROM + * does configure CS0 to 0x08000000 before dispatch. So, if + * you want your code to live below that address, you have to + * be prepared to jump though hoops, to reset the base address. + */ +#if defined(CONFIG_OMAP2420H4) +/* GPMC */ +#ifdef CONFIG_VIRTIO_A /* Pre version B */ +# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ +# define H4_CS1_BASE 0x04000000 /* debug board */ +# define H4_CS2_BASE 0x0A000000 /* wifi board */ +#else +# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ +# define H4_CS1_BASE 0x08000000 /* debug board */ +# define H4_CS2_BASE 0x0A000000 /* wifi board */ +#endif + +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) + +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +#define PERIFERAL_PORT_BASE 0x480FE003 + +/* FPGA on Debug board.*/ +#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) +#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) +#endif /* endif CONFIG_2420H4 */ + +#endif + diff --git a/uart-loader/include/asm/arch-arm1136/omap2430.h b/uart-loader/include/asm/arch-arm1136/omap2430.h new file mode 100644 index 0000000..cf2b0f9 --- /dev/null +++ b/uart-loader/include/asm/arch-arm1136/omap2430.h @@ -0,0 +1,255 @@ +/* + * (C) Copyright 2004-2005 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP2430_SYS_H_ +#define _OMAP2430_SYS_H_ + +#include + + +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + +/* device type */ +#define DEVICE_MASK (BIT8|BIT9|BIT10) +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* + * 2430 specific Section + */ +#define OMAP243X_CORE_L4_IO_BASE 0x48000000 +#define OMAP243X_WAKEUP_L4_IO_BASE 0x49000000 +#define OMAP24XX_L4_IO_BASE OMAP243X_CORE_L4_IO_BASE + + +/* CONTROL */ +#define OMAP24XX_CTRL_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x2000) +#define CONTROL_STATUS (OMAP24XX_CTRL_BASE + 0x2F8) + +/* TAP information */ +#define OMAP24XX_TAP_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0xA000) +#define TAP_IDCODE_REG (OMAP24XX_TAP_BASE+0x204) + +/* + GPMC : In 2430 NOR and NAND can coexist. + During NAND booting , NAND is at CS0 and NOR at CS1 + and Debug FPGA is GPMC_CS5 +*/ +#define OMAP24XX_GPMC_BASE (0x6E000000) + +#define GPMC_SYSCONFIG (OMAP24XX_GPMC_BASE+0x10) +#define GPMC_SYSSTATUS (OMAP24XX_GPMC_BASE+0x14) +#define GPMC_IRQENABLE (OMAP24XX_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP24XX_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP24XX_GPMC_BASE+0x50) +#define GPMC_CONFIG1_0 (OMAP24XX_GPMC_BASE+0x60) +#define GPMC_CONFIG2_0 (OMAP24XX_GPMC_BASE+0x64) +#define GPMC_CONFIG3_0 (OMAP24XX_GPMC_BASE+0x68) +#define GPMC_CONFIG4_0 (OMAP24XX_GPMC_BASE+0x6C) +#define GPMC_CONFIG5_0 (OMAP24XX_GPMC_BASE+0x70) +#define GPMC_CONFIG6_0 (OMAP24XX_GPMC_BASE+0x74) +#define GPMC_CONFIG7_0 (OMAP24XX_GPMC_BASE+0x78) +#define GPMC_CONFIG1_1 (OMAP24XX_GPMC_BASE+0x90) +#define GPMC_CONFIG2_1 (OMAP24XX_GPMC_BASE+0x94) +#define GPMC_CONFIG3_1 (OMAP24XX_GPMC_BASE+0x98) +#define GPMC_CONFIG4_1 (OMAP24XX_GPMC_BASE+0x9C) +#define GPMC_CONFIG5_1 (OMAP24XX_GPMC_BASE+0xA0) +#define GPMC_CONFIG6_1 (OMAP24XX_GPMC_BASE+0xA4) +#define GPMC_CONFIG7_1 (OMAP24XX_GPMC_BASE+0xA8) +#define GPMC_CONFIG1_5 (OMAP24XX_GPMC_BASE+0x150) +#define GPMC_CONFIG2_5 (OMAP24XX_GPMC_BASE+0x154) +#define GPMC_CONFIG3_5 (OMAP24XX_GPMC_BASE+0x158) +#define GPMC_CONFIG4_5 (OMAP24XX_GPMC_BASE+0x15C) +#define GPMC_CONFIG5_5 (OMAP24XX_GPMC_BASE+0x160) +#define GPMC_CONFIG6_5 (OMAP24XX_GPMC_BASE+0x164) +#define GPMC_CONFIG7_5 (OMAP24XX_GPMC_BASE+0x168) + + +/* SMS */ +#define OMAP24XX_SMS_BASE 0x6C000000 +#define SMS_SYSCONFIG (OMAP24XX_SMS_BASE+0x10) + +/* SDRC */ +#define OMAP24XX_SDRC_BASE 0x6D000000 +#define OMAP24XX_SDRC_CS0 0x80000000 +#define OMAP24XX_SDRC_CS1 0xA0000000 +#define SDRC_SYSCONFIG (OMAP24XX_SDRC_BASE+0x10) +#define SDRC_STATUS (OMAP24XX_SDRC_BASE+0x14) +#define SDRC_SHARING (OMAP24XX_SDRC_BASE+0x44) +#define SDRC_DLLA_CTRL (OMAP24XX_SDRC_BASE+0x60) +#define SDRC_DLLA_STATUS (OMAP24XX_SDRC_BASE+0x64) +#define SDRC_DLLB_CTRL (OMAP24XX_SDRC_BASE+0x68) +#define SDRC_POWER (OMAP24XX_SDRC_BASE+0x70) +#define SDRC_MCFG_0 (OMAP24XX_SDRC_BASE+0x80) +#define SDRC_MR_0 (OMAP24XX_SDRC_BASE+0x84) +#define SDRC_ACTIM_CTRLA_0 (OMAP24XX_SDRC_BASE+0x9C) +#define SDRC_ACTIM_CTRLB_0 (OMAP24XX_SDRC_BASE+0xA0) +#define SDRC_MCFG_1 (OMAP24XX_SDRC_BASE+0xB0) +#define SDRC_ACTIM_CTRLA_1 (OMAP24XX_SDRC_BASE+0xC4) +#define SDRC_ACTIM_CTRLB_1 (OMAP24XX_SDRC_BASE+0xC8) +#define SDRC_RFR_CTRL (OMAP24XX_SDRC_BASE+0xA4) +#define SDRC_MANUAL_0 (OMAP24XX_SDRC_BASE+0xA8) +#define SDRC_RFR_CTRL1 (OMAP24XX_SDRC_BASE+0xD4) + +#define LOADDLL BIT2 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET BIT1 +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + + +/* UART */ +#define OMAP2430_UART1 0x4806A000 +#define OMAP2430_UART2 0x4806C000 +#define OMAP2430_UART3 0x4806E000 + +/* General Purpose Timers */ +#define OMAP24XX_GPT1 (OMAP243X_WAKEUP_L4_IO_BASE+0x18000) +#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000) +#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000) +#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000) +#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000) +#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000) +#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000) +#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000) +#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000) +#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000) +#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000) +#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000 + +/* timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x14000) +#define WD2_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x16000) +#define WD3_BASE (OMAP24XX_L4_IO_BASE+0x24000) /* not present */ +#define WD4_BASE (OMAP24XX_L4_IO_BASE+0x26000) + +/* 32KTIMER */ +#define SYNC_32KTIMER_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x20000) +#define S32K_CR (SYNC_32KTIMER_BASE+0x10) + +#define WWPS 0x34 /* r */ +#define WSPR 0x48 /* rw */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define OMAP24XX_CM_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x06000) + +#define PRCM_CLKSRC_CTRL (OMAP24XX_CM_BASE+0x060) +#define PRCM_CLKOUT_CTRL (OMAP24XX_CM_BASE+0x070) +#define PRCM_CLKEMUL_CTRL (OMAP24XX_CM_BASE+0x078) +#define PRCM_CLKCFG_CTRL (OMAP24XX_CM_BASE+0x080) +#define PRCM_CLKCFG_STATUS (OMAP24XX_CM_BASE+0x084) +#define CM_CLKSEL_MPU (OMAP24XX_CM_BASE+0x140) +#define CM_FCLKEN1_CORE (OMAP24XX_CM_BASE+0x200) +#define CM_FCLKEN2_CORE (OMAP24XX_CM_BASE+0x204) +#define CM_ICLKEN1_CORE (OMAP24XX_CM_BASE+0x210) +#define CM_ICLKEN2_CORE (OMAP24XX_CM_BASE+0x214) +#define CM_CLKSEL1_CORE (OMAP24XX_CM_BASE+0x240) +#define CM_CLKSEL_WKUP (OMAP24XX_CM_BASE+0x440) +#define CM_CLKSEL2_CORE (OMAP24XX_CM_BASE+0x244) +#define CM_FCLKEN_GFX (OMAP24XX_CM_BASE+0x300) +#define CM_ICLKEN_GFX (OMAP24XX_CM_BASE+0x310) +#define CM_CLKSEL_GFX (OMAP24XX_CM_BASE+0x340) +#define RM_RSTCTRL_GFX (OMAP24XX_CM_BASE+0x350) +#define CM_FCLKEN_WKUP (OMAP24XX_CM_BASE+0x400) +#define CM_ICLKEN_WKUP (OMAP24XX_CM_BASE+0x410) +#define PM_RSTCTRL_WKUP (OMAP24XX_CM_BASE+0x450) +#define CM_CLKEN_PLL (OMAP24XX_CM_BASE+0x500) +#define CM_IDLEST_CKGEN (OMAP24XX_CM_BASE+0x520) +#define CM_CLKSEL1_PLL (OMAP24XX_CM_BASE+0x540) +#define CM_CLKSEL2_PLL (OMAP24XX_CM_BASE+0x544) +#define CM_CLKSEL_DSP (OMAP24XX_CM_BASE+0x840) +#define CM_CLKSEL_MDM (OMAP24XX_CM_BASE+0xC40) + +/* SMX-APE */ +#define SMX_APE_BASE 0x68000000 +#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) +#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) + +/* IVA2 */ +#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) + +/* + * The 2430's chip selects are programmable. The mask ROM + * does configure CS0 to 0x08000000 before dispatch. So, if + * you want your code to live below that address, you have to + * be prepared to jump though hoops, to reset the base address. + */ +#if defined(CONFIG_OMAP243X) + +/* GPMC */ +/* This is being used by the macros in mem.h. PHYS_FLASH_1 is defined to H4_CS0_BASE */ +# define H4_CS1_BASE 0x09000000 /* flash (64 Meg aligned) */ +#define CFG_FLASH_BASE H4_CS1_BASE +#define DEBUG_BASE 0x08000000 + +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) + +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +#define PERIFERAL_PORT_BASE 0x480FE003 + +#endif /* endif CONFIG_2430SDP */ + +#endif + diff --git a/uart-loader/include/asm/arch-arm1136/sizes.h b/uart-loader/include/asm/arch-arm1136/sizes.h new file mode 100644 index 0000000..3dddd8e --- /dev/null +++ b/uart-loader/include/asm/arch-arm1136/sizes.h @@ -0,0 +1,50 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_31M 0x01F00000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __sizes_h */ + diff --git a/uart-loader/include/asm/arch-arm1136/sys_info.h b/uart-loader/include/asm/arch-arm1136/sys_info.h new file mode 100644 index 0000000..94a09cd --- /dev/null +++ b/uart-loader/include/asm/arch-arm1136/sys_info.h @@ -0,0 +1,139 @@ +/* + * Copyright 2005 (C) Texas Instruments, + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP24XX_SYS_INFO_H_ +#define _OMAP24XX_SYS_INFO_H_ + +#if 0 +typedef struct h4_system_data { + /* base board info */ + u32 base_b_rev; /* rev from base board i2c */ + /* cpu board info */ + u32 cpu_b_rev; /* rev from cpu board i2c */ + u32 cpu_b_mux; /* mux type on daughter board */ + u32 cpu_b_ddr_type; /* mem type */ + u32 cpu_b_ddr_speed; /* ddr speed rating */ + u32 cpu_b_switches; /* boot ctrl switch settings */ + /* cpu info */ + u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ + u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ +} h4_sys_data; + +#endif + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_2420 0x2420 +#define CPU_2422 0x2422 /* 2420 + 64M stacked */ +#define CPU_2423 0x2423 /* 2420 + 96M stacked */ +#define CPU_2430 0x2430 + +/* 242x real hardware: + * ES1 = rev 0 + * ES2 = rev 1 + * ES2.05 = rev 2 + * ES2.1 = rev 3 + * ES2.1.1 = rev 4 + */ + +/* 242x code defines: + * ES1 = 0+1 = 1 + * ES2 = 1+1 = 2 + * ES2.05 = 2+1 = 3 + * ES2.1 = 3+1 = 4 + * Es2.1.1 = 4+1 = 5 + */ +#define CPU_2422_ES1 1 +#define CPU_2422_ES2 2 +#define CPU_2422_ES2_05 3 +#define CPU_2422_ES2_1 4 +#define CPU_2422_ES2_1_1 5 + +#define CPU_2420_ES1 1 +#define CPU_2420_ES2 2 +#define CPU_2420_ES2_05 3 +#define CPU_2420_ES2_1 4 +#define CPU_2420_ES2_1_1 5 + +#define CPU_242X_ES1 1 +#define CPU_242X_ES2 2 +#define CPU_242X_ES2_05 3 +#define CPU_242X_ES2_1 4 +#define CPU_242X_ES2_1_1 5 + +#define CPU_2420_2422_ES1 1 +#define CPU_2420_2422_ES2_1 4 + +/* 243x real hardware: + * ES1 = rev 0 + * ES2 = rev 1 + * + * 243x code defines: + * ES1 = 0+1 = 1 + * ES2 = 1+1 = 2 + */ +#define CPU_2430_ES1 1 +#define CPU_2430_ES2 2 + +#ifdef VPOM2430 +# define CPU_2430_VIRTIO 3 +#else +# define CPU_2430_VIRTIO 1 +#endif +#define CPU_2430_ZEBU 0xD + +#define CPU_2420_CHIPID 0x0B5D9000 +#define CPU_2430_CHIPID 0x0B68A000 +#define CPU_24XX_ID_MASK 0x0FFFF000 +#define CPU_242X_REV_MASK 0xF0000000 +#define CPU_242X_PID_MASK 0x000F0000 + +#define BOARD_H4_MENELAUS 1 +#define BOARD_H4_SDP 2 +#define BOARD_H4_MENELAUS_HRP 3 +#define BOARD_SDP_2430 4 + +#define GPMC_MUXED 1 +#define GPMC_NONMUXED 0 + +#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ +#define TYPE_NOR 0x000 +#define TYPE_ONENAND 0x800 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ + +#endif diff --git a/uart-loader/include/asm/arch-arm926ejs/sizes.h b/uart-loader/include/asm/arch-arm926ejs/sizes.h new file mode 100644 index 0000000..ef0b99b --- /dev/null +++ b/uart-loader/include/asm/arch-arm926ejs/sizes.h @@ -0,0 +1,51 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307 + * USA + */ +/* DO NOT EDIT!! - this file automatically generated + * from .s file by awk -f s2h.awk + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __sizes_h */ diff --git a/uart-loader/include/asm/arch-omap3/bits.h b/uart-loader/include/asm/arch-omap3/bits.h new file mode 120000 index 0000000..036fe66 --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/bits.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-omap3/bits.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-omap3/clocks.h b/uart-loader/include/asm/arch-omap3/clocks.h new file mode 120000 index 0000000..894fadf --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/clocks.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-omap3/clocks.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-omap3/clocks343x.h b/uart-loader/include/asm/arch-omap3/clocks343x.h new file mode 120000 index 0000000..92f7376 --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/clocks343x.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-omap3/clocks343x.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-omap3/cpu.h b/uart-loader/include/asm/arch-omap3/cpu.h new file mode 120000 index 0000000..5c88731 --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/cpu.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-omap3/cpu.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-omap3/dpll_table_34xx.S b/uart-loader/include/asm/arch-omap3/dpll_table_34xx.S new file mode 120000 index 0000000..803f515 --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/dpll_table_34xx.S @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-omap3/dpll_table_34xx.S \ No newline at end of file diff --git a/uart-loader/include/asm/arch-omap3/dpll_table_36xx.S b/uart-loader/include/asm/arch-omap3/dpll_table_36xx.S new file mode 120000 index 0000000..e8f2f9b --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/dpll_table_36xx.S @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-omap3/dpll_table_36xx.S \ No newline at end of file diff --git a/uart-loader/include/asm/arch-omap3/mem.h b/uart-loader/include/asm/arch-omap3/mem.h new file mode 120000 index 0000000..b49b783 --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/mem.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-omap3/mem.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-omap3/mmc.h b/uart-loader/include/asm/arch-omap3/mmc.h new file mode 100644 index 0000000..7bceb5f --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/mmc.h @@ -0,0 +1,187 @@ +/* + * linux/drivers/mmc/mmc_pxa.h + * + * Author: Vladimir Shebordaev, Igor Oblakov + * Copyright: MontaVista Software Inc. + * + * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __MMC_PXA_P_H__ +#define __MMC_PXA_P_H__ + +/* PXA-250 MMC controller registers */ + +/* MMC_STRPCL */ +#define MMC_STRPCL_STOP_CLK (0x0001UL) +#define MMC_STRPCL_START_CLK (0x0002UL) + +/* MMC_STAT */ + +#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN\ + | MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE \ + | MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR) + +/* MMC_CLKRT */ +#define MMC_CLKRT_20MHZ (0x0000UL) +#define MMC_CLKRT_10MHZ (0x0001UL) +#define MMC_CLKRT_5MHZ (0x0002UL) +#define MMC_CLKRT_2_5MHZ (0x0003UL) +#define MMC_CLKRT_1_25MHZ (0x0004UL) +#define MMC_CLKRT_0_625MHZ (0x0005UL) +#define MMC_CLKRT_0_3125MHZ (0x0006UL) + +/* MMC_SPI */ +#define MMC_SPI_DISABLE (0x00UL) +#define MMC_SPI_EN (0x01UL) +#define MMC_SPI_CS_EN (0x01UL << 2) +#define MMC_SPI_CS_ADDRESS (0x01UL << 3) +#define MMC_SPI_CRC_ON (0x01UL << 1) + +/* MMC_CMDAT */ +#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7) +#define MMC_CMDAT_INIT (0x0001UL << 6) +#define MMC_CMDAT_BUSY (0x0001UL << 5) +#define MMC_CMDAT_STREAM (0x0001UL << 4) +#define MMC_CMDAT_BLOCK (0x0000UL << 4) +#define MMC_CMDAT_WRITE (0x0001UL << 3) +#define MMC_CMDAT_READ (0x0000UL << 3) +#define MMC_CMDAT_DATA_EN (0x0001UL << 2) +#define MMC_CMDAT_R1 (0x0001UL) +#define MMC_CMDAT_R2 (0x0002UL) +#define MMC_CMDAT_R3 (0x0003UL) + +/* MMC_RESTO */ +#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ + +/* MMC_RDTO */ +#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ + +/* MMC_BLKLEN */ +#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ + +/* MMC_PRTBUF */ +#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) +#define MMC_PRTBUF_BUF_FULL (0x00UL) + +/* MMC_I_MASK */ +#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6) +#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5) +#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) +#define MMC_I_MASK_STOP_CMD (0x01UL << 3) +#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) +#define MMC_I_MASK_PRG_DONE (0x01UL << 1) +#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL) +#define MMC_I_MASK_ALL (0x07fUL) + + +/* MMC_I_REG */ +#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) +#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) +#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4) +#define MMC_I_REG_STOP_CMD (0x01UL << 3) +#define MMC_I_REG_END_CMD_RES (0x01UL << 2) +#define MMC_I_REG_PRG_DONE (0x01UL << 1) +#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) +#define MMC_I_REG_ALL (0x007fUL) + +/* MMC_CMD */ +#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ +#define CMD(x) (x) + +#define MMC_DEFAULT_RCA 1 + +#define MMC_BLOCK_SIZE 512 +#define MMC_CMD_RESET 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RCA 3 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_BLOCK 17 +#define MMC_CMD_RD_BLK_MULTI 18 +#define MMC_CMD_WRITE_BLOCK 24 + +#define MMC_MAX_BLOCK_SIZE 512 + +#define MMC_R1_IDLE_STATE 0x01 +#define MMC_R1_ERASE_STATE 0x02 +#define MMC_R1_ILLEGAL_CMD 0x04 +#define MMC_R1_COM_CRC_ERR 0x08 +#define MMC_R1_ERASE_SEQ_ERR 0x01 +#define MMC_R1_ADDR_ERR 0x02 +#define MMC_R1_PARAM_ERR 0x04 + +#define MMC_R1B_WP_ERASE_SKIP 0x0002 +#define MMC_R1B_ERR 0x0004 +#define MMC_R1B_CC_ERR 0x0008 +#define MMC_R1B_CARD_ECC_ERR 0x0010 +#define MMC_R1B_WP_VIOLATION 0x0020 +#define MMC_R1B_ERASE_PARAM 0x0040 +#define MMC_R1B_OOR 0x0080 +#define MMC_R1B_IDLE_STATE 0x0100 +#define MMC_R1B_ERASE_RESET 0x0200 +#define MMC_R1B_ILLEGAL_CMD 0x0400 +#define MMC_R1B_COM_CRC_ERR 0x0800 +#define MMC_R1B_ERASE_SEQ_ERR 0x1000 +#define MMC_R1B_ADDR_ERR 0x2000 +#define MMC_R1B_PARAM_ERR 0x4000 + +typedef struct mmc_cid { +/* FIXME: BYTE_ORDER */ + unsigned char year:4, + month:4; + unsigned char sn[3]; + unsigned char fwrev:4, + hwrev:4; + unsigned char name[6]; + unsigned char id[3]; +} mmc_cid_t; + +typedef struct mmc_csd +{ + unsigned char ecc:2, + file_format:2, + tmp_write_protect:1, + perm_write_protect:1, + copy:1, + file_format_grp:1; + unsigned long int content_prot_app:1, + rsvd3:4, + write_bl_partial:1, + write_bl_len:4, + r2w_factor:3, + default_ecc:2, + wp_grp_enable:1, + wp_grp_size:5, + erase_grp_mult:5, + erase_grp_size:5, + c_size_mult1:3, + vdd_w_curr_max:3, + vdd_w_curr_min:3, + vdd_r_curr_max:3, + vdd_r_curr_min:3, + c_size:12, + rsvd2:2, + dsr_imp:1, + read_blk_misalign:1, + write_blk_misalign:1, + read_bl_partial:1; + + unsigned short read_bl_len:4, + ccc:12; + unsigned char tran_speed; + unsigned char nsac; + unsigned char taac; + unsigned char rsvd1:2, + spec_vers:4, + csd_structure:2; +} mmc_csd_t; + + +#endif /* __MMC_PXA_P_H__ */ diff --git a/uart-loader/include/asm/arch-omap3/mux.h b/uart-loader/include/asm/arch-omap3/mux.h new file mode 120000 index 0000000..a745fbd --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/mux.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-omap3/mux.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-omap3/omap3430.h b/uart-loader/include/asm/arch-omap3/omap3430.h new file mode 120000 index 0000000..69502f2 --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/omap3430.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-omap3/omap3430.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-omap3/rev.h b/uart-loader/include/asm/arch-omap3/rev.h new file mode 120000 index 0000000..66918c9 --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/rev.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-omap3/rev.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-omap3/sizes.h b/uart-loader/include/asm/arch-omap3/sizes.h new file mode 120000 index 0000000..4eda715 --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/sizes.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-omap3/sizes.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-omap3/sys_info.h b/uart-loader/include/asm/arch-omap3/sys_info.h new file mode 120000 index 0000000..2e4d1d0 --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/sys_info.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-omap3/sys_info.h \ No newline at end of file diff --git a/uart-loader/include/asm/arch-omap3/sys_proto.h b/uart-loader/include/asm/arch-omap3/sys_proto.h new file mode 120000 index 0000000..3a032c8 --- /dev/null +++ b/uart-loader/include/asm/arch-omap3/sys_proto.h @@ -0,0 +1 @@ +../../../../u-boot/include/asm-arm/arch-omap3/sys_proto.h \ No newline at end of file diff --git a/uart-loader/include/asm/atomic.h b/uart-loader/include/asm/atomic.h new file mode 100644 index 0000000..ba9e4b7 --- /dev/null +++ b/uart-loader/include/asm/atomic.h @@ -0,0 +1,113 @@ +/* + * linux/include/asm-arm/atomic.h + * + * Copyright (c) 1996 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + * 13-04-1997 RMK Made functions atomic! + * 07-12-1997 RMK Upgraded for v2.1. + * 26-08-1998 PJB Added #ifdef __KERNEL__ + */ +#ifndef __ASM_ARM_ATOMIC_H +#define __ASM_ARM_ATOMIC_H + +#include + +#ifdef CONFIG_SMP +#error SMP not supported +#endif + +typedef struct { volatile int counter; } atomic_t; + +#define ATOMIC_INIT(i) { (i) } + +#ifdef __KERNEL__ +#include + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v,i) (((v)->counter) = (i)) + +static inline void atomic_add(int i, volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic_sub(int i, volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} + +static inline void atomic_inc(volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter += 1; + local_irq_restore(flags); +} + +static inline void atomic_dec(volatile atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter -= 1; + local_irq_restore(flags); +} + +static inline int atomic_dec_and_test(volatile atomic_t *v) +{ + unsigned long flags; + int val; + + local_irq_save(flags); + val = v->counter; + v->counter = val -= 1; + local_irq_restore(flags); + + return val == 0; +} + +static inline int atomic_add_negative(int i, volatile atomic_t *v) +{ + unsigned long flags; + int val; + + local_irq_save(flags); + val = v->counter; + v->counter = val += i; + local_irq_restore(flags); + + return val < 0; +} + +static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) +{ + unsigned long flags; + + local_irq_save(flags); + *addr &= ~mask; + local_irq_restore(flags); +} + +/* Atomic operations are already serializing on ARM */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() + +#endif +#endif diff --git a/uart-loader/include/asm/byteorder.h b/uart-loader/include/asm/byteorder.h new file mode 120000 index 0000000..be6afe8 --- /dev/null +++ b/uart-loader/include/asm/byteorder.h @@ -0,0 +1 @@ +../../../u-boot/include/asm-arm/byteorder.h \ No newline at end of file diff --git a/uart-loader/include/asm/posix_types.h b/uart-loader/include/asm/posix_types.h new file mode 100644 index 0000000..c412486 --- /dev/null +++ b/uart-loader/include/asm/posix_types.h @@ -0,0 +1,79 @@ +/* + * linux/include/asm-arm/posix_types.h + * + * Copyright (C) 1996-1998 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 27-06-1996 RMK Created + */ +#ifndef __ARCH_ARM_POSIX_TYPES_H +#define __ARCH_ARM_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) + +#undef __FD_CLR +#define __FD_CLR(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) + +#undef __FD_ISSET +#define __FD_ISSET(fd, fdsetp) \ + ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) \ + (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) + +#endif + +#endif diff --git a/uart-loader/include/asm/setup.h b/uart-loader/include/asm/setup.h new file mode 100644 index 0000000..89df4dc --- /dev/null +++ b/uart-loader/include/asm/setup.h @@ -0,0 +1,269 @@ +/* + * linux/include/asm/setup.h + * + * Copyright (C) 1997-1999 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Structure passed to kernel to tell it about the + * hardware it's running on. See linux/Documentation/arm/Setup + * for more info. + * + * NOTE: + * This file contains two ways to pass information from the boot + * loader to the kernel. The old struct param_struct is deprecated, + * but it will be kept in the kernel for 5 years from now + * (2001). This will allow boot loaders to convert to the new struct + * tag way. + */ +#ifndef __ASMARM_SETUP_H +#define __ASMARM_SETUP_H + +/* + * Usage: + * - do not go blindly adding fields, add them at the end + * - when adding fields, don't rely on the address until + * a patch from me has been released + * - unused fields should be zero (for future expansion) + * - this structure is relatively short-lived - only + * guaranteed to contain useful data in setup_arch() + */ +#define COMMAND_LINE_SIZE 1024 + +/* This is the old deprecated way to pass parameters to the kernel */ +struct param_struct { + union { + struct { + unsigned long page_size; /* 0 */ + unsigned long nr_pages; /* 4 */ + unsigned long ramdisk_size; /* 8 */ + unsigned long flags; /* 12 */ +#define FLAG_READONLY 1 +#define FLAG_RDLOAD 4 +#define FLAG_RDPROMPT 8 + unsigned long rootdev; /* 16 */ + unsigned long video_num_cols; /* 20 */ + unsigned long video_num_rows; /* 24 */ + unsigned long video_x; /* 28 */ + unsigned long video_y; /* 32 */ + unsigned long memc_control_reg; /* 36 */ + unsigned char sounddefault; /* 40 */ + unsigned char adfsdrives; /* 41 */ + unsigned char bytes_per_char_h; /* 42 */ + unsigned char bytes_per_char_v; /* 43 */ + unsigned long pages_in_bank[4]; /* 44 */ + unsigned long pages_in_vram; /* 60 */ + unsigned long initrd_start; /* 64 */ + unsigned long initrd_size; /* 68 */ + unsigned long rd_start; /* 72 */ + unsigned long system_rev; /* 76 */ + unsigned long system_serial_low; /* 80 */ + unsigned long system_serial_high; /* 84 */ + unsigned long mem_fclk_21285; /* 88 */ + } s; + char unused[256]; + } u1; + union { + char paths[8][128]; + struct { + unsigned long magic; + char n[1024 - sizeof(unsigned long)]; + } s; + } u2; + char commandline[COMMAND_LINE_SIZE]; +}; + + +/* + * The new way of passing information: a list of tagged entries + */ + +/* The list ends with an ATAG_NONE node. */ +#define ATAG_NONE 0x00000000 + +struct tag_header { + u32 size; + u32 tag; +}; + +/* The list must start with an ATAG_CORE node */ +#define ATAG_CORE 0x54410001 + +struct tag_core { + u32 flags; /* bit 0 = read-only */ + u32 pagesize; + u32 rootdev; +}; + +/* it is allowed to have multiple ATAG_MEM nodes */ +#define ATAG_MEM 0x54410002 + +struct tag_mem32 { + u32 size; + u32 start; /* physical start address */ +}; + +/* VGA text type displays */ +#define ATAG_VIDEOTEXT 0x54410003 + +struct tag_videotext { + u8 x; + u8 y; + u16 video_page; + u8 video_mode; + u8 video_cols; + u16 video_ega_bx; + u8 video_lines; + u8 video_isvga; + u16 video_points; +}; + +/* describes how the ramdisk will be used in kernel */ +#define ATAG_RAMDISK 0x54410004 + +struct tag_ramdisk { + u32 flags; /* bit 0 = load, bit 1 = prompt */ + u32 size; /* decompressed ramdisk size in _kilo_ bytes */ + u32 start; /* starting block of floppy-based RAM disk image */ +}; + +/* describes where the compressed ramdisk image lives (virtual address) */ +/* + * this one accidentally used virtual addresses - as such, + * its depreciated. + */ +#define ATAG_INITRD 0x54410005 + +/* describes where the compressed ramdisk image lives (physical address) */ +#define ATAG_INITRD2 0x54420005 + +struct tag_initrd { + u32 start; /* physical start address */ + u32 size; /* size of compressed ramdisk image in bytes */ +}; + +/* board serial number. "64 bits should be enough for everybody" */ +#define ATAG_SERIAL 0x54410006 + +struct tag_serialnr { + u32 low; + u32 high; +}; + +/* board revision */ +#define ATAG_REVISION 0x54410007 + +struct tag_revision { + u32 rev; +}; + +/* initial values for vesafb-type framebuffers. see struct screen_info + * in include/linux/tty.h + */ +#define ATAG_VIDEOLFB 0x54410008 + +struct tag_videolfb { + u16 lfb_width; + u16 lfb_height; + u16 lfb_depth; + u16 lfb_linelength; + u32 lfb_base; + u32 lfb_size; + u8 red_size; + u8 red_pos; + u8 green_size; + u8 green_pos; + u8 blue_size; + u8 blue_pos; + u8 rsvd_size; + u8 rsvd_pos; +}; + +/* command line: \0 terminated string */ +#define ATAG_CMDLINE 0x54410009 + +struct tag_cmdline { + char cmdline[1]; /* this is the minimum size */ +}; + +/* acorn RiscPC specific information */ +#define ATAG_ACORN 0x41000101 + +struct tag_acorn { + u32 memc_control_reg; + u32 vram_pages; + u8 sounddefault; + u8 adfsdrives; +}; + +/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */ +#define ATAG_MEMCLK 0x41000402 + +struct tag_memclk { + u32 fmemclk; +}; + +struct tag { + struct tag_header hdr; + union { + struct tag_core core; + struct tag_mem32 mem; + struct tag_videotext videotext; + struct tag_ramdisk ramdisk; + struct tag_initrd initrd; + struct tag_serialnr serialnr; + struct tag_revision revision; + struct tag_videolfb videolfb; + struct tag_cmdline cmdline; + + /* + * Acorn specific + */ + struct tag_acorn acorn; + + /* + * DC21285 specific + */ + struct tag_memclk memclk; + } u; +}; + +struct tagtable { + u32 tag; + int (*parse)(const struct tag *); +}; + +#define __tag __attribute__((unused, __section__(".taglist"))) +#define __tagtable(tag, fn) \ +static struct tagtable __tagtable_##fn __tag = { tag, fn } + +#define tag_member_present(tag,member) \ + ((unsigned long)(&((struct tag *)0L)->member + 1) \ + <= (tag)->hdr.size * 4) + +#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size)) +#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) + +#define for_each_tag(t,base) \ + for (t = base; t->hdr.size; t = tag_next(t)) + +/* + * Memory map description + */ +#define NR_BANKS 8 + +struct meminfo { + int nr_banks; + unsigned long end; + struct { + unsigned long start; + unsigned long size; + int node; + } bank[NR_BANKS]; +}; + +extern struct meminfo meminfo; + +#endif diff --git a/uart-loader/include/asm/sizes.h b/uart-loader/include/asm/sizes.h new file mode 100644 index 0000000..f8d92ca --- /dev/null +++ b/uart-loader/include/asm/sizes.h @@ -0,0 +1,52 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* DO NOT EDIT!! - this file automatically generated + * from .s file by awk -f s2h.awk + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif + +/* END */ diff --git a/uart-loader/include/asm/string.h b/uart-loader/include/asm/string.h new file mode 100644 index 0000000..c3ea582 --- /dev/null +++ b/uart-loader/include/asm/string.h @@ -0,0 +1,47 @@ +#ifndef __ASM_ARM_STRING_H +#define __ASM_ARM_STRING_H + +/* + * We don't do inline string functions, since the + * optimised inline asm versions are not small. + */ + +#undef __HAVE_ARCH_STRRCHR +extern char * strrchr(const char * s, int c); + +#undef __HAVE_ARCH_STRCHR +extern char * strchr(const char * s, int c); + +#undef __HAVE_ARCH_MEMCPY +extern void * memcpy(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMMOVE +extern void * memmove(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMCHR +extern void * memchr(const void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMZERO +#undef __HAVE_ARCH_MEMSET +extern void * memset(void *, int, __kernel_size_t); + +#if 0 +extern void __memzero(void *ptr, __kernel_size_t n); + +#define memset(p,v,n) \ + ({ \ + if ((n) != 0) { \ + if (__builtin_constant_p((v)) && (v) == 0) \ + __memzero((p),(n)); \ + else \ + memset((p),(v),(n)); \ + } \ + (p); \ + }) + +#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); }) +#else +extern void memzero(void *ptr, __kernel_size_t n); +#endif + +#endif diff --git a/uart-loader/include/asm/types.h b/uart-loader/include/asm/types.h new file mode 100644 index 0000000..13e9806 --- /dev/null +++ b/uart-loader/include/asm/types.h @@ -0,0 +1,50 @@ +#ifndef __ASM_ARM_TYPES_H +#define __ASM_ARM_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +#endif /* __KERNEL__ */ + +#endif diff --git a/uart-loader/include/asm/x-load-arm.h b/uart-loader/include/asm/x-load-arm.h new file mode 100644 index 0000000..eef268e --- /dev/null +++ b/uart-loader/include/asm/x-load-arm.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2004 + * Texas Instruments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _X_LOAD_ARM_H_ +#define _X_LOAD_ARM_H_ 1 + +/* for the following variables, see start.S */ +extern ulong _armboot_start; /* code start */ +extern ulong _bss_start; /* code + data end == BSS start */ +extern ulong _bss_end; /* BSS end */ + +#endif /* _X_LOAD_ARM_H_ */ diff --git a/uart-loader/include/command.h b/uart-loader/include/command.h new file mode 120000 index 0000000..f4bd05e --- /dev/null +++ b/uart-loader/include/command.h @@ -0,0 +1 @@ +../../u-boot/include/command.h \ No newline at end of file diff --git a/uart-loader/include/common.h b/uart-loader/include/common.h new file mode 100644 index 0000000..fe8bc90 --- /dev/null +++ b/uart-loader/include/common.h @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2004 + * Texas Instruments + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __COMMON_H_ +#define __COMMON_H_ 1 + +#undef _LINUX_CONFIG_H +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +typedef unsigned char uchar; +typedef volatile unsigned long vu_long; +typedef volatile unsigned short vu_short; +typedef volatile unsigned char vu_char; + +#include +#include +#include + +#ifdef CONFIG_ARM +#define asmlinkage /* nothing */ +#endif + + +#ifdef CONFIG_ARM +# include +# include /* ARM version to be fixed! */ +#endif /* CONFIG_ARM */ + +#ifdef CFG_PRINTF +#define printf(fmt,args...) serial_printf (fmt ,##args) +#define getc() serial_getc() +#else +#define printf(fmt,args...) +#define getc() ' ' +#endif /* CFG_PRINTF */ + +/* board/$(BOARD)/$(BOARD).c */ +int board_init (void); +int nand_init (void); +int mmc_boot (void); +void board_hang (void); + +/* cpu/$(CPU)/cpu.c */ +int cpu_init (void); +#ifdef CFG_UDELAY +void udelay (unsigned long usec); +#endif + +/* nand driver */ +#define NAND_CMD_READ0 0 +#define NAND_CMD_READ1 1 +#define NAND_CMD_READOOB 0x50 +#define NAND_CMD_STATUS 0x70 +#define NAND_CMD_READID 0x90 +#define NAND_CMD_RESET 0xff + +/* Extended Commands for Large page devices */ +#define NAND_CMD_READSTART 0x30 + +int nand_chip(void); +int nand_read_block(uchar *buf, ulong block_addr); + +int onenand_chip(void); +int onenand_read_block(unsigned char *buf, ulong block); + + +#ifdef CFG_PRINTF + +/* serial driver */ +int serial_init (void); +void serial_setbrg (void); +void serial_putc (const char); +void serial_puts (const char *); +int serial_getc (void); +int serial_tstc (void); + +/* lib/printf.c */ +void serial_printf (const char *fmt, ...); +#endif + +/* lib/crc.c */ +void nand_calculate_ecc (const u_char *dat, u_char *ecc_code); +int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc); + +/* lib/board.c */ +void hang (void) __attribute__ ((noreturn)); +#endif /* __COMMON_H_ */ diff --git a/uart-loader/include/configs/omap3430labrador.h b/uart-loader/include/configs/omap3430labrador.h new file mode 100644 index 0000000..e1e2665 --- /dev/null +++ b/uart-loader/include/configs/omap3430labrador.h @@ -0,0 +1,220 @@ +/* + * (C) Copyright 2006 + * Texas Instruments + * Richard Woodruff + * + * X-Loader Configuation settings for the TI OMAP SDP3430 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* serial printf facility takes about 3.5K */ +#define CFG_PRINTF +//#undef CFG_PRINTF + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_3430LABRADOR 1 /* working on Labrador */ +//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ + +#include /* get chip and board defs */ + +/* uncomment it if you need timer based udelay(). it takes about 250 bytes */ +//#define CFG_UDELAY + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + +//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ +#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=500MHz - VDD1=1.20v */ + +/* Memory type */ +#define CFG_3430SDRAM_DDR 1 + +/* The actual register values are defined in u-boot- mem.h */ +/* SDRAM Bank Allocation method */ +//#define SDRC_B_R_C 1 +//#define SDRC_B1_R_B0_C 1 +#define SDRC_R_B_C 1 + +/* Boot type */ +#define CFG_NAND 1 +//#define CFG_ONENAND 1 + +# define NAND_BASE_ADR NAND_BASE /* NAND flash */ +# define ONENAND_BASE ONENAND_MAP /* OneNand flash */ + +/* To use the 256/512 byte s/w ecc define CFG_SW_ECC_(256/512) */ +/* Use the 512 byte hw ecc in rom code layout */ +#define NAND_HW_ROMCODE_ECC_LAYOUT + +#ifdef CFG_NAND +#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M /* u = ofdon't need so much for nand port */ +#define OMAP34XX_GPMC_CS0_MAP NAND_BASE_ADR +#else +#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M +#define OMAP34XX_GPMC_CS0_MAP ONENAND_BASE +#define ONENAND_ADDR ONENAND_BASE /* physical address of OneNAND at CS0*/ +#endif + + +#ifdef CFG_PRINTF + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (48000000) +#define CFG_NS16550_COM3 OMAP34XX_UART3 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL3 3 /* UART3 on board */ +#define CONFIG_CONS_INDEX 3 + +#define CONFIG_BAUDRATE 115200 +#define CFG_PBSIZE 256 + +#endif /* CFG_PRINTF */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LOADADDR 0x80008000 + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#ifdef CFG_NAND + +/*----------------------------------------------------------------------- + * Board NAND Info. + */ + + +#define CFG_NAND_K9F1G08R0A /* Micron 16-bit 256MB chip large page NAND chip*/ +#define NAND_16BIT + +/* NAND is partitioned: + * 0x00000000 - 0x0007FFFF Booting Image + * 0x00080000 - 0x000BFFFF U-Boot Image + * 0x000C0000 - 0x000FFFFF U-Boot Env Data (X-loader doesn't care) + * 0x00100000 - 0x002FFFFF Kernel Image + * 0x00300000 - 0x08000000 depends on application + */ +#define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */ +#define NAND_UBOOT_END 0x00C0000 /* Giving a space of 2 blocks = 256KB */ +#define NAND_BLOCK_SIZE 0x20000 + +#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) +#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) +#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) +#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) + +#ifdef NAND_16BIT +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u16 *)GPMC_NAND_DATA_0 = d;} while(0) +#define READ_NAND(adr) \ + (*(volatile u16 *)GPMC_NAND_DATA_0) +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) + +#else /* to support 8-bit NAND devices */ +#define WRITE_NAND_COMMAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d;} while(0) +#define WRITE_NAND_ADDRESS(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d;} while(0) +#define WRITE_NAND(d, adr) \ + do {*(volatile u8 *)GPMC_NAND_DATA_0 = d;} while(0) +#define READ_NAND(adr) \ + (*(volatile u8 *)GPMC_NAND_DATA_0); +#define NAND_WAIT_READY() +#define NAND_WP_OFF() \ + do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() \ + do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) + +#endif + +#define NAND_CTL_CLRALE(adr) +#define NAND_CTL_SETALE(adr) +#define NAND_CTL_CLRCLE(adr) +#define NAND_CTL_SETCLE(adr) +#define NAND_DISABLE_CE() +#define NAND_ENABLE_CE() + +#else +/*----------------------------------------------------------------------- + * Board oneNAND Info. + */ +#define CFG_SYNC_BURST_READ 1 + +/* OneNAND is partitioned: + * 0x0000000 - 0x0080000 X-Loader + * 0x0080000 - 0x00c0000 U-boot Image + * 0x00c0000 - 0x00e0000 U-Boot Env Data (X-loader doesn't care) + * 0x00e0000 - 0x0120000 Kernel Image + * 0x0120000 - 0x4000000 depends on application + */ + +#define ONENAND_START_BLOCK 4 +#define ONENAND_END_BLOCK 6 +#define ONENAND_PAGE_SIZE 2048 /* 2KB */ +#define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */ + +#endif /* oneNAND */ + +/* Enable CONFIG_MMC macro if MMC boot support is required */ +/* if loadb and MMC support are enabled together, the size of x-loader + (code + data) becomes greater than 32K - the size of SRAM. So don't enable + them together. + */ +#if !defined(START_LOADB_DOWNLOAD) +#define CONFIG_MMC 1 +#endif +#if defined(CONFIG_MMC) + #define CFG_CMD_MMC 1 + #define CFG_CMD_FAT 1 +#endif + +#endif /* __CONFIG_H */ + diff --git a/uart-loader/include/fat.h b/uart-loader/include/fat.h new file mode 120000 index 0000000..aeeb5a0 --- /dev/null +++ b/uart-loader/include/fat.h @@ -0,0 +1 @@ +../../u-boot/include/fat.h \ No newline at end of file diff --git a/uart-loader/include/ide.h b/uart-loader/include/ide.h new file mode 120000 index 0000000..9c84a17 --- /dev/null +++ b/uart-loader/include/ide.h @@ -0,0 +1 @@ +../../u-boot/include/ide.h \ No newline at end of file diff --git a/uart-loader/include/linux/byteorder b/uart-loader/include/linux/byteorder new file mode 120000 index 0000000..f000c3b --- /dev/null +++ b/uart-loader/include/linux/byteorder @@ -0,0 +1 @@ +../../../u-boot/include/linux/byteorder \ No newline at end of file diff --git a/uart-loader/include/linux/config.h b/uart-loader/include/linux/config.h new file mode 100644 index 0000000..a0194cb --- /dev/null +++ b/uart-loader/include/linux/config.h @@ -0,0 +1,6 @@ +#ifndef _LINUX_CONFIG_H +#define _LINUX_CONFIG_H + +/* #include */ + +#endif diff --git a/uart-loader/include/linux/posix_types.h b/uart-loader/include/linux/posix_types.h new file mode 100644 index 0000000..bd37e1f --- /dev/null +++ b/uart-loader/include/linux/posix_types.h @@ -0,0 +1,48 @@ +#ifndef _LINUX_POSIX_TYPES_H +#define _LINUX_POSIX_TYPES_H + +#include + +/* + * This allows for 1024 file descriptors: if NR_OPEN is ever grown + * beyond that you'll have to change this too. But 1024 fd's seem to be + * enough even for such "real" unices like OSF/1, so hopefully this is + * one limit that doesn't have to be changed [again]. + * + * Note that POSIX wants the FD_CLEAR(fd,fdsetp) defines to be in + * (and thus ) - but this is a more logical + * place for them. Solved by having dummy defines in . + */ + +/* + * Those macros may have been defined in . But we always + * use the ones here. + */ +#undef __NFDBITS +#define __NFDBITS (8 * sizeof(unsigned long)) + +#undef __FD_SETSIZE +#define __FD_SETSIZE 1024 + +#undef __FDSET_LONGS +#define __FDSET_LONGS (__FD_SETSIZE/__NFDBITS) + +#undef __FDELT +#define __FDELT(d) ((d) / __NFDBITS) + +#undef __FDMASK +#define __FDMASK(d) (1UL << ((d) % __NFDBITS)) + +typedef struct { + unsigned long fds_bits [__FDSET_LONGS]; +} __kernel_fd_set; + +/* Type of a signal handler. */ +typedef void (*__kernel_sighandler_t)(int); + +/* Type of a SYSV IPC key. */ +typedef int __kernel_key_t; + +#include + +#endif /* _LINUX_POSIX_TYPES_H */ diff --git a/uart-loader/include/linux/stat.h b/uart-loader/include/linux/stat.h new file mode 120000 index 0000000..3bc0369 --- /dev/null +++ b/uart-loader/include/linux/stat.h @@ -0,0 +1 @@ +../../../u-boot/include/linux/stat.h \ No newline at end of file diff --git a/uart-loader/include/linux/stddef.h b/uart-loader/include/linux/stddef.h new file mode 100644 index 0000000..81e34c2 --- /dev/null +++ b/uart-loader/include/linux/stddef.h @@ -0,0 +1,18 @@ +#ifndef _LINUX_STDDEF_H +#define _LINUX_STDDEF_H + +#undef NULL +#if defined(__cplusplus) +#define NULL 0 +#else +#define NULL ((void *)0) +#endif + +#ifndef _SIZE_T +#include +#endif + +#undef offsetof +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) + +#endif diff --git a/uart-loader/include/linux/time.h b/uart-loader/include/linux/time.h new file mode 120000 index 0000000..d630a65 --- /dev/null +++ b/uart-loader/include/linux/time.h @@ -0,0 +1 @@ +../../../u-boot/include/linux/time.h \ No newline at end of file diff --git a/uart-loader/include/linux/types.h b/uart-loader/include/linux/types.h new file mode 100644 index 0000000..df4808f --- /dev/null +++ b/uart-loader/include/linux/types.h @@ -0,0 +1,130 @@ +#ifndef _LINUX_TYPES_H +#define _LINUX_TYPES_H + +#ifdef __KERNEL__ +#include +#endif + +#include +#include + +#ifndef __KERNEL_STRICT_NAMES + +typedef __kernel_fd_set fd_set; +typedef __kernel_dev_t dev_t; +typedef __kernel_ino_t ino_t; +typedef __kernel_mode_t mode_t; +typedef __kernel_nlink_t nlink_t; +typedef __kernel_off_t off_t; +typedef __kernel_pid_t pid_t; +typedef __kernel_daddr_t daddr_t; +typedef __kernel_key_t key_t; +typedef __kernel_suseconds_t suseconds_t; + +#ifdef __KERNEL__ +typedef __kernel_uid32_t uid_t; +typedef __kernel_gid32_t gid_t; +typedef __kernel_uid16_t uid16_t; +typedef __kernel_gid16_t gid16_t; + +#ifdef CONFIG_UID16 +/* This is defined by include/asm-{arch}/posix_types.h */ +typedef __kernel_old_uid_t old_uid_t; +typedef __kernel_old_gid_t old_gid_t; +#endif /* CONFIG_UID16 */ + +/* libc5 includes this file to define uid_t, thus uid_t can never change + * when it is included by non-kernel code + */ +#else +typedef __kernel_uid_t uid_t; +typedef __kernel_gid_t gid_t; +#endif /* __KERNEL__ */ + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __kernel_loff_t loff_t; +#endif + +/* + * The following typedefs are also protected by individual ifdefs for + * historical reasons: + */ +#ifndef _SIZE_T +#define _SIZE_T +typedef __kernel_size_t size_t; +#endif + +#ifndef _SSIZE_T +#define _SSIZE_T +typedef __kernel_ssize_t ssize_t; +#endif + +#ifndef _PTRDIFF_T +#define _PTRDIFF_T +typedef __kernel_ptrdiff_t ptrdiff_t; +#endif + +#ifndef _TIME_T +#define _TIME_T +typedef __kernel_time_t time_t; +#endif + +#ifndef _CLOCK_T +#define _CLOCK_T +typedef __kernel_clock_t clock_t; +#endif + +#ifndef _CADDR_T +#define _CADDR_T +typedef __kernel_caddr_t caddr_t; +#endif + +/* bsd */ +typedef unsigned char u_char; +typedef unsigned short u_short; +typedef unsigned int u_int; +typedef unsigned long u_long; + +/* sysv */ +typedef unsigned char unchar; +typedef unsigned short ushort; +typedef unsigned int uint; +typedef unsigned long ulong; + +#ifndef __BIT_TYPES_DEFINED__ +#define __BIT_TYPES_DEFINED__ + +typedef __u8 u_int8_t; +typedef __s8 int8_t; +typedef __u16 u_int16_t; +typedef __s16 int16_t; +typedef __u32 u_int32_t; +typedef __s32 int32_t; + +#endif /* !(__BIT_TYPES_DEFINED__) */ + +typedef __u8 uint8_t; +typedef __u16 uint16_t; +typedef __u32 uint32_t; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __u64 uint64_t; +typedef __u64 u_int64_t; +typedef __s64 int64_t; +#endif + +#endif /* __KERNEL_STRICT_NAMES */ + +/* + * Below are truly Linux-specific types that should never collide with + * any application/library that wants linux/types.h. + */ + +struct ustat { + __kernel_daddr_t f_tfree; + __kernel_ino_t f_tinode; + char f_fname[6]; + char f_fpack[6]; +}; + +#endif /* _LINUX_TYPES_H */ diff --git a/uart-loader/include/malloc.h b/uart-loader/include/malloc.h new file mode 120000 index 0000000..9e84013 --- /dev/null +++ b/uart-loader/include/malloc.h @@ -0,0 +1 @@ +../../u-boot/include/malloc.h \ No newline at end of file diff --git a/uart-loader/include/mmc.h b/uart-loader/include/mmc.h new file mode 120000 index 0000000..1e59fb9 --- /dev/null +++ b/uart-loader/include/mmc.h @@ -0,0 +1 @@ +../../u-boot/include/mmc.h \ No newline at end of file diff --git a/uart-loader/include/ns16550.h b/uart-loader/include/ns16550.h new file mode 100644 index 0000000..36d2d40 --- /dev/null +++ b/uart-loader/include/ns16550.h @@ -0,0 +1,130 @@ +/* + *This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * NS16550 Serial Port + * originally from linux source (arch/ppc/boot/ns16550.h) + * modified slightly to + * have addresses as offsets from CFG_ISA_BASE + * added a few more definitions + * added prototypes for ns16550.c + * reduced no of com ports to 2 + * modifications (c) Rob Taylor, Flying Pig Systems. 2000. + */ + +#if (CFG_NS16550_REG_SIZE == 1) +struct NS16550 { + unsigned char rbr; /* 0 */ + unsigned char ier; /* 1 */ + unsigned char fcr; /* 2 */ + unsigned char lcr; /* 3 */ + unsigned char mcr; /* 4 */ + unsigned char lsr; /* 5 */ + unsigned char msr; /* 6 */ + unsigned char scr; /* 7 */ +} __attribute__ ((packed)); +#elif (CFG_NS16550_REG_SIZE == 2) +struct NS16550 { + unsigned short rbr; /* 0 */ + unsigned short ier; /* 1 */ + unsigned short fcr; /* 2 */ + unsigned short lcr; /* 3 */ + unsigned short mcr; /* 4 */ + unsigned short lsr; /* 5 */ + unsigned short msr; /* 6 */ + unsigned short scr; /* 7 */ +} __attribute__ ((packed)); +#elif (CFG_NS16550_REG_SIZE == 4) +struct NS16550 { + unsigned long rbr; /* 0 */ + unsigned long ier; /* 1 */ + unsigned long fcr; /* 2 */ + unsigned long lcr; /* 3 */ + unsigned long mcr; /* 4 */ + unsigned long lsr; /* 5 */ + unsigned long msr; /* 6 */ + unsigned long scr; /* 7 */ +} __attribute__ ((packed)); +#elif (CFG_NS16550_REG_SIZE == -4) +struct NS16550 { + unsigned char rbr; /* 0 */ + int pad1:24; + unsigned char ier; /* 1 */ + int pad2:24; + unsigned char fcr; /* 2 */ + int pad3:24; + unsigned char lcr; /* 3 */ + int pad4:24; + unsigned char mcr; /* 4 */ + int pad5:24; + unsigned char lsr; /* 5 */ + int pad6:24; + unsigned char msr; /* 6 */ + int pad7:24; + unsigned char scr; /* 7 */ + int pad8:24; +#if defined(CONFIG_OMAP) + unsigned char mdr1; /* mode select reset TL16C750*/ +#endif +#ifdef CONFIG_OMAP1510 + int pad9:24; + unsigned long pad[10]; + unsigned char osc_12m_sel; + int pad10:24; +#endif +} __attribute__ ((packed)); +#else +#error "Please define NS16550 registers size." +#endif + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +typedef volatile struct NS16550 *NS16550_t; + +#define FCR_FIFO_EN 0x01 /* Fifo enable */ +#define FCR_RXSR 0x02 /* Receiver soft reset */ +#define FCR_TXSR 0x04 /* Transmitter soft reset */ + +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_DMA_EN 0x04 +#define MCR_TX_DFR 0x08 + +#define LCR_WLS_MSK 0x03 /* character length slect mask */ +#define LCR_WLS_5 0x00 /* 5 bit character length */ +#define LCR_WLS_6 0x01 /* 6 bit character length */ +#define LCR_WLS_7 0x02 /* 7 bit character length */ +#define LCR_WLS_8 0x03 /* 8 bit character length */ +#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define LCR_PEN 0x08 /* Parity eneble */ +#define LCR_EPS 0x10 /* Even Parity Select */ +#define LCR_STKP 0x20 /* Stick Parity */ +#define LCR_SBRK 0x40 /* Set Break */ +#define LCR_BKSE 0x80 /* Bank select enable */ + +#define LSR_DR 0x01 /* Data ready */ +#define LSR_OE 0x02 /* Overrun */ +#define LSR_PE 0x04 /* Parity error */ +#define LSR_FE 0x08 /* Framing error */ +#define LSR_BI 0x10 /* Break */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define LSR_TEMT 0x40 /* Xmitter empty */ +#define LSR_ERR 0x80 /* Error */ + +#ifdef CONFIG_OMAP1510 +#define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */ +#endif + +/* useful defaults for LCR */ +#define LCR_8N1 0x03 + +void NS16550_init (NS16550_t com_port, int baud_divisor); +void NS16550_putc (NS16550_t com_port, char c); +char NS16550_getc (NS16550_t com_port); +int NS16550_tstc (NS16550_t com_port); +void NS16550_reinit (NS16550_t com_port, int baud_divisor); diff --git a/uart-loader/include/part.h b/uart-loader/include/part.h new file mode 120000 index 0000000..766e417 --- /dev/null +++ b/uart-loader/include/part.h @@ -0,0 +1 @@ +../../u-boot/include/part.h \ No newline at end of file diff --git a/uart-loader/lib/Makefile b/uart-loader/lib/Makefile new file mode 100644 index 0000000..341cd54 --- /dev/null +++ b/uart-loader/lib/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2004 Texas Instruments +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(ARCH).a + +AOBJS = _udivsi3.o _umodsi3.o + +COBJS = board.o ecc_256.o ecc_512.o printf.o div0.o + +OBJS = $(AOBJS) $(COBJS) + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/uart-loader/lib/_udivsi3.S b/uart-loader/lib/_udivsi3.S new file mode 100644 index 0000000..2cdcd48 --- /dev/null +++ b/uart-loader/lib/_udivsi3.S @@ -0,0 +1,77 @@ +/* # 1 "libgcc1.S" */ +@ libgcc1 routines for ARM cpu. +@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) +dividend .req r0 +divisor .req r1 +result .req r2 +curbit .req r3 +/* ip .req r12 */ +/* sp .req r13 */ +/* lr .req r14 */ +/* pc .req r15 */ + .text + .globl __udivsi3 + .type __udivsi3 ,function + .align 0 + __udivsi3 : + cmp divisor, #0 + beq Ldiv0 + mov curbit, #1 + mov result, #0 + cmp dividend, divisor + bcc Lgot_result +Loop1: + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. + cmp divisor, #0x10000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #4 + movcc curbit, curbit, lsl #4 + bcc Loop1 +Lbignum: + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. + cmp divisor, #0x80000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #1 + movcc curbit, curbit, lsl #1 + bcc Lbignum +Loop3: + @ Test for possible subtractions, and note which bits + @ are done in the result. On the final pass, this may subtract + @ too much from the dividend, but the result will be ok, since the + @ "bit" will have been shifted out at the bottom. + cmp dividend, divisor + subcs dividend, dividend, divisor + orrcs result, result, curbit + cmp dividend, divisor, lsr #1 + subcs dividend, dividend, divisor, lsr #1 + orrcs result, result, curbit, lsr #1 + cmp dividend, divisor, lsr #2 + subcs dividend, dividend, divisor, lsr #2 + orrcs result, result, curbit, lsr #2 + cmp dividend, divisor, lsr #3 + subcs dividend, dividend, divisor, lsr #3 + orrcs result, result, curbit, lsr #3 + cmp dividend, #0 @ Early termination? + movnes curbit, curbit, lsr #4 @ No, any more bits to do? + movne divisor, divisor, lsr #4 + bne Loop3 +Lgot_result: + mov r0, result + mov pc, lr +Ldiv0: + str lr, [sp, #-4]! + bl __div0 (PLT) + mov r0, #0 @ about as wrong as it could be + ldmia sp!, {pc} + .size __udivsi3 , . - __udivsi3 +/* # 235 "libgcc1.S" */ +/* # 320 "libgcc1.S" */ +/* # 421 "libgcc1.S" */ +/* # 433 "libgcc1.S" */ +/* # 456 "libgcc1.S" */ +/* # 500 "libgcc1.S" */ +/* # 580 "libgcc1.S" */ diff --git a/uart-loader/lib/_umodsi3.S b/uart-loader/lib/_umodsi3.S new file mode 100644 index 0000000..e4aebe8 --- /dev/null +++ b/uart-loader/lib/_umodsi3.S @@ -0,0 +1,88 @@ +/* # 1 "libgcc1.S" */ +@ libgcc1 routines for ARM cpu. +@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) +/* # 145 "libgcc1.S" */ +dividend .req r0 +divisor .req r1 +overdone .req r2 +curbit .req r3 +/* ip .req r12 */ +/* sp .req r13 */ +/* lr .req r14 */ +/* pc .req r15 */ + .text + .globl __umodsi3 + .type __umodsi3 ,function + .align 0 + __umodsi3 : + cmp divisor, #0 + beq Ldiv0 + mov curbit, #1 + cmp dividend, divisor + movcc pc, lr +Loop1: + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. + cmp divisor, #0x10000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #4 + movcc curbit, curbit, lsl #4 + bcc Loop1 +Lbignum: + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. + cmp divisor, #0x80000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #1 + movcc curbit, curbit, lsl #1 + bcc Lbignum +Loop3: + @ Test for possible subtractions. On the final pass, this may + @ subtract too much from the dividend, so keep track of which + @ subtractions are done, we can fix them up afterwards... + mov overdone, #0 + cmp dividend, divisor + subcs dividend, dividend, divisor + cmp dividend, divisor, lsr #1 + subcs dividend, dividend, divisor, lsr #1 + orrcs overdone, overdone, curbit, ror #1 + cmp dividend, divisor, lsr #2 + subcs dividend, dividend, divisor, lsr #2 + orrcs overdone, overdone, curbit, ror #2 + cmp dividend, divisor, lsr #3 + subcs dividend, dividend, divisor, lsr #3 + orrcs overdone, overdone, curbit, ror #3 + mov ip, curbit + cmp dividend, #0 @ Early termination? + movnes curbit, curbit, lsr #4 @ No, any more bits to do? + movne divisor, divisor, lsr #4 + bne Loop3 + @ Any subtractions that we should not have done will be recorded in + @ the top three bits of "overdone". Exactly which were not needed + @ are governed by the position of the bit, stored in ip. + @ If we terminated early, because dividend became zero, + @ then none of the below will match, since the bit in ip will not be + @ in the bottom nibble. + ands overdone, overdone, #0xe0000000 + moveq pc, lr @ No fixups needed + tst overdone, ip, ror #3 + addne dividend, dividend, divisor, lsr #3 + tst overdone, ip, ror #2 + addne dividend, dividend, divisor, lsr #2 + tst overdone, ip, ror #1 + addne dividend, dividend, divisor, lsr #1 + mov pc, lr +Ldiv0: + str lr, [sp, #-4]! + bl __div0 (PLT) + mov r0, #0 @ about as wrong as it could be + ldmia sp!, {pc} + .size __umodsi3 , . - __umodsi3 +/* # 320 "libgcc1.S" */ +/* # 421 "libgcc1.S" */ +/* # 433 "libgcc1.S" */ +/* # 456 "libgcc1.S" */ +/* # 500 "libgcc1.S" */ +/* # 580 "libgcc1.S" */ diff --git a/uart-loader/lib/board.c b/uart-loader/lib/board.c new file mode 100644 index 0000000..535f7eb --- /dev/null +++ b/uart-loader/lib/board.c @@ -0,0 +1,242 @@ +/* + * Copyright (C) 2005 Texas Instruments. + * + * (C) Copyright 2004 + * Jian Zhang, Texas Instruments, jzhang@ti.com. + * + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CFG_PRINTF +int print_info(void) +{ + printf ("\n\nTexas Instruments X-Loader 1.41 (" + __DATE__ " - " __TIME__ ")\n"); + return 0; +} +#endif +typedef int (init_fnc_t) (void); + +init_fnc_t *init_sequence[] = { + cpu_init, /* basic cpu dependent setup */ + board_init, /* basic board dependent setup */ +#ifdef CFG_PRINTF + serial_init, /* serial communications setup */ + print_info, +#endif + nand_init, /* board specific nand init */ + NULL, +}; + +#ifdef CFG_CMD_FAT +extern char * strcpy(char * dest,const char *src); +#else +char * strcpy(char * dest,const char *src) +{ + char *tmp = dest; + + while ((*dest++ = *src++) != '\0') + /* nothing */; + return tmp; +} +#endif + +#ifdef CONFIG_MMC +int mmc_read_bootloader(int dev, int part) +{ + long size; + unsigned long offset = CFG_LOADADDR; + block_dev_desc_t *dev_desc = NULL; + unsigned char ret = 0; + + ret = mmc_init(dev); + if (ret != 0){ + printf("\n MMC init failed \n"); + return -1; + } + + if (part) { /* FAT Read for extenal SD card */ + dev_desc = mmc_get_dev(dev); + size = file_fat_read("u-boot.bin", (unsigned char *)offset, 0); + if (size == -1) + return -1; + } else { /* RAW read for EMMC */ + ret = mmc_read(dev, 0x400, (unsigned char *)offset, 0x60000); + if (ret != 1) + return -1; + } + + return 0; +} +#endif + +extern int do_load_serial_bin(ulong offset, int baudrate); +extern int do_comand_line(void); + +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + +void start_armboot (void) +{ + init_fnc_t **init_fnc_ptr; + int i; + uchar *buf; + char boot_dev_name[8]; + u32 boot_device = 0; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + if ((*init_fnc_ptr)() != 0) { + hang (); + } + } +#ifdef START_LOADB_DOWNLOAD + strcpy(boot_dev_name, "UART"); + do_load_serial_bin (CFG_LOADADDR, 115200); + do_comand_line(); +#else // START_LOADB_DOWNLOAD + /* Read boot device from saved scratch pad */ + boot_device = __raw_readl(0x480029c0) & 0xff; + buf = (uchar*) CFG_LOADADDR; + + switch(boot_device) { + case 0x03: + strcpy(boot_dev_name, "ONENAND"); +#if defined(CFG_ONENAND) + for (i = ONENAND_START_BLOCK; i < ONENAND_END_BLOCK; i++) { + if (!onenand_read_block(buf, i)) + buf += ONENAND_BLOCK_SIZE; + else + goto error; + } +#endif + break; + case 0x02: + default: + strcpy(boot_dev_name, "NAND"); +#if defined(CFG_NAND) + for (i = NAND_UBOOT_START; i < NAND_UBOOT_END; + i+= NAND_BLOCK_SIZE) { + if (!nand_read_block(buf, i)) + buf += NAND_BLOCK_SIZE; /* advance buf ptr */ + } +#endif + break; + case 0x05: + strcpy(boot_dev_name, "EMMC"); +#if defined(CONFIG_MMC) + if (mmc_read_bootloader(1, 0) != 0) + goto error; +#else + goto error; +#endif + break; + case 0x06: + strcpy(boot_dev_name, "MMC/SD1"); +#if defined(CONFIG_MMC) && defined(CFG_CMD_FAT) + if (mmc_read_bootloader(0, 1) != 0) + goto error; +#else + goto error; +#endif + break; + }; +#endif // START_LOADB_DOWNLOAD + /* go run U-Boot and never return */ +// printf("Address of serial_printf = %08x\n", &serial_printf); + printf("Starting OS Bootloader from %s ...\n", boot_dev_name); + ((init_fnc_t *)CFG_LOADADDR)(); + + /* should never come here */ +#if defined(CFG_ONENAND) || defined(CONFIG_MMC) +error: +#endif + printf("Could not load or run bootloader!\n"); + hang(); +} + +#if 0 +#include + + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} +static inline void udelay(unsigned long us) +{ + delay(us * 200); /* approximate */ +} + +#define __raw_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) + +#define MUX_VAL(OFFSET,VALUE)\ +__raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) + +void hang (void) +{ + /* call board specific hang function */ + board_hang(); + + /* if board_hang() returns, hange here */ + printf("X-Loader hangs\n"); + + for(;;) { + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | EN | M4)) /*GPT_PWM11/GPIO57*/ + udelay(500*1000); + MUX_VAL(CP(GPMC_nCS6), (IEN | PTU | EN | M4)) /*GPT_PWM11/GPIO57*/ + udelay(500*1000); + } +} + +#else + +void hang (void) +{ + /* call board specific hang function */ + board_hang(); + + /* if board_hang() returns, hange here */ + printf("X-Loader hangs\n"); + + for(;;) + ; +} + +#endif diff --git a/uart-loader/lib/div0.c b/uart-loader/lib/div0.c new file mode 100644 index 0000000..6267bf1 --- /dev/null +++ b/uart-loader/lib/div0.c @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Replacement (=dummy) for GNU/Linux division-by zero handler */ +void __div0 (void) +{ + extern void hang (void); + + hang(); +} diff --git a/uart-loader/lib/ecc_256.c b/uart-loader/lib/ecc_256.c new file mode 100644 index 0000000..92c310f --- /dev/null +++ b/uart-loader/lib/ecc_256.c @@ -0,0 +1,329 @@ +/* + * (C) Copyright 2000 Texas Instruments + * + * This file os based on the following u-boot file: + * common/cmd_nand.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifndef CFG_SW_ECC_512 + +/* + * Pre-calculated 256-way 1 byte column parity + */ +static const u_char nand_ecc_precalc_table[] = { + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 +}; + + +#ifdef NAND_LEGACY +/* + * Creates non-inverted ECC code from line parity + */ +static void nand_trans_result(u_char reg2, u_char reg3, + u_char *ecc_code) +{ + u_char a, b, i, tmp1, tmp2; + + /* Initialize variables */ + a = b = 0x80; + tmp1 = tmp2 = 0; + + /* Calculate first ECC byte */ + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + a >>= 1; + } + + /* Calculate second ECC byte */ + b = 0x80; + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + a >>= 1; + } + + /* Store two of the ECC bytes */ + ecc_code[0] = tmp1; + ecc_code[1] = tmp2; +} + +/* + * Calculate 3 byte ECC code for 256 byte block + */ +/* ECC Calculation is different between NAND and NAND Legacy code + * in U-Boot. If NAND_LEGACY is enabled in u-boot it should be + * enabled in the config file in x-loader also + */ +void nand_calculate_ecc (const u_char *dat, u_char *ecc_code) +{ + u_char idx, reg1, reg3; + int j; + + /* Initialize variables */ + reg1 = reg3 = 0; + ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; + + /* Build up column parity */ + for(j = 0; j < 256; j++) { + + /* Get CP0 - CP5 from table */ + idx = nand_ecc_precalc_table[dat[j]]; + reg1 ^= idx; + + /* All bit XOR = 1 ? */ + if (idx & 0x40) { + reg3 ^= (u_char) j; + + } + } + + /* Create non-inverted ECC code from line parity */ + nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code); + + /* Calculate final ECC code */ + ecc_code[0] = ~ecc_code[0]; + ecc_code[1] = ~ecc_code[1]; + ecc_code[2] = ((~reg1) << 2) | 0x03; +} + +/* + * Detect and correct a 1 bit error for 256 byte block + */ +int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + u_char a, b, c, d1, d2, d3, add, bit, i; + + /* Do error detection */ + d1 = calc_ecc[0] ^ read_ecc[0]; + d2 = calc_ecc[1] ^ read_ecc[1]; + d3 = calc_ecc[2] ^ read_ecc[2]; + + if ((d1 | d2 | d3) == 0) { + /* No errors */ + return 0; + } + else { + a = (d1 ^ (d1 >> 1)) & 0x55; + b = (d2 ^ (d2 >> 1)) & 0x55; + c = (d3 ^ (d3 >> 1)) & 0x54; + + /* Found and will correct single bit error in the data */ + if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { + c = 0x80; + add = 0; + a = 0x80; + for (i=0; i<4; i++) { + if (d1 & c) + add |= a; + c >>= 2; + a >>= 1; + } + c = 0x80; + for (i=0; i<4; i++) { + if (d2 & c) + add |= a; + c >>= 2; + a >>= 1; + } + bit = 0; + b = 0x04; + c = 0x80; + for (i=0; i<3; i++) { + if (d3 & c) + bit |= b; + c >>= 2; + b >>= 1; + } + b = 0x01; + a = dat[add]; + a ^= (b << bit); + dat[add] = a; + return 1; + } + else { + i = 0; + while (d1) { + if (d1 & 0x01) + ++i; + d1 >>= 1; + } + while (d2) { + if (d2 & 0x01) + ++i; + d2 >>= 1; + } + while (d3) { + if (d3 & 0x01) + ++i; + d3 >>= 1; + } + if (i == 1) { + /* ECC Code Error Correction */ + read_ecc[0] = calc_ecc[0]; + read_ecc[1] = calc_ecc[1]; + read_ecc[2] = calc_ecc[2]; + return 2; + } + else { + /* Uncorrectable Error */ + return -1; + } + } + } + + /* Should never happen */ + return -1; +} +#else /* not NAND_LEGACY */ +void nand_calculate_ecc(const u_char *dat, u_char *ecc_code) +{ + uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; + int i; + + /* Initialize variables */ + reg1 = reg2 = reg3 = 0; + + /* Build up column parity */ + for(i = 0; i < 256; i++) { + /* Get CP0 - CP5 from table */ + idx = nand_ecc_precalc_table[*dat++]; + reg1 ^= (idx & 0x3f); + + /* All bit XOR = 1 ? */ + if (idx & 0x40) { + reg3 ^= (uint8_t) i; + reg2 ^= ~((uint8_t) i); + } + } + + /* Create non-inverted ECC code from line parity */ + tmp1 = (reg3 & 0x80) >> 0; /* B7 -> B7 */ + tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */ + tmp1 |= (reg3 & 0x40) >> 1; /* B6 -> B5 */ + tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */ + tmp1 |= (reg3 & 0x20) >> 2; /* B5 -> B3 */ + tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */ + tmp1 |= (reg3 & 0x10) >> 3; /* B4 -> B1 */ + tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */ + + tmp2 = (reg3 & 0x08) << 4; /* B3 -> B7 */ + tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */ + tmp2 |= (reg3 & 0x04) << 3; /* B2 -> B5 */ + tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */ + tmp2 |= (reg3 & 0x02) << 2; /* B1 -> B3 */ + tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */ + tmp2 |= (reg3 & 0x01) << 1; /* B0 -> B1 */ + tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */ + + /* Calculate final ECC code */ + ecc_code[0] = ~tmp1; + ecc_code[1] = ~tmp2; + ecc_code[2] = ((~reg1) << 2) | 0x03; +} + +static inline int countbits(uint32_t byte) +{ + int res = 0; + + for (;byte; byte >>= 1) + res += byte & 0x01; + return res; +} + +/* + * nand_correct_data - [NAND Interface] Detect and correct bit error(s) + * @mtd: MTD block structure + * @dat: raw data read from the chip + * @read_ecc: ECC from the chip + * @calc_ecc: the ECC calculated from raw data + * + * Detect and correct a 1 bit error for 256 byte block + */ +int nand_correct_data(u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + uint8_t s0, s1, s2; + + s0 = calc_ecc[0] ^ read_ecc[0]; + s1 = calc_ecc[1] ^ read_ecc[1]; + s2 = calc_ecc[2] ^ read_ecc[2]; + + if ((s0 | s1 | s2) == 0) + return 0; + +/* Check for a single bit error */ + if( ((s0 ^ (s0 >> 1)) & 0x55) == 0x55 && + ((s1 ^ (s1 >> 1)) & 0x55) == 0x55 && + ((s2 ^ (s2 >> 1)) & 0x54) == 0x54) { + + uint32_t byteoffs, bitnum; + + byteoffs = (s1 << 0) & 0x80; + byteoffs |= (s1 << 1) & 0x40; + byteoffs |= (s1 << 2) & 0x20; + byteoffs |= (s1 << 3) & 0x10; + + byteoffs |= (s0 >> 4) & 0x08; + byteoffs |= (s0 >> 3) & 0x04; + byteoffs |= (s0 >> 2) & 0x02; + byteoffs |= (s0 >> 1) & 0x01; + + bitnum = (s2 >> 5) & 0x04; + bitnum |= (s2 >> 4) & 0x02; + bitnum |= (s2 >> 3) & 0x01; + + dat[byteoffs] ^= (1 << bitnum); + + return 1; + } + + if(countbits(s0 | ((uint32_t)s1 << 8) | ((uint32_t)s2 <<16)) == 1) + return 1; + + return -1; +} +#endif /* NAND_LEGACY */ +#endif /* ! CFG_SW_ECC_512 */ diff --git a/uart-loader/lib/ecc_512.c b/uart-loader/lib/ecc_512.c new file mode 100644 index 0000000..29647c6 --- /dev/null +++ b/uart-loader/lib/ecc_512.c @@ -0,0 +1,420 @@ +/* + * (C) Copyright 2000 Texas Instruments + * + * This file os based on the following u-boot file: + * common/cmd_nand.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifdef CFG_SW_ECC_512 + +/* + * invparity is a 256 byte table that contains the odd parity + * for each byte. So if the number of bits in a byte is even, + * the array element is 1, and when the number of bits is odd + * the array eleemnt is 0. + */ +static const char invparity[256] = { + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1 +}; + +/* + * bitsperbyte contains the number of bits per byte + * this is only used for testing and repairing parity + * (a precalculated value slightly improves performance) + */ +static const char bitsperbyte[256] = { + 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, +}; + +/* + * addressbits is a lookup table to filter out the bits from the xor-ed + * ecc data that identify the faulty location. + * this is only used for repairing parity + * see the comments in nand_correct_data for more details + */ +static const char addressbits[256] = { + 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, + 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, + 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, + 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, + 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, + 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, + 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, + 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, + 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, + 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, + 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, + 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, + 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, + 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, + 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, + 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f, + 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, + 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, + 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, + 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f +}; + +/* + * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256/512-byte + * block + * @mtd: MTD block structure + * @buf: input buffer with raw data + * @code: output buffer with ECC + */ +void nand_calculate_ecc(const u_char *buf, u_char *code) +{ + int i; + const uint32_t *bp = (uint32_t *)buf; + /* 256 or 512 bytes/ecc */ + int eccsize = 512; + const uint32_t eccsize_mult = eccsize >> 8; + uint32_t cur; /* current value in buffer */ + /* rp0..rp15..rp17 are the various accumulated parities (per byte) */ + uint32_t rp0, rp1, rp2, rp3, rp4, rp5, rp6, rp7; + uint32_t rp8, rp9, rp10, rp11, rp12, rp13, rp14, rp15, rp16; + uint32_t rp17 = 0; + uint32_t par; /* the cumulative parity for all data */ + uint32_t tmppar; /* the cumulative parity for this iteration; + for rp12, rp14 and rp16 at the end of the + loop */ + par = 0; + rp4 = 0; + rp6 = 0; + rp8 = 0; + rp10 = 0; + rp12 = 0; + rp14 = 0; + rp16 = 0; + + /* + * The loop is unrolled a number of times; + * This avoids if statements to decide on which rp value to update + * Also we process the data by longwords. + * Note: passing unaligned data might give a performance penalty. + * It is assumed that the buffers are aligned. + * tmppar is the cumulative sum of this iteration. + * needed for calculating rp12, rp14, rp16 and par + * also used as a performance improvement for rp6, rp8 and rp10 + */ + for (i = 0; i < eccsize_mult << 2; i++) { + cur = *bp++; + tmppar = cur; + rp4 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp6 ^= tmppar; + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp8 ^= tmppar; + + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + rp6 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp6 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp10 ^= tmppar; + + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + rp6 ^= cur; + rp8 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp6 ^= cur; + rp8 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + rp8 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp8 ^= cur; + + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + rp6 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp6 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + cur = *bp++; + tmppar ^= cur; + + par ^= tmppar; + if ((i & 0x1) == 0) + rp12 ^= tmppar; + if ((i & 0x2) == 0) + rp14 ^= tmppar; + if (eccsize_mult == 2 && (i & 0x4) == 0) + rp16 ^= tmppar; + } + + /* + * handle the fact that we use longword operations + * we'll bring rp4..rp14..rp16 back to single byte entities by + * shifting and xoring first fold the upper and lower 16 bits, + * then the upper and lower 8 bits. + */ + rp4 ^= (rp4 >> 16); + rp4 ^= (rp4 >> 8); + rp4 &= 0xff; + rp6 ^= (rp6 >> 16); + rp6 ^= (rp6 >> 8); + rp6 &= 0xff; + rp8 ^= (rp8 >> 16); + rp8 ^= (rp8 >> 8); + rp8 &= 0xff; + rp10 ^= (rp10 >> 16); + rp10 ^= (rp10 >> 8); + rp10 &= 0xff; + rp12 ^= (rp12 >> 16); + rp12 ^= (rp12 >> 8); + rp12 &= 0xff; + rp14 ^= (rp14 >> 16); + rp14 ^= (rp14 >> 8); + rp14 &= 0xff; + if (eccsize_mult == 2) { + rp16 ^= (rp16 >> 16); + rp16 ^= (rp16 >> 8); + rp16 &= 0xff; + } + + /* + * we also need to calculate the row parity for rp0..rp3 + * This is present in par, because par is now + * rp3 rp3 rp2 rp2 in little endian and + * rp2 rp2 rp3 rp3 in big endian + * as well as + * rp1 rp0 rp1 rp0 in little endian and + * rp0 rp1 rp0 rp1 in big endian + * First calculate rp2 and rp3 + */ + rp3 = (par >> 16); + rp3 ^= (rp3 >> 8); + rp3 &= 0xff; + rp2 = par & 0xffff; + rp2 ^= (rp2 >> 8); + rp2 &= 0xff; + + /* reduce par to 16 bits then calculate rp1 and rp0 */ + par ^= (par >> 16); + rp1 = (par >> 8) & 0xff; + rp0 = (par & 0xff); + + /* finally reduce par to 8 bits */ + par ^= (par >> 8); + par &= 0xff; + + /* + * and calculate rp5..rp15..rp17 + * note that par = rp4 ^ rp5 and due to the commutative property + * of the ^ operator we can say: + * rp5 = (par ^ rp4); + * The & 0xff seems superfluous, but benchmarking learned that + * leaving it out gives slightly worse results. No idea why, probably + * it has to do with the way the pipeline in pentium is organized. + */ + rp5 = (par ^ rp4) & 0xff; + rp7 = (par ^ rp6) & 0xff; + rp9 = (par ^ rp8) & 0xff; + rp11 = (par ^ rp10) & 0xff; + rp13 = (par ^ rp12) & 0xff; + rp15 = (par ^ rp14) & 0xff; + if (eccsize_mult == 2) + rp17 = (par ^ rp16) & 0xff; + + /* + * Finally calculate the ecc bits. + * Again here it might seem that there are performance optimisations + * possible, but benchmarks showed that on the system this is developed + * the code below is the fastest + */ + code[1] = + (invparity[rp7] << 7) | + (invparity[rp6] << 6) | + (invparity[rp5] << 5) | + (invparity[rp4] << 4) | + (invparity[rp3] << 3) | + (invparity[rp2] << 2) | + (invparity[rp1] << 1) | + (invparity[rp0]); + code[0] = + (invparity[rp15] << 7) | + (invparity[rp14] << 6) | + (invparity[rp13] << 5) | + (invparity[rp12] << 4) | + (invparity[rp11] << 3) | + (invparity[rp10] << 2) | + (invparity[rp9] << 1) | + (invparity[rp8]); + if (eccsize_mult == 1) + code[2] = + (invparity[par & 0xf0] << 7) | + (invparity[par & 0x0f] << 6) | + (invparity[par & 0xcc] << 5) | + (invparity[par & 0x33] << 4) | + (invparity[par & 0xaa] << 3) | + (invparity[par & 0x55] << 2) | + 3; + else + code[2] = + (invparity[par & 0xf0] << 7) | + (invparity[par & 0x0f] << 6) | + (invparity[par & 0xcc] << 5) | + (invparity[par & 0x33] << 4) | + (invparity[par & 0xaa] << 3) | + (invparity[par & 0x55] << 2) | + (invparity[rp17] << 1) | + (invparity[rp16] << 0); +} + +/** + * nand_correct_data - [NAND Interface] Detect and correct bit error(s) + * @mtd: MTD block structure + * @buf: raw data read from the chip + * @read_ecc: ECC from the chip + * @calc_ecc: the ECC calculated from raw data + * + * Detect and correct a 1 bit error for 256/512 byte block + */ +int nand_correct_data(unsigned char *buf, + unsigned char *read_ecc, unsigned char *calc_ecc) +{ + unsigned char b0, b1, b2; + uint32_t byte_addr; + unsigned char bit_addr; + /* 256 or 512 bytes/ecc */ + int eccsize = 512; + const uint32_t eccsize_mult = eccsize >> 8; + /* + * b0 to b2 indicate which bit is faulty (if any) + * we might need the xor result more than once, + * so keep them in a local var + */ + b0 = read_ecc[1] ^ calc_ecc[1]; + b1 = read_ecc[0] ^ calc_ecc[0]; + b2 = read_ecc[2] ^ calc_ecc[2]; + + /* check if there are any bitfaults */ + + /* repeated if statements are slightly more efficient than switch ... */ + /* ordered in order of likelihood */ + + if ((b0 | b1 | b2) == 0) + return 0; /* no error */ + + if ((((b0 ^ (b0 >> 1)) & 0x55) == 0x55) && + (((b1 ^ (b1 >> 1)) & 0x55) == 0x55) && + ((eccsize_mult == 1 && ((b2 ^ (b2 >> 1)) & 0x54) == 0x54) || + (eccsize_mult == 2 && ((b2 ^ (b2 >> 1)) & 0x55) == 0x55))) { + /* single bit error */ + /* + * rp17/rp15/13/11/9/7/5/3/1 indicate which byte is the faulty + * byte, cp 5/3/1 indicate the faulty bit. + * A lookup table (called addressbits) is used to filter + * the bits from the byte they are in. + * A marginal optimisation is possible by having three + * different lookup tables. + * One as we have now (for b0), one for b2 + * (that would avoid the >> 1), and one for b1 (with all values + * << 4). However it was felt that introducing two more tables + * hardly justify the gain. + * + * The b2 shift is there to get rid of the lowest two bits. + * We could also do addressbits[b2] >> 1 but for the + * performace it does not make any difference + */ + if (eccsize_mult == 1) + byte_addr = (addressbits[b1] << 4) + addressbits[b0]; + else + byte_addr = (addressbits[b2 & 0x3] << 8) + + (addressbits[b1] << 4) + addressbits[b0]; + bit_addr = addressbits[b2 >> 2]; + /* flip the bit */ + buf[byte_addr] ^= (1 << bit_addr); + return 1; + + } + /* count nr of bits; use table lookup, faster than calculating it */ + if ((bitsperbyte[b0] + bitsperbyte[b1] + bitsperbyte[b2]) == 1) + return 1; /* error in ecc data; no action needed */ + + return -1; +} +#endif /* CFG_SW_ECC_512 */ diff --git a/uart-loader/lib/printf.c b/uart-loader/lib/printf.c new file mode 100644 index 0000000..91d22fc --- /dev/null +++ b/uart-loader/lib/printf.c @@ -0,0 +1,304 @@ +/* + * (C) Copyright 2004 Texas Instruments + * + * Based on the following file: + * linux/lib/vsprintf.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */ +/* + * Wirzenius wrote this portably, Torvalds fucked it up :-) + */ + +#include +#include + +#ifdef CFG_PRINTF + +/* we use this so that we can do without the ctype library */ +#define is_digit(c) ((c) >= '0' && (c) <= '9') + +size_t strnlen(const char * s, size_t count) +{ + const char *sc; + + for (sc = s; count-- && *sc != '\0'; ++sc) + /* nothing */; + return sc - s; +} + +static int skip_atoi(const char **s) +{ + int i=0; + + while (is_digit(**s)) + i = i*10 + *((*s)++) - '0'; + return i; +} + +#define ZEROPAD 1 /* pad with zero */ +#define SIGN 2 /* unsigned/signed long */ +#define PLUS 4 /* show plus */ +#define SPACE 8 /* space if plus */ +#define LEFT 16 /* left justified */ +#define SPECIAL 32 /* 0x */ +#define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ + +#define do_div(n,base) ({ \ +int __res; \ +__res = ((unsigned long) n) % (unsigned) base; \ +n = ((unsigned long) n) / (unsigned) base; \ +__res; }) + +static char * number(char * str, long num, int base, int size, int precision + ,int type) +{ + char c,sign,tmp[66]; + const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; + int i; + + if (type & LARGE) + digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; + if (type & LEFT) + type &= ~ZEROPAD; + if (base < 2 || base > 36) + return 0; + c = (type & ZEROPAD) ? '0' : ' '; + sign = 0; + if (type & SIGN) { + if (num < 0) { + sign = '-'; + num = -num; + size--; + } else if (type & PLUS) { + sign = '+'; + size--; + } else if (type & SPACE) { + sign = ' '; + size--; + } + } + if (type & SPECIAL) { + if (base == 16) + size -= 2; + else if (base == 8) + size--; + } + i = 0; + if (num == 0) + tmp[i++]='0'; + else while (num != 0) + tmp[i++] = digits[do_div(num,base)]; + if (i > precision) + precision = i; + size -= precision; + if (!(type&(ZEROPAD+LEFT))) + while(size-->0) + *str++ = ' '; + if (sign) + *str++ = sign; + if (type & SPECIAL) { + if (base==8) + *str++ = '0'; + else if (base==16) { + *str++ = '0'; + *str++ = digits[33]; + } + } + if (!(type & LEFT)) + while (size-- > 0) + *str++ = c; + while (i < precision--) + *str++ = '0'; + while (i-- > 0) + *str++ = tmp[i]; + while (size-- > 0) + *str++ = ' '; + return str; +} + + +static int vsprintf(char *buf, const char *fmt, va_list args) +{ + int len; + unsigned long num; + int i, base; + char * str; + const char *s; + + int flags; /* flags to number() */ + + int field_width; /* width of output field */ + int precision; /* min. # of digits for integers; max + number of chars for from string */ + int qualifier; /* 'h', 'l', or 'L' for integer fields */ + + for (str=buf ; *fmt ; ++fmt) { + if (*fmt != '%') { + *str++ = *fmt; + continue; + } + + /* process flags */ + flags = 0; + repeat: + ++fmt; /* this also skips first '%' */ + switch (*fmt) { + case '-': flags |= LEFT; goto repeat; + case '+': flags |= PLUS; goto repeat; + case ' ': flags |= SPACE; goto repeat; + case '#': flags |= SPECIAL; goto repeat; + case '0': flags |= ZEROPAD; goto repeat; + } + + /* get field width */ + field_width = -1; + if (is_digit(*fmt)) + field_width = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + field_width = va_arg(args, int); + if (field_width < 0) { + field_width = -field_width; + flags |= LEFT; + } + } + + /* get the precision */ + precision = -1; + if (*fmt == '.') { + ++fmt; + if (is_digit(*fmt)) + precision = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + precision = va_arg(args, int); + } + if (precision < 0) + precision = 0; + } + + /* get the conversion qualifier */ + qualifier = -1; + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') { + qualifier = *fmt; + ++fmt; + } + + /* default base */ + base = 10; + + switch (*fmt) { + case 'c': + if (!(flags & LEFT)) + while (--field_width > 0) + *str++ = ' '; + *str++ = (unsigned char) va_arg(args, int); + while (--field_width > 0) + *str++ = ' '; + continue; + + case 's': + s = va_arg(args, char *); + if (!s) + s = ""; + + len = strnlen(s, precision); + + if (!(flags & LEFT)) + while (len < field_width--) + *str++ = ' '; + for (i = 0; i < len; ++i) + *str++ = *s++; + while (len < field_width--) + *str++ = ' '; + continue; + + case 'p': + if (field_width == -1) { + field_width = 2*sizeof(void *); + flags |= ZEROPAD; + } + str = number(str, + (unsigned long) va_arg(args, void *), 16, + field_width, precision, flags); + continue; + + + case 'n': + if (qualifier == 'l') { + long * ip = va_arg(args, long *); + *ip = (str - buf); + } else { + int * ip = va_arg(args, int *); + *ip = (str - buf); + } + continue; + + case '%': + *str++ = '%'; + continue; + + /* integer number formats - set up the flags and "break" */ + case 'o': + base = 8; + break; + + case 'X': + flags |= LARGE; + case 'x': + base = 16; + break; + + case 'd': + case 'i': + flags |= SIGN; + case 'u': + break; + + default: + *str++ = '%'; + if (*fmt) + *str++ = *fmt; + else + --fmt; + continue; + } + if (qualifier == 'l') + num = va_arg(args, unsigned long); + else if (qualifier == 'h') { + num = (unsigned short) va_arg(args, int); + if (flags & SIGN) + num = (short) num; + } else if (flags & SIGN) + num = va_arg(args, int); + else + num = va_arg(args, unsigned int); + str = number(str, num, base, field_width, precision, flags); + } + *str = '\0'; + return str-buf; +} + +void serial_printf (const char *fmt, ...) +{ + va_list args; + uint i; + char printbuffer[CFG_PBSIZE]; + + va_start (args, fmt); + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + i = vsprintf (printbuffer, fmt, args); + va_end (args); + + /* Print the string */ + serial_puts (printbuffer); +} +#endif diff --git a/uart-loader/mkconfig b/uart-loader/mkconfig new file mode 100755 index 0000000..43b6f09 --- /dev/null +++ b/uart-loader/mkconfig @@ -0,0 +1,61 @@ +#!/bin/sh -e + +# Script to create header files and links to configure +# X-Loader for a specific board. +# +# Parameters: Target Architecture CPU Board +# +# (C) 2004 Texas Instruments +# (C) 2002 DENX Software Engineering, Wolfgang Denk +# + +APPEND=no # Default: Create new config file + +while [ $# -gt 0 ] ; do + case "$1" in + --) shift ; break ;; + -a) shift ; APPEND=yes ;; + *) break ;; + esac +done + +[ $# -lt 4 ] && exit 1 +[ $# -gt 5 ] && exit 1 + +echo "Configuring for $1 board..." + +cd ./include + +# +# Create link to architecture specific headers +# +rm -f asm/arch +ln -s arch-$3 asm/arch + +if [ "$2" = "arm" ] ; then + rm -f asm/proc + ln -s proc-armv asm/proc +fi + +# +# Create include file for Make +# +echo "ARCH = $2" > config.mk +echo "CPU = $3" >> config.mk +echo "BOARD = $4" >> config.mk + +[ "$5" ] && echo "VENDOR = $5" >> config.mk + +# +# Create board specific header file +# +if [ "$APPEND" = "yes" ] # Append to existing config file +then + echo >> config.h +else + > config.h # Create new config file +fi +echo "/* Automatically generated - do not edit */" >>config.h +echo "#include " >>config.h + +exit 0 diff --git a/uart-loader/scripts/mkoneboot.sh b/uart-loader/scripts/mkoneboot.sh new file mode 100644 index 0000000..f0862a5 --- /dev/null +++ b/uart-loader/scripts/mkoneboot.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +IMAGE1=x-load.bin.ift +IMAGE2=x-load-signed.ift +TMP=oneloader +PAGESIZE=2048 + +size=`ls -la $IMAGE1 | awk -F' ' '{ printf $5}'` +let remain=$PAGESIZE-$size +dd if=/dev/zero of=$IMAGE2 bs=1 count=512 +#dd if=/dev/zero of=zerofile bs=$remain count=1 > /dev/null 2> /dev/null +cat $IMAGE1>>$IMAGE2 + +rm -f $IMAGE1 + +echo "Create $IMAGE2 completed..." diff --git a/uart-loader/scripts/signGP.c b/uart-loader/scripts/signGP.c new file mode 100644 index 0000000..0e8ed07 --- /dev/null +++ b/uart-loader/scripts/signGP.c @@ -0,0 +1,73 @@ +// +// signGP.c +// Read the x-load.bin file and write out the x-load.bin.ift file. +// The signed image is the original pre-pended with the size of the image +// and the load address. If not entered on command line, file name is +// assumed to be x-load.bin in current directory and load address is +// 0x40200800. + +#include +#include +#include +#include +#include +#include + + +main(int argc, char *argv[]) +{ + int i; + char ifname[FILENAME_MAX], ofname[FILENAME_MAX], ch; + FILE *ifile, *ofile; + unsigned long loadaddr, len; + struct stat sinfo; + + + // Default to x-load.bin and 0x40200800. + strcpy(ifname, "x-load.bin"); + loadaddr = 0x40200800; + + if ((argc == 2) || (argc == 3)) + strcpy(ifname, argv[1]); + + if (argc == 3) + loadaddr = strtol(argv[2], NULL, 16); + + // Form the output file name. + strcpy(ofname, ifname); + strcat(ofname, ".ift"); + + // Open the input file. + ifile = fopen(ifname, "rb"); + if (ifile == NULL) { + printf("Cannot open %s\n", ifname); + exit(0); + } + + // Get file length. + stat(ifname, &sinfo); + len = sinfo.st_size; + + // Open the output file and write it. + ofile = fopen(ofname, "wb"); + if (ofile == NULL) { + printf("Cannot open %s\n", ofname); + fclose(ifile); + exit(0); + } + + // Pad 1 sector of zeroes. + //ch = 0x00; + //for (i=0; i<0x200; i++) + // fwrite(&ch, 1, 1, ofile); + + fwrite(&len, 1, 4, ofile); + fwrite(&loadaddr, 1, 4, ofile); + for (i=0; i