From e1bbb64ec2ca8ddf1dec91ae1e08ef96ee53639a Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Tue, 11 Jan 2011 17:31:17 +0100 Subject: fixed issue with submodules --- x-loader | 1 - x-loader/include/asm/arch-arm1136/clocks242x.h | 147 +++++++++++++++++++++++++ 2 files changed, 147 insertions(+), 1 deletion(-) delete mode 160000 x-loader create mode 100644 x-loader/include/asm/arch-arm1136/clocks242x.h (limited to 'x-loader/include/asm/arch-arm1136/clocks242x.h') diff --git a/x-loader b/x-loader deleted file mode 160000 index 1c9276a..0000000 --- a/x-loader +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 1c9276af4d6a5b7014a7630a1abeddf3b3177563 diff --git a/x-loader/include/asm/arch-arm1136/clocks242x.h b/x-loader/include/asm/arch-arm1136/clocks242x.h new file mode 100644 index 0000000..0ae1c4e --- /dev/null +++ b/x-loader/include/asm/arch-arm1136/clocks242x.h @@ -0,0 +1,147 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP242X_CLOCKS_H_ +#define _OMAP242X_CLOCKS_H_ + +/****************************************************************************; +; PRCM Scheme I +; +; Enable clocks and DPLL for: +; DPLL=330, DPLLout=660 M=1,N=55 CM_CLKSEL1_PLL[21:8] 12/2*55 +; Core=660 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=330 (mpu domain) 2 CM_CLKSEL_MPU[4:0] +; DSPF=220 (dsp domain) 3 CM_CLKSEL_DSP[4:0] +; DSPI=110 6 CM_CLKSEL_DSP[6:5] +; DSP_S activated CM_CLKSEL_DSP[7] +; IVAF=165 (dsp domain) 4 CM_CLKSEL_DSP[12:8] +; IVAF=82.5 auto +; IVAI auto +; IVA_MPU auto +; IVA_S bypass CM_CLKSEL_DSP[13] +; GFXF=82.5 (gfx domain) 8 CM_CLKSEL_FGX[2:0] +; SSI_SSRF=220 3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=110 auto +; L3=165Mhz (sdram) 4 CM_CLKSEL1_CORE[4:0] +; L4=82.5Mhz 8 +; C_L4_USB=41.25 16 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define I_DPLL_OUT_X2 0x2 /* x2 core out */ +#define I_MPU_DIV 0x2 /* mpu = core/2 */ +#define I_DSP_DIV 0x3c3 /* dsp & iva divider */ +#define I_GFX_DIV 0x2 +#define I_BUS_DIV 0x04601044 +#ifdef INPUT_CLK_13MHZ +#define I_DPLL_330 0x0114AC00 /* 13MHz */ +#else +#define I_DPLL_330 0x01837100 /* 12MHz */ +#endif + +/****************************************************************************; +; PRCM Scheme II +; +; Enable clocks and DPLL for: +; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 +; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] +; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] +; DSPI=100 6 CM_CLKSEL_DSP[6:5] +; DSP_S bypass CM_CLKSEL_DSP[7] +; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8] +; IVAF=100 auto +; IVAI auto +; IVA_MPU auto +; IVA_S bypass CM_CLKSEL_DSP[13] +; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0] +; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=100 auto +; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0] +; L4=100Mhz 6 +; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define II_DPLL_OUT_X2 0x2 /* x2 core out */ +#define II_MPU_DIV 0x2 /* mpu = core/2 */ +#define II_DSP_DIV 0x343 /* dsp & iva divider */ +#define II_GFX_DIV 0x2 +#define II_BUS_DIV 0x04601026 +#ifdef INPUT_CLK_13MHZ +#define II_DPLL_300 0x0112CC00 /* 13MHz */ +#else +#define II_DPLL_300 0x01832100 /* 12MHz */ +#endif + +/****************************************************************************; +; PRCM Scheme III +; +; Enable clocks and DPLL for: +; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 +; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] +; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] +; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] +; DSP_S ACTIVATED CM_CLKSEL_DSP[7] +; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8] +; IVAF=88.67 auto +; IVAI auto +; IVA_MPU auto +; IVA_S ACTIVATED CM_CLKSEL_DSP[13] +; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]: +; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=88.67 auto +; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0] +; L4=66.5Mhz /8 +; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define III_DPLL_OUT_X2 0x2 /* x2 core out */ +#define III_MPU_DIV 0x2 /* mpu = core/2 */ +#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ +#define III_GFX_DIV 0x2 +#define III_BUS_DIV 0x08301044 +#ifdef INPUT_CLK_13MHZ +#define III_DPLL_266 0x0110AC00 /* 13MHz */ +#else +#define III_DPLL_266 0x01885500 /* 12MHz */ +#endif + +/* set defaults for boot up */ +#ifdef PRCM_CONFIG_I +# define DPLL_OUT I_DPLL_OUT_X2 +# define MPU_DIV I_MPU_DIV +# define DSP_DIV I_DSP_DIV +# define GFX_DIV I_GFX_DIV +# define BUS_DIV I_BUS_DIV +# define DPLL_VAL I_DPLL_266 +#elif PRCM_CONFIG_II +# define DPLL_OUT II_DPLL_OUT_X2 +# define MPU_DIV II_MPU_DIV +# define DSP_DIV II_DSP_DIV +# define GFX_DIV II_GFX_DIV +# define BUS_DIV II_BUS_DIV +# define DPLL_VAL II_DPLL_300 +#elif PRCM_CONFIG_III +# define DPLL_OUT III_DPLL_OUT_X2 +# define MPU_DIV III_MPU_DIV +# define DSP_DIV III_DSP_DIV +# define GFX_DIV III_GFX_DIV +# define BUS_DIV III_BUS_DIV +# define DPLL_VAL III_DPLL_266 +#endif + +#endif -- cgit v1.1