summaryrefslogtreecommitdiffstats
path: root/audio/audio_hw.h
blob: f8445553e0742e6dcf24bf237bfc8eef73cd105b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
/*
 * Copyright (C) 2011 The Android Open Source Project
 * Copyright (C) 2012 Wolfson Microelectronics plc
 * Copyright (C) 2012 The CyanogenMod Project
 *               Daniel Hillenbrand <codeworkx@cyanogenmod.com>
 *               Guillaume "XpLoDWilD" Lesniak <xplodgui@gmail.com>
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

/* ALSA cards for WM1811 */
#define CARD_DEFAULT  0

#define PORT_PLAYBACK 0
#define PORT_CAPTURE  0
#define PORT_MODEM    1
#define PORT_BT       2

#define PCM_WRITE pcm_write

#define PLAYBACK_PERIOD_SIZE  880
#define PLAYBACK_PERIOD_COUNT 8
#define PLAYBACK_SHORT_PERIOD_COUNT 2

#define CAPTURE_PERIOD_SIZE   1056
#define CAPTURE_PERIOD_COUNT  2

#define SHORT_PERIOD_SIZE 192

//
// deep buffer
//
/* screen on */
#define DEEP_BUFFER_SHORT_PERIOD_SIZE 1056
#define PLAYBACK_DEEP_BUFFER_SHORT_PERIOD_COUNT 4
/* screen off */
#define DEEP_BUFFER_LONG_PERIOD_SIZE 880
#define PLAYBACK_DEEP_BUFFER_LONG_PERIOD_COUNT 8


/* minimum sleep time in out_write() when write threshold is not reached */
#define MIN_WRITE_SLEEP_US 5000

#define RESAMPLER_BUFFER_FRAMES (PLAYBACK_PERIOD_SIZE * 2)
#define RESAMPLER_BUFFER_SIZE (4 * RESAMPLER_BUFFER_FRAMES)

#define DEFAULT_OUT_SAMPLING_RATE 44100
#define MM_LOW_POWER_SAMPLING_RATE 44100
#define MM_FULL_POWER_SAMPLING_RATE 44100
#define DEFAULT_IN_SAMPLING_RATE 44100

/* sampling rate when using VX port for narrow band */
#define VX_NB_SAMPLING_RATE 8000
/* sampling rate when using VX port for wide band */
#define VX_WB_SAMPLING_RATE 16000

/* product-specific defines */
#define PRODUCT_DEVICE_PROPERTY "ro.product.device"
#define PRODUCT_NAME_PROPERTY   "ro.product.name"

#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))

#define STRING_TO_ENUM(string) { #string, string }

struct string_to_enum {
    const char *name;
    uint32_t value;
};

const struct string_to_enum out_channels_name_to_enum_table[] = {
    STRING_TO_ENUM(AUDIO_CHANNEL_OUT_STEREO),
    STRING_TO_ENUM(AUDIO_CHANNEL_OUT_5POINT1),
    STRING_TO_ENUM(AUDIO_CHANNEL_OUT_7POINT1),
};

enum pcm_type {
    PCM_NORMAL = 0,
    PCM_SPDIF,
    PCM_HDMI,
    PCM_TOTAL,
};

enum output_type {
    OUTPUT_DEEP_BUF,      // deep PCM buffers output stream
    OUTPUT_LOW_LATENCY,   // low latency output stream
    OUTPUT_HDMI,
    OUTPUT_TOTAL
};

enum tty_modes {
    TTY_MODE_OFF,
    TTY_MODE_VCO,
    TTY_MODE_HCO,
    TTY_MODE_FULL
};

struct route_setting
{
    char *ctl_name;
    int intval;
    char *strval;
};

struct route_setting voicecall_default[] = {
    { .ctl_name = "HP Output Mode", .intval = 0, },
    { .ctl_name = "AIF2 Mode", .intval = 0, },
    { .ctl_name = "AIF2DACL Source", .intval = 0, },
    { .ctl_name = "AIF2DACR Source", .intval = 0, },
    { .ctl_name = "DAC1L Mixer AIF1.1 Switch", .intval = 1, },
    { .ctl_name = "DAC1R Mixer AIF1.1 Switch", .intval = 1, },
    { .ctl_name = "DAC1L Mixer AIF2 Switch", .intval = 1, },
    { .ctl_name = "DAC1R Mixer AIF2 Switch", .intval = 1, },
    { .ctl_name = "AIF2DAC Mux", .strval = "AIF2DACDAT", },
    { .ctl_name = NULL, },
};

struct route_setting voicecall_default_disable[] = {
    { .ctl_name = "AIF2 Mode", .intval = 0, },
    { .ctl_name = "AIF2DACL Source", .intval = 0, },
    { .ctl_name = "AIF2DACR Source", .intval = 1, },
    { .ctl_name = "DAC1L Mixer AIF2 Switch", .intval = 0, },
    { .ctl_name = "DAC1R Mixer AIF2 Switch", .intval = 0, },
    { .ctl_name = "AIF2DAC Mux", .strval = "AIF2DACDAT", },
    { .ctl_name = NULL, },
};

struct route_setting default_input[] = {
    { .ctl_name = "Main Mic Switch", .intval = 1, },
    { .ctl_name = "IN1L Volume", .intval = 30, },
    { .ctl_name = "MIXINL IN1L Switch", .intval = 1, },
    { .ctl_name = "MIXINL IN1L Volume", .intval = 0, },
    { .ctl_name = "DAC2 Volume", .intval = 96, },
    { .ctl_name = "AIF2ADC Volume", .intval = 112, },
    { .ctl_name = "AIF1ADC1 HPF Mode", .intval = 1, },
    { .ctl_name = "AIF1ADC1 HPF Switch", .intval = 1, },
    { .ctl_name = "AIF1ADCL Source", .intval = 0, },
    { .ctl_name = "AIF1ADCR Source", .intval = 0, },
    { .ctl_name = "AIF2ADCL Source", .intval = 0, },
    { .ctl_name = "AIF2ADCR Source", .intval = 0, },
    { .ctl_name = NULL, },
};

struct route_setting default_input_disable[] = {
    { .ctl_name = "Main Mic Switch", .intval = 0, },
    { .ctl_name = "AIF1ADC1 HPF Mode", .intval = 0, },
    { .ctl_name = "AIF1ADC1 HPF Switch", .intval = 0, },
    { .ctl_name = NULL, },
};

struct route_setting headset_input[] = {
    { .ctl_name = "Headset Mic Switch", .intval = 1, },
    { .ctl_name = "IN1R Volume", .intval = 9, },
    { .ctl_name = "MIXINL IN1L Switch", .intval = 0, },
    { .ctl_name = "MIXINL IN1L Volume", .intval = 1, },
    { .ctl_name = "MIXINR IN1R Switch", .intval = 1, },
    { .ctl_name = "MIXINR IN1R Volume", .intval = 1, },
    { .ctl_name = "MIXINR IN1RP Volume", .intval = 1, },
    { .ctl_name = "DAC2 Right Sidetone Volume", .intval = 12, },
    { .ctl_name = "DAC2 Volume", .intval = 96, },
    { .ctl_name = "AIF2ADC Volume", .intval = 96, },
    { .ctl_name = "AIF1ADCL Source", .intval = 1, },
    { .ctl_name = "AIF1ADCR Source", .intval = 1, },
    { .ctl_name = "AIF2ADCL Source", .intval = 1, },
    { .ctl_name = "AIF2ADCR Source", .intval = 1, },
    { .ctl_name = NULL, },
};

struct route_setting bt_output[] = {
    { .ctl_name = "AIF2DAC2L Mixer AIF2 Switch", .intval = 1, },
    { .ctl_name = "AIF2DAC2R Mixer AIF2 Switch", .intval = 1, },
    { .ctl_name = "AIF2DAC Volume", .intval = 96, },
    { .ctl_name = "DAC2 Volume", .intval = 96, },
    { .ctl_name = "AIF2ADC Volume", .intval = 96, },
    { .ctl_name = NULL, },
};

struct route_setting bt_input[] = {
    { .ctl_name = "AIF2ADC Mux", .intval = 1, },
    { .ctl_name = "AIF2DACR Source", .intval = 1, },
    { .ctl_name = "HP Switch", .intval = 0, },
    { .ctl_name = "DAC1L Mixer AIF2 Switch", .intval = 1, },
    { .ctl_name = "DAC1R Mixer AIF2 Switch", .intval = 1, },
    { .ctl_name = "AIF1ADC1R Mixer AIF2 Switch", .intval = 0, },
    { .ctl_name = "AIF1ADC1L Mixer AIF2 Switch", .intval = 0, },
    { .ctl_name = "AIF2DAC2R Mixer Right Sidetone Switch", .intval = 0, },
    { .ctl_name = "AIF2DAC2R Mixer Left Sidetone Switch", .intval = 1, },
    { .ctl_name = "AIF1ADC1R Mixer AIF2 Switch", .intval = 0, },
    { .ctl_name = "AIF1ADC1L Mixer AIF2 Switch", .intval = 0, },
    { .ctl_name = "MIXINL IN1L Switch", .intval = 0, },
    { .ctl_name = NULL, },
};