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| author | Craig Topper <craig.topper@gmail.com> | 2013-10-12 05:41:08 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2013-10-12 05:41:08 +0000 |
| commit | 017d8a3e23b719ece59f2498582db7f25d65c1b9 (patch) | |
| tree | 6a8c4b868aefa17a26b30517a65dc0fc6e60a72d | |
| parent | f9318673178309288f9320efe02d529419ac32a2 (diff) | |
| download | external_llvm-017d8a3e23b719ece59f2498582db7f25d65c1b9.zip external_llvm-017d8a3e23b719ece59f2498582db7f25d65c1b9.tar.gz external_llvm-017d8a3e23b719ece59f2498582db7f25d65c1b9.tar.bz2 | |
Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192525 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrAVX512.td | 6 | ||||
| -rw-r--r-- | utils/TableGen/X86RecognizableInstr.cpp | 5 |
2 files changed, 6 insertions, 5 deletions
diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index fd28b1c..3fd725c 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -1177,6 +1177,7 @@ def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$sr [(set VR128X:$dst, (v2i64 (scalar_to_vector GR64:$src)))], IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG; +let isCodeGenOnly = 1 in { def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src), "vmovq{z}\t{$src, $dst|$dst, $src}", [(set FR64:$dst, (bitconvert GR64:$src))], @@ -1185,6 +1186,7 @@ def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src) "vmovq{z}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (bitconvert FR64:$src))], IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>; +} def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src), "vmovq{z}\t{$src, $dst|$dst, $src}", [(store (i64 (bitconvert FR64:$src)), addr:$dst)], @@ -1193,6 +1195,7 @@ def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$s // Move Int Doubleword to Single Scalar // +let isCodeGenOnly = 1 in { def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src), "vmovd{z}\t{$src, $dst|$dst, $src}", [(set FR32X:$dst, (bitconvert GR32:$src))], @@ -1202,6 +1205,7 @@ def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$sr "vmovd{z}\t{$src, $dst|$dst, $src}", [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))], IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>; +} // Move Packed Doubleword Int to Packed Double Int // @@ -1236,6 +1240,7 @@ def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs), // Move Scalar Single to Double Int // +let isCodeGenOnly = 1 in { def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32X:$src), "vmovd{z}\t{$src, $dst|$dst, $src}", @@ -1246,6 +1251,7 @@ def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs), "vmovd{z}\t{$src, $dst|$dst, $src}", [(store (i32 (bitconvert FR32X:$src)), addr:$dst)], IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>; +} // Move Quadword Int to Packed Quadword Int // diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index c6770b8..d3320f9 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -541,11 +541,6 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const { Name == "XRELEASE_PREFIX") return FILTER_WEAK; - if (HasFROperands && Name.find("MOV") != Name.npos && - ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || - (Name.find("to") != Name.npos))) - return FILTER_STRONG; - return FILTER_NORMAL; } |