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| author | Chad Rosier <mcrosier@apple.com> | 2013-06-26 22:23:32 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2013-06-26 22:23:32 +0000 |
| commit | 096c0a03313ea43a1e4035645b02bf99fd35801a (patch) | |
| tree | 5334cd1acef7a48b018c0d8f972845381ab975f7 | |
| parent | 6b97ebe9a32342207b24a5f73ebbf3070ec8d189 (diff) | |
| download | external_llvm-096c0a03313ea43a1e4035645b02bf99fd35801a.zip external_llvm-096c0a03313ea43a1e4035645b02bf99fd35801a.tar.gz external_llvm-096c0a03313ea43a1e4035645b02bf99fd35801a.tar.bz2 | |
[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
function to lookup the proper tablegen'ed register enumeration. Previously,
it was using the encoded value directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185026 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 5 | ||||
| -rw-r--r-- | test/MC/Disassembler/Mips/mips32.txt | 8 | ||||
| -rw-r--r-- | test/MC/Disassembler/Mips/mips32_le.txt | 8 | ||||
| -rw-r--r-- | test/MC/Disassembler/Mips/mips32r2.txt | 8 | ||||
| -rw-r--r-- | test/MC/Disassembler/Mips/mips32r2_le.txt | 8 |
5 files changed, 20 insertions, 17 deletions
diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 4af6703..b6b265c 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -405,7 +405,10 @@ static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateReg(RegNo)); + if (RegNo > 31) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); + Inst.addOperand(MCOperand::CreateReg(Reg)); return MCDisassembler::Success; } diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index ef8bf71..5c2d5ca 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -158,8 +158,8 @@ # CHECK: ceil.w.s $f6, $f7 0x46 0x00 0x39 0x8e -# CHECK: cfc1 $6, $7 -0x44 0x46 0x38 0x00 +# CHECK: cfc1 $6, $fcc0 +0x44 0x46 0x08 0x00 # CHECK: clo $6, $7 0x70 0xe6 0x30 0x21 @@ -167,8 +167,8 @@ # CHECK: clz $6, $7 0x70 0xe6 0x30 0x20 -# CHECK: ctc1 $6, $7 -0x44 0xc6 0x38 0x00 +# CHECK: ctc1 $6, $fcc0 +0x44 0xc6 0x08 0x00 # CHECK: cvt.d.s $f6, $f7 0x46 0x00 0x39 0xa1 diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index a0885a4..f0553c6 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -158,8 +158,8 @@ # CHECK: ceil.w.s $f6, $f7 0x8e 0x39 0x00 0x46 -# CHECK: cfc1 $6, $7 -0x00 0x38 0x46 0x44 +# CHECK: cfc1 $6, $fcc0 +0x00 0x08 0x46 0x44 # CHECK: clo $6, $7 0x21 0x30 0xe6 0x70 @@ -167,8 +167,8 @@ # CHECK: clz $6, $7 0x20 0x30 0xe6 0x70 -# CHECK: ctc1 $6, $7 -0x00 0x38 0xc6 0x44 +# CHECK: ctc1 $6, $fcc0 +0x00 0x08 0xc6 0x44 # CHECK: cvt.d.s $f6, $f7 0xa1 0x39 0x00 0x46 diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt index 991eaa6..ac20e41 100644 --- a/test/MC/Disassembler/Mips/mips32r2.txt +++ b/test/MC/Disassembler/Mips/mips32r2.txt @@ -158,8 +158,8 @@ # CHECK: ceil.w.s $f6, $f7 0x46 0x00 0x39 0x8e -# CHECK: cfc1 $6, $7 -0x44 0x46 0x38 0x00 +# CHECK: cfc1 $6, $fcc0 +0x44 0x46 0x08 0x00 # CHECK: clo $6, $7 0x70 0xe6 0x30 0x21 @@ -167,8 +167,8 @@ # CHECK: clz $6, $7 0x70 0xe6 0x30 0x20 -# CHECK: ctc1 $6, $7 -0x44 0xc6 0x38 0x00 +# CHECK: ctc1 $6, $fcc0 +0x44 0xc6 0x08 0x00 # CHECK: cvt.d.s $f6, $f7 0x46 0x00 0x39 0xa1 diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt index 10c2938..a9131a3 100644 --- a/test/MC/Disassembler/Mips/mips32r2_le.txt +++ b/test/MC/Disassembler/Mips/mips32r2_le.txt @@ -158,8 +158,8 @@ # CHECK: ceil.w.s $f6, $f7 0x8e 0x39 0x00 0x46 -# CHECK: cfc1 $6, $7 -0x00 0x38 0x46 0x44 +# CHECK: cfc1 $6, $fcc0 +0x00 0x08 0x46 0x44 # CHECK: clo $6, $7 0x21 0x30 0xe6 0x70 @@ -167,8 +167,8 @@ # CHECK: clz $6, $7 0x20 0x30 0xe6 0x70 -# CHECK: ctc1 $6, $7 -0x00 0x38 0xc6 0x44 +# CHECK: ctc1 $6, $fcc0 +0x00 0x08 0xc6 0x44 # CHECK: cvt.d.s $f6, $f7 0xa1 0x39 0x00 0x46 |