diff options
| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-05-11 11:00:02 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-05-11 11:00:02 +0000 |
| commit | 37c2f716741b63067753d9d9c0f39b55afb7e877 (patch) | |
| tree | 8fd3124ee32a5b295eee00f8f7435cde300a1d64 | |
| parent | eae570ed4a2f43ae796772f3b197a8d8311b6918 (diff) | |
| download | external_llvm-37c2f716741b63067753d9d9c0f39b55afb7e877.zip external_llvm-37c2f716741b63067753d9d9c0f39b55afb7e877.tar.gz external_llvm-37c2f716741b63067753d9d9c0f39b55afb7e877.tar.bz2 | |
Make SPU backend not assert on jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103466 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.cpp | 3 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/jumptable.ll | 21 |
2 files changed, 24 insertions, 0 deletions
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index 066c5b0..4c53c98 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -467,6 +467,9 @@ SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, // If there is only one terminator instruction, process it. if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { if (isUncondBranch(LastInst)) { + // Check for jump tables + if (!LastInst->getOperand(0).isMBB()) + return true; TBB = LastInst->getOperand(0).getMBB(); return false; } else if (isCondBranch(LastInst)) { diff --git a/test/CodeGen/CellSPU/jumptable.ll b/test/CodeGen/CellSPU/jumptable.ll new file mode 100644 index 0000000..d7d1ef4 --- /dev/null +++ b/test/CodeGen/CellSPU/jumptable.ll @@ -0,0 +1,21 @@ +;RUN: llc --march=cellspu %s -o - | FileCheck %s +; This is to check that emitting jumptables doesn't crash llc +define i32 @test(i32 %param) { +entry: +;CHECK: ai $4, $3, -1 +;CHECK: clgti $5, $4, 3 +;CHECK: brnz $5,.LBB0_2 + switch i32 %param, label %bb1 [ + i32 1, label %bb3 + i32 2, label %bb2 + i32 3, label %bb3 + i32 4, label %bb1 + ] + +bb1: + ret i32 1 +bb2: + ret i32 2 +bb3: + ret i32 3 +} |
