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| author | Stepan Dyatkovskiy <stpworld@narod.ru> | 2013-05-08 14:51:27 +0000 |
|---|---|---|
| committer | Stepan Dyatkovskiy <stpworld@narod.ru> | 2013-05-08 14:51:27 +0000 |
| commit | 44b6b530e94d5b05e1b2ddbb174c477b0ce56638 (patch) | |
| tree | 627f990166c85551d2c45de0931dc9f51b63761b | |
| parent | 0b132946ea36f1495b864b3305a34c1e5e28c45d (diff) | |
| download | external_llvm-44b6b530e94d5b05e1b2ddbb174c477b0ce56638.zip external_llvm-44b6b530e94d5b05e1b2ddbb174c477b0ce56638.tar.gz external_llvm-44b6b530e94d5b05e1b2ddbb174c477b0ce56638.tar.bz2 | |
For r181148: fixed warning 'enumeral and non-enumeral type in conditional expression'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181437 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 0f7beb1..fd77732 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -1795,7 +1795,7 @@ ARMTargetLowering::HandleByVal( // else parameter would be splitted between registers and stack, // end register would be r4 in this case. unsigned ByValRegBegin = reg; - unsigned ByValRegEnd = (size < excess) ? reg + size/4 : ARM::R4; + unsigned ByValRegEnd = (size < excess) ? reg + size/4 : (unsigned)ARM::R4; State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd); // Note, first register is allocated in the beginning of function already, // allocate remained amount of registers we need. |