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| author | Chris Lattner <sabre@nondot.org> | 2010-09-05 02:18:34 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-09-05 02:18:34 +0000 |
| commit | 083b9e18e561b1b7f00a159a6936c7b81e3c8a2b (patch) | |
| tree | 54525601bcdb388c49b9d014c90e6cbe8dbc1467 /include/llvm/CodeGen | |
| parent | fa2d83d5a9a3fabe46c671ca2d54625b26b0e637 (diff) | |
| download | external_llvm-083b9e18e561b1b7f00a159a6936c7b81e3c8a2b.zip external_llvm-083b9e18e561b1b7f00a159a6936c7b81e3c8a2b.tar.gz external_llvm-083b9e18e561b1b7f00a159a6936c7b81e3c8a2b.tar.bz2 | |
implement rdar://6653118 - fastisel should fold loads where possible.
Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:
int foo(int x, int y, int z) {
return x+y+z;
}
used to compile into:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
movl 4(%rsp), %esi
addl %edx, %esi
movl (%rsp), %edx
addl %esi, %edx
movl %edx, %eax
addq $12, %rsp
ret
Now we produce:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
addl 4(%rsp), %edx ## Folded load
addl (%rsp), %edx ## Folded load
movl %edx, %eax
addq $12, %rsp
ret
Fewer instructions and less register use = faster compiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113102 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen')
| -rw-r--r-- | include/llvm/CodeGen/FastISel.h | 12 | ||||
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAGISel.h | 2 |
2 files changed, 13 insertions, 1 deletions
diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h index 79b1554..d7506be 100644 --- a/include/llvm/CodeGen/FastISel.h +++ b/include/llvm/CodeGen/FastISel.h @@ -39,6 +39,7 @@ class TargetLowering; class TargetMachine; class TargetRegisterClass; class TargetRegisterInfo; +class LoadInst; /// FastISel - This is a fast-path instruction selection class that /// generates poor code and doesn't support illegal types or non-trivial @@ -102,7 +103,16 @@ public: /// index value. std::pair<unsigned, bool> getRegForGEPIndex(const Value *V); - /// recomputeInsertPt - Reset InsertPt to prepare for insterting instructions + /// TryToFoldLoad - The specified machine instr operand is a vreg, and that + /// vreg is being provided by the specified load instruction. If possible, + /// try to fold the load as an operand to the instruction, returning true if + /// possible. + virtual bool TryToFoldLoad(MachineInstr * /*MI*/, unsigned /*OpNo*/, + const LoadInst * /*LI*/) { + return false; + } + + /// recomputeInsertPt - Reset InsertPt to prepare for inserting instructions /// into the current block. void recomputeInsertPt(); diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index 01d05dd..51895a6 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -34,6 +34,7 @@ namespace llvm { class ScheduleHazardRecognizer; class GCFunctionInfo; class ScheduleDAGSDNodes; + class LoadInst; /// SelectionDAGISel - This is the common base class used for SelectionDAG-based /// pattern-matching instruction selectors. @@ -282,6 +283,7 @@ private: void PrepareEHLandingPad(); void SelectAllBasicBlocks(const Function &Fn); + bool TryToFoldFastISelLoad(const LoadInst *LI, FastISel *FastIS); void FinishBasicBlock(); void SelectBasicBlock(BasicBlock::const_iterator Begin, |
