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author | Stephen Hines <srhines@google.com> | 2014-12-04 02:59:27 +0000 |
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committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | 2014-12-04 02:59:28 +0000 |
commit | 876d6995443e99d13696f3941c3a789a4daa7c7a (patch) | |
tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /include/llvm/MC/MCSchedule.h | |
parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
parent | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (diff) | |
download | external_llvm-876d6995443e99d13696f3941c3a789a4daa7c7a.zip external_llvm-876d6995443e99d13696f3941c3a789a4daa7c7a.tar.gz external_llvm-876d6995443e99d13696f3941c3a789a4daa7c7a.tar.bz2 |
Merge "Update aosp/master LLVM for rebase to r222494."
Diffstat (limited to 'include/llvm/MC/MCSchedule.h')
-rw-r--r-- | include/llvm/MC/MCSchedule.h | 57 |
1 files changed, 23 insertions, 34 deletions
diff --git a/include/llvm/MC/MCSchedule.h b/include/llvm/MC/MCSchedule.h index 862a0fd..1adfedd 100644 --- a/include/llvm/MC/MCSchedule.h +++ b/include/llvm/MC/MCSchedule.h @@ -133,10 +133,7 @@ struct MCSchedClassDesc { /// provides a detailed reservation table describing each cycle of instruction /// execution. Subtargets may define any or all of the above categories of data /// depending on the type of CPU and selected scheduler. -class MCSchedModel { -public: - static MCSchedModel DefaultSchedModel; // For unknown processors. - +struct MCSchedModel { // IssueWidth is the maximum number of instructions that may be scheduled in // the same per-cycle group. unsigned IssueWidth; @@ -186,10 +183,11 @@ public: // takes to recover from a branch misprediction. unsigned MispredictPenalty; static const unsigned DefaultMispredictPenalty = 10; + + bool PostRAScheduler; // default value is false bool CompleteModel; -private: unsigned ProcID; const MCProcResourceDesc *ProcResourceTable; const MCSchedClassDesc *SchedClassTable; @@ -199,35 +197,6 @@ private: friend class InstrItineraryData; const InstrItinerary *InstrItineraries; -public: - // Default's must be specified as static const literals so that tablegenerated - // target code can use it in static initializers. The defaults need to be - // initialized in this default ctor because some clients directly instantiate - // MCSchedModel instead of using a generated itinerary. - MCSchedModel(): IssueWidth(DefaultIssueWidth), - MicroOpBufferSize(DefaultMicroOpBufferSize), - LoopMicroOpBufferSize(DefaultLoopMicroOpBufferSize), - LoadLatency(DefaultLoadLatency), - HighLatency(DefaultHighLatency), - MispredictPenalty(DefaultMispredictPenalty), - CompleteModel(true), ProcID(0), ProcResourceTable(nullptr), - SchedClassTable(nullptr), NumProcResourceKinds(0), - NumSchedClasses(0), InstrItineraries(nullptr) { - (void)NumProcResourceKinds; - (void)NumSchedClasses; - } - - // Table-gen driven ctor. - MCSchedModel(unsigned iw, int mbs, int lmbs, unsigned ll, unsigned hl, - unsigned mp, bool cm, unsigned pi, const MCProcResourceDesc *pr, - const MCSchedClassDesc *sc, unsigned npr, unsigned nsc, - const InstrItinerary *ii): - IssueWidth(iw), MicroOpBufferSize(mbs), LoopMicroOpBufferSize(lmbs), - LoadLatency(ll), HighLatency(hl), - MispredictPenalty(mp), CompleteModel(cm), ProcID(pi), - ProcResourceTable(pr), SchedClassTable(sc), NumProcResourceKinds(npr), - NumSchedClasses(nsc), InstrItineraries(ii) {} - unsigned getProcessorID() const { return ProcID; } /// Does this machine model include instruction-level scheduling. @@ -254,6 +223,26 @@ public: assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx"); return &SchedClassTable[SchedClassIdx]; } + + // /\brief Returns a default initialized model. Used for unknown processors. + static MCSchedModel GetDefaultSchedModel() { + MCSchedModel Ret = { DefaultIssueWidth, + DefaultMicroOpBufferSize, + DefaultLoopMicroOpBufferSize, + DefaultLoadLatency, + DefaultHighLatency, + DefaultMispredictPenalty, + false, + true, + 0, + nullptr, + nullptr, + 0, + 0, + nullptr + }; + return Ret; + } }; } // End llvm namespace |