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| author | Logan Chien <loganchien@google.com> | 2011-10-20 00:08:13 +0800 |
|---|---|---|
| committer | Logan Chien <loganchien@google.com> | 2011-10-20 00:09:35 +0800 |
| commit | 0ebc07a576037e4e36f68bf5cece32740ca120c0 (patch) | |
| tree | c2e40648043d01498ee25af839a071193561e425 /lib/CodeGen/RegAllocBasic.cpp | |
| parent | 62383e889e0b06fd12a6b88311717cd33a1925c4 (diff) | |
| parent | cdd8e46bec4e975d00a5abea808d8eb4138515c5 (diff) | |
| download | external_llvm-0ebc07a576037e4e36f68bf5cece32740ca120c0.zip external_llvm-0ebc07a576037e4e36f68bf5cece32740ca120c0.tar.gz external_llvm-0ebc07a576037e4e36f68bf5cece32740ca120c0.tar.bz2 | |
Merge with LLVM upstream 2011/10/20 (r142530)
Conflicts:
lib/Support/Unix/Host.inc
Change-Id: Idc00db3b63912dca6348bddd9f8a1af2a8d5d147
Diffstat (limited to 'lib/CodeGen/RegAllocBasic.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocBasic.cpp | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/lib/CodeGen/RegAllocBasic.cpp b/lib/CodeGen/RegAllocBasic.cpp index 5ea26ad..5496d69 100644 --- a/lib/CodeGen/RegAllocBasic.cpp +++ b/lib/CodeGen/RegAllocBasic.cpp @@ -20,7 +20,6 @@ #include "RenderMachineFunction.h" #include "Spiller.h" #include "VirtRegMap.h" -#include "RegisterCoalescer.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/Statistic.h" #include "llvm/Analysis/AliasAnalysis.h" @@ -160,7 +159,7 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved<LiveDebugVariables>(); if (StrongPHIElim) AU.addRequiredID(StrongPHIEliminationID); - AU.addRequiredTransitive<RegisterCoalescer>(); + AU.addRequiredTransitiveID(RegisterCoalescerPassID); AU.addRequired<CalculateSpillWeights>(); AU.addRequired<LiveStacks>(); AU.addPreserved<LiveStacks>(); @@ -439,6 +438,7 @@ void RegAllocBase::addMBBLiveIns(MachineFunction *MF) { LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg]; if (LiveUnion.empty()) continue; + DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " live-in:"); MachineFunction::iterator MBB = llvm::next(MF->begin()); MachineFunction::iterator MFE = MF->end(); SlotIndex Start, Stop; @@ -449,6 +449,8 @@ void RegAllocBase::addMBBLiveIns(MachineFunction *MF) { if (SI.start() <= Start) { if (!MBB->isLiveIn(PhysReg)) MBB->addLiveIn(PhysReg); + DEBUG(dbgs() << "\tBB#" << MBB->getNumber() << ':' + << PrintReg(SI.value()->reg, TRI)); } else if (SI.start() > Stop) MBB = Indexes->getMBBFromIndex(SI.start().getPrevIndex()); if (++MBB == MFE) @@ -456,6 +458,7 @@ void RegAllocBase::addMBBLiveIns(MachineFunction *MF) { tie(Start, Stop) = Indexes->getMBBRange(MBB); SI.advanceTo(Start); } + DEBUG(dbgs() << '\n'); } } @@ -495,8 +498,9 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, // Found an available register. return PhysReg; } + Queries[interfReg].collectInterferingVRegs(1); LiveInterval *interferingVirtReg = - Queries[interfReg].firstInterference().liveUnionPos().value(); + Queries[interfReg].interferingVRegs().front(); // The current VirtReg must either be spillable, or one of its interferences // must have less spill weight. |