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| author | Hal Finkel <hfinkel@anl.gov> | 2013-05-16 19:58:38 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-05-16 19:58:38 +0000 |
| commit | c482454e3cc2a33a2cf2d1cf0881c7c5e2641c80 (patch) | |
| tree | 6880887689abe3c97fd79a896ab470b8da4090b7 /lib/Support/regcomp.c | |
| parent | 02e168003f45cf8e0a277c6b8c85c1a3032b1dec (diff) | |
| download | external_llvm-c482454e3cc2a33a2cf2d1cf0881c7c5e2641c80.zip external_llvm-c482454e3cc2a33a2cf2d1cf0881c7c5e2641c80.tar.gz external_llvm-c482454e3cc2a33a2cf2d1cf0881c7c5e2641c80.tar.bz2 | |
Create an new preheader in PPCCTRLoops to avoid counter register clobbers
Some IR-level instructions (such as FP <-> i64 conversions) are not chained
w.r.t. the mtctr intrinsic and yet may become function calls that clobber the
counter register. At the selection-DAG level, these might be reordered with the
mtctr intrinsic causing miscompiles. To avoid this situation, if an existing
preheader has instructions that might use the counter register, create a new
preheader for the mtctr intrinsic. This extra block will be remerged with the
old preheader at the MI level, but will prevent unwanted reordering at the
selection-DAG level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182045 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Support/regcomp.c')
0 files changed, 0 insertions, 0 deletions