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| author | Tim Northover <Tim.Northover@arm.com> | 2013-02-06 09:04:56 +0000 |
|---|---|---|
| committer | Tim Northover <Tim.Northover@arm.com> | 2013-02-06 09:04:56 +0000 |
| commit | 9e3b31345f0d17b757e183a8384db92616256926 (patch) | |
| tree | 33d5bbc47edbeb3d0563dc918a8d008c953af3bd /lib/Target/Mips/MipsSubtarget.cpp | |
| parent | 95ce4c2ffb0ff31a79b060fb112659322a5be3bf (diff) | |
| download | external_llvm-9e3b31345f0d17b757e183a8384db92616256926.zip external_llvm-9e3b31345f0d17b757e183a8384db92616256926.tar.gz external_llvm-9e3b31345f0d17b757e183a8384db92616256926.tar.bz2 | |
Add icache prefetch operations to AArch64
This adds hints to the various "prfm" instructions so that they can
affect the instruction cache as well as the data cache.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174495 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSubtarget.cpp')
0 files changed, 0 insertions, 0 deletions