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| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-12-20 23:56:43 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-12-20 23:56:43 +0000 |
| commit | c0ea04389c9fc0b73d0cbd90ec3a5bc076d25d7b (patch) | |
| tree | ab59ff01925c24f27eba2a658f62d4158e643db6 /lib/Target/Mips | |
| parent | 4d2b0f3ce79cafca3b9aafd420da10a25e444f0d (diff) | |
| download | external_llvm-c0ea04389c9fc0b73d0cbd90ec3a5bc076d25d7b.zip external_llvm-c0ea04389c9fc0b73d0cbd90ec3a5bc076d25d7b.tar.gz external_llvm-c0ea04389c9fc0b73d0cbd90ec3a5bc076d25d7b.tar.bz2 | |
Add definition of DSBH (Double Swap Bytes within Halfwords) and
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147017 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 6 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 4 |
2 files changed, 9 insertions, 1 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 681c7ae..f799417 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -199,6 +199,10 @@ def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>; def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>; def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>; +/// Double Word Swap Bytes/HalfWords +def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>; +def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>; + def LEA_ADDiu64 : EffectiveAddress<"addiu\t$rt, $addr", CPU64Regs, mem_ea_64>; let Uses = [SP_64] in @@ -316,3 +320,5 @@ def : Pat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; // Sign extend in register def : Pat<(i64 (sext_inreg CPU64Regs:$src, i32)), (SLL64_64 CPU64Regs:$src)>; +// bswap pattern +def : Pat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>; diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index cfdce3a..d0ee632 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -221,8 +221,10 @@ MipsTargetLowering(MipsTargetMachine &TM) if (!Subtarget->hasBitCount()) setOperationAction(ISD::CTLZ, MVT::i32, Expand); - if (!Subtarget->hasSwap()) + if (!Subtarget->hasSwap()) { setOperationAction(ISD::BSWAP, MVT::i32, Expand); + setOperationAction(ISD::BSWAP, MVT::i64, Expand); + } setTargetDAGCombine(ISD::ADDE); setTargetDAGCombine(ISD::SUBE); |